diff -r f935aa562118 -r 98f9cef66a34 hotspot/src/cpu/sparc/vm/sparc.ad
--- a/hotspot/src/cpu/sparc/vm/sparc.ad	Fri Feb 27 08:34:19 2009 -0800
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad	Fri Feb 27 13:27:09 2009 -0800
@@ -189,7 +189,7 @@
 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 // wants 0-63, so we have to convert every time we want to use fp regs
 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
-// 255 is a flag meaning 'dont go here'.
+// 255 is a flag meaning "don't go here".
 // I believe we can't handle callee-save doubles D32 and up until
 // the place in the sparc stack crawler that asserts on the 255 is
 // fixed up.
@@ -462,7 +462,7 @@
 
 // Macros to extract hi & lo halves from a long pair.
 // G0 is not part of any long pair, so assert on that.
-// Prevents accidently using G1 instead of G0.
+// Prevents accidentally using G1 instead of G0.
 #define LONG_HI_REG(x) (x)
 #define LONG_LO_REG(x) (x)
 
@@ -1431,7 +1431,7 @@
 
 #ifndef _LP64
   // In the LP64 build, all registers can be moved as aligned/adjacent
-  // pairs, so there's never any need to move the high bits seperately.
+  // pairs, so there's never any need to move the high bits separately.
   // The 32-bit builds have to deal with the 32-bit ABI which can force
   // all sorts of silly alignment problems.
 
@@ -1624,7 +1624,7 @@
   Register temp_reg   = G3;
   assert( G5_ic_reg != temp_reg, "conflicting registers" );
 
-  // Load klass from reciever
+  // Load klass from receiver
   __ load_klass(O0, temp_reg);
   // Compare against expected klass
   __ cmp(temp_reg, G5_ic_reg);
@@ -4149,7 +4149,7 @@
 
 //----------OPERAND CLASSES----------------------------------------------------
 // Operand Classes are groups of operands that are used to simplify
-// instruction definitions by not requiring the AD writer to specify seperate
+// instruction definitions by not requiring the AD writer to specify separate
 // instructions for every form of operand when the instruction accepts
 // multiple operand types with the same basic encoding and format.  The classic
 // case of this is memory operands.
@@ -6847,7 +6847,7 @@
   ins_pipe(sdiv_reg_reg);
 %}
 
-// Magic constant, reciprical of 10
+// Magic constant, reciprocal of 10
 instruct loadConI_x66666667(iRegIsafe dst) %{
   effect( DEF dst );
 
@@ -6857,7 +6857,7 @@
   ins_pipe(ialu_hi_lo_reg);
 %}
 
-// Register Shift Right Arithmatic Long by 32-63
+// Register Shift Right Arithmetic Long by 32-63
 instruct sra_31( iRegI dst, iRegI src ) %{
   effect( DEF dst, USE src );
   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
@@ -9048,7 +9048,7 @@
 // These must follow all instruction definitions as they use the names
 // defined in the instructions definitions.
 //
-// peepmatch ( root_instr_name [preceeding_instruction]* );
+// peepmatch ( root_instr_name [preceding_instruction]* );
 //
 // peepconstraint %{
 // (instruction_number.operand_name relational_op instruction_number.operand_name