8181836: BadKindHelper.html and BoundsHelper.html contains broken link in the javadoc
Reviewed-by: chegar
/*
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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#ifndef OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP
#define OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP
#include "runtime/orderAccess.hpp"
#include "vm_version_s390.hpp"
// Implementation of class OrderAccess.
//
// machine barrier instructions:
//
// - z_sync two-way memory barrier, aka fence
//
// semantic barrier instructions:
// (as defined in orderAccess.hpp)
//
// - z_release orders Store|Store, (maps to compiler barrier)
// Load|Store
// - z_acquire orders Load|Store, (maps to compiler barrier)
// Load|Load
// - z_fence orders Store|Store, (maps to z_sync)
// Load|Store,
// Load|Load,
// Store|Load
//
// Only load-after-store-order is not guaranteed on z/Architecture, i.e. only 'fence'
// is needed.
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions.
#define inlasm_compiler_barrier() __asm__ volatile ("" : : : "memory");
// "bcr 15, 0" is used as two way memory barrier.
#define inlasm_zarch_sync() __asm__ __volatile__ ("bcr 15, 0" : : : "memory");
// Release and acquire are empty on z/Architecture, but potential
// optimizations of gcc must be forbidden by OrderAccess::release and
// OrderAccess::acquire.
#define inlasm_zarch_release() inlasm_compiler_barrier()
#define inlasm_zarch_acquire() inlasm_compiler_barrier()
#define inlasm_zarch_fence() inlasm_zarch_sync()
inline void OrderAccess::loadload() { inlasm_compiler_barrier(); }
inline void OrderAccess::storestore() { inlasm_compiler_barrier(); }
inline void OrderAccess::loadstore() { inlasm_compiler_barrier(); }
inline void OrderAccess::storeload() { inlasm_zarch_sync(); }
inline void OrderAccess::acquire() { inlasm_zarch_acquire(); }
inline void OrderAccess::release() { inlasm_zarch_release(); }
inline void OrderAccess::fence() { inlasm_zarch_sync(); }
template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = *p; inlasm_zarch_acquire(); return t; }
template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = *p; inlasm_zarch_acquire(); return t; }
template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = *p; inlasm_zarch_acquire(); return t; }
template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = *p; inlasm_zarch_acquire(); return t; }
#undef inlasm_compiler_barrier
#undef inlasm_zarch_sync
#undef inlasm_zarch_release
#undef inlasm_zarch_acquire
#undef inlasm_zarch_fence
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_LINUX_S390_VM_ORDERACCESS_LINUX_S390_INLINE_HPP