/*+
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 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.+
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.+
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 *+
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 * This code is free software; you can redistribute it and/or modify it+
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 * under the terms of the GNU General Public License version 2 only, as+
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 * published by the Free Software Foundation.+
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 *+
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 * This code is distributed in the hope that it will be useful, but WITHOUT+
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or+
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License+
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 * version 2 for more details (a copy is included in the LICENSE file that+
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 * accompanied this code).+
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 *+
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 * You should have received a copy of the GNU General Public License version+
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 * 2 along with this work; if not, write to the Free Software Foundation,+
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.+
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 *+
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA+
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 * or visit www.oracle.com if you need additional information or have any+
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 * questions.+
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 *+
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 */+
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+
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#ifndef CPU_X86_VM_GLOBALS_X86_HPP+
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#define CPU_X86_VM_GLOBALS_X86_HPP+
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+
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#include "utilities/globalDefinitions.hpp"+
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#include "utilities/macros.hpp"+
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+
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// Sets the default values for platform dependent flags used by the runtime system.+
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// (see globals.hpp)+
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+
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define_pd_global(bool, ConvertSleepToYield,      true);+
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define_pd_global(bool, ShareVtableStubs,         true);+
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define_pd_global(bool, CountInterpCalls,         true);+
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define_pd_global(bool, NeedsDeoptSuspend,        false); // only register window machines need this+
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+
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define_pd_global(bool, ImplicitNullChecks,       true);  // Generate code for implicit null checks+
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define_pd_global(bool, UncommonNullCast,         true);  // Uncommon-trap NULLs past to check cast+
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+
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// See 4827828 for this change. There is no globals_core_i486.hpp. I can't+
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// assign a different value for C2 without touching a number of files. Use+
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// #ifdef to minimize the change as it's late in Mantis. -- FIXME.+
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// c1 doesn't have this problem because the fix to 4858033 assures us+
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// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns+
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// the uep and the vep doesn't get real alignment but just slops on by+
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// only assured that the entry instruction meets the 5 byte size requirement.+
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#ifdef COMPILER2+
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define_pd_global(intx, CodeEntryAlignment,       32);+
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#else+
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define_pd_global(intx, CodeEntryAlignment,       16);+
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#endif // COMPILER2+
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define_pd_global(intx, OptoLoopAlignment,        16);+
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define_pd_global(intx, InlineFrequencyCount,     100);+
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define_pd_global(intx, InlineSmallCode,          1000);+
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+
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define_pd_global(intx, StackYellowPages, NOT_WINDOWS(2) WINDOWS_ONLY(3));+
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define_pd_global(intx, StackRedPages, 1);+
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#ifdef AMD64+
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// Very large C++ stack frames using solaris-amd64 optimized builds+
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// due to lack of optimization caused by C++ compiler bugs+
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define_pd_global(intx, StackShadowPages, NOT_WIN64(20) WIN64_ONLY(6) DEBUG_ONLY(+2));+
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#else+
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define_pd_global(intx, StackShadowPages, 4 DEBUG_ONLY(+5));+
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#endif // AMD64+
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+
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define_pd_global(intx, PreInflateSpin,           10);+
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+
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define_pd_global(bool, RewriteBytecodes,     true);+
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define_pd_global(bool, RewriteFrequentPairs, true);+
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+
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#ifdef _ALLBSD_SOURCE+
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define_pd_global(bool, UseMembar,            true);+
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#else+
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define_pd_global(bool, UseMembar,            false);+
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#endif+
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+
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// GC Ergo Flags+
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define_pd_global(uintx, CMSYoungGenPerWorker, 64*M);  // default max size of CMS young gen, per GC worker thread+
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+
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#define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \+
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                                                                            \+
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  develop(bool, IEEEPrecision, true,                                        \+
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          "Enables IEEE precision (for INTEL only)")                        \+
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                                                                            \+
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  product(intx, FenceInstruction, 0,                                        \+
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          "(Unsafe,Unstable) Experimental")                                 \+
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                                                                            \+
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  product(intx,  ReadPrefetchInstr, 0,                                      \+
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          "Prefetch instruction to prefetch ahead")                         \+
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                                                                            \+
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  product(bool, UseStoreImmI16, true,                                       \+
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          "Use store immediate 16-bits value instruction on x86")           \+
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                                                                            \+
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  product(intx, UseAVX, 99,                                                 \+
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          "Highest supported AVX instructions set on x86/x64")              \+
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                                                                            \+
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  product(bool, UseCLMUL, false,                                            \+
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          "Control whether CLMUL instructions can be used on x86/x64")      \+
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                                                                            \+
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  diagnostic(bool, UseIncDec, true,                                         \+
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          "Use INC, DEC instructions on x86")                               \+
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                                                                            \+
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  product(bool, UseNewLongLShift, false,                                    \+
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          "Use optimized bitwise shift left")                               \+
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                                                                            \+
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  product(bool, UseAddressNop, false,                                       \+
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          "Use '0F 1F [addr]' NOP instructions on x86 cpus")                \+
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                                                                            \+
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  product(bool, UseXmmLoadAndClearUpper, true,                              \+
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          "Load low part of XMM register and clear upper part")             \+
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                                                                            \+
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  product(bool, UseXmmRegToRegMoveAll, false,                               \+
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          "Copy all XMM register bits when moving value between registers") \+
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                                                                            \+
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  product(bool, UseXmmI2D, false,                                           \+
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          "Use SSE2 CVTDQ2PD instruction to convert Integer to Double")     \+
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                                                                            \+
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  product(bool, UseXmmI2F, false,                                           \+
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          "Use SSE2 CVTDQ2PS instruction to convert Integer to Float")      \+
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                                                                            \+
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  product(bool, UseUnalignedLoadStores, false,                              \+
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          "Use SSE2 MOVDQU instruction for Arraycopy")                      \+
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                                                                            \+
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  product(bool, UseFastStosb, false,                                        \+
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          "Use fast-string operation for zeroing: rep stosb")               \+
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                                                                            \+
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  /* assembler */                                                           \+
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  product(bool, Use486InstrsOnly, false,                                    \+
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          "Use 80486 Compliant instruction subset")                         \+
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                                                                            \+
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  product(bool, UseCountLeadingZerosInstruction, false,                     \+
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          "Use count leading zeros instruction")                            \+
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+
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#endif // CPU_X86_VM_GLOBALS_X86_HPP+
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