hotspot/src/cpu/aarch64/vm/aarch64.ad
changeset 31517 f1dc80fd7748
parent 31516 97b3293d2613
child 31860 c765af1b93c9
equal deleted inserted replaced
31516:97b3293d2613 31517:f1dc80fd7748
  7462   %}
  7462   %}
  7463 
  7463 
  7464   ins_pipe(ialu_reg);
  7464   ins_pipe(ialu_reg);
  7465 %}
  7465 %}
  7466 
  7466 
       
  7467 //---------- Population Count Instructions -------------------------------------
       
  7468 //
       
  7469 
       
  7470 instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
       
  7471   predicate(UsePopCountInstruction);
       
  7472   match(Set dst (PopCountI src));
       
  7473   effect(TEMP tmp);
       
  7474   ins_cost(INSN_COST * 13);
       
  7475 
       
  7476   format %{ "movw   $src, $src\n\t"
       
  7477             "mov    $tmp, $src\t# vector (1D)\n\t"
       
  7478             "cnt    $tmp, $tmp\t# vector (8B)\n\t"
       
  7479             "addv   $tmp, $tmp\t# vector (8B)\n\t"
       
  7480             "mov    $dst, $tmp\t# vector (1D)" %}
       
  7481   ins_encode %{
       
  7482     __ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
       
  7483     __ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
       
  7484     __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7485     __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7486     __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
       
  7487   %}
       
  7488 
       
  7489   ins_pipe(pipe_class_default);
       
  7490 %}
       
  7491 
       
  7492 instruct popCountI_mem(iRegINoSp dst, memory mem, vRegF tmp) %{
       
  7493   predicate(UsePopCountInstruction);
       
  7494   match(Set dst (PopCountI (LoadI mem)));
       
  7495   effect(TEMP tmp);
       
  7496   ins_cost(INSN_COST * 13);
       
  7497 
       
  7498   format %{ "ldrs   $tmp, $mem\n\t"
       
  7499             "cnt    $tmp, $tmp\t# vector (8B)\n\t"
       
  7500             "addv   $tmp, $tmp\t# vector (8B)\n\t"
       
  7501             "mov    $dst, $tmp\t# vector (1D)" %}
       
  7502   ins_encode %{
       
  7503     FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
       
  7504     loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrs, tmp_reg, $mem->opcode(),
       
  7505                as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
       
  7506     __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7507     __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7508     __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
       
  7509   %}
       
  7510 
       
  7511   ins_pipe(pipe_class_default);
       
  7512 %}
       
  7513 
       
  7514 // Note: Long.bitCount(long) returns an int.
       
  7515 instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
       
  7516   predicate(UsePopCountInstruction);
       
  7517   match(Set dst (PopCountL src));
       
  7518   effect(TEMP tmp);
       
  7519   ins_cost(INSN_COST * 13);
       
  7520 
       
  7521   format %{ "mov    $tmp, $src\t# vector (1D)\n\t"
       
  7522             "cnt    $tmp, $tmp\t# vector (8B)\n\t"
       
  7523             "addv   $tmp, $tmp\t# vector (8B)\n\t"
       
  7524             "mov    $dst, $tmp\t# vector (1D)" %}
       
  7525   ins_encode %{
       
  7526     __ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
       
  7527     __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7528     __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7529     __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
       
  7530   %}
       
  7531 
       
  7532   ins_pipe(pipe_class_default);
       
  7533 %}
       
  7534 
       
  7535 instruct popCountL_mem(iRegINoSp dst, memory mem, vRegD tmp) %{
       
  7536   predicate(UsePopCountInstruction);
       
  7537   match(Set dst (PopCountL (LoadL mem)));
       
  7538   effect(TEMP tmp);
       
  7539   ins_cost(INSN_COST * 13);
       
  7540 
       
  7541   format %{ "ldrd   $tmp, $mem\n\t"
       
  7542             "cnt    $tmp, $tmp\t# vector (8B)\n\t"
       
  7543             "addv   $tmp, $tmp\t# vector (8B)\n\t"
       
  7544             "mov    $dst, $tmp\t# vector (1D)" %}
       
  7545   ins_encode %{
       
  7546     FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
       
  7547     loadStore(MacroAssembler(&cbuf), &MacroAssembler::ldrd, tmp_reg, $mem->opcode(),
       
  7548                as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
       
  7549     __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7550     __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
       
  7551     __ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
       
  7552   %}
       
  7553 
       
  7554   ins_pipe(pipe_class_default);
       
  7555 %}
       
  7556 
  7467 // ============================================================================
  7557 // ============================================================================
  7468 // MemBar Instruction
  7558 // MemBar Instruction
  7469 
  7559 
  7470 instruct load_fence() %{
  7560 instruct load_fence() %{
  7471   match(LoadFence);
  7561   match(LoadFence);