6568 instruct cacheWB(indirect addr)

  6569 %{

  6570   predicate(VM_Version::supports_data_cache_line_flush());

  6571   match(CacheWB addr);

  6572 

  6573   ins_cost(100);

  6574   format %{"cache wb $addr" %}

  6575   ins_encode %{

  6576     assert($addr->index_position() < 0, "should be");

  6577     assert($addr$$disp == 0, "should be");

  6578     __ cache_wb(Address($addr$$base$$Register, 0));

  6579   %}

  6580   ins_pipe(pipe_slow); // XXX

  6581 %}

  6582 

  6583 instruct cacheWBPreSync()

  6584 %{

  6585   predicate(VM_Version::supports_data_cache_line_flush());

  6586   match(CacheWBPreSync);

  6587 

  6588   ins_cost(100);

  6589   format %{"cache wb presync" %}

  6590   ins_encode %{

  6591     __ cache_wbsync(true);

  6592   %}

  6593   ins_pipe(pipe_slow); // XXX

  6594 %}

  6595 

  6596 instruct cacheWBPostSync()

  6597 %{

  6598   predicate(VM_Version::supports_data_cache_line_flush());

  6599   match(CacheWBPostSync);

  6600 

  6601   ins_cost(100);

  6602   format %{"cache wb postsync" %}

  6603   ins_encode %{

  6604     __ cache_wbsync(false);

  6605   %}

  6606   ins_pipe(pipe_slow); // XXX

  6607 %}

  6608