src/hotspot/cpu/sparc/nativeInst_sparc.hpp
changeset 58932 8623f75be895
parent 58050 9fba708740d6
equal deleted inserted replaced
58931:304c63b17b07 58932:8623f75be895
   574 //
   574 //
   575 // Note that it is identical to NativeMovConstReg with the exception of a nop between the
   575 // Note that it is identical to NativeMovConstReg with the exception of a nop between the
   576 // sethi and the add.  The nop is required to be in the delay slot of the call instruction
   576 // sethi and the add.  The nop is required to be in the delay slot of the call instruction
   577 // which overwrites the sethi during patching.
   577 // which overwrites the sethi during patching.
   578 class NativeMovConstRegPatching;
   578 class NativeMovConstRegPatching;
   579 inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction {
   579 inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);
       
   580 class NativeMovConstRegPatching: public NativeInstruction {
   580  public:
   581  public:
   581   enum Sparc_specific_constants {
   582   enum Sparc_specific_constants {
   582     sethi_offset           = 0,
   583     sethi_offset           = 0,
   583     nop_offset             = 7 * BytesPerInstWord,
   584     nop_offset             = 7 * BytesPerInstWord,
   584     add_offset             = nop_offset   + BytesPerInstWord,
   585     add_offset             = nop_offset   + BytesPerInstWord,
   662     // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
   663     // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
   663     int i0 = long_at(0);
   664     int i0 = long_at(0);
   664     return (is_op(i0, Assembler::ldst_op));
   665     return (is_op(i0, Assembler::ldst_op));
   665   }
   666   }
   666 
   667 
   667   address instruction_address() const           { return addr_at(0); }
   668   address instruction_address() const { return addr_at(0); }
   668   address next_instruction_address() const      {
   669 
   669     return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord));
   670   int num_bytes_to_end_of_patch() const {
   670   }
   671     return is_immediate()? BytesPerInstWord :
       
   672                            NativeMovConstReg::instruction_size;
       
   673   }
       
   674 
   671   intptr_t   offset() const                             {
   675   intptr_t   offset() const                             {
   672      return is_immediate()? inv_simm(long_at(0), offset_width) :
   676      return is_immediate()? inv_simm(long_at(0), offset_width) :
   673                             nativeMovConstReg_at(addr_at(0))->data();
   677                             nativeMovConstReg_at(addr_at(0))->data();
   674   }
   678   }
   675   void  set_offset(intptr_t x) {
   679   void  set_offset(intptr_t x) {
   681   }
   685   }
   682 
   686 
   683   void  add_offset_in_bytes(intptr_t radd_offset)     {
   687   void  add_offset_in_bytes(intptr_t radd_offset)     {
   684       set_offset (offset() + radd_offset);
   688       set_offset (offset() + radd_offset);
   685   }
   689   }
   686 
       
   687   void  copy_instruction_to(address new_instruction_address);
       
   688 
   690 
   689   void verify();
   691   void verify();
   690   void print ();
   692   void print ();
   691 
   693 
   692   // unit test stuff
   694   // unit test stuff