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1 /* |
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2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP |
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26 #define CPU_X86_VM_C1_FRAMEMAP_X86_HPP |
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27 |
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28 // On i486 the frame looks as follows: |
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29 // |
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30 // +-----------------------------+---------+----------------------------------------+----------------+----------- |
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31 // | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . |
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32 // +-----------------------------+---------+----------------------------------------+----------------+----------- |
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33 // |
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34 // The FPU registers are mapped with their offset from TOS; therefore the |
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35 // status of FPU stack must be updated during code emission. |
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36 |
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37 public: |
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38 static const int pd_c_runtime_reserved_arg_size; |
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39 |
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40 enum { |
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41 nof_xmm_regs = pd_nof_xmm_regs_frame_map, |
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42 nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map, |
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43 first_available_sp_in_frame = 0, |
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44 #ifndef _LP64 |
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45 frame_pad_in_bytes = 8, |
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46 nof_reg_args = 2 |
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47 #else |
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48 frame_pad_in_bytes = 16, |
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49 nof_reg_args = 6 |
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50 #endif // _LP64 |
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51 }; |
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52 |
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53 private: |
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54 static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs]; |
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55 |
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56 static XMMRegister _xmm_regs[nof_xmm_regs]; |
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57 |
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58 public: |
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59 static LIR_Opr receiver_opr; |
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60 |
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61 static LIR_Opr rsi_opr; |
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62 static LIR_Opr rdi_opr; |
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63 static LIR_Opr rbx_opr; |
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64 static LIR_Opr rax_opr; |
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65 static LIR_Opr rdx_opr; |
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66 static LIR_Opr rcx_opr; |
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67 static LIR_Opr rsp_opr; |
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68 static LIR_Opr rbp_opr; |
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69 |
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70 static LIR_Opr rsi_oop_opr; |
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71 static LIR_Opr rdi_oop_opr; |
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72 static LIR_Opr rbx_oop_opr; |
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73 static LIR_Opr rax_oop_opr; |
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74 static LIR_Opr rdx_oop_opr; |
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75 static LIR_Opr rcx_oop_opr; |
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76 |
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77 static LIR_Opr rsi_metadata_opr; |
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78 static LIR_Opr rdi_metadata_opr; |
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79 static LIR_Opr rbx_metadata_opr; |
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80 static LIR_Opr rax_metadata_opr; |
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81 static LIR_Opr rdx_metadata_opr; |
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82 static LIR_Opr rcx_metadata_opr; |
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83 |
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84 #ifdef _LP64 |
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85 |
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86 static LIR_Opr r8_opr; |
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87 static LIR_Opr r9_opr; |
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88 static LIR_Opr r10_opr; |
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89 static LIR_Opr r11_opr; |
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90 static LIR_Opr r12_opr; |
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91 static LIR_Opr r13_opr; |
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92 static LIR_Opr r14_opr; |
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93 static LIR_Opr r15_opr; |
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94 |
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95 static LIR_Opr r8_oop_opr; |
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96 static LIR_Opr r9_oop_opr; |
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97 |
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98 static LIR_Opr r11_oop_opr; |
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99 static LIR_Opr r12_oop_opr; |
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100 static LIR_Opr r13_oop_opr; |
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101 static LIR_Opr r14_oop_opr; |
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102 |
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103 static LIR_Opr r8_metadata_opr; |
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104 static LIR_Opr r9_metadata_opr; |
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105 |
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106 static LIR_Opr r11_metadata_opr; |
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107 static LIR_Opr r12_metadata_opr; |
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108 static LIR_Opr r13_metadata_opr; |
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109 static LIR_Opr r14_metadata_opr; |
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110 |
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111 #endif // _LP64 |
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112 |
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113 static LIR_Opr long0_opr; |
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114 static LIR_Opr long1_opr; |
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115 static LIR_Opr fpu0_float_opr; |
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116 static LIR_Opr fpu0_double_opr; |
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117 static LIR_Opr xmm0_float_opr; |
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118 static LIR_Opr xmm0_double_opr; |
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119 |
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120 #ifdef _LP64 |
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121 static LIR_Opr as_long_opr(Register r) { |
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122 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
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123 } |
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124 static LIR_Opr as_pointer_opr(Register r) { |
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125 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); |
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126 } |
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127 #else |
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128 static LIR_Opr as_long_opr(Register r, Register r2) { |
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129 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2)); |
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130 } |
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131 static LIR_Opr as_pointer_opr(Register r) { |
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132 return LIR_OprFact::single_cpu(cpu_reg2rnr(r)); |
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133 } |
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134 #endif // _LP64 |
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135 |
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136 // VMReg name for spilled physical FPU stack slot n |
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137 static VMReg fpu_regname (int n); |
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138 |
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139 static XMMRegister nr2xmmreg(int rnr); |
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140 |
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141 static bool is_caller_save_register (LIR_Opr opr) { return true; } |
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142 static bool is_caller_save_register (Register r) { return true; } |
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143 |
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144 static LIR_Opr caller_save_xmm_reg_at(int i) { |
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145 assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds"); |
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146 return _caller_save_xmm_regs[i]; |
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147 } |
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148 |
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149 static int adjust_reg_range(int range) { |
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150 // Reduce the number of available regs (to free r12) in case of compressed oops |
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151 if (UseCompressedOops || UseCompressedClassPointers) return range - 1; |
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152 return range; |
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153 } |
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154 |
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155 static int get_num_caller_save_xmms(void) { |
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156 int num_caller_save_xmm_regs = nof_caller_save_xmm_regs; |
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157 #ifdef _LP64 |
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158 if (UseAVX < 3) { |
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159 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2; |
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160 } |
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161 #endif |
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162 return num_caller_save_xmm_regs; |
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163 } |
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164 |
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165 static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); } |
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166 static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); } |
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167 static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); } |
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168 |
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169 #endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP |
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170 |