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1 /* |
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2 * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright (c) 2012, 2015 SAP SE. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #include "precompiled.hpp" |
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27 #include "c1/c1_FrameMap.hpp" |
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28 #include "c1/c1_LIR.hpp" |
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29 #include "runtime/sharedRuntime.hpp" |
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30 #include "vmreg_ppc.inline.hpp" |
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31 |
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32 |
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33 const int FrameMap::pd_c_runtime_reserved_arg_size = 7; |
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34 |
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35 |
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36 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { |
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37 LIR_Opr opr = LIR_OprFact::illegalOpr; |
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38 VMReg r_1 = reg->first(); |
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39 VMReg r_2 = reg->second(); |
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40 if (r_1->is_stack()) { |
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41 // Convert stack slot to an SP offset. |
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42 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
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43 // so we must add it in here. |
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44 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
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45 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); |
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46 } else if (r_1->is_Register()) { |
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47 Register reg = r_1->as_Register(); |
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48 //if (outgoing) { |
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49 // assert(!reg->is_in(), "should be using I regs"); |
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50 //} else { |
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51 // assert(!reg->is_out(), "should be using O regs"); |
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52 //} |
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53 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
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54 opr = as_long_opr(reg); |
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55 } else if (type == T_OBJECT || type == T_ARRAY) { |
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56 opr = as_oop_opr(reg); |
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57 } else { |
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58 opr = as_opr(reg); |
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59 } |
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60 } else if (r_1->is_FloatRegister()) { |
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61 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
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62 FloatRegister f = r_1->as_FloatRegister(); |
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63 if (type == T_DOUBLE) { |
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64 opr = as_double_opr(f); |
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65 } else { |
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66 opr = as_float_opr(f); |
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67 } |
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68 } |
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69 return opr; |
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70 } |
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71 |
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72 // FrameMap |
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73 //-------------------------------------------------------- |
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74 |
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75 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; |
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76 |
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77 LIR_Opr FrameMap::R0_opr; |
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78 LIR_Opr FrameMap::R1_opr; |
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79 LIR_Opr FrameMap::R2_opr; |
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80 LIR_Opr FrameMap::R3_opr; |
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81 LIR_Opr FrameMap::R4_opr; |
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82 LIR_Opr FrameMap::R5_opr; |
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83 LIR_Opr FrameMap::R6_opr; |
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84 LIR_Opr FrameMap::R7_opr; |
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85 LIR_Opr FrameMap::R8_opr; |
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86 LIR_Opr FrameMap::R9_opr; |
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87 LIR_Opr FrameMap::R10_opr; |
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88 LIR_Opr FrameMap::R11_opr; |
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89 LIR_Opr FrameMap::R12_opr; |
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90 LIR_Opr FrameMap::R13_opr; |
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91 LIR_Opr FrameMap::R14_opr; |
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92 LIR_Opr FrameMap::R15_opr; |
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93 LIR_Opr FrameMap::R16_opr; |
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94 LIR_Opr FrameMap::R17_opr; |
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95 LIR_Opr FrameMap::R18_opr; |
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96 LIR_Opr FrameMap::R19_opr; |
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97 LIR_Opr FrameMap::R20_opr; |
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98 LIR_Opr FrameMap::R21_opr; |
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99 LIR_Opr FrameMap::R22_opr; |
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100 LIR_Opr FrameMap::R23_opr; |
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101 LIR_Opr FrameMap::R24_opr; |
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102 LIR_Opr FrameMap::R25_opr; |
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103 LIR_Opr FrameMap::R26_opr; |
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104 LIR_Opr FrameMap::R27_opr; |
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105 LIR_Opr FrameMap::R28_opr; |
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106 LIR_Opr FrameMap::R29_opr; |
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107 LIR_Opr FrameMap::R30_opr; |
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108 LIR_Opr FrameMap::R31_opr; |
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109 |
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110 LIR_Opr FrameMap::R0_oop_opr; |
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111 //LIR_Opr FrameMap::R1_oop_opr; |
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112 LIR_Opr FrameMap::R2_oop_opr; |
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113 LIR_Opr FrameMap::R3_oop_opr; |
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114 LIR_Opr FrameMap::R4_oop_opr; |
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115 LIR_Opr FrameMap::R5_oop_opr; |
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116 LIR_Opr FrameMap::R6_oop_opr; |
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117 LIR_Opr FrameMap::R7_oop_opr; |
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118 LIR_Opr FrameMap::R8_oop_opr; |
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119 LIR_Opr FrameMap::R9_oop_opr; |
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120 LIR_Opr FrameMap::R10_oop_opr; |
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121 LIR_Opr FrameMap::R11_oop_opr; |
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122 LIR_Opr FrameMap::R12_oop_opr; |
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123 //LIR_Opr FrameMap::R13_oop_opr; |
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124 LIR_Opr FrameMap::R14_oop_opr; |
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125 LIR_Opr FrameMap::R15_oop_opr; |
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126 //LIR_Opr FrameMap::R16_oop_opr; |
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127 LIR_Opr FrameMap::R17_oop_opr; |
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128 LIR_Opr FrameMap::R18_oop_opr; |
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129 LIR_Opr FrameMap::R19_oop_opr; |
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130 LIR_Opr FrameMap::R20_oop_opr; |
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131 LIR_Opr FrameMap::R21_oop_opr; |
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132 LIR_Opr FrameMap::R22_oop_opr; |
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133 LIR_Opr FrameMap::R23_oop_opr; |
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134 LIR_Opr FrameMap::R24_oop_opr; |
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135 LIR_Opr FrameMap::R25_oop_opr; |
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136 LIR_Opr FrameMap::R26_oop_opr; |
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137 LIR_Opr FrameMap::R27_oop_opr; |
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138 LIR_Opr FrameMap::R28_oop_opr; |
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139 //LIR_Opr FrameMap::R29_oop_opr; |
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140 LIR_Opr FrameMap::R30_oop_opr; |
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141 LIR_Opr FrameMap::R31_oop_opr; |
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142 |
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143 LIR_Opr FrameMap::R0_metadata_opr; |
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144 //LIR_Opr FrameMap::R1_metadata_opr; |
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145 LIR_Opr FrameMap::R2_metadata_opr; |
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146 LIR_Opr FrameMap::R3_metadata_opr; |
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147 LIR_Opr FrameMap::R4_metadata_opr; |
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148 LIR_Opr FrameMap::R5_metadata_opr; |
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149 LIR_Opr FrameMap::R6_metadata_opr; |
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150 LIR_Opr FrameMap::R7_metadata_opr; |
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151 LIR_Opr FrameMap::R8_metadata_opr; |
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152 LIR_Opr FrameMap::R9_metadata_opr; |
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153 LIR_Opr FrameMap::R10_metadata_opr; |
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154 LIR_Opr FrameMap::R11_metadata_opr; |
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155 LIR_Opr FrameMap::R12_metadata_opr; |
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156 //LIR_Opr FrameMap::R13_metadata_opr; |
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157 LIR_Opr FrameMap::R14_metadata_opr; |
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158 LIR_Opr FrameMap::R15_metadata_opr; |
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159 //LIR_Opr FrameMap::R16_metadata_opr; |
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160 LIR_Opr FrameMap::R17_metadata_opr; |
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161 LIR_Opr FrameMap::R18_metadata_opr; |
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162 LIR_Opr FrameMap::R19_metadata_opr; |
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163 LIR_Opr FrameMap::R20_metadata_opr; |
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164 LIR_Opr FrameMap::R21_metadata_opr; |
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165 LIR_Opr FrameMap::R22_metadata_opr; |
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166 LIR_Opr FrameMap::R23_metadata_opr; |
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167 LIR_Opr FrameMap::R24_metadata_opr; |
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168 LIR_Opr FrameMap::R25_metadata_opr; |
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169 LIR_Opr FrameMap::R26_metadata_opr; |
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170 LIR_Opr FrameMap::R27_metadata_opr; |
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171 LIR_Opr FrameMap::R28_metadata_opr; |
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172 //LIR_Opr FrameMap::R29_metadata_opr; |
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173 LIR_Opr FrameMap::R30_metadata_opr; |
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174 LIR_Opr FrameMap::R31_metadata_opr; |
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175 |
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176 LIR_Opr FrameMap::SP_opr; |
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177 |
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178 LIR_Opr FrameMap::R0_long_opr; |
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179 LIR_Opr FrameMap::R3_long_opr; |
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180 |
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181 LIR_Opr FrameMap::F1_opr; |
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182 LIR_Opr FrameMap::F1_double_opr; |
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183 |
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184 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
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185 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
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186 |
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187 FloatRegister FrameMap::nr2floatreg (int rnr) { |
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188 assert(_init_done, "tables not initialized"); |
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189 debug_only(fpu_range_check(rnr);) |
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190 return _fpu_regs[rnr]; |
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191 } |
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192 |
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193 |
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194 // Returns true if reg could be smashed by a callee. |
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195 bool FrameMap::is_caller_save_register (LIR_Opr reg) { |
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196 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } |
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197 if (reg->is_double_cpu()) { |
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198 return is_caller_save_register(reg->as_register_lo()) || |
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199 is_caller_save_register(reg->as_register_hi()); |
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200 } |
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201 return is_caller_save_register(reg->as_register()); |
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202 } |
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203 |
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204 |
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205 bool FrameMap::is_caller_save_register (Register r) { |
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206 // not visible to allocator: R0: scratch, R1: SP |
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207 // r->encoding() < 2 + nof_caller_save_cpu_regs(); |
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208 return true; // Currently all regs are caller save. |
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209 } |
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210 |
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211 |
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212 void FrameMap::initialize() { |
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213 assert(!_init_done, "once"); |
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214 |
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215 int i = 0; |
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216 |
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217 // Put generally available registers at the beginning (allocated, saved for GC). |
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218 for (int j = 0; j < nof_cpu_regs; ++j) { |
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219 Register rj = as_Register(j); |
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220 if (reg_needs_save(rj)) { |
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221 map_register(i++, rj); |
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222 } |
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223 } |
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224 assert(i == nof_cpu_regs_reg_alloc, "number of allocated registers"); |
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225 |
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226 // The following registers are not normally available. |
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227 for (int j = 0; j < nof_cpu_regs; ++j) { |
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228 Register rj = as_Register(j); |
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229 if (!reg_needs_save(rj)) { |
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230 map_register(i++, rj); |
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231 } |
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232 } |
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233 assert(i == nof_cpu_regs, "number of CPU registers"); |
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234 |
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235 for (i = 0; i < nof_fpu_regs; i++) { |
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236 _fpu_regs[i] = as_FloatRegister(i); |
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237 } |
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238 |
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239 _init_done = true; |
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240 |
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241 R0_opr = as_opr(R0); |
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242 R1_opr = as_opr(R1); |
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243 R2_opr = as_opr(R2); |
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244 R3_opr = as_opr(R3); |
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245 R4_opr = as_opr(R4); |
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246 R5_opr = as_opr(R5); |
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247 R6_opr = as_opr(R6); |
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248 R7_opr = as_opr(R7); |
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249 R8_opr = as_opr(R8); |
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250 R9_opr = as_opr(R9); |
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251 R10_opr = as_opr(R10); |
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252 R11_opr = as_opr(R11); |
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253 R12_opr = as_opr(R12); |
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254 R13_opr = as_opr(R13); |
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255 R14_opr = as_opr(R14); |
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256 R15_opr = as_opr(R15); |
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257 R16_opr = as_opr(R16); |
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258 R17_opr = as_opr(R17); |
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259 R18_opr = as_opr(R18); |
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260 R19_opr = as_opr(R19); |
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261 R20_opr = as_opr(R20); |
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262 R21_opr = as_opr(R21); |
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263 R22_opr = as_opr(R22); |
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264 R23_opr = as_opr(R23); |
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265 R24_opr = as_opr(R24); |
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266 R25_opr = as_opr(R25); |
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267 R26_opr = as_opr(R26); |
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268 R27_opr = as_opr(R27); |
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269 R28_opr = as_opr(R28); |
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270 R29_opr = as_opr(R29); |
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271 R30_opr = as_opr(R30); |
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272 R31_opr = as_opr(R31); |
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273 |
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274 R0_oop_opr = as_oop_opr(R0); |
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275 //R1_oop_opr = as_oop_opr(R1); |
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276 R2_oop_opr = as_oop_opr(R2); |
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277 R3_oop_opr = as_oop_opr(R3); |
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278 R4_oop_opr = as_oop_opr(R4); |
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279 R5_oop_opr = as_oop_opr(R5); |
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280 R6_oop_opr = as_oop_opr(R6); |
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281 R7_oop_opr = as_oop_opr(R7); |
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282 R8_oop_opr = as_oop_opr(R8); |
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283 R9_oop_opr = as_oop_opr(R9); |
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284 R10_oop_opr = as_oop_opr(R10); |
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285 R11_oop_opr = as_oop_opr(R11); |
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286 R12_oop_opr = as_oop_opr(R12); |
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287 //R13_oop_opr = as_oop_opr(R13); |
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288 R14_oop_opr = as_oop_opr(R14); |
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289 R15_oop_opr = as_oop_opr(R15); |
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290 //R16_oop_opr = as_oop_opr(R16); |
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291 R17_oop_opr = as_oop_opr(R17); |
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292 R18_oop_opr = as_oop_opr(R18); |
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293 R19_oop_opr = as_oop_opr(R19); |
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294 R20_oop_opr = as_oop_opr(R20); |
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295 R21_oop_opr = as_oop_opr(R21); |
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296 R22_oop_opr = as_oop_opr(R22); |
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297 R23_oop_opr = as_oop_opr(R23); |
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298 R24_oop_opr = as_oop_opr(R24); |
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299 R25_oop_opr = as_oop_opr(R25); |
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300 R26_oop_opr = as_oop_opr(R26); |
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301 R27_oop_opr = as_oop_opr(R27); |
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302 R28_oop_opr = as_oop_opr(R28); |
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303 //R29_oop_opr = as_oop_opr(R29); |
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304 R30_oop_opr = as_oop_opr(R30); |
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305 R31_oop_opr = as_oop_opr(R31); |
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306 |
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307 R0_metadata_opr = as_metadata_opr(R0); |
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308 //R1_metadata_opr = as_metadata_opr(R1); |
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309 R2_metadata_opr = as_metadata_opr(R2); |
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310 R3_metadata_opr = as_metadata_opr(R3); |
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311 R4_metadata_opr = as_metadata_opr(R4); |
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312 R5_metadata_opr = as_metadata_opr(R5); |
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313 R6_metadata_opr = as_metadata_opr(R6); |
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314 R7_metadata_opr = as_metadata_opr(R7); |
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315 R8_metadata_opr = as_metadata_opr(R8); |
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316 R9_metadata_opr = as_metadata_opr(R9); |
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317 R10_metadata_opr = as_metadata_opr(R10); |
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318 R11_metadata_opr = as_metadata_opr(R11); |
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319 R12_metadata_opr = as_metadata_opr(R12); |
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320 //R13_metadata_opr = as_metadata_opr(R13); |
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321 R14_metadata_opr = as_metadata_opr(R14); |
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322 R15_metadata_opr = as_metadata_opr(R15); |
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323 //R16_metadata_opr = as_metadata_opr(R16); |
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324 R17_metadata_opr = as_metadata_opr(R17); |
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325 R18_metadata_opr = as_metadata_opr(R18); |
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326 R19_metadata_opr = as_metadata_opr(R19); |
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327 R20_metadata_opr = as_metadata_opr(R20); |
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328 R21_metadata_opr = as_metadata_opr(R21); |
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329 R22_metadata_opr = as_metadata_opr(R22); |
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330 R23_metadata_opr = as_metadata_opr(R23); |
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331 R24_metadata_opr = as_metadata_opr(R24); |
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332 R25_metadata_opr = as_metadata_opr(R25); |
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333 R26_metadata_opr = as_metadata_opr(R26); |
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334 R27_metadata_opr = as_metadata_opr(R27); |
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335 R28_metadata_opr = as_metadata_opr(R28); |
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336 //R29_metadata_opr = as_metadata_opr(R29); |
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337 R30_metadata_opr = as_metadata_opr(R30); |
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338 R31_metadata_opr = as_metadata_opr(R31); |
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339 |
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340 SP_opr = as_pointer_opr(R1_SP); |
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341 |
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342 R0_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R0), cpu_reg2rnr(R0)); |
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343 R3_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R3), cpu_reg2rnr(R3)); |
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344 |
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345 F1_opr = as_float_opr(F1); |
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346 F1_double_opr = as_double_opr(F1); |
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347 |
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348 // All the allocated cpu regs are caller saved. |
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349 for (int i = 0; i < max_nof_caller_save_cpu_regs; i++) { |
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350 _caller_save_cpu_regs[i] = LIR_OprFact::single_cpu(i); |
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351 } |
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352 |
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353 // All the fpu regs are caller saved. |
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354 for (int i = 0; i < nof_caller_save_fpu_regs; i++) { |
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355 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); |
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356 } |
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357 } |
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358 |
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359 |
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360 Address FrameMap::make_new_address(ByteSize sp_offset) const { |
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361 return Address(R1_SP, STACK_BIAS + in_bytes(sp_offset)); |
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362 } |
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363 |
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364 |
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365 VMReg FrameMap::fpu_regname (int n) { |
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366 return as_FloatRegister(n)->as_VMReg(); |
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367 } |
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368 |
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369 |
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370 LIR_Opr FrameMap::stack_pointer() { |
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371 return SP_opr; |
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372 } |
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373 |
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374 |
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375 // JSR 292 |
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376 // On PPC64, there is no need to save the SP, because neither |
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377 // method handle intrinsics, nor compiled lambda forms modify it. |
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378 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
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379 return LIR_OprFact::illegalOpr; |
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380 } |
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381 |
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382 |
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383 bool FrameMap::validate_frame() { |
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384 int max_offset = in_bytes(framesize_in_bytes()); |
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385 int java_index = 0; |
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386 for (int i = 0; i < _incoming_arguments->length(); i++) { |
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387 LIR_Opr opr = _incoming_arguments->at(i); |
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388 if (opr->is_stack()) { |
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389 max_offset = MAX2(_argument_locations->at(java_index), max_offset); |
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390 } |
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391 java_index += type2size[opr->type()]; |
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392 } |
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393 return Assembler::is_simm16(max_offset + STACK_BIAS); |
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394 } |