3969 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {

  3970   NOT_LP64(assert(VM_Version::supports_sse2(), ""));

  3971   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);

  3972   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);

  3973   emit_int8((unsigned char)0xF5);

  3974   emit_int8((unsigned char)(0xC0 | encode));

  3975 }

  3976 

  3977 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {

  3978   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :

  3979     (vector_len == AVX_256bit ? VM_Version::supports_avx2() :

  3980     (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");

  3981   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);

  3982   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);

  3983   emit_int8((unsigned char)0xF5);

  3984   emit_int8((unsigned char)(0xC0 | encode));

  3985 }

  3986 

  3987 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {

  3988   assert(VM_Version::supports_evex(), "");

  3989   assert(VM_Version::supports_vnni(), "must support vnni");

  3990   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);

  3991   attributes.set_is_evex_instruction();

  3992   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  3993   emit_int8(0x52);

  3994   emit_int8((unsigned char)(0xC0 | encode));

  3995 }

  3996