1 /* |
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2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 package sun.jvm.hotspot.debugger.ia64; |
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26 |
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27 import sun.jvm.hotspot.debugger.*; |
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28 import sun.jvm.hotspot.debugger.cdbg.*; |
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29 |
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30 /** Specifies the thread context on ia64 platform; only a sub-portion |
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31 of the context is guaranteed to be present on all operating |
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32 systems. */ |
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33 |
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34 public abstract class IA64ThreadContext implements ThreadContext { |
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35 // Refer to winnt.h CONTEXT structure - Nov 2001 edition Platform SDK |
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36 // only a relevant subset of CONTEXT structure is used here. |
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37 // For eg. floating point registers are ignored. |
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38 |
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39 // NOTE: the indices for the various registers must be maintained as |
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40 // listed across various operating systems. However, only a |
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41 // subset of the registers' values are guaranteed to be present |
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42 |
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43 // global registers r0-r31 |
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44 public static final int GR0 = 0; |
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45 public static final int GR1 = 1; |
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46 public static final int GR2 = 2; |
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47 public static final int GR3 = 3; |
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48 public static final int GR4 = 4; |
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49 public static final int GR5 = 5; |
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50 public static final int GR6 = 6; |
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51 public static final int GR7 = 7; |
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52 public static final int GR8 = 8; |
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53 public static final int GR9 = 9; |
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54 public static final int GR10 = 10; |
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55 public static final int GR11 = 11; |
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56 public static final int GR12 = 12; |
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57 public static final int SP = GR12; |
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58 public static final int GR13 = 13; |
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59 public static final int GR14 = 14; |
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60 public static final int GR15 = 15; |
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61 public static final int GR16 = 16; |
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62 public static final int GR17 = 17; |
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63 public static final int GR18 = 18; |
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64 public static final int GR19 = 19; |
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65 public static final int GR20 = 20; |
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66 public static final int GR21 = 21; |
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67 public static final int GR22 = 22; |
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68 public static final int GR23 = 23; |
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69 public static final int GR24 = 24; |
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70 public static final int GR25 = 25; |
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71 public static final int GR26 = 26; |
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72 public static final int GR27 = 27; |
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73 public static final int GR28 = 28; |
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74 public static final int GR29 = 29; |
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75 public static final int GR30 = 30; |
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76 public static final int GR31 = 31; |
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77 |
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78 // Nat bits for r1-r31 |
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79 public static final int INT_NATS = 32; |
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80 |
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81 // predicates |
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82 public static final int PREDS = 33; |
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83 |
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84 // branch registers |
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85 public static final int BR0 = 34; |
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86 public static final int BR_RP = BR0; |
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87 public static final int BR1 = 35; |
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88 public static final int BR2 = 36; |
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89 public static final int BR3 = 37; |
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90 public static final int BR4 = 38; |
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91 public static final int BR5 = 39; |
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92 public static final int BR6 = 40; |
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93 public static final int BR7 = 41; |
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94 |
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95 // application registers |
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96 public static final int AP_UNAT = 42; // User Nat Collection register |
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97 public static final int AP_LC = 43; // Loop counter register |
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98 public static final int AP_EC = 43; // Epilog counter register |
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99 public static final int AP_CCV = 45; // CMPXCHG value register |
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100 public static final int AP_DCR = 46; // Default control register |
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101 |
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102 // register stack info |
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103 public static final int RS_PFS = 47; // Previous function state |
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104 public static final int AP_PFS = RS_PFS; |
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105 public static final int RS_BSP = 48; // Backing store pointer |
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106 public static final int AR_BSP = RS_BSP; |
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107 public static final int RS_BSPSTORE = 49; |
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108 public static final int AP_BSPSTORE = RS_BSPSTORE; |
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109 public static final int RS_RSC = 50; // RSE configuration |
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110 public static final int AP_RSC = RS_RSC; |
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111 public static final int RS_RNAT = 51; // RSE Nat collection register |
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112 public static final int AP_RNAT = RS_RNAT; |
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113 |
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114 // trap status register |
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115 public static final int ST_IPSR = 52; // Interuption Processor Status |
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116 public static final int ST_IIP = 53; // Interruption IP |
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117 public static final int ST_IFS = 54; // Interruption Function State |
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118 |
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119 // debug registers |
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120 public static final int DB_I0 = 55; |
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121 public static final int DB_I1 = 56; |
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122 public static final int DB_I2 = 57; |
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123 public static final int DB_I3 = 58; |
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124 public static final int DB_I4 = 59; |
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125 public static final int DB_I5 = 60; |
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126 public static final int DB_I6 = 61; |
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127 public static final int DB_I7 = 62; |
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128 |
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129 public static final int DB_D0 = 63; |
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130 public static final int DB_D1 = 64; |
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131 public static final int DB_D2 = 65; |
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132 public static final int DB_D3 = 66; |
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133 public static final int DB_D4 = 67; |
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134 public static final int DB_D5 = 68; |
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135 public static final int DB_D6 = 69; |
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136 public static final int DB_D7 = 70; |
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137 |
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138 public static final int NPRGREG = 71; |
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139 |
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140 private static final String[] regNames = { |
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141 "GR0", "GR1", "GR2", "GR3", "GR4", "GR5", "GR6", "GR7", "GR8", |
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142 "GR9", "GR10", "GR11", "GR12", "GR13", "GR14", "GR15", "GR16", |
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143 "GR17","GR18", "GR19", "GR20", "GR21", "GR22", "GR23", "GR24", |
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144 "GR25","GR26", "GR27", "GR28", "GR29", "GR30", "GR31", |
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145 "INT_NATS", "PREDS", |
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146 "BR0", "BR1", "BR2", "BR3", "BR4", "BR5", "BR6", "BR7", |
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147 "AP_UNAT", "AP_LC", "AP_EC", "AP_CCV", "AP_DCR", |
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148 "RS_FPS", "RS_BSP", "RS_BSPSTORE", "RS_RSC", "RS_RNAT", |
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149 "ST_IPSR", "ST_IIP", "ST_IFS", |
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150 "DB_I0", "DB_I1", "DB_I2", "DB_I3", "DB_I4", "DB_I5", "DB_I6", "DB_I7", |
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151 "DB_D0", "DB_D1", "DB_D2", "DB_D3", "DB_D4", "DB_D5", "DB_D6", "DB_D7" |
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152 }; |
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153 |
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154 private long[] data; |
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155 |
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156 public IA64ThreadContext() { |
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157 data = new long[NPRGREG]; |
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158 } |
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159 |
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160 public int getNumRegisters() { |
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161 return NPRGREG; |
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162 } |
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163 |
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164 public String getRegisterName(int index) { |
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165 return regNames[index]; |
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166 } |
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167 |
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168 public void setRegister(int index, long value) { |
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169 data[index] = value; |
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170 } |
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171 |
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172 public long getRegister(int index) { |
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173 return data[index]; |
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174 } |
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175 |
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176 public CFrame getTopFrame(Debugger dbg) { |
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177 return null; |
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178 } |
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179 |
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180 /** This can't be implemented in this class since we would have to |
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181 tie the implementation to, for example, the debugging system */ |
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182 public abstract void setRegisterAsAddress(int index, Address value); |
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183 |
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184 /** This can't be implemented in this class since we would have to |
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185 tie the implementation to, for example, the debugging system */ |
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186 public abstract Address getRegisterAsAddress(int index); |
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187 } |
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