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hotspot/src/cpu/sparc/vm/assembler_sparc.hpp
changeset 10027 20cd71f29262
parent 9976 6fef34e63df1
child 10252 0981ce1c3eef
equal deleted inserted replaced
10018:ffb1197de2aa 10027:20cd71f29262 
   714     stdc_op3     = 0x37,
 
   714     stdc_op3     = 0x37,
 
   715 
   715 
   716     casa_op3     = 0x3c,
 
   716     casa_op3     = 0x3c,
 
   717     casxa_op3    = 0x3e,
 
   717     casxa_op3    = 0x3e,
 
   718 
   718 
       
   719     mftoi_op3    = 0x36,
 
       
   720 
   719     alt_bit_op3  = 0x10,
 
   721     alt_bit_op3  = 0x10,
 
   720      cc_bit_op3  = 0x10
 
   722      cc_bit_op3  = 0x10
 
   721   };
 
   723   };
 
   722 
   724 
   723   enum opfs {
 
   725   enum opfs {
 
   748     fitos_opf   = 0xc4,
 
   750     fitos_opf   = 0xc4,
 
   749     fdtos_opf   = 0xc6,
 
   751     fdtos_opf   = 0xc6,
 
   750     fitod_opf   = 0xc8,
 
   752     fitod_opf   = 0xc8,
 
   751     fstod_opf   = 0xc9,
 
   753     fstod_opf   = 0xc9,
 
   752     fstoi_opf   = 0xd1,
 
   754     fstoi_opf   = 0xd1,
 
   753     fdtoi_opf   = 0xd2
 
   755     fdtoi_opf   = 0xd2,
 
       
   756 
       
   757     mdtox_opf   = 0x110,
 
       
   758     mstouw_opf  = 0x111,
 
       
   759     mstosw_opf  = 0x113,
 
       
   760     mxtod_opf   = 0x118,
 
       
   761     mwtos_opf   = 0x119
 
   754   };
 
   762   };
 
   755 
   763 
   756   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };
 
   764   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };
 
   757 
   765 
   758   enum Condition {
 
   766   enum Condition {
 
  1059   // create a low10 __value__ (not a field) for a given a 32-bit constant
 
  1067   // create a low10 __value__ (not a field) for a given a 32-bit constant
 
  1060   static int low10( int x ) {
 
  1068   static int low10( int x ) {
 
  1061     return x & ((1 << 10) - 1);
 
  1069     return x & ((1 << 10) - 1);
 
  1062   }
 
  1070   }
 
  1063 
  1071 
       
  1072   // instruction only in VIS3
 
       
  1073   static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 
       
  1074 
  1064   // instruction only in v9
 
  1075   // instruction only in v9
 
  1065   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
 
  1076   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
 
  1066 
  1077 
  1067   // instruction only in v8
 
  1078   // instruction only in v8
 
  1068   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
 
  1079   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
 
  1245   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
 
  1256   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
 
  1246   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
 
  1257   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
 
  1247 
  1258 
  1248   // pp 159
 
  1259   // pp 159
 
  1249 
  1260 
  1250   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
 
  1261   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
 
  1251   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
 
  1262   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
 
  1252 
  1263 
  1253   // pp 160
 
  1264   // pp 160
 
  1254 
  1265 
  1255   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
 
  1266   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
 
  1256 
  1267 
  1257   // pp 161
 
  1268   // pp 161
 
  1258 
  1269 
  1259   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
 
  1270   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
 
  1260   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
 
  1271   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
 
  1261 
  1272 
  1262   // pp 162
 
  1273   // pp 162
 
  1263 
  1274 
  1264   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
 
  1275   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
 
  1265 
  1276 
  1707                                                                            u_field(1, 13, 13) |
 
  1718                                                                            u_field(1, 13, 13) |
 
  1708                                                                            simm(simm13a, 13)); }
 
  1719                                                                            simm(simm13a, 13)); }
 
  1709   inline void wrasi(  Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
 
  1720   inline void wrasi(  Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
 
  1710   inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
 
  1721   inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
 
  1711 
  1722 
       
  1723 
       
  1724   // VIS3 instructions
 
       
  1725 
       
  1726   void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
 
       
  1727   void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
 
       
  1728   void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
 
       
  1729 
       
  1730   void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
 
       
  1731   void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
 
       
  1732 
       
  1733 
       
  1734 
       
  1735 
  1712   // For a given register condition, return the appropriate condition code
 
  1736   // For a given register condition, return the appropriate condition code
 
  1713   // Condition (the one you would use to get the same effect after "tst" on
 
  1737   // Condition (the one you would use to get the same effect after "tst" on
 
  1714   // the target register.)
 
  1738   // the target register.)
 
  1715   Assembler::Condition reg_cond_to_cc_cond(RCondition in);
 
  1739   Assembler::Condition reg_cond_to_cc_cond(RCondition in);
 
  1716 
  1740
jdk-sandbox