5346 // Shift values for add/sub extension shift

  5347 operand immIExt()

  5348 %{

  5349   predicate(0 <= n->get_int() && (n->get_int() <= 4));

  5350   match(ConI);

  5351 

  5352   op_cost(0);

  5353   format %{ %}

  5354   interface(CONST_INTER);

  5355 %}

  5356 

 13048 

 13049 instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)

 13050 %{

 13051   match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13052   ins_cost(1.9 * INSN_COST);

 13053   format %{ "add  $dst, $src1, $src2, sxtb #lshift2" %}

 13054 

 13055    ins_encode %{

 13056      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13057             as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));

 13058    %}

 13059   ins_pipe(ialu_reg_reg_shift);

 13060 %}

 13061 

 13062 instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)

 13063 %{

 13064   match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13065   ins_cost(1.9 * INSN_COST);

 13066   format %{ "add  $dst, $src1, $src2, sxth #lshift2" %}

 13067 

 13068    ins_encode %{

 13069      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13070             as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));

 13071    %}

 13072   ins_pipe(ialu_reg_reg_shift);

 13073 %}

 13074 

 13075 instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)

 13076 %{

 13077   match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13078   ins_cost(1.9 * INSN_COST);

 13079   format %{ "add  $dst, $src1, $src2, sxtw #lshift2" %}

 13080 

 13081    ins_encode %{

 13082      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13083             as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));

 13084    %}

 13085   ins_pipe(ialu_reg_reg_shift);

 13086 %}

 13087 

 13088 instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)

 13089 %{

 13090   match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13091   ins_cost(1.9 * INSN_COST);

 13092   format %{ "sub  $dst, $src1, $src2, sxtb #lshift2" %}

 13093 

 13094    ins_encode %{

 13095      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13096             as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));

 13097    %}

 13098   ins_pipe(ialu_reg_reg_shift);

 13099 %}

 13100 

 13101 instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)

 13102 %{

 13103   match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13104   ins_cost(1.9 * INSN_COST);

 13105   format %{ "sub  $dst, $src1, $src2, sxth #lshift2" %}

 13106 

 13107    ins_encode %{

 13108      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13109             as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));

 13110    %}

 13111   ins_pipe(ialu_reg_reg_shift);

 13112 %}

 13113 

 13114 instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)

 13115 %{

 13116   match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));

 13117   ins_cost(1.9 * INSN_COST);

 13118   format %{ "sub  $dst, $src1, $src2, sxtw #lshift2" %}

 13119 

 13120    ins_encode %{

 13121      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13122             as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));

 13123    %}

 13124   ins_pipe(ialu_reg_reg_shift);

 13125 %}

 13126 

 13127 instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)

 13128 %{

 13129   match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));

 13130   ins_cost(1.9 * INSN_COST);

 13131   format %{ "addw  $dst, $src1, $src2, sxtb #lshift2" %}

 13132 

 13133    ins_encode %{

 13134      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),

 13135             as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));

 13136    %}

 13137   ins_pipe(ialu_reg_reg_shift);

 13138 %}

 13139 

 13140 instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)

 13141 %{

 13142   match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));

 13143   ins_cost(1.9 * INSN_COST);

 13144   format %{ "addw  $dst, $src1, $src2, sxth #lshift2" %}

 13145 

 13146    ins_encode %{

 13147      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),

 13148             as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));

 13149    %}

 13150   ins_pipe(ialu_reg_reg_shift);

 13151 %}

 13152 

 13153 instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)

 13154 %{

 13155   match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));

 13156   ins_cost(1.9 * INSN_COST);

 13157   format %{ "subw  $dst, $src1, $src2, sxtb #lshift2" %}

 13158 

 13159    ins_encode %{

 13160      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),

 13161             as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));

 13162    %}

 13163   ins_pipe(ialu_reg_reg_shift);

 13164 %}

 13165 

 13166 instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)

 13167 %{

 13168   match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));

 13169   ins_cost(1.9 * INSN_COST);

 13170   format %{ "subw  $dst, $src1, $src2, sxth #lshift2" %}

 13171 

 13172    ins_encode %{

 13173      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),

 13174             as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));

 13175    %}

 13176   ins_pipe(ialu_reg_reg_shift);

 13177 %}

 13178 

 13179 

 13180 instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)

 13181 %{

 13182   match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));

 13183   ins_cost(1.9 * INSN_COST);

 13184   format %{ "add  $dst, $src1, $src2, sxtw #lshift" %}

 13185 

 13186    ins_encode %{

 13187      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13188             as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));

 13189    %}

 13190   ins_pipe(ialu_reg_reg_shift);

 13191 %};

 13192 

 13193 instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)

 13194 %{

 13195   match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));

 13196   ins_cost(1.9 * INSN_COST);

 13197   format %{ "sub  $dst, $src1, $src2, sxtw #lshift" %}

 13198 

 13199    ins_encode %{

 13200      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13201             as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));

 13202    %}

 13203   ins_pipe(ialu_reg_reg_shift);

 13204 %};

 13205 

 13206 

 13207 instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)

 13208 %{

 13209   match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));

 13210   ins_cost(1.9 * INSN_COST);

 13211   format %{ "add  $dst, $src1, $src2, uxtb #lshift" %}

 13212 

 13213    ins_encode %{

 13214      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13215             as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));

 13216    %}

 13217   ins_pipe(ialu_reg_reg_shift);

 13218 %}

 13219 

 13220 instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)

 13221 %{

 13222   match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));

 13223   ins_cost(1.9 * INSN_COST);

 13224   format %{ "add  $dst, $src1, $src2, uxth #lshift" %}

 13225 

 13226    ins_encode %{

 13227      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13228             as_Register($src2$$reg), ext::uxth, ($lshift$$constant));

 13229    %}

 13230   ins_pipe(ialu_reg_reg_shift);

 13231 %}

 13232 

 13233 instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)

 13234 %{

 13235   match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));

 13236   ins_cost(1.9 * INSN_COST);

 13237   format %{ "add  $dst, $src1, $src2, uxtw #lshift" %}

 13238 

 13239    ins_encode %{

 13240      __ add(as_Register($dst$$reg), as_Register($src1$$reg),

 13241             as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));

 13242    %}

 13243   ins_pipe(ialu_reg_reg_shift);

 13244 %}

 13245 

 13246 instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)

 13247 %{

 13248   match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));

 13249   ins_cost(1.9 * INSN_COST);

 13250   format %{ "sub  $dst, $src1, $src2, uxtb #lshift" %}

 13251 

 13252    ins_encode %{

 13253      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13254             as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));

 13255    %}

 13256   ins_pipe(ialu_reg_reg_shift);

 13257 %}

 13258 

 13259 instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)

 13260 %{

 13261   match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));

 13262   ins_cost(1.9 * INSN_COST);

 13263   format %{ "sub  $dst, $src1, $src2, uxth #lshift" %}

 13264 

 13265    ins_encode %{

 13266      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13267             as_Register($src2$$reg), ext::uxth, ($lshift$$constant));

 13268    %}

 13269   ins_pipe(ialu_reg_reg_shift);

 13270 %}

 13271 

 13272 instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)

 13273 %{

 13274   match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));

 13275   ins_cost(1.9 * INSN_COST);

 13276   format %{ "sub  $dst, $src1, $src2, uxtw #lshift" %}

 13277 

 13278    ins_encode %{

 13279      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),

 13280             as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));

 13281    %}

 13282   ins_pipe(ialu_reg_reg_shift);

 13283 %}

 13284 

 13285 instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)

 13286 %{

 13287   match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));

 13288   ins_cost(1.9 * INSN_COST);

 13289   format %{ "addw  $dst, $src1, $src2, uxtb #lshift" %}

 13290 

 13291    ins_encode %{

 13292      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),

 13293             as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));

 13294    %}

 13295   ins_pipe(ialu_reg_reg_shift);

 13296 %}

 13297 

 13298 instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)

 13299 %{

 13300   match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));

 13301   ins_cost(1.9 * INSN_COST);

 13302   format %{ "addw  $dst, $src1, $src2, uxth #lshift" %}

 13303 

 13304    ins_encode %{

 13305      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),

 13306             as_Register($src2$$reg), ext::uxth, ($lshift$$constant));

 13307    %}

 13308   ins_pipe(ialu_reg_reg_shift);

 13309 %}

 13310 

 13311 instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)

 13312 %{

 13313   match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));

 13314   ins_cost(1.9 * INSN_COST);

 13315   format %{ "subw  $dst, $src1, $src2, uxtb #lshift" %}

 13316 

 13317    ins_encode %{

 13318      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),

 13319             as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));

 13320    %}

 13321   ins_pipe(ialu_reg_reg_shift);

 13322 %}

 13323 

 13324 instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)

 13325 %{

 13326   match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));

 13327   ins_cost(1.9 * INSN_COST);

 13328   format %{ "subw  $dst, $src1, $src2, uxth #lshift" %}

 13329 

 13330    ins_encode %{

 13331      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),

 13332             as_Register($src2$$reg), ext::uxth, ($lshift$$constant));

 13333    %}

 13334   ins_pipe(ialu_reg_reg_shift);

 13335 %}