hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
author twisti
Wed, 16 Nov 2011 01:39:50 -0800
changeset 11190 d561d41f241a
parent 10976 04322f78fd46
child 11430 718fc06da49a
child 11409 6e4f4db7908e
permissions -rw-r--r--
7003454: order constants in constant table by number of references in code Reviewed-by: kvn, never, bdelsart
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/*
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 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "c1/c1_Compilation.hpp"
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#include "c1/c1_LIRAssembler.hpp"
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#include "c1/c1_MacroAssembler.hpp"
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#include "c1/c1_Runtime1.hpp"
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#include "c1/c1_ValueStack.hpp"
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#include "ci/ciArrayKlass.hpp"
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#include "ci/ciInstance.hpp"
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#include "gc_interface/collectedHeap.hpp"
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#include "memory/barrierSet.hpp"
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#include "memory/cardTableModRefBS.hpp"
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#include "nativeInst_sparc.hpp"
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#include "oops/objArrayKlass.hpp"
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#include "runtime/sharedRuntime.hpp"
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#define __ _masm->
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//------------------------------------------------------------
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bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
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  if (opr->is_constant()) {
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    LIR_Const* constant = opr->as_constant_ptr();
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    switch (constant->type()) {
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      case T_INT: {
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        jint value = constant->as_jint();
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        return Assembler::is_simm13(value);
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      }
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      default:
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        return false;
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    }
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  }
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  return false;
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}
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bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
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  switch (op->code()) {
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    case lir_null_check:
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    return true;
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    case lir_add:
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    case lir_ushr:
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    case lir_shr:
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    case lir_shl:
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      // integer shifts and adds are always one instruction
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      return op->result_opr()->is_single_cpu();
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    case lir_move: {
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      LIR_Op1* op1 = op->as_Op1();
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      LIR_Opr src = op1->in_opr();
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      LIR_Opr dst = op1->result_opr();
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      if (src == dst) {
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        NEEDS_CLEANUP;
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        // this works around a problem where moves with the same src and dst
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        // end up in the delay slot and then the assembler swallows the mov
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        // since it has no effect and then it complains because the delay slot
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        // is empty.  returning false stops the optimizer from putting this in
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        // the delay slot
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        return false;
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      }
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      // don't put moves involving oops into the delay slot since the VerifyOops code
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      // will make it much larger than a single instruction.
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      if (VerifyOops) {
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        return false;
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      }
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      if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
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          ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
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        return false;
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      }
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      if (UseCompressedOops) {
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        if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
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        if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
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      }
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      if (dst->is_register()) {
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        if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
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          return !PatchALot;
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        } else if (src->is_single_stack()) {
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          return true;
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        }
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      }
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      if (src->is_register()) {
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        if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
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          return !PatchALot;
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        } else if (dst->is_single_stack()) {
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          return true;
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        }
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      }
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      if (dst->is_register() &&
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          ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
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           (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
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        return true;
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      }
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      return false;
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    }
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    default:
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      return false;
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  }
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  ShouldNotReachHere();
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}
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LIR_Opr LIR_Assembler::receiverOpr() {
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  return FrameMap::O0_oop_opr;
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}
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LIR_Opr LIR_Assembler::osrBufferPointer() {
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  return FrameMap::I0_opr;
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}
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int LIR_Assembler::initial_frame_size_in_bytes() {
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  return in_bytes(frame_map()->framesize_in_bytes());
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}
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// inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
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// we fetch the class of the receiver (O0) and compare it with the cached class.
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// If they do not match we jump to slow case.
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int LIR_Assembler::check_icache() {
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  int offset = __ offset();
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  __ inline_cache_check(O0, G5_inline_cache_reg);
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  return offset;
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}
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void LIR_Assembler::osr_entry() {
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  // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
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  //
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  //   1. Create a new compiled activation.
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  //   2. Initialize local variables in the compiled activation.  The expression stack must be empty
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  //      at the osr_bci; it is not initialized.
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  //   3. Jump to the continuation address in compiled code to resume execution.
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  // OSR entry point
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  offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
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  BlockBegin* osr_entry = compilation()->hir()->osr_entry();
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  ValueStack* entry_state = osr_entry->end()->state();
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  int number_of_locks = entry_state->locks_size();
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  // Create a frame for the compiled activation.
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  __ build_frame(initial_frame_size_in_bytes());
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  // OSR buffer is
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  //
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  // locals[nlocals-1..0]
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  // monitors[number_of_locks-1..0]
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  //
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  // locals is a direct copy of the interpreter frame so in the osr buffer
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  // so first slot in the local array is the last local from the interpreter
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  // and last slot is local[0] (receiver) from the interpreter
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  //
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  // Similarly with locks. The first lock slot in the osr buffer is the nth lock
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  // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
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  // in the interpreter frame (the method lock if a sync method)
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   194
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  // Initialize monitors in the compiled activation.
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  //   I0: pointer to osr buffer
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  //
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  // All other registers are dead at this point and the locals will be
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  // copied into place by code emitted in the IR.
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   200
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  Register OSR_buf = osrBufferPointer()->as_register();
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  { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
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    int monitor_offset = BytesPerWord * method()->max_locals() +
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      (2 * BytesPerWord) * (number_of_locks - 1);
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    // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
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    // the OSR buffer using 2 word entries: first the lock and then
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    // the oop.
1
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    for (int i = 0; i < number_of_locks; i++) {
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      int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
1
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#ifdef ASSERT
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      // verify the interpreter's monitor has a non-null object
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      {
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        Label L;
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        __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
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        __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
1
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        __ stop("locked object is NULL");
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        __ bind(L);
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   218
      }
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#endif // ASSERT
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      // Copy the lock field into the compiled activation.
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      __ ld_ptr(OSR_buf, slot_offset + 0, O7);
1
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      __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
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      __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
1
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      __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
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   225
    }
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   226
  }
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   227
}
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   228
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   229
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// Optimized Library calls
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// This is the fast version of java.lang.String.compare; it has not
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   232
// OSR-entry and therefore, we generate a slow version for OSR's
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   233
void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
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  Register str0 = left->as_register();
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   235
  Register str1 = right->as_register();
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   236
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  Label Ldone;
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   238
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   239
  Register result = dst->as_register();
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   240
  {
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    // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
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    // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
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    // Also, get string0.count-string1.count in o7 and get the condition code set
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    // Note: some instructions have been hoisted for better instruction scheduling
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   245
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    Register tmp0 = L0;
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   247
    Register tmp1 = L1;
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    Register tmp2 = L2;
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   249
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   250
    int  value_offset = java_lang_String:: value_offset_in_bytes(); // char array
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   251
    int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
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    int  count_offset = java_lang_String:: count_offset_in_bytes();
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   253
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    __ load_heap_oop(str0, value_offset, tmp0);
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    __ ld(str0, offset_offset, tmp2);
1
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    __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
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    __ ld(str0, count_offset, str0);
1
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   258
    __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
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   259
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    // str1 may be null
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   261
    add_debug_info_for_null_check_here(info);
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   262
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    __ load_heap_oop(str1, value_offset, tmp1);
1
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   264
    __ add(tmp0, tmp2, tmp0);
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   265
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    __ ld(str1, offset_offset, tmp2);
1
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    __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
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    __ ld(str1, count_offset, str1);
1
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   269
    __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
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   270
    __ subcc(str0, str1, O7);
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   271
    __ add(tmp1, tmp2, tmp1);
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  }
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   273
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   274
  {
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   275
    // Compute the minimum of the string lengths, scale it and store it in limit
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    Register count0 = I0;
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   277
    Register count1 = I1;
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   278
    Register limit  = L3;
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   279
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   280
    Label Lskip;
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   281
    __ sll(count0, exact_log2(sizeof(jchar)), limit);             // string0 is shorter
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   282
    __ br(Assembler::greater, true, Assembler::pt, Lskip);
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   283
    __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit);  // string1 is shorter
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   284
    __ bind(Lskip);
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   285
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   286
    // If either string is empty (or both of them) the result is the difference in lengths
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   287
    __ cmp(limit, 0);
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   288
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
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   289
    __ delayed()->mov(O7, result);  // result is difference in lengths
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   290
  }
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   291
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   292
  {
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   293
    // Neither string is empty
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   294
    Label Lloop;
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   295
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   296
    Register base0 = L0;
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   297
    Register base1 = L1;
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   298
    Register chr0  = I0;
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   299
    Register chr1  = I1;
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   300
    Register limit = L3;
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   301
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   302
    // Shift base0 and base1 to the end of the arrays, negate limit
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   303
    __ add(base0, limit, base0);
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   304
    __ add(base1, limit, base1);
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   305
    __ neg(limit);  // limit = -min{string0.count, strin1.count}
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   306
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   307
    __ lduh(base0, limit, chr0);
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   308
    __ bind(Lloop);
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   309
    __ lduh(base1, limit, chr1);
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   310
    __ subcc(chr0, chr1, chr0);
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   311
    __ br(Assembler::notZero, false, Assembler::pn, Ldone);
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   312
    assert(chr0 == result, "result must be pre-placed");
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   313
    __ delayed()->inccc(limit, sizeof(jchar));
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   314
    __ br(Assembler::notZero, true, Assembler::pt, Lloop);
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   315
    __ delayed()->lduh(base0, limit, chr0);
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   316
  }
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   317
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   318
  // If strings are equal up to min length, return the length difference.
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   319
  __ mov(O7, result);
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   320
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   321
  // Otherwise, return the difference between the first mismatched chars.
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   322
  __ bind(Ldone);
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   323
}
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   324
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   325
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   326
// --------------------------------------------------------------------------------------------
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   327
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   328
void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
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   329
  if (!GenerateSynchronizationCode) return;
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   330
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   331
  Register obj_reg = obj_opr->as_register();
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   332
  Register lock_reg = lock_opr->as_register();
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   333
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   334
  Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
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   335
  Register reg = mon_addr.base();
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   336
  int offset = mon_addr.disp();
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   337
  // compute pointer to BasicLock
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   338
  if (mon_addr.is_simm13()) {
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   339
    __ add(reg, offset, lock_reg);
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   340
  }
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   341
  else {
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   342
    __ set(offset, lock_reg);
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   343
    __ add(reg, lock_reg, lock_reg);
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   344
  }
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   345
  // unlock object
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   346
  MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
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   347
  // _slow_case_stubs->append(slow_case);
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   348
  // temporary fix: must be created after exceptionhandler, therefore as call stub
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   349
  _slow_case_stubs->append(slow_case);
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   350
  if (UseFastLocking) {
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   351
    // try inlined fast unlocking first, revert to slow locking if it fails
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   352
    // note: lock_reg points to the displaced header since the displaced header offset is 0!
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   353
    assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
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   354
    __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
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   355
  } else {
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   356
    // always do slow unlocking
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   357
    // note: the slow unlocking code could be inlined here, however if we use
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   358
    //       slow unlocking, speed doesn't matter anyway and this solution is
489c9b5090e2 Initial load
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   359
    //       simpler and requires less duplicated code - additionally, the
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   360
    //       slow unlocking code is the same in either case which simplifies
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   361
    //       debugging
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   362
    __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
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   363
    __ delayed()->nop();
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   364
  }
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   365
  // done
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   366
  __ bind(*slow_case->continuation());
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   367
}
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   368
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   369
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   370
int LIR_Assembler::emit_exception_handler() {
1
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   371
  // if the last instruction is a call (typically to do a throw which
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   372
  // is coming at the end after block reordering) the return address
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   373
  // must still point into the code area in order to avoid assertion
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   374
  // failures when searching for the corresponding bci => add a nop
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   375
  // (was bug 5/14/1999 - gri)
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   376
  __ nop();
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   377
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   378
  // generate code for exception handler
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   379
  ciMethod* method = compilation()->method();
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   380
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   381
  address handler_base = __ start_a_stub(exception_handler_size);
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duke
parents:
diff changeset
   382
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
  if (handler_base == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
    // not enough space left for the handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
   385
    bailout("exception handler overflow");
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   386
    return -1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
  }
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   388
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
  int offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
8495
a4959965eaa3 7012914: JSR 292 MethodHandlesTest C1: frame::verify_return_pc(return_address) failed: must be a return pc
twisti
parents: 7883
diff changeset
   391
  __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
  __ delayed()->nop();
8495
a4959965eaa3 7012914: JSR 292 MethodHandlesTest C1: frame::verify_return_pc(return_address) failed: must be a return pc
twisti
parents: 7883
diff changeset
   393
  __ should_not_reach_here();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
  assert(code_offset() - offset <= exception_handler_size, "overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
  __ end_a_stub();
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   396
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   397
  return offset;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   398
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   400
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   401
// Emit the code to remove the frame from the stack in the exception
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   402
// unwind path.
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   403
int LIR_Assembler::emit_unwind_handler() {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   404
#ifndef PRODUCT
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   405
  if (CommentedAssembly) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   406
    _masm->block_comment("Unwind handler");
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   407
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   408
#endif
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   409
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   410
  int offset = code_offset();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   411
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   412
  // Fetch the exception from TLS and clear out exception related thread state
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   413
  __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   414
  __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   415
  __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   416
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   417
  __ bind(_unwind_handler_entry);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   418
  __ verify_not_null_oop(O0);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   419
  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   420
    __ mov(O0, I0);  // Preserve the exception
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   421
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   422
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   423
  // Preform needed unlocking
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   424
  MonitorExitStub* stub = NULL;
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   425
  if (method()->is_synchronized()) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   426
    monitor_address(0, FrameMap::I1_opr);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   427
    stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   428
    __ unlock_object(I3, I2, I1, *stub->entry());
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   429
    __ bind(*stub->continuation());
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   430
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   431
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   432
  if (compilation()->env()->dtrace_method_probes()) {
6756
01ac7b1701eb 6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
never
parents: 6461
diff changeset
   433
    __ mov(G2_thread, O0);
01ac7b1701eb 6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
never
parents: 6461
diff changeset
   434
    jobject2reg(method()->constant_encoding(), O1);
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   435
    __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   436
    __ delayed()->nop();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   437
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   438
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   439
  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   440
    __ mov(I0, O0);  // Restore the exception
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   441
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   442
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   443
  // dispatch to the unwind logic
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   444
  __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   445
  __ delayed()->nop();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   446
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   447
  // Emit the slow path assembly
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   448
  if (stub != NULL) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   449
    stub->emit_code(this);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   450
  }
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   451
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   452
  return offset;
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   453
}
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   454
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
   455
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   456
int LIR_Assembler::emit_deopt_handler() {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
  // if the last instruction is a call (typically to do a throw which
489c9b5090e2 Initial load
duke
parents:
diff changeset
   458
  // is coming at the end after block reordering) the return address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
  // must still point into the code area in order to avoid assertion
489c9b5090e2 Initial load
duke
parents:
diff changeset
   460
  // failures when searching for the corresponding bci => add a nop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   461
  // (was bug 5/14/1999 - gri)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   462
  __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
489c9b5090e2 Initial load
duke
parents:
diff changeset
   464
  // generate code for deopt handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
  ciMethod* method = compilation()->method();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
  address handler_base = __ start_a_stub(deopt_handler_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
  if (handler_base == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
    // not enough space left for the handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
    bailout("deopt handler overflow");
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   470
    return -1;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   471
  }
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   472
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
  int offset = code_offset();
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   474
  AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   475
  __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
  __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
  assert(code_offset() - offset <= deopt_handler_size, "overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
  debug_only(__ stop("should have gone to the caller");)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
  __ end_a_stub();
4752
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   480
67a506670cd0 6921352: JSR 292 needs its own deopt handler
twisti
parents: 4749
diff changeset
   481
  return offset;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
void LIR_Assembler::jobject2reg(jobject o, Register reg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
  if (o == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
    __ set(NULL_WORD, reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
    int oop_index = __ oop_recorder()->find_index(o);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
    RelocationHolder rspec = oop_Relocation::spec(oop_index);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
    __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
  // Allocate a new index in oop table to hold the oop once it's been patched
489c9b5090e2 Initial load
duke
parents:
diff changeset
   498
  int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   501
  AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   502
  assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
  // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
  // NULL will be dynamically patched later and the patched value may be large.  We must
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
  // therefore generate the sethi/add as a placeholders
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   506
  __ patchable_set(addrlit, reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
  patching_epilog(patch, lir_patch_normal, reg, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
void LIR_Assembler::emit_op3(LIR_Op3* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
  Register Rdividend = op->in_opr1()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
  Register Rdivisor  = noreg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
  Register Rscratch  = op->in_opr3()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
  Register Rresult   = op->result_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
  int divisor = -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
  if (op->in_opr2()->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
    Rdivisor = op->in_opr2()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
    divisor = op->in_opr2()->as_constant_ptr()->as_jint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
    assert(Assembler::is_simm13(divisor), "can only handle simm13");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
  assert(Rdividend != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
  assert(Rdivisor  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
  assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
  if (Rdivisor == noreg && is_power_of_2(divisor)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
    // convert division by a power of two into some shifts and logical operations
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
    if (op->code() == lir_idiv) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
      if (divisor == 2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
        __ srl(Rdividend, 31, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
        __ sra(Rdividend, 31, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
        __ and3(Rscratch, divisor - 1, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
      __ add(Rdividend, Rscratch, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
      __ sra(Rscratch, log2_intptr(divisor), Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
      return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
      if (divisor == 2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
        __ srl(Rdividend, 31, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
        __ sra(Rdividend, 31, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
        __ and3(Rscratch, divisor - 1,Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
      __ add(Rdividend, Rscratch, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
      __ andn(Rscratch, divisor - 1,Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
      __ sub(Rdividend, Rscratch, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
      return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
  __ sra(Rdividend, 31, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
  __ wry(Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
  if (!VM_Version::v9_instructions_work()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
    // v9 doesn't require these nops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
  add_debug_info_for_div0_here(op->info());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
  if (Rdivisor != noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
    __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
    assert(Assembler::is_simm13(divisor), "can only handle simm13");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
    __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
  Label skip;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
  __ br(Assembler::overflowSet, true, Assembler::pn, skip);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
  __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
  __ bind(skip);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
  if (op->code() == lir_irem) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
    if (Rdivisor != noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
      __ smul(Rscratch, Rdivisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
      __ smul(Rscratch, divisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
    __ sub(Rdividend, Rscratch, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
  assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
  if (op->block() != NULL)  _branch_target_blocks.append(op->block());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
  if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
  assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
  if (op->cond() == lir_cond_always) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
    __ br(Assembler::always, false, Assembler::pt, *(op->label()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
  } else if (op->code() == lir_cond_float_branch) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
    assert(op->ublock() != NULL, "must have unordered successor");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
    bool is_unordered = (op->ublock() == op->block());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
    Assembler::Condition acond;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
    switch (op->cond()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
      case lir_cond_equal:         acond = Assembler::f_equal;    break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
      case lir_cond_notEqual:      acond = Assembler::f_notEqual; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
      case lir_cond_less:          acond = (is_unordered ? Assembler::f_unorderedOrLess          : Assembler::f_less);           break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
      case lir_cond_greater:       acond = (is_unordered ? Assembler::f_unorderedOrGreater       : Assembler::f_greater);        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
      case lir_cond_lessEqual:     acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual   : Assembler::f_lessOrEqual);    break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
      case lir_cond_greaterEqual:  acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
      default :                         ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
    };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
    if (!VM_Version::v9_instructions_work()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
      __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   618
    __ fb( acond, false, Assembler::pn, *(op->label()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   619
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
    assert (op->code() == lir_branch, "just checking");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
    Assembler::Condition acond;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
    switch (op->cond()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
      case lir_cond_equal:        acond = Assembler::equal;                break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
      case lir_cond_notEqual:     acond = Assembler::notEqual;             break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
      case lir_cond_less:         acond = Assembler::less;                 break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   627
      case lir_cond_lessEqual:    acond = Assembler::lessEqual;            break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   628
      case lir_cond_greaterEqual: acond = Assembler::greaterEqual;         break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   629
      case lir_cond_greater:      acond = Assembler::greater;              break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   630
      case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   631
      case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;    break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
      default:                         ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
    };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
    // sparc has different condition codes for testing 32-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
    // vs. 64-bit values.  We could always test xcc is we could
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
    // guarantee that 32-bit loads always sign extended but that isn't
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
    // true and since sign extension isn't free, it would impose a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
    // slight cost.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
    if  (op->type() == T_INT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
      __ br(acond, false, Assembler::pn, *(op->label()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
    } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
      __ brx(acond, false, Assembler::pn, *(op->label()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
  // The peephole pass fills the delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
  Bytecodes::Code code = op->bytecode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  LIR_Opr dst = op->result_opr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
  switch(code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
    case Bytecodes::_i2l: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
      Register rlo  = dst->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
      Register rhi  = dst->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
      Register rval = op->in_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
      __ sra(rval, 0, rlo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
      __ mov(rval, rlo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
      __ sra(rval, BitsPerInt-1, rhi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   667
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
    case Bytecodes::_i2d:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
    case Bytecodes::_i2f: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
      bool is_double = (code == Bytecodes::_i2d);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
      FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
      FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
      FloatRegister rsrc = op->in_opr()->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
      if (rsrc != rdst) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
        __ fmov(FloatRegisterImpl::S, rsrc, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
      __ fitof(w, rdst, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
    case Bytecodes::_f2i:{
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
      FloatRegister rsrc = op->in_opr()->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
      Address       addr = frame_map()->address_for_slot(dst->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
      Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
      // result must be 0 if value is NaN; test by comparing value to itself
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
      __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
      if (!VM_Version::v9_instructions_work()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
        __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
      __ fb(Assembler::f_unordered, true, Assembler::pn, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
      __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
      __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
      // move integer result from float register to int register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
      __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
      __ bind (L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
    case Bytecodes::_l2i: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
      Register rlo  = op->in_opr()->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
      Register rhi  = op->in_opr()->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
      Register rdst = dst->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
      __ sra(rlo, 0, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
      __ mov(rlo, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
    case Bytecodes::_d2f:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
    case Bytecodes::_f2d: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
      bool is_double = (code == Bytecodes::_f2d);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
      assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
      LIR_Opr val = op->in_opr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
      FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
      FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
      FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
      FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
      __ ftof(vw, dw, rval, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
    case Bytecodes::_i2s:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
    case Bytecodes::_i2b: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
      Register rval = op->in_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
      Register rdst = dst->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
      int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
      __ sll (rval, shift, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
      __ sra (rdst, shift, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
    case Bytecodes::_i2c: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
      Register rval = op->in_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
      Register rdst = dst->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
      int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
      __ sll (rval, shift, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
      __ srl (rdst, shift, rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
    default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   740
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   741
489c9b5090e2 Initial load
duke
parents:
diff changeset
   742
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
void LIR_Assembler::align_call(LIR_Code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
  // do nothing since all instructions are word aligned on sparc
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   748
void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   749
  __ call(op->addr(), rtype);
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
   750
  // The peephole pass fills the delay slot, add_call_info is done in
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
   751
  // LIR_Assembler::emit_delay.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   755
void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
  RelocationHolder rspec = virtual_call_Relocation::spec(pc());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
  __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
  __ relocate(rspec);
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   759
  __ call(op->addr(), relocInfo::none);
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
   760
  // The peephole pass fills the delay slot, add_call_info is done in
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
   761
  // LIR_Assembler::emit_delay.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   765
void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   766
  add_debug_info_for_null_check_here(op->info());
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   767
  __ load_klass(O0, G3_scratch);
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10976
diff changeset
   768
  if (Assembler::is_simm13(op->vtable_offset())) {
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   769
    __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
    // This will generate 2 instructions
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4898
diff changeset
   772
    __ set(op->vtable_offset(), G5_method);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
    // ld_ptr, set_hi, set
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
    __ ld_ptr(G3_scratch, G5_method, G5_method);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
  }
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   776
  __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
  __ callr(G3_scratch, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
  // the peephole pass fills the delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   781
int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
  int store_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
  if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
    assert(!unaligned, "can't handle this");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
    // for offsets larger than a simm13 we setup the offset in O7
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   786
    __ set(offset, O7);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   787
    store_offset = store(from_reg, base, O7, type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
  } else {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   789
    if (type == T_ARRAY || type == T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   790
      __ verify_oop(from_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   791
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
    store_offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
    switch (type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
      case T_BOOLEAN: // fall through
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
      case T_BYTE  : __ stb(from_reg->as_register(), base, offset); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
      case T_CHAR  : __ sth(from_reg->as_register(), base, offset); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
      case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
      case T_INT   : __ stw(from_reg->as_register(), base, offset); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
      case T_LONG  :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
        if (unaligned || PatchALot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
          __ srax(from_reg->as_register_lo(), 32, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
          __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
          __ stw(O7,                         base, offset + hi_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
          __ stx(from_reg->as_register_lo(), base, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
        assert(Assembler::is_simm13(offset + 4), "must be");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
        __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
        __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
        break;
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   814
      case T_ADDRESS:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   815
        __ st_ptr(from_reg->as_register(), base, offset);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   816
        break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
      case T_ARRAY : // fall through
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   818
      case T_OBJECT:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   819
        {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   820
          if (UseCompressedOops && !wide) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   821
            __ encode_heap_oop(from_reg->as_register(), G3_scratch);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   822
            store_offset = code_offset();
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   823
            __ stw(G3_scratch, base, offset);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   824
          } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   825
            __ st_ptr(from_reg->as_register(), base, offset);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   826
          }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   827
          break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   828
        }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   829
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
      case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
      case T_DOUBLE:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
        {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
          FloatRegister reg = from_reg->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
          // split unaligned stores
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
          if (unaligned || PatchALot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
            assert(Assembler::is_simm13(offset + 4), "must be");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
            __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
            __ stf(FloatRegisterImpl::S, reg,              base, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
          } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
            __ stf(FloatRegisterImpl::D, reg, base, offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
      default      : ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   846
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   847
  return store_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   851
int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   852
  if (type == T_ARRAY || type == T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   853
    __ verify_oop(from_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   854
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
  int store_offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
  switch (type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
    case T_BOOLEAN: // fall through
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
    case T_BYTE  : __ stb(from_reg->as_register(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
    case T_CHAR  : __ sth(from_reg->as_register(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
    case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
    case T_INT   : __ stw(from_reg->as_register(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
    case T_LONG  :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
      __ stx(from_reg->as_register_lo(), base, disp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
      assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
      __ std(from_reg->as_register_hi(), base, disp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
      break;
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   870
    case T_ADDRESS:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   871
      __ st_ptr(from_reg->as_register(), base, disp);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   872
      break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
    case T_ARRAY : // fall through
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   874
    case T_OBJECT:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   875
      {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   876
        if (UseCompressedOops && !wide) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   877
          __ encode_heap_oop(from_reg->as_register(), G3_scratch);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   878
          store_offset = code_offset();
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   879
          __ stw(G3_scratch, base, disp);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   880
        } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   881
          __ st_ptr(from_reg->as_register(), base, disp);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   882
        }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   883
        break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   884
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
    case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
    case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
    default      : ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
  return store_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   893
int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   894
  int load_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
  if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
    assert(base != O7, "destroying register");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
    assert(!unaligned, "can't handle this");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
    // for offsets larger than a simm13 we setup the offset in O7
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
   899
    __ set(offset, O7);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   900
    load_offset = load(base, O7, to_reg, type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
    load_offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
    switch(type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
      case T_BOOLEAN: // fall through
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
      case T_BYTE  : __ ldsb(base, offset, to_reg->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
      case T_CHAR  : __ lduh(base, offset, to_reg->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   907
      case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
      case T_INT   : __ ld(base, offset, to_reg->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
      case T_LONG  :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
        if (!unaligned) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
          __ ldx(base, offset, to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
          assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
                 "must be sequential");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
          __ ldd(base, offset, to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
          assert(base != to_reg->as_register_lo(), "can't handle this");
4430
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 3908
diff changeset
   921
          assert(O7 != to_reg->as_register_lo(), "can't handle this");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
          __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
4430
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 3908
diff changeset
   923
          __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
          __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
4430
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 3908
diff changeset
   925
          __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
          if (base == to_reg->as_register_lo()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
            __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
            __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
          } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   931
            __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   932
            __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   933
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   934
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   935
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
        break;
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   937
      case T_ADDRESS:  __ ld_ptr(base, offset, to_reg->as_register()); break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
      case T_ARRAY : // fall through
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   939
      case T_OBJECT:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   940
        {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   941
          if (UseCompressedOops && !wide) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   942
            __ lduw(base, offset, to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   943
            __ decode_heap_oop(to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   944
          } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   945
            __ ld_ptr(base, offset, to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   946
          }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   947
          break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   948
        }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
      case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
      case T_DOUBLE:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
        {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
          FloatRegister reg = to_reg->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
          // split unaligned loads
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
          if (unaligned || PatchALot) {
4430
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 3908
diff changeset
   955
            __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 3908
diff changeset
   956
            __ ldf(FloatRegisterImpl::S, base, offset,     reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
          } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
            __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   962
      default      : ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
    }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   964
    if (type == T_ARRAY || type == T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   965
      __ verify_oop(to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   966
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
  return load_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   972
int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
  int load_offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
  switch(type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
    case T_BOOLEAN: // fall through
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   976
    case T_BYTE  :  __ ldsb(base, disp, to_reg->as_register()); break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   977
    case T_CHAR  :  __ lduh(base, disp, to_reg->as_register()); break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   978
    case T_SHORT :  __ ldsh(base, disp, to_reg->as_register()); break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   979
    case T_INT   :  __ ld(base, disp, to_reg->as_register()); break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   980
    case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
    case T_ARRAY : // fall through
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   982
    case T_OBJECT:
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   983
      {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   984
          if (UseCompressedOops && !wide) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   985
            __ lduw(base, disp, to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   986
            __ decode_heap_oop(to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   987
          } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   988
            __ ld_ptr(base, disp, to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   989
          }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   990
          break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
   991
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
    case T_FLOAT:  __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
    case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
    case T_LONG  :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
      __ ldx(base, disp, to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
      assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
             "must be sequential");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
      __ ldd(base, disp, to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
    default      : ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
  }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1005
  if (type == T_ARRAY || type == T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1006
    __ verify_oop(to_reg->as_register());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1007
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
  return load_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1010
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
  LIR_Const* c = src->as_constant_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
  switch (c->type()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
    case T_INT:
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1015
    case T_FLOAT: {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1016
      Register src_reg = O7;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1017
      int value = c->as_jint_bits();
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1018
      if (value == 0) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1019
        src_reg = G0;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1020
      } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1021
        __ set(value, O7);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1022
      }
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1023
      Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1024
      __ stw(src_reg, addr.base(), addr.disp());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1025
      break;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1026
    }
5048
c31b6243f37e 6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents: 5046
diff changeset
  1027
    case T_ADDRESS: {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
      Register src_reg = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
      int value = c->as_jint_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
      if (value == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
        src_reg = G0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
        __ set(value, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
      Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1036
      __ st_ptr(src_reg, addr.base(), addr.disp());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1038
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
    case T_OBJECT: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
      Register src_reg = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
      jobject2reg(c->as_jobject(), src_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
      Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
      __ st_ptr(src_reg, addr.base(), addr.disp());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
    case T_LONG:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1047
    case T_DOUBLE: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1048
      Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1050
      Register tmp = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1051
      int value_lo = c->as_jint_lo_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1052
      if (value_lo == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
        tmp = G0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
        __ set(value_lo, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
      __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1058
      int value_hi = c->as_jint_hi_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
      if (value_hi == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
        tmp = G0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
        __ set(value_hi, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
      __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1065
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
    default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1068
      Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1070
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1073
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1074
  LIR_Const* c = src->as_constant_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1075
  LIR_Address* addr     = dest->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1076
  Register base = addr->base()->as_pointer_register();
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1077
  int offset = -1;
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1078
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1079
  switch (c->type()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1080
    case T_INT:
5048
c31b6243f37e 6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents: 5046
diff changeset
  1081
    case T_FLOAT:
c31b6243f37e 6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents: 5046
diff changeset
  1082
    case T_ADDRESS: {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1083
      LIR_Opr tmp = FrameMap::O7_opr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1084
      int value = c->as_jint_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
      if (value == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1086
        tmp = FrameMap::G0_opr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1087
      } else if (Assembler::is_simm13(value)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1088
        __ set(value, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1089
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
      if (addr->index()->is_valid()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
        assert(addr->disp() == 0, "must be zero");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1092
        offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
        assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1095
        offset = store(tmp, base, addr->disp(), type, wide, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
    case T_LONG:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
    case T_DOUBLE: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
      assert(!addr->index()->is_valid(), "can't handle reg reg address here");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
      assert(Assembler::is_simm13(addr->disp()) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
             Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1105
      LIR_Opr tmp = FrameMap::O7_opr;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
      int value_lo = c->as_jint_lo_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
      if (value_lo == 0) {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1108
        tmp = FrameMap::G0_opr;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
        __ set(value_lo, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
      }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1112
      offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
      int value_hi = c->as_jint_hi_bits();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
      if (value_hi == 0) {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1115
        tmp = FrameMap::G0_opr;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
        __ set(value_hi, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
      }
10976
04322f78fd46 7103261: crash with jittester on sparc
never
parents: 10508
diff changeset
  1119
      store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1122
    case T_OBJECT: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1123
      jobject obj = c->as_jobject();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
      LIR_Opr tmp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
      if (obj == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
        tmp = FrameMap::G0_opr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
        tmp = FrameMap::O7_opr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
        jobject2reg(c->as_jobject(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
      // handle either reg+reg or reg+disp address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
      if (addr->index()->is_valid()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
        assert(addr->disp() == 0, "must be zero");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1134
        offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
        assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1137
        offset = store(tmp, base, addr->disp(), type, wide, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1138
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1141
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1142
    default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
      Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
  }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1145
  if (info != NULL) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1146
    assert(offset != -1, "offset should've been set");
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1147
    add_debug_info_for_null_check(offset, info);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1148
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
  LIR_Const* c = src->as_constant_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
  LIR_Opr to_reg = dest;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
  switch (c->type()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
    case T_INT:
5048
c31b6243f37e 6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents: 5046
diff changeset
  1158
    case T_ADDRESS:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
        jint con = c->as_jint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
        if (to_reg->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
          assert(patch_code == lir_patch_none, "no patching handled here");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
          __ set(con, to_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
          assert(to_reg->is_single_fpu(), "wrong register kind");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
          __ set(con, O7);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1169
          Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1170
          __ st(O7, temp_slot);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1171
          __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1172
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1173
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1174
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1175
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
    case T_LONG:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1177
      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
        jlong con = c->as_jlong();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
        if (to_reg->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
          __ set(con,  to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
          __ set(low(con),  to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
          __ set(high(con), to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
        } else if (to_reg->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
          __ set(con, to_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
          assert(to_reg->is_double_fpu(), "wrong register kind");
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1194
          Address temp_slot_lo(SP, ((frame::register_save_words  ) * wordSize) + STACK_BIAS);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1195
          Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1196
          __ set(low(con),  O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1197
          __ st(O7, temp_slot_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
          __ set(high(con), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
          __ st(O7, temp_slot_hi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
          __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1204
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1205
    case T_OBJECT:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
        if (patch_code == lir_patch_none) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
          jobject2reg(c->as_jobject(), to_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1209
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
          jobject2reg_with_patching(to_reg->as_register(), info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1211
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1212
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
    case T_FLOAT:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
        address const_addr = __ float_constant(c->as_jfloat());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
        if (const_addr == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
          bailout("const section overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
        RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1223
        AddressLiteral const_addrlit(const_addr, rspec);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
        if (to_reg->is_single_fpu()) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1225
          __ patchable_sethi(const_addrlit, O7);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
          __ relocate(rspec);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1227
          __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1229
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
          assert(to_reg->is_single_cpu(), "Must be a cpu register.");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1232
          __ set(const_addrlit, O7);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1233
          __ ld(O7, 0, to_reg->as_register());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1237
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
    case T_DOUBLE:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
      {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1240
        address const_addr = __ double_constant(c->as_jdouble());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
        if (const_addr == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
          bailout("const section overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
        RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
        if (to_reg->is_double_fpu()) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1248
          AddressLiteral const_addrlit(const_addr, rspec);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1249
          __ patchable_sethi(const_addrlit, O7);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
          __ relocate(rspec);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1251
          __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
          assert(to_reg->is_double_cpu(), "Must be a long register.");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1255
          __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1256
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1257
          __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
          __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
    default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1270
Address LIR_Assembler::as_Address(LIR_Address* addr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1271
  Register reg = addr->base()->as_register();
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1272
  return Address(reg, addr->disp());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1273
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
  switch (type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
    case T_INT:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
    case T_FLOAT: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
      Register tmp = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
      Address from = frame_map()->address_for_slot(src->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1282
      Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1283
      __ lduw(from.base(), from.disp(), tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1284
      __ stw(tmp, to.base(), to.disp());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1285
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1287
    case T_OBJECT: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
      Register tmp = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
      Address from = frame_map()->address_for_slot(src->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
      Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
      __ ld_ptr(from.base(), from.disp(), tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
      __ st_ptr(tmp, to.base(), to.disp());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
    case T_LONG:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
    case T_DOUBLE: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
      Register tmp = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
      Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
      Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1300
      __ lduw(from.base(), from.disp(), tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1301
      __ stw(tmp, to.base(), to.disp());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1302
      __ lduw(from.base(), from.disp() + 4, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
      __ stw(tmp, to.base(), to.disp() + 4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1304
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
    default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1308
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1309
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
  Address base = as_Address(addr);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1315
  return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
  Address base = as_Address(addr);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1321
  return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1326
                            LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
  LIR_Address* addr = src_opr->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
  LIR_Opr to_reg = dest;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
  Register src = addr->base()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1332
  Register disp_reg = noreg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
  int disp_value = addr->disp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
  bool needs_patching = (patch_code != lir_patch_none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1335
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1336
  if (addr->base()->type() == T_OBJECT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
    __ verify_oop(src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
  PatchingStub* patch = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1341
  if (needs_patching) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
    patch = new PatchingStub(_masm, PatchingStub::access_field_id);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
    assert(!to_reg->is_double_cpu() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
           patch_code == lir_patch_none ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
           patch_code == lir_patch_normal, "patching doesn't match register");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1346
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1347
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1348
  if (addr->index()->is_illegal()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
    if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
      if (needs_patching) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1351
        __ patchable_set(0, O7);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1352
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1353
        __ set(disp_value, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
      disp_reg = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1356
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1357
  } else if (unaligned || PatchALot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1358
    __ add(src, addr->index()->as_register(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1359
    src = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1360
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
    disp_reg = addr->index()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
    assert(disp_value == 0, "can't handle 3 operand addresses");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1363
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1365
  // remember the offset of the load.  The patching_epilog must be done
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
  // before the call to add_debug_info, otherwise the PcDescs don't get
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1367
  // entered in increasing order.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1368
  int offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1369
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
  assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
  if (disp_reg == noreg) {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1372
    offset = load(src, disp_value, to_reg, type, wide, unaligned);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
    assert(!unaligned, "can't handle this");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1375
    offset = load(src, disp_reg, to_reg, type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1376
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
  if (patch != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
    patching_epilog(patch, patch_code, src, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1380
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1381
  if (info != NULL) add_debug_info_for_null_check(offset, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1382
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1383
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
void LIR_Assembler::prefetchr(LIR_Opr src) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
  LIR_Address* addr = src->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
  Address from_addr = as_Address(addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
  if (VM_Version::has_v9()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
    __ prefetch(from_addr, Assembler::severalReads);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
void LIR_Assembler::prefetchw(LIR_Opr src) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
  LIR_Address* addr = src->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
  Address from_addr = as_Address(addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
  if (VM_Version::has_v9()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
    __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1401
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1403
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
  Address addr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
  if (src->is_single_word()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
    addr = frame_map()->address_for_slot(src->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
  } else if (src->is_double_word())  {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
    addr = frame_map()->address_for_double_slot(src->double_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
  bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1414
  load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1416
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1417
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
  Address addr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
  if (dest->is_single_word()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
    addr = frame_map()->address_for_slot(dest->single_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
  } else if (dest->is_double_word())  {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
    addr = frame_map()->address_for_slot(dest->double_stack_ix());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1425
  bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1426
  store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1427
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
  if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1432
    if (from_reg->is_double_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
      // double to double moves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1434
      assert(to_reg->is_double_fpu(), "should match");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1435
      __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
      // float to float moves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
      assert(to_reg->is_single_fpu(), "should match");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1439
      __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1440
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1441
  } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
    if (from_reg->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
      __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1445
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1446
      assert(to_reg->is_double_cpu() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1447
             from_reg->as_register_hi() != to_reg->as_register_lo() &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1448
             from_reg->as_register_lo() != to_reg->as_register_hi(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1449
             "should both be long and not overlap");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1450
      // long to long moves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1451
      __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1452
      __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1453
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1454
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1455
    } else if (to_reg->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1456
      // int to int moves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1457
      __ mov(from_reg->as_register(), to_reg->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1458
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1459
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
      // int to int moves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1461
      __ mov(from_reg->as_register(), to_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1462
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1463
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1464
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1465
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1466
  if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1467
    __ verify_oop(to_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1468
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1469
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
                            LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1474
                            bool wide, bool unaligned) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1475
  LIR_Address* addr = dest->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1476
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
  Register src = addr->base()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
  Register disp_reg = noreg;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
  int disp_value = addr->disp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
  bool needs_patching = (patch_code != lir_patch_none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
  if (addr->base()->is_oop_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
    __ verify_oop(src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
  PatchingStub* patch = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
  if (needs_patching) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
    patch = new PatchingStub(_masm, PatchingStub::access_field_id);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
    assert(!from_reg->is_double_cpu() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
           patch_code == lir_patch_none ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
           patch_code == lir_patch_normal, "patching doesn't match register");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
  if (addr->index()->is_illegal()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
    if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1496
      if (needs_patching) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1497
        __ patchable_set(0, O7);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
        __ set(disp_value, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
      disp_reg = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
  } else if (unaligned || PatchALot) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
    __ add(src, addr->index()->as_register(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
    src = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
    disp_reg = addr->index()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
    assert(disp_value == 0, "can't handle 3 operand addresses");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
  // remember the offset of the store.  The patching_epilog must be done
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
  // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
  // entered in increasing order.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
  int offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
  assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
  if (disp_reg == noreg) {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1518
    offset = store(from_reg, src, disp_value, type, wide, unaligned);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1519
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1520
    assert(!unaligned, "can't handle this");
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  1521
    offset = store(from_reg, src, disp_reg, type, wide);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1523
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
  if (patch != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1525
    patching_epilog(patch, patch_code, src, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1526
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1527
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
  if (info != NULL) add_debug_info_for_null_check(offset, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1532
void LIR_Assembler::return_op(LIR_Opr result) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1533
  // the poll may need a register so just pick one that isn't the return register
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1534
#if defined(TIERED) && !defined(_LP64)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
  if (result->type_field() == LIR_OprDesc::long_type) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
    // Must move the result to G1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
    // Must leave proper result in O0,O1 and G1 (TIERED only)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
    __ sllx(I0, 32, G1);          // Shift bits into high G1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
    __ srl (I1, 0, I1);           // Zero extend O1 (harmless?)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
    __ or3 (I1, G1, G1);          // OR 64 bits into G1
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1541
#ifdef ASSERT
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1542
    // mangle it so any problems will show up
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1543
    __ set(0xdeadbeef, I0);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1544
    __ set(0xdeadbeef, I1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  1545
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
#endif // TIERED
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
  __ set((intptr_t)os::get_polling_page(), L0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1549
  __ relocate(relocInfo::poll_return_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
  __ ld_ptr(L0, 0, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
  __ ret();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
  __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
  __ set((intptr_t)os::get_polling_page(), tmp->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
  if (info != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
    add_debug_info_for_branch(info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
    __ relocate(relocInfo::poll_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1564
  int offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
  __ ld_ptr(tmp->as_register(), 0, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1566
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1567
  return offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1570
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1571
void LIR_Assembler::emit_static_call_stub() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1572
  address call_pc = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1573
  address stub = __ start_a_stub(call_stub_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
  if (stub == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
    bailout("static call stub overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
    return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1577
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1578
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
  int start = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
  __ relocate(static_stub_Relocation::spec(call_pc));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
  __ set_oop(NULL, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1583
  // must be set to -1 at code generation time
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1584
  AddressLiteral addrlit(-1);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  1585
  __ jump_to(addrlit, G3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1586
  __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1587
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1588
  assert(__ offset() - start <= call_stub_size, "stub too big");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
  __ end_a_stub();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1590
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1591
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1592
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1593
void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1594
  if (opr1->is_single_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
    __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
  } else if (opr1->is_double_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
    __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
  } else if (opr1->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1599
    if (opr2->is_constant()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1600
      switch (opr2->as_constant_ptr()->type()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1601
        case T_INT:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1602
          { jint con = opr2->as_constant_ptr()->as_jint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
            if (Assembler::is_simm13(con)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
              __ cmp(opr1->as_register(), con);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1605
            } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
              __ set(con, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
              __ cmp(opr1->as_register(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
        case T_OBJECT:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
          // there are only equal/notequal comparisions on objects
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1614
          { jobject con = opr2->as_constant_ptr()->as_jobject();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1615
            if (con == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1616
              __ cmp(opr1->as_register(), 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1617
            } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1618
              jobject2reg(con, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1619
              __ cmp(opr1->as_register(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1620
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1621
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1623
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1624
        default:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1626
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1627
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
      if (opr2->is_address()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
        LIR_Address * addr = opr2->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
        BasicType type = addr->type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1632
        if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
        else                    __ ld(as_Address(addr), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
        __ cmp(opr1->as_register(), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1636
        __ cmp(opr1->as_register(), opr2->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1638
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1639
  } else if (opr1->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1640
    Register xlo = opr1->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
    Register xhi = opr1->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
    if (opr2->is_constant() && opr2->as_jlong() == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1643
      assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1644
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1645
      __ orcc(xhi, G0, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1646
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1647
      __ orcc(xhi, xlo, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1648
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1649
    } else if (opr2->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1650
      Register ylo = opr2->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1651
      Register yhi = opr2->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1653
      __ cmp(xlo, ylo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1654
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1655
      __ subcc(xlo, ylo, xlo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
      __ subccc(xhi, yhi, xhi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1657
      if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
        __ orcc(xhi, xlo, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1661
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1662
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1663
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
  } else if (opr1->is_address()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1665
    LIR_Address * addr = opr1->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1666
    BasicType type = addr->type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1667
    assert (opr2->is_constant(), "Checking");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1668
    if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1669
    else                    __ ld(as_Address(addr), O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1670
    __ cmp(O7, opr2->as_constant_ptr()->as_jint());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1671
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1672
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1673
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1674
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1675
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1676
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1677
void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1678
  if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1679
    bool is_unordered_less = (code == lir_ucmp_fd2i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1680
    if (left->is_single_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1681
      __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1682
    } else if (left->is_double_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1683
      __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1684
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1685
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1686
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1687
  } else if (code == lir_cmp_l2i) {
5253
d2c37eee9a65 6942223: c1 64 bit fixes
iveresov
parents: 5249
diff changeset
  1688
#ifdef _LP64
d2c37eee9a65 6942223: c1 64 bit fixes
iveresov
parents: 5249
diff changeset
  1689
    __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
d2c37eee9a65 6942223: c1 64 bit fixes
iveresov
parents: 5249
diff changeset
  1690
#else
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1691
    __ lcmp(left->as_register_hi(),  left->as_register_lo(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1692
            right->as_register_hi(), right->as_register_lo(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1693
            dst->as_register());
5253
d2c37eee9a65 6942223: c1 64 bit fixes
iveresov
parents: 5249
diff changeset
  1694
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1695
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1696
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1697
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1699
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1700
7713
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1701
void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1702
  Assembler::Condition acond;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
  switch (condition) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1704
    case lir_cond_equal:        acond = Assembler::equal;        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
    case lir_cond_notEqual:     acond = Assembler::notEqual;     break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
    case lir_cond_less:         acond = Assembler::less;         break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1707
    case lir_cond_lessEqual:    acond = Assembler::lessEqual;    break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1708
    case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
    case lir_cond_greater:      acond = Assembler::greater;      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
    case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned;      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
    case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
    default:                         ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
  if (opr1->is_constant() && opr1->type() == T_INT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1716
    Register dest = result->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1717
    // load up first part of constant before branch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1718
    // and do the rest in the delay slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1719
    if (!Assembler::is_simm13(opr1->as_jint())) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1720
      __ sethi(opr1->as_jint(), dest);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1721
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1722
  } else if (opr1->is_constant()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
    const2reg(opr1, result, lir_patch_none, NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1724
  } else if (opr1->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1725
    reg2reg(opr1, result);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1726
  } else if (opr1->is_stack()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1727
    stack2reg(opr1, result, result->type());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1728
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1729
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1730
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1731
  Label skip;
7713
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1732
#ifdef _LP64
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1733
    if  (type == T_INT) {
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1734
      __ br(acond, false, Assembler::pt, skip);
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1735
    } else
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1736
#endif
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  1737
      __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1738
  if (opr1->is_constant() && opr1->type() == T_INT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1739
    Register dest = result->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1740
    if (Assembler::is_simm13(opr1->as_jint())) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1741
      __ delayed()->or3(G0, opr1->as_jint(), dest);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1742
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1743
      // the sethi has been done above, so just put in the low 10 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1744
      __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1745
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1746
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1747
    // can't do anything useful in the delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1748
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1749
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1750
  if (opr2->is_constant()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1751
    const2reg(opr2, result, lir_patch_none, NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1752
  } else if (opr2->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1753
    reg2reg(opr2, result);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1754
  } else if (opr2->is_stack()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1755
    stack2reg(opr2, result, result->type());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1756
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1757
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1758
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1759
  __ bind(skip);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1760
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1761
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1762
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1763
void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1764
  assert(info == NULL, "unused on this code path");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1765
  assert(left->is_register(), "wrong items state");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1766
  assert(dest->is_register(), "wrong items state");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1768
  if (right->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
    if (dest->is_float_kind()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1771
      FloatRegister lreg, rreg, res;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1772
      FloatRegisterImpl::Width w;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1773
      if (right->is_single_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1774
        w = FloatRegisterImpl::S;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1775
        lreg = left->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
        rreg = right->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
        res  = dest->as_float_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1779
        w = FloatRegisterImpl::D;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1780
        lreg = left->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1781
        rreg = right->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1782
        res  = dest->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1783
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1784
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1785
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1786
        case lir_add: __ fadd(w, lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1787
        case lir_sub: __ fsub(w, lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1788
        case lir_mul: // fall through
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
        case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
        case lir_div: // fall through
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
        case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1794
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1795
    } else if (dest->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1796
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1797
      Register dst_lo = dest->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1798
      Register op1_lo = left->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1799
      Register op2_lo = right->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
        case lir_add:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
          __ add(op1_lo, op2_lo, dst_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
        case lir_sub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
          __ sub(op1_lo, op2_lo, dst_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
      Register op1_lo = left->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
      Register op1_hi = left->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
      Register op2_lo = right->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
      Register op2_hi = right->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
      Register dst_lo = dest->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1818
      Register dst_hi = dest->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1820
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1821
        case lir_add:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
          __ addcc(op1_lo, op2_lo, dst_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
          __ addc (op1_hi, op2_hi, dst_hi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
        case lir_sub:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
          __ subcc(op1_lo, op2_lo, dst_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
          __ subc (op1_hi, op2_hi, dst_hi);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1831
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1832
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1833
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1834
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1835
      assert (right->is_single_cpu(), "Just Checking");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1836
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1837
      Register lreg = left->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
      Register res  = dest->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
      Register rreg = right->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
        case lir_add:  __ add  (lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1842
        case lir_sub:  __ sub  (lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1843
        case lir_mul:  __ mult (lreg, rreg, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1846
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1847
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1848
    assert (right->is_constant(), "must be constant");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1849
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1850
    if (dest->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1851
      Register lreg = left->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1852
      Register res  = dest->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
      int    simm13 = right->as_constant_ptr()->as_jint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1854
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1855
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1856
        case lir_add:  __ add  (lreg, simm13, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1857
        case lir_sub:  __ sub  (lreg, simm13, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
        case lir_mul:  __ mult (lreg, simm13, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1859
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
      Register lreg = left->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
      Register res  = dest->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1864
      long con = right->as_constant_ptr()->as_jlong();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
      assert(Assembler::is_simm13(con), "must be simm13");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1866
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
        case lir_add:  __ add  (lreg, (int)con, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
        case lir_sub:  __ sub  (lreg, (int)con, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1870
        case lir_mul:  __ mult (lreg, (int)con, res); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1871
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1875
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1876
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1877
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
void LIR_Assembler::fpop() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1879
  // do nothing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1881
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1883
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1884
  switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1885
    case lir_sin:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1886
    case lir_tan:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
    case lir_cos: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
      assert(thread->is_valid(), "preserve the thread object for performance reasons");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1889
      assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1891
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1892
    case lir_sqrt: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1893
      assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1894
      FloatRegister src_reg = value->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
      FloatRegister dst_reg = dest->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
      __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1897
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1898
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1899
    case lir_abs: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1900
      assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1901
      FloatRegister src_reg = value->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1902
      FloatRegister dst_reg = dest->as_double_reg();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1903
      __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1904
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1905
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
    default: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
      ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1908
      break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1913
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1914
void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1915
  if (right->is_constant()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1916
    if (dest->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1917
      int simm13 = right->as_constant_ptr()->as_jint();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1918
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1919
        case lir_logic_and:   __ and3 (left->as_register(), simm13, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1920
        case lir_logic_or:    __ or3  (left->as_register(), simm13, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1921
        case lir_logic_xor:   __ xor3 (left->as_register(), simm13, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1922
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1923
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1924
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1925
      long c = right->as_constant_ptr()->as_jlong();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1926
      assert(c == (int)c && Assembler::is_simm13(c), "out of range");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1927
      int simm13 = (int)c;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1928
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1929
        case lir_logic_and:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1930
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1931
          __ and3 (left->as_register_hi(), 0,      dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1932
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1933
          __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1934
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1935
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1936
        case lir_logic_or:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1937
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1938
          __ or3 (left->as_register_hi(), 0,      dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1939
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1940
          __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1941
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1942
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1943
        case lir_logic_xor:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1944
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1945
          __ xor3 (left->as_register_hi(), 0,      dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1946
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1947
          __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1948
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1949
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1951
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1952
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1953
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1954
    assert(right->is_register(), "right should be in register");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1955
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1956
    if (dest->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1957
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1958
        case lir_logic_and:   __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1959
        case lir_logic_or:    __ or3  (left->as_register(), right->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1960
        case lir_logic_xor:   __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1961
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1962
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1963
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1964
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1965
      Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1966
                                                                        left->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1967
      Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1968
                                                                          right->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1969
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1970
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1971
        case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1972
        case lir_logic_or:  __ or3  (l, r, dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1973
        case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1976
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1977
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
        case lir_logic_and:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1979
          __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
          __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1981
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1983
        case lir_logic_or:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1984
          __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1985
          __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1986
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1987
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1988
        case lir_logic_xor:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
          __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1990
          __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
          break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1992
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1993
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1994
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1998
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1999
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
int LIR_Assembler::shift_amount(BasicType t) {
202
dc13bf0e5d5d 6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents: 1
diff changeset
  2002
  int elem_size = type2aelembytes(t);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
  switch (elem_size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
    case 1 : return 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2005
    case 2 : return 1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
    case 4 : return 2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
    case 8 : return 3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
  return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2013
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2014
void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2015
  assert(exceptionOop->as_register() == Oexception, "should match");
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2016
  assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2017
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2018
  info->add_register_oop(exceptionOop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2019
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2020
  // reuse the debug info from the safepoint poll for the throw op itself
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2021
  address pc_for_athrow  = __ pc();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2022
  int pc_for_athrow_offset = __ offset();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2023
  RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2024
  __ set(pc_for_athrow, Oissuing_pc, rspec);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2025
  add_call_info(pc_for_athrow_offset, info); // for exception handler
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2026
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2027
  __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2028
  __ delayed()->nop();
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2029
}
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2030
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2031
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2032
void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2033
  assert(exceptionOop->as_register() == Oexception, "should match");
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2034
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2035
  __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2036
  __ delayed()->nop();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2038
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2039
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
  Register src = op->src()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2042
  Register dst = op->dst()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2043
  Register src_pos = op->src_pos()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2044
  Register dst_pos = op->dst_pos()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2045
  Register length  = op->length()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2046
  Register tmp = op->tmp()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2047
  Register tmp2 = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2048
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
  int flags = op->flags();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2050
  ciArrayKlass* default_type = op->expected_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2051
  BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2052
  if (basic_type == T_ARRAY) basic_type = T_OBJECT;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2053
9105
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2054
#ifdef _LP64
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2055
  // higher 32bits must be null
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2056
  __ sra(dst_pos, 0, dst_pos);
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2057
  __ sra(src_pos, 0, src_pos);
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2058
  __ sra(length, 0, length);
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2059
#endif
afc81a03564f 7033732: C1: When calling c2 arraycopy stubs offsets and length must have clear upper 32bits
iveresov
parents: 9102
diff changeset
  2060
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2061
  // set up the arraycopy stub information
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2062
  ArrayCopyStub* stub = op->stub();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2064
  // always do stub if no type information is available.  it's ok if
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2065
  // the known type isn't loaded since the code sanity checks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2066
  // in debug mode and the type isn't required when we know the exact type
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2067
  // also check that the type is an array type.
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2068
  if (op->expected_type() == NULL) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2069
    __ mov(src,     O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2070
    __ mov(src_pos, O1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2071
    __ mov(dst,     O2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
    __ mov(dst_pos, O3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
    __ mov(length,  O4);
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2074
    address copyfunc_addr = StubRoutines::generic_arraycopy();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2075
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2076
    if (copyfunc_addr == NULL) { // Use C version if stub was not generated
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2077
      __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2078
    } else {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2079
#ifndef PRODUCT
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2080
      if (PrintC1Statistics) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2081
        address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2082
        __ inc_counter(counter, G1, G3);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2083
      }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2084
#endif
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2085
      __ call_VM_leaf(tmp, copyfunc_addr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2086
    }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2087
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2088
    if (copyfunc_addr != NULL) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2089
      __ xor3(O0, -1, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2090
      __ sub(length, tmp, length);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2091
      __ add(src_pos, tmp, src_pos);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2092
      __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2093
      __ delayed()->add(dst_pos, tmp, dst_pos);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2094
    } else {
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2095
      __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2096
      __ delayed()->nop();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2097
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2098
    __ bind(*stub->continuation());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2099
    return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2100
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2101
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
  assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2104
  // make sure src and dst are non-null and load array length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
  if (flags & LIR_OpArrayCopy::src_null_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2106
    __ tst(src);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2107
    __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2108
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
  if (flags & LIR_OpArrayCopy::dst_null_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2112
    __ tst(dst);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2113
    __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2114
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2115
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2116
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2117
  if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2118
    // test src_pos register
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2119
    __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2123
  if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2124
    // test dst_pos register
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2125
    __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2126
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2127
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2128
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
  if (flags & LIR_OpArrayCopy::length_positive_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2130
    // make sure length isn't negative
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2131
    __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2132
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2133
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2134
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2135
  if (flags & LIR_OpArrayCopy::src_range_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2136
    __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2137
    __ add(length, src_pos, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
    __ cmp(tmp2, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
    __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2140
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2141
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2142
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2143
  if (flags & LIR_OpArrayCopy::dst_range_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2144
    __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2145
    __ add(length, dst_pos, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2146
    __ cmp(tmp2, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2147
    __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2148
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2149
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2150
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2151
  int shift = shift_amount(basic_type);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2152
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2153
  if (flags & LIR_OpArrayCopy::type_check) {
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2154
    // We don't know the array types are compatible
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2155
    if (basic_type != T_OBJECT) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2156
      // Simple test for basic type arrays
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2157
      if (UseCompressedOops) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2158
        // We don't need decode because we just need to compare
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2159
        __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2160
        __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2161
        __ cmp(tmp, tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2162
        __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2163
      } else {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2164
        __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2165
        __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2166
        __ cmp(tmp, tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2167
        __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2168
      }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2169
      __ delayed()->nop();
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2170
    } else {
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2171
      // For object arrays, if src is a sub class of dst then we can
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2172
      // safely do the copy.
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2173
      address copyfunc_addr = StubRoutines::checkcast_arraycopy();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2174
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2175
      Label cont, slow;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2176
      assert_different_registers(tmp, tmp2, G3, G1);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2177
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2178
      __ load_klass(src, G3);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2179
      __ load_klass(dst, G1);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2180
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2181
      __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2182
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2183
      __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2184
      __ delayed()->nop();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2185
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2186
      __ cmp(G3, 0);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2187
      if (copyfunc_addr != NULL) { // use stub if available
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2188
        // src is not a sub class of dst so we have to do a
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2189
        // per-element check.
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2190
        __ br(Assembler::notEqual, false, Assembler::pt, cont);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2191
        __ delayed()->nop();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2192
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2193
        __ bind(slow);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2194
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2195
        int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2196
        if ((flags & mask) != mask) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2197
          // Check that at least both of them object arrays.
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2198
          assert(flags & mask, "one of the two should be known to be an object array");
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2199
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2200
          if (!(flags & LIR_OpArrayCopy::src_objarray)) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2201
            __ load_klass(src, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2202
          } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2203
            __ load_klass(dst, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2204
          }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2205
          int lh_offset = klassOopDesc::header_size() * HeapWordSize +
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2206
            Klass::layout_helper_offset_in_bytes();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2207
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2208
          __ lduw(tmp, lh_offset, tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2209
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2210
          jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2211
          __ set(objArray_lh, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2212
          __ cmp(tmp, tmp2);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2213
          __ br(Assembler::notEqual, false, Assembler::pt,  *stub->entry());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2214
          __ delayed()->nop();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2215
        }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2216
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2217
        Register src_ptr = O0;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2218
        Register dst_ptr = O1;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2219
        Register len     = O2;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2220
        Register chk_off = O3;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2221
        Register super_k = O4;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2222
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2223
        __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2224
        if (shift == 0) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2225
          __ add(src_ptr, src_pos, src_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2226
        } else {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2227
          __ sll(src_pos, shift, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2228
          __ add(src_ptr, tmp, src_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2229
        }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2230
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2231
        __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2232
        if (shift == 0) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2233
          __ add(dst_ptr, dst_pos, dst_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2234
        } else {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2235
          __ sll(dst_pos, shift, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2236
          __ add(dst_ptr, tmp, dst_ptr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2237
        }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2238
        __ mov(length, len);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2239
        __ load_klass(dst, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2240
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2241
        int ek_offset = (klassOopDesc::header_size() * HeapWordSize +
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2242
                         objArrayKlass::element_klass_offset_in_bytes());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2243
        __ ld_ptr(tmp, ek_offset, super_k);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2244
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2245
        int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2246
                          Klass::super_check_offset_offset_in_bytes());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2247
        __ lduw(super_k, sco_offset, chk_off);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2248
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2249
        __ call_VM_leaf(tmp, copyfunc_addr);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2250
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2251
#ifndef PRODUCT
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2252
        if (PrintC1Statistics) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2253
          Label failed;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2254
          __ br_notnull_short(O0, Assembler::pn, failed);
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2255
          __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2256
          __ bind(failed);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2257
        }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2258
#endif
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2259
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2260
        __ br_null(O0, false, Assembler::pt,  *stub->continuation());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2261
        __ delayed()->xor3(O0, -1, tmp);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2262
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2263
#ifndef PRODUCT
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2264
        if (PrintC1Statistics) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2265
          __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2266
        }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2267
#endif
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2268
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2269
        __ sub(length, tmp, length);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2270
        __ add(src_pos, tmp, src_pos);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2271
        __ br(Assembler::always, false, Assembler::pt, *stub->entry());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2272
        __ delayed()->add(dst_pos, tmp, dst_pos);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2273
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2274
        __ bind(cont);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2275
      } else {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2276
        __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2277
        __ delayed()->nop();
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2278
        __ bind(cont);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2279
      }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2280
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2281
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2282
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2283
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2284
  if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2285
    // Sanity check the known type with the incoming class.  For the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2286
    // primitive case the types must match exactly with src.klass and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2287
    // dst.klass each exactly matching the default type.  For the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2288
    // object array case, if no type check is needed then either the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2289
    // dst type is exactly the expected type and the src type is a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2290
    // subtype which we can't check or src is the same array as dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2291
    // but not necessarily exactly of type default_type.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2292
    Label known_ok, halt;
3908
24b55ad4c228 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 2867
diff changeset
  2293
    jobject2reg(op->expected_type()->constant_encoding(), tmp);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2294
    if (UseCompressedOops) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2295
      // tmp holds the default type. It currently comes uncompressed after the
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2296
      // load of a constant, so encode it.
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2297
      __ encode_heap_oop(tmp);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2298
      // load the raw value of the dst klass, since we will be comparing
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2299
      // uncompressed values directly.
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2300
      __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2301
      if (basic_type != T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2302
        __ cmp(tmp, tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2303
        __ br(Assembler::notEqual, false, Assembler::pn, halt);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2304
        // load the raw value of the src klass.
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2305
        __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2306
        __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2307
      } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2308
        __ cmp(tmp, tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2309
        __ br(Assembler::equal, false, Assembler::pn, known_ok);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2310
        __ delayed()->cmp(src, dst);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2311
        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2312
        __ delayed()->nop();
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2313
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
    } else {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2315
      __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2316
      if (basic_type != T_OBJECT) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2317
        __ cmp(tmp, tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2318
        __ brx(Assembler::notEqual, false, Assembler::pn, halt);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2319
        __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2320
        __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2321
      } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2322
        __ cmp(tmp, tmp2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2323
        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2324
        __ delayed()->cmp(src, dst);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2325
        __ brx(Assembler::equal, false, Assembler::pn, known_ok);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2326
        __ delayed()->nop();
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2327
      }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2329
    __ bind(halt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2330
    __ stop("incorrect type information in arraycopy");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
    __ bind(known_ok);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2334
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2335
#ifndef PRODUCT
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2336
  if (PrintC1Statistics) {
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2337
    address counter = Runtime1::arraycopy_count_address(basic_type);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2338
    __ inc_counter(counter, G1, G3);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2339
  }
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2340
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2341
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
  Register src_ptr = O0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2343
  Register dst_ptr = O1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2344
  Register len     = O2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2345
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2346
  __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2347
  if (shift == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2348
    __ add(src_ptr, src_pos, src_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2349
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2350
    __ sll(src_pos, shift, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2351
    __ add(src_ptr, tmp, src_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2352
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2353
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2354
  __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2355
  if (shift == 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2356
    __ add(dst_ptr, dst_pos, dst_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2357
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2358
    __ sll(dst_pos, shift, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2359
    __ add(dst_ptr, tmp, dst_ptr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2360
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2361
9102
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2362
  bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2363
  bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2364
  const char *name;
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2365
  address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2366
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2367
  // arraycopy stubs takes a length in number of elements, so don't scale it.
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2368
  __ mov(length, len);
4708a4aefb33 7033154: Improve C1 arraycopy performance
roland
parents: 8495
diff changeset
  2369
  __ call_VM_leaf(tmp, entry);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2370
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2371
  __ bind(*stub->continuation());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2372
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2373
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2375
void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2376
  if (dest->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2377
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2378
    if (left->type() == T_OBJECT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2379
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2380
        case lir_shl:  __ sllx  (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2381
        case lir_shr:  __ srax  (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2382
        case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2383
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2384
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2385
    } else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2386
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2387
      switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2388
        case lir_shl:  __ sll   (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2389
        case lir_shr:  __ sra   (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2390
        case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
        default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2392
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2395
    switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2396
      case lir_shl:  __ sllx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2397
      case lir_shr:  __ srax  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2398
      case lir_ushr: __ srlx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2399
      default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2401
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2402
    switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2403
      case lir_shl:  __ lshl  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2404
      case lir_shr:  __ lshr  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2405
      case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2406
      default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2407
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2408
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2409
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2410
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2411
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2412
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2413
void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2414
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2415
  if (left->type() == T_OBJECT) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2416
    count = count & 63;  // shouldn't shift by more than sizeof(intptr_t)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2417
    Register l = left->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2418
    Register d = dest->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2419
    switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2420
      case lir_shl:  __ sllx  (l, count, d); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2421
      case lir_shr:  __ srax  (l, count, d); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2422
      case lir_ushr: __ srlx  (l, count, d); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2423
      default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2424
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2425
    return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2426
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2427
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2428
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2429
  if (dest->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2430
    count = count & 0x1F; // Java spec
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2431
    switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2432
      case lir_shl:  __ sll   (left->as_register(), count, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2433
      case lir_shr:  __ sra   (left->as_register(), count, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2434
      case lir_ushr: __ srl   (left->as_register(), count, dest->as_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2435
      default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2436
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2437
  } else if (dest->is_double_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2438
    count = count & 63; // Java spec
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2439
    switch (code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2440
      case lir_shl:  __ sllx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2441
      case lir_shr:  __ srax  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2442
      case lir_ushr: __ srlx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2443
      default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2444
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2445
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2446
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2447
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2448
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2449
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2450
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2451
void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2452
  assert(op->tmp1()->as_register()  == G1 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2453
         op->tmp2()->as_register()  == G3 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2454
         op->tmp3()->as_register()  == G4 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2455
         op->obj()->as_register()   == O0 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2456
         op->klass()->as_register() == G5, "must be");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2457
  if (op->init_check()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2458
    __ ld(op->klass()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2459
          instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2460
          op->tmp1()->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2461
    add_debug_info_for_null_check_here(op->stub()->info());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2462
    __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2463
    __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2464
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2465
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2466
  __ allocate_object(op->obj()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2467
                     op->tmp1()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2468
                     op->tmp2()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2469
                     op->tmp3()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2470
                     op->header_size(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2471
                     op->object_size(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2472
                     op->klass()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2473
                     *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2474
  __ bind(*op->stub()->continuation());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2475
  __ verify_oop(op->obj()->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2476
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2477
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2478
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2479
void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2480
  assert(op->tmp1()->as_register()  == G1 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2481
         op->tmp2()->as_register()  == G3 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2482
         op->tmp3()->as_register()  == G4 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2483
         op->tmp4()->as_register()  == O1 &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2484
         op->klass()->as_register() == G5, "must be");
7883
f29abf6b3466 7010618: C1: array length should be treated at int on 64bit during array allocation
iveresov
parents: 7713
diff changeset
  2485
f29abf6b3466 7010618: C1: array length should be treated at int on 64bit during array allocation
iveresov
parents: 7713
diff changeset
  2486
  LP64_ONLY( __ signx(op->len()->as_register()); )
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2487
  if (UseSlowPath ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2488
      (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2489
      (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
5334
b2d040a8d375 6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents: 5253
diff changeset
  2490
    __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2491
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2492
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2493
    __ allocate_array(op->obj()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2494
                      op->len()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2495
                      op->tmp1()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2496
                      op->tmp2()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2497
                      op->tmp3()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2498
                      arrayOopDesc::header_size(op->type()),
202
dc13bf0e5d5d 6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents: 1
diff changeset
  2499
                      type2aelembytes(op->type()),
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2500
                      op->klass()->as_register(),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2501
                      *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2502
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2503
  __ bind(*op->stub()->continuation());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2504
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2505
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2506
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2507
void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2508
                                        ciMethodData *md, ciProfileData *data,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2509
                                        Register recv, Register tmp1, Label* update_done) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2510
  uint i;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2511
  for (i = 0; i < VirtualCallData::row_limit(); i++) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2512
    Label next_test;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2513
    // See if the receiver is receiver[n].
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2514
    Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2515
                          mdo_offset_bias);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2516
    __ ld_ptr(receiver_addr, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2517
    __ verify_oop(tmp1);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2518
    __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2519
    Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2520
                      mdo_offset_bias);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2521
    __ ld_ptr(data_addr, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2522
    __ add(tmp1, DataLayout::counter_increment, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2523
    __ st_ptr(tmp1, data_addr);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2524
    __ ba(*update_done);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2525
    __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2526
    __ bind(next_test);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2527
  }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2528
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2529
  // Didn't find receiver; find next empty slot and fill it in
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2530
  for (i = 0; i < VirtualCallData::row_limit(); i++) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2531
    Label next_test;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2532
    Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2533
                      mdo_offset_bias);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2534
    __ ld_ptr(recv_addr, tmp1);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2535
    __ br_notnull_short(tmp1, Assembler::pt, next_test);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2536
    __ st_ptr(recv, recv_addr);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2537
    __ set(DataLayout::counter_increment, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2538
    __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2539
              mdo_offset_bias);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2540
    __ ba(*update_done);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2541
    __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2542
    __ bind(next_test);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2543
  }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2544
}
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2545
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2546
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2547
void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2548
                                    ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
7432
f06f1253c317 7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents: 7427
diff changeset
  2549
  md = method->method_data_or_null();
f06f1253c317 7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents: 7427
diff changeset
  2550
  assert(md != NULL, "Sanity");
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2551
  data = md->bci_to_data(bci);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2552
  assert(data != NULL,       "need data for checkcast");
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2553
  assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2554
  if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2555
    // The offset is large so bias the mdo by the base of the slot so
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2556
    // that the ld can use simm13s to reference the slots of the data
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2557
    mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2558
  }
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2559
}
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2560
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2561
void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2562
  // we always need a stub for the failure case.
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2563
  CodeStub* stub = op->stub();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2564
  Register obj = op->object()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2565
  Register k_RInfo = op->tmp1()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2566
  Register klass_RInfo = op->tmp2()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2567
  Register dst = op->result_opr()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2568
  Register Rtmp1 = op->tmp3()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2569
  ciKlass* k = op->klass();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2570
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2571
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2572
  if (obj == k_RInfo) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2573
    k_RInfo = klass_RInfo;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2574
    klass_RInfo = obj;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2575
  }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2576
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2577
  ciMethodData* md;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2578
  ciProfileData* data;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2579
  int mdo_offset_bias = 0;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2580
  if (op->should_profile()) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2581
    ciMethod* method = op->profiled_method();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2582
    assert(method != NULL, "Should have method");
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2583
    setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2584
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2585
    Label not_null;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2586
    __ br_notnull_short(obj, Assembler::pn, not_null);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2587
    Register mdo      = k_RInfo;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2588
    Register data_val = Rtmp1;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2589
    jobject2reg(md->constant_encoding(), mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2590
    if (mdo_offset_bias > 0) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2591
      __ set(mdo_offset_bias, data_val);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2592
      __ add(mdo, data_val, mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2593
    }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2594
    Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2595
    __ ldub(flags_addr, data_val);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2596
    __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2597
    __ stb(data_val, flags_addr);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2598
    __ ba(*obj_is_null);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2599
    __ delayed()->nop();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2600
    __ bind(not_null);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2601
  } else {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2602
    __ br_null(obj, false, Assembler::pn, *obj_is_null);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2603
    __ delayed()->nop();
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2604
  }
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2605
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2606
  Label profile_cast_failure, profile_cast_success;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2607
  Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2608
  Label *success_target = op->should_profile() ? &profile_cast_success : success;
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2609
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2610
  // patching may screw with our temporaries on sparc,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2611
  // so let's do it before loading the class
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2612
  if (k->is_loaded()) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2613
    jobject2reg(k->constant_encoding(), k_RInfo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2614
  } else {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2615
    jobject2reg_with_patching(k_RInfo, op->info_for_patch());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2616
  }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2617
  assert(obj != k_RInfo, "must be different");
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2618
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2619
  // get object class
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2620
  // not a safepoint as obj null check happens earlier
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2621
  __ load_klass(obj, klass_RInfo);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2622
  if (op->fast_check()) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2623
    assert_different_registers(klass_RInfo, k_RInfo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2624
    __ cmp(k_RInfo, klass_RInfo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2625
    __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2626
    __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2627
  } else {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2628
    bool need_slow_path = true;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2629
    if (k->is_loaded()) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2630
      if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2631
        need_slow_path = false;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2632
      // perform the fast part of the checking logic
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2633
      __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2634
                                       (need_slow_path ? success_target : NULL),
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2635
                                       failure_target, NULL,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2636
                                       RegisterOrConstant(k->super_check_offset()));
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2637
    } else {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2638
      // perform the fast part of the checking logic
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2639
      __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2640
                                       failure_target, NULL);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2641
    }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2642
    if (need_slow_path) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2643
      // call out-of-line instance of __ check_klass_subtype_slow_path(...):
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2644
      assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2645
      __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2646
      __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2647
      __ cmp(G3, 0);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2648
      __ br(Assembler::equal, false, Assembler::pn, *failure_target);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2649
      __ delayed()->nop();
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2650
      // Fall through to success case
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2651
    }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2652
  }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2653
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2654
  if (op->should_profile()) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2655
    Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2656
    assert_different_registers(obj, mdo, recv, tmp1);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2657
    __ bind(profile_cast_success);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2658
    jobject2reg(md->constant_encoding(), mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2659
    if (mdo_offset_bias > 0) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2660
      __ set(mdo_offset_bias, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2661
      __ add(mdo, tmp1, mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2662
    }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2663
    __ load_klass(obj, recv);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2664
    type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2665
    // Jump over the failure case
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2666
    __ ba(*success);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2667
    __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2668
    // Cast failure case
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2669
    __ bind(profile_cast_failure);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2670
    jobject2reg(md->constant_encoding(), mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2671
    if (mdo_offset_bias > 0) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2672
      __ set(mdo_offset_bias, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2673
      __ add(mdo, tmp1, mdo);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2674
    }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2675
    Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2676
    __ ld_ptr(data_addr, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2677
    __ sub(tmp1, DataLayout::counter_increment, tmp1);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2678
    __ st_ptr(tmp1, data_addr);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2679
    __ ba(*failure);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2680
    __ delayed()->nop();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2681
  }
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2682
  __ ba(*success);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2683
  __ delayed()->nop();
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2684
}
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2685
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2686
void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2687
  LIR_Code code = op->code();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2688
  if (code == lir_store_check) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2689
    Register value = op->object()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2690
    Register array = op->array()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2691
    Register k_RInfo = op->tmp1()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2692
    Register klass_RInfo = op->tmp2()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2693
    Register Rtmp1 = op->tmp3()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2694
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2695
    __ verify_oop(value);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2696
    CodeStub* stub = op->stub();
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2697
    // check if it needs to be profiled
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2698
    ciMethodData* md;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2699
    ciProfileData* data;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2700
    int mdo_offset_bias = 0;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2701
    if (op->should_profile()) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2702
      ciMethod* method = op->profiled_method();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2703
      assert(method != NULL, "Should have method");
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2704
      setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2705
    }
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2706
    Label profile_cast_success, profile_cast_failure, done;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2707
    Label *success_target = op->should_profile() ? &profile_cast_success : &done;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2708
    Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2709
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2710
    if (op->should_profile()) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2711
      Label not_null;
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2712
      __ br_notnull_short(value, Assembler::pn, not_null);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2713
      Register mdo      = k_RInfo;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2714
      Register data_val = Rtmp1;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2715
      jobject2reg(md->constant_encoding(), mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2716
      if (mdo_offset_bias > 0) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2717
        __ set(mdo_offset_bias, data_val);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2718
        __ add(mdo, data_val, mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2719
      }
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2720
      Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2721
      __ ldub(flags_addr, data_val);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2722
      __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2723
      __ stb(data_val, flags_addr);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2724
      __ ba_short(done);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2725
      __ bind(not_null);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2726
    } else {
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2727
      __ br_null_short(value, Assembler::pn, done);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2728
    }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2729
    add_debug_info_for_null_check_here(op->info_for_exception());
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2730
    __ load_klass(array, k_RInfo);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2731
    __ load_klass(value, klass_RInfo);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2732
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2733
    // get instance klass
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2734
    __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1388
diff changeset
  2735
    // perform the fast part of the checking logic
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2736
    __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1388
diff changeset
  2737
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1388
diff changeset
  2738
    // call out-of-line instance of __ check_klass_subtype_slow_path(...):
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1388
diff changeset
  2739
    assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2740
    __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2741
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2742
    __ cmp(G3, 0);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2743
    __ br(Assembler::equal, false, Assembler::pn, *failure_target);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2744
    __ delayed()->nop();
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2745
    // fall through to the success case
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2746
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2747
    if (op->should_profile()) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2748
      Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2749
      assert_different_registers(value, mdo, recv, tmp1);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2750
      __ bind(profile_cast_success);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2751
      jobject2reg(md->constant_encoding(), mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2752
      if (mdo_offset_bias > 0) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2753
        __ set(mdo_offset_bias, tmp1);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2754
        __ add(mdo, tmp1, mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2755
      }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2756
      __ load_klass(value, recv);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2757
      type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2758
      __ ba_short(done);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2759
      // Cast failure case
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2760
      __ bind(profile_cast_failure);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2761
      jobject2reg(md->constant_encoding(), mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2762
      if (mdo_offset_bias > 0) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2763
        __ set(mdo_offset_bias, tmp1);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2764
        __ add(mdo, tmp1, mdo);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2765
      }
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2766
      Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2767
      __ ld_ptr(data_addr, tmp1);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2768
      __ sub(tmp1, DataLayout::counter_increment, tmp1);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2769
      __ st_ptr(tmp1, data_addr);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2770
      __ ba(*stub->entry());
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2771
      __ delayed()->nop();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2772
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2773
    __ bind(done);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2774
  } else if (code == lir_checkcast) {
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2775
    Register obj = op->object()->as_register();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2776
    Register dst = op->result_opr()->as_register();
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2777
    Label success;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2778
    emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2779
    __ bind(success);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2780
    __ mov(obj, dst);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2781
  } else if (code == lir_instanceof) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2782
    Register obj = op->object()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2783
    Register dst = op->result_opr()->as_register();
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2784
    Label success, failure, done;
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2785
    emit_typecheck_helper(op, &success, &failure, &failure);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2786
    __ bind(failure);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2787
    __ set(0, dst);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 9105
diff changeset
  2788
    __ ba_short(done);
6461
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2789
    __ bind(success);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2790
    __ set(1, dst);
cfc616b49f58 6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents: 6453
diff changeset
  2791
    __ bind(done);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2792
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2793
    ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2794
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2795
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2796
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2797
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2798
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2799
void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2800
  if (op->code() == lir_cas_long) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2801
    assert(VM_Version::supports_cx8(), "wrong machine");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2802
    Register addr = op->addr()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2803
    Register cmp_value_lo = op->cmp_value()->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2804
    Register cmp_value_hi = op->cmp_value()->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2805
    Register new_value_lo = op->new_value()->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2806
    Register new_value_hi = op->new_value()->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2807
    Register t1 = op->tmp1()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2808
    Register t2 = op->tmp2()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2809
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2810
    __ mov(cmp_value_lo, t1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2811
    __ mov(new_value_lo, t2);
7713
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2812
    // perform the compare and swap operation
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2813
    __ casx(addr, t1, t2);
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2814
    // generate condition code - if the swap succeeded, t2 ("new value" reg) was
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2815
    // overwritten with the original value in "addr" and will be equal to t1.
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2816
    __ cmp(t1, t2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2817
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2818
    // move high and low halves of long values into single registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2819
    __ sllx(cmp_value_hi, 32, t1);         // shift high half into temp reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2820
    __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2821
    __ or3(t1, cmp_value_lo, t1);          // t1 holds 64-bit compare value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2822
    __ sllx(new_value_hi, 32, t2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2823
    __ srl(new_value_lo, 0, new_value_lo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2824
    __ or3(t2, new_value_lo, t2);          // t2 holds 64-bit value to swap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2825
    // perform the compare and swap operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2826
    __ casx(addr, t1, t2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2827
    // generate condition code - if the swap succeeded, t2 ("new value" reg) was
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2828
    // overwritten with the original value in "addr" and will be equal to t1.
7713
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2829
    // Produce icc flag for 32bit.
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2830
    __ sub(t1, t2, t2);
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2831
    __ srlx(t2, 32, t1);
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2832
    __ orcc(t2, t1, G0);
1e06d2419258 7009231: C1: Incorrect CAS code for longs on SPARC 32bit
iveresov
parents: 7435
diff changeset
  2833
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2834
  } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2835
    Register addr = op->addr()->as_pointer_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2836
    Register cmp_value = op->cmp_value()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2837
    Register new_value = op->new_value()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2838
    Register t1 = op->tmp1()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2839
    Register t2 = op->tmp2()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2840
    __ mov(cmp_value, t1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2841
    __ mov(new_value, t2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2842
    if (op->code() == lir_cas_obj) {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2843
      if (UseCompressedOops) {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2844
        __ encode_heap_oop(t1);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2845
        __ encode_heap_oop(t2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2846
        __ cas(addr, t1, t2);
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2847
      } else {
7435
3da377e9db3f 7004530: casx used for 32 bit cas after 7003554
never
parents: 7432
diff changeset
  2848
        __ cas_ptr(addr, t1, t2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2849
      }
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2850
    } else {
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2851
      __ cas(addr, t1, t2);
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  2852
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2853
    __ cmp(t1, t2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2854
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2855
    Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2856
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2857
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2858
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2859
void LIR_Assembler::set_24bit_FPU() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2860
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2861
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2862
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2863
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2864
void LIR_Assembler::reset_FPU() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2865
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2866
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2867
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2868
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2869
void LIR_Assembler::breakpoint() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2870
  __ breakpoint_trap();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2871
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2872
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2873
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2874
void LIR_Assembler::push(LIR_Opr opr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2875
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2876
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2877
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2878
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2879
void LIR_Assembler::pop(LIR_Opr opr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2880
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2881
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2882
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2883
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2884
void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2885
  Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2886
  Register dst = dst_opr->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2887
  Register reg = mon_addr.base();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2888
  int offset = mon_addr.disp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2889
  // compute pointer to BasicLock
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2890
  if (mon_addr.is_simm13()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2891
    __ add(reg, offset, dst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2892
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2893
    __ set(offset, dst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2894
    __ add(dst, reg, dst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2895
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2896
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2897
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2898
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2899
void LIR_Assembler::emit_lock(LIR_OpLock* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2900
  Register obj = op->obj_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2901
  Register hdr = op->hdr_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2902
  Register lock = op->lock_opr()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2903
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2904
  // obj may not be an oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2905
  if (op->code() == lir_lock) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2906
    MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2907
    if (UseFastLocking) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2908
      assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2909
      // add debug info for NullPointerException only if one is possible
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2910
      if (op->info() != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2911
        add_debug_info_for_null_check_here(op->info());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2912
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2913
      __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2914
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2915
      // always do slow locking
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2916
      // note: the slow locking code could be inlined here, however if we use
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2917
      //       slow locking, speed doesn't matter anyway and this solution is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2918
      //       simpler and requires less duplicated code - additionally, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2919
      //       slow locking code is the same in either case which simplifies
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2920
      //       debugging
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2921
      __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2922
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2923
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2924
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2925
    assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2926
    if (UseFastLocking) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2927
      assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2928
      __ unlock_object(hdr, obj, lock, *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2929
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2930
      // always do slow unlocking
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2931
      // note: the slow unlocking code could be inlined here, however if we use
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2932
      //       slow unlocking, speed doesn't matter anyway and this solution is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2933
      //       simpler and requires less duplicated code - additionally, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2934
      //       slow unlocking code is the same in either case which simplifies
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2935
      //       debugging
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2936
      __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2937
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2938
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2939
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2940
  __ bind(*op->stub()->continuation());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2941
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2942
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2943
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2944
void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2945
  ciMethod* method = op->profiled_method();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2946
  int bci          = op->profiled_bci();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2947
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2948
  // Update counter for all call types
7432
f06f1253c317 7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents: 7427
diff changeset
  2949
  ciMethodData* md = method->method_data_or_null();
f06f1253c317 7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents: 7427
diff changeset
  2950
  assert(md != NULL, "Sanity");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2951
  ciProfileData* data = md->bci_to_data(bci);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2952
  assert(data->is_CounterData(), "need CounterData for calls");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2953
  assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2954
  Register mdo  = op->mdo()->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2955
#ifdef _LP64
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2956
  assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2957
  Register tmp1 = op->tmp1()->as_register_lo();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2958
#else
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2959
  assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2960
  Register tmp1 = op->tmp1()->as_register();
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2961
#endif
3908
24b55ad4c228 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 2867
diff changeset
  2962
  jobject2reg(md->constant_encoding(), mdo);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2963
  int mdo_offset_bias = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2964
  if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2965
                            data->size_in_bytes())) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2966
    // The offset is large so bias the mdo by the base of the slot so
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2967
    // that the ld can use simm13s to reference the slots of the data
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2968
    mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2969
    __ set(mdo_offset_bias, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2970
    __ add(mdo, O7, mdo);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2971
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2972
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  2973
  Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2974
  Bytecodes::Code bc = method->java_code_at_bci(bci);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2975
  // Perform additional virtual call profiling for invokevirtual and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2976
  // invokeinterface bytecodes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2977
  if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2978
      C1ProfileVirtualCalls) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2979
    assert(op->recv()->is_single_cpu(), "recv must be allocated");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2980
    Register recv = op->recv()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2981
    assert_different_registers(mdo, tmp1, recv);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2982
    assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2983
    ciKlass* known_klass = op->known_holder();
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2984
    if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2985
      // We know the type that will be seen at this call site; we can
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2986
      // statically update the methodDataOop rather than needing to do
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2987
      // dynamic tests on the receiver type
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2988
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2989
      // NOTE: we should probably put a lock around this search to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2990
      // avoid collisions by concurrent compilations
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2991
      ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2992
      uint i;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2993
      for (i = 0; i < VirtualCallData::row_limit(); i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2994
        ciKlass* receiver = vc_data->receiver(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2995
        if (known_klass->equals(receiver)) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  2996
          Address data_addr(mdo, md->byte_offset_of_slot(data,
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  2997
                                                         VirtualCallData::receiver_count_offset(i)) -
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2998
                            mdo_offset_bias);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  2999
          __ ld_ptr(data_addr, tmp1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3000
          __ add(tmp1, DataLayout::counter_increment, tmp1);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3001
          __ st_ptr(tmp1, data_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3002
          return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3003
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3004
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3005
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3006
      // Receiver type not found in profile data; select an empty slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3007
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3008
      // Note that this is less efficient than it should be because it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3009
      // always does a write to the receiver part of the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3010
      // VirtualCallData rather than just the first time
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3011
      for (i = 0; i < VirtualCallData::row_limit(); i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3012
        ciKlass* receiver = vc_data->receiver(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3013
        if (receiver == NULL) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  3014
          Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3015
                            mdo_offset_bias);
3908
24b55ad4c228 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 2867
diff changeset
  3016
          jobject2reg(known_klass->constant_encoding(), tmp1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3017
          __ st_ptr(tmp1, recv_addr);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2332
diff changeset
  3018
          Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3019
                            mdo_offset_bias);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3020
          __ ld_ptr(data_addr, tmp1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3021
          __ add(tmp1, DataLayout::counter_increment, tmp1);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3022
          __ st_ptr(tmp1, data_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3023
          return;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3024
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3025
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3026
    } else {
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  3027
      __ load_klass(recv, recv);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3028
      Label update_done;
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3029
      type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
4892
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3030
      // Receiver did not match any saved receiver and there is no empty row for it.
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3031
      // Increment total counter to indicate polymorphic case.
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3032
      __ ld_ptr(counter_addr, tmp1);
4892
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3033
      __ add(tmp1, DataLayout::counter_increment, tmp1);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3034
      __ st_ptr(tmp1, counter_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3035
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3036
      __ bind(update_done);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3037
    }
4892
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3038
  } else {
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3039
    // Static call
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3040
    __ ld_ptr(counter_addr, tmp1);
4892
e977b527544a 6923002: assert(false,"this call site should not be polymorphic")
kvn
parents: 4752
diff changeset
  3041
    __ add(tmp1, DataLayout::counter_increment, tmp1);
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3042
    __ st_ptr(tmp1, counter_addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3043
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3044
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3045
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3046
void LIR_Assembler::align_backward_branch_target() {
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5052
diff changeset
  3047
  __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3048
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3050
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3051
void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3052
  // make sure we are expecting a delay
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3053
  // this has the side effect of clearing the delay state
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3054
  // so we can use _masm instead of _masm->delayed() to do the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3055
  // code generation.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3056
  __ delayed();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3057
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3058
  // make sure we only emit one instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3059
  int offset = code_offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3060
  op->delay_op()->emit_code(this);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3061
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3062
  if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3063
    op->delay_op()->print();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3064
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3065
  assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3066
         "only one instruction can go in a delay slot");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3067
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3068
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3069
  // we may also be emitting the call info for the instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3070
  // which we are the delay slot of.
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
  3071
  CodeEmitInfo* call_info = op->call_info();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3072
  if (call_info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3073
    add_call_info(code_offset(), call_info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3074
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3075
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3076
  if (VerifyStackAtCalls) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3077
    _masm->sub(FP, SP, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3078
    _masm->cmp(O7, initial_frame_size_in_bytes());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3079
    _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3080
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3081
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3082
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3083
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3084
void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3085
  assert(left->is_register(), "can only handle registers");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3086
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3087
  if (left->is_single_cpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3088
    __ neg(left->as_register(), dest->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3089
  } else if (left->is_single_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3090
    __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3091
  } else if (left->is_double_fpu()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3092
    __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3093
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3094
    assert (left->is_double_cpu(), "Must be a long");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3095
    Register Rlow = left->as_register_lo();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3096
    Register Rhi = left->as_register_hi();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3097
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3098
    __ sub(G0, Rlow, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3099
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3100
    __ subcc(G0, Rlow, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3101
    __ subc (G0, Rhi,  dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3102
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3103
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3104
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3105
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3106
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3107
void LIR_Assembler::fxch(int i) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3108
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3109
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3110
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3111
void LIR_Assembler::fld(int i) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3112
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3113
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3114
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3115
void LIR_Assembler::ffree(int i) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3116
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3117
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3118
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3119
void LIR_Assembler::rt_call(LIR_Opr result, address dest,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3120
                            const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3121
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3122
  // if tmp is invalid, then the function being called doesn't destroy the thread
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3123
  if (tmp->is_valid()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3124
    __ save_thread(tmp->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3125
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3126
  __ call(dest, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3127
  __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3128
  if (info != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3129
    add_call_info_here(info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3130
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3131
  if (tmp->is_valid()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3132
    __ restore_thread(tmp->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3133
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3134
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3135
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3136
  __ verify_thread();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3137
#endif // ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3138
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3139
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3140
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3141
void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3142
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3143
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3144
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3145
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3146
  NEEDS_CLEANUP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3147
  if (type == T_LONG) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3148
    LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3149
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3150
    // (extended to allow indexed as well as constant displaced for JSR-166)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3151
    Register idx = noreg; // contains either constant offset or index
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3152
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3153
    int disp = mem_addr->disp();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3154
    if (mem_addr->index() == LIR_OprFact::illegalOpr) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3155
      if (!Assembler::is_simm13(disp)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3156
        idx = O7;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3157
        __ set(disp, idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3158
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3159
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3160
      assert(disp == 0, "not both indexed and disp");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3161
      idx = mem_addr->index()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3162
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3163
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3164
    int null_check_offset = -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3165
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3166
    Register base = mem_addr->base()->as_register();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3167
    if (src->is_register() && dest->is_address()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3168
      // G4 is high half, G5 is low half
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3169
      if (VM_Version::v9_instructions_work()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3170
        // clear the top bits of G5, and scale up G4
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3171
        __ srl (src->as_register_lo(),  0, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3172
        __ sllx(src->as_register_hi(), 32, G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3173
        // combine the two halves into the 64 bits of G4
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3174
        __ or3(G4, G5, G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3175
        null_check_offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3176
        if (idx == noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3177
          __ stx(G4, base, disp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3178
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3179
          __ stx(G4, base, idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3180
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3181
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3182
        __ mov (src->as_register_hi(), G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3183
        __ mov (src->as_register_lo(), G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3184
        null_check_offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3185
        if (idx == noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3186
          __ std(G4, base, disp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3187
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3188
          __ std(G4, base, idx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3189
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3190
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3191
    } else if (src->is_address() && dest->is_register()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3192
      null_check_offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3193
      if (VM_Version::v9_instructions_work()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3194
        if (idx == noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3195
          __ ldx(base, disp, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3196
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3197
          __ ldx(base, idx, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3198
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3199
        __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3200
        __ mov (G5, dest->as_register_lo());     // copy low half into lo
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3201
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3202
        if (idx == noreg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3203
          __ ldd(base, disp, G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3204
        } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3205
          __ ldd(base, idx, G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3206
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3207
        // G4 is high half, G5 is low half
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3208
        __ mov (G4, dest->as_register_hi());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3209
        __ mov (G5, dest->as_register_lo());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3210
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3211
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3212
      Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3213
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3214
    if (info != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3215
      add_debug_info_for_null_check(null_check_offset, info);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3216
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3217
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3218
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3219
    // use normal move for all other volatiles since they don't need
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3220
    // special handling to remain atomic.
7427
d7b79a367474 6985015: C1 needs to support compressed oops
iveresov
parents: 7397
diff changeset
  3221
    move_op(src, dest, type, lir_patch_none, info, false, false, false);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3222
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3223
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3224
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3225
void LIR_Assembler::membar() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3226
  // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3227
  __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3228
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3229
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3230
void LIR_Assembler::membar_acquire() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3231
  // no-op on TSO
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3232
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3233
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3234
void LIR_Assembler::membar_release() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3235
  // no-op on TSO
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3236
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3237
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3238
// Pack two sequential registers containing 32 bit values
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3239
// into a single 64 bit register.
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3240
// src and src->successor() are packed into dst
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3241
// src and dst may be the same register.
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3242
// Note: src is destroyed
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3243
void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3244
  Register rs = src->as_register();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3245
  Register rd = dst->as_register_lo();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3246
  __ sllx(rs, 32, rs);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3247
  __ srl(rs->successor(), 0, rs->successor());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3248
  __ or3(rs, rs->successor(), rd);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3249
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3250
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3251
// Unpack a 64 bit value in a register into
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3252
// two sequential registers.
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3253
// src is unpacked into dst and dst->successor()
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3254
void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3255
  Register rs = src->as_register_lo();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3256
  Register rd = dst->as_register_hi();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3257
  assert_different_registers(rs, rd, rd->successor());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3258
  __ srlx(rs, 32, rd);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3259
  __ srl (rs,  0, rd->successor());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3260
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3261
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3262
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3263
void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3264
  LIR_Address* addr = addr_opr->as_address_ptr();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3265
  assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3266
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3267
  __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3268
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3269
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3270
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3271
void LIR_Assembler::get_thread(LIR_Opr result_reg) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3272
  assert(result_reg->is_register(), "check");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3273
  __ mov(G2_thread, result_reg->as_register());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3274
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3275
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3276
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3277
void LIR_Assembler::peephole(LIR_List* lir) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3278
  LIR_OpList* inst = lir->instructions_list();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3279
  for (int i = 0; i < inst->length(); i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3280
    LIR_Op* op = inst->at(i);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3281
    switch (op->code()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3282
      case lir_cond_float_branch:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3283
      case lir_branch: {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3284
        LIR_OpBranch* branch = op->as_OpBranch();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3285
        assert(branch->info() == NULL, "shouldn't be state on branches anymore");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3286
        LIR_Op* delay_op = NULL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3287
        // we'd like to be able to pull following instructions into
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3288
        // this slot but we don't know enough to do it safely yet so
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3289
        // only optimize block to block control flow.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3290
        if (LIRFillDelaySlots && branch->block()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3291
          LIR_Op* prev = inst->at(i - 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3292
          if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3293
            // swap previous instruction into delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3294
            inst->at_put(i - 1, op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3295
            inst->at_put(i, new LIR_OpDelay(prev, op->info()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3296
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3297
            if (LIRTracePeephole) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3298
              tty->print_cr("delayed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3299
              inst->at(i - 1)->print();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3300
              inst->at(i)->print();
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
  3301
              tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3302
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3303
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3304
            continue;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3305
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3306
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3307
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3308
        if (!delay_op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3309
          delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3310
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3311
        inst->insert_before(i + 1, delay_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3312
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3313
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3314
      case lir_static_call:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3315
      case lir_virtual_call:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3316
      case lir_icvirtual_call:
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
  3317
      case lir_optvirtual_call:
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
  3318
      case lir_dynamic_call: {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3319
        LIR_Op* prev = inst->at(i - 1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3320
        if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3321
            (op->code() != lir_virtual_call ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3322
             !prev->result_opr()->is_single_cpu() ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3323
             prev->result_opr()->as_register() != O0) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3324
            LIR_Assembler::is_single_instruction(prev)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3325
          // Only moves without info can be put into the delay slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3326
          // Also don't allow the setup of the receiver in the delay
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3327
          // slot for vtable calls.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3328
          inst->at_put(i - 1, op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3329
          inst->at_put(i, new LIR_OpDelay(prev, op->info()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3330
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3331
          if (LIRTracePeephole) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3332
            tty->print_cr("delayed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3333
            inst->at(i - 1)->print();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3334
            inst->at(i)->print();
5687
b862d1f189bd 6930772: JSR 292 needs to support SPARC C1
twisti
parents: 5334
diff changeset
  3335
            tty->cr();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3336
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3337
#endif
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3338
        } else {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3339
          LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3340
          inst->insert_before(i + 1, delay_op);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3341
          i++;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3342
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3343
6453
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3344
#if defined(TIERED) && !defined(_LP64)
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3345
        // fixup the return value from G1 to O0/O1 for long returns.
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3346
        // It's done here instead of in LIRGenerator because there's
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3347
        // such a mismatch between the single reg and double reg
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3348
        // calling convention.
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3349
        LIR_OpJavaCall* callop = op->as_OpJavaCall();
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3350
        if (callop->result_opr() == FrameMap::out_long_opr) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3351
          LIR_OpJavaCall* call;
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3352
          LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3353
          for (int a = 0; a < arguments->length(); a++) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3354
            arguments[a] = callop->arguments()[a];
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3355
          }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3356
          if (op->code() == lir_virtual_call) {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3357
            call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3358
                                      callop->vtable_offset(), arguments, callop->info());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3359
          } else {
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3360
            call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3361
                                      callop->addr(), arguments, callop->info());
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3362
          }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3363
          inst->at_put(i - 1, call);
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3364
          inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3365
                                                 T_LONG, lir_patch_none, NULL));
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3366
        }
970dc585ab63 6953144: Tiered compilation
iveresov
parents: 5702
diff changeset
  3367
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3368
        break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3369
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3370
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3371
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3372
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3373
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3375
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3376
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3377
#undef __