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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP
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#define OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP
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#include "runtime/atomic.hpp"
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#include "runtime/os.hpp"
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#include "vm_version_s390.hpp"
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// Note that the compare-and-swap instructions on System z perform
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// a serialization function before the storage operand is fetched
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// and again after the operation is completed.
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//
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// Used constraint modifiers:
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// = write-only access: Value on entry to inline-assembler code irrelevant.
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// + read/write access: Value on entry is used; on exit value is changed.
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// read-only access: Value on entry is used and never changed.
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// & early-clobber access: Might be modified before all read-only operands
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// have been used.
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// a address register operand (not GR0).
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// d general register operand (including GR0)
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// Q memory operand w/o index register.
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// 0..9 operand reference (by operand position).
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// Used for operands that fill multiple roles. One example would be a
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// write-only operand receiving its initial value from a read-only operand.
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// Refer to cmpxchg(..) operand #0 and variable cmp_val for a real-life example.
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//
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// On System z, all store operations are atomic if the address where the data is stored into
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// is an integer multiple of the data length. Furthermore, all stores are ordered:
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// a store which occurs conceptually before another store becomes visible to other CPUs
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// before the other store becomes visible.
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inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; }
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inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; }
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inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; }
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inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; }
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inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; }
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inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; }
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inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; }
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inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; }
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inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; }
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inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; }
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inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; }
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inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; }
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//------------
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// Atomic::add
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//------------
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// These methods force the value in memory to be augmented by the passed increment.
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// Both, memory value and increment, are treated as 32bit signed binary integers.
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// No overflow exceptions are recognized, and the condition code does not hold
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// information about the value in memory.
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//
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// The value in memory is updated by using a compare-and-swap instruction. The
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// instruction is retried as often as required.
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//
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// The return value of the method is the value that was successfully stored. At the
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// time the caller receives back control, the value in memory may have changed already.
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inline jint Atomic::add(jint inc, volatile jint*dest) {
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unsigned int old, upd;
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if (VM_Version::has_LoadAndALUAtomicV1()) {
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__asm__ __volatile__ (
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" LGFR 0,%[inc] \n\t" // save increment
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" LA 3,%[mem] \n\t" // force data address into ARG2
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// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value
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// " LAA 2,0,0(3) \n\t" // actually coded instruction
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" .byte 0xeb \n\t" // LAA main opcode
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" .byte 0x20 \n\t" // R1,R3
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" .byte 0x30 \n\t" // R2,disp1
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" .byte 0x00 \n\t" // disp2,disp3
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" .byte 0x00 \n\t" // disp4,disp5
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" .byte 0xf8 \n\t" // LAA minor opcode
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" AR 2,0 \n\t" // calc new value in register
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" LR %[upd],2 \n\t" // move to result register
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//---< outputs >---
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: [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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: [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc", "r0", "r2", "r3"
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);
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} else {
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__asm__ __volatile__ (
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" LLGF %[old],%[mem] \n\t" // get old value
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"0: LA %[upd],0(%[inc],%[old]) \n\t" // calc result
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" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
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" JNE 0b \n\t" // no success? -> retry
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//---< outputs >---
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: [old] "=&a" (old) // write-only, old counter value
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, [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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: [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc"
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);
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}
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return (jint)upd;
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}
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inline intptr_t Atomic::add_ptr(intptr_t inc, volatile intptr_t* dest) {
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unsigned long old, upd;
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if (VM_Version::has_LoadAndALUAtomicV1()) {
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__asm__ __volatile__ (
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" LGR 0,%[inc] \n\t" // save increment
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" LA 3,%[mem] \n\t" // force data address into ARG2
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// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value
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// " LAAG 2,0,0(3) \n\t" // actually coded instruction
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" .byte 0xeb \n\t" // LAA main opcode
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" .byte 0x20 \n\t" // R1,R3
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" .byte 0x30 \n\t" // R2,disp1
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" .byte 0x00 \n\t" // disp2,disp3
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" .byte 0x00 \n\t" // disp4,disp5
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" .byte 0xe8 \n\t" // LAA minor opcode
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" AGR 2,0 \n\t" // calc new value in register
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" LGR %[upd],2 \n\t" // move to result register
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//---< outputs >---
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: [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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: [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc", "r0", "r2", "r3"
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);
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} else {
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__asm__ __volatile__ (
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" LG %[old],%[mem] \n\t" // get old value
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"0: LA %[upd],0(%[inc],%[old]) \n\t" // calc result
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" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
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" JNE 0b \n\t" // no success? -> retry
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//---< outputs >---
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: [old] "=&a" (old) // write-only, old counter value
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, [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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: [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc"
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);
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}
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return (intptr_t)upd;
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}
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inline void* Atomic::add_ptr(intptr_t add_value, volatile void* dest) {
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return (void*)add_ptr(add_value, (volatile intptr_t*)dest);
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}
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//------------
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// Atomic::inc
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//------------
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// These methods force the value in memory to be incremented (augmented by 1).
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// Both, memory value and increment, are treated as 32bit signed binary integers.
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// No overflow exceptions are recognized, and the condition code does not hold
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// information about the value in memory.
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//
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// The value in memory is updated by using a compare-and-swap instruction. The
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// instruction is retried as often as required.
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inline void Atomic::inc(volatile jint* dest) {
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unsigned int old, upd;
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if (VM_Version::has_LoadAndALUAtomicV1()) {
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// tty->print_cr("Atomic::inc called... dest @%p", dest);
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__asm__ __volatile__ (
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" LGHI 2,1 \n\t" // load increment
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" LA 3,%[mem] \n\t" // force data address into ARG2
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// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value
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// " LAA 2,2,0(3) \n\t" // actually coded instruction
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" .byte 0xeb \n\t" // LAA main opcode
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" .byte 0x22 \n\t" // R1,R3
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" .byte 0x30 \n\t" // R2,disp1
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" .byte 0x00 \n\t" // disp2,disp3
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" .byte 0x00 \n\t" // disp4,disp5
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" .byte 0xf8 \n\t" // LAA minor opcode
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" AGHI 2,1 \n\t" // calc new value in register
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" LR %[upd],2 \n\t" // move to result register
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//---< outputs >---
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: [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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:
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// : [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc", "r2", "r3"
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);
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} else {
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__asm__ __volatile__ (
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" LLGF %[old],%[mem] \n\t" // get old value
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"0: LA %[upd],1(,%[old]) \n\t" // calc result
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" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
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" JNE 0b \n\t" // no success? -> retry
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//---< outputs >---
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: [old] "=&a" (old) // write-only, old counter value
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, [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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:
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//---< clobbered >---
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: "cc"
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);
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}
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}
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inline void Atomic::inc_ptr(volatile intptr_t* dest) {
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unsigned long old, upd;
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if (VM_Version::has_LoadAndALUAtomicV1()) {
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__asm__ __volatile__ (
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" LGHI 2,1 \n\t" // load increment
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" LA 3,%[mem] \n\t" // force data address into ARG2
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// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value
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// " LAAG 2,2,0(3) \n\t" // actually coded instruction
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" .byte 0xeb \n\t" // LAA main opcode
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" .byte 0x22 \n\t" // R1,R3
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" .byte 0x30 \n\t" // R2,disp1
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" .byte 0x00 \n\t" // disp2,disp3
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" .byte 0x00 \n\t" // disp4,disp5
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" .byte 0xe8 \n\t" // LAA minor opcode
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" AGHI 2,1 \n\t" // calc new value in register
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" LR %[upd],2 \n\t" // move to result register
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//---< outputs >---
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: [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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:
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// : [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc", "r2", "r3"
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);
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} else {
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__asm__ __volatile__ (
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" LG %[old],%[mem] \n\t" // get old value
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"0: LA %[upd],1(,%[old]) \n\t" // calc result
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" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
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" JNE 0b \n\t" // no success? -> retry
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//---< outputs >---
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: [old] "=&a" (old) // write-only, old counter value
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, [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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:
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//---< clobbered >---
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: "cc"
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);
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}
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}
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inline void Atomic::inc_ptr(volatile void* dest) {
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inc_ptr((volatile intptr_t*)dest);
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}
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//------------
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// Atomic::dec
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//------------
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// These methods force the value in memory to be decremented (augmented by -1).
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// Both, memory value and decrement, are treated as 32bit signed binary integers.
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// No overflow exceptions are recognized, and the condition code does not hold
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// information about the value in memory.
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//
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// The value in memory is updated by using a compare-and-swap instruction. The
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// instruction is retried as often as required.
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inline void Atomic::dec(volatile jint* dest) {
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unsigned int old, upd;
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if (VM_Version::has_LoadAndALUAtomicV1()) {
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__asm__ __volatile__ (
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" LGHI 2,-1 \n\t" // load increment
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" LA 3,%[mem] \n\t" // force data address into ARG2
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// " LAA %[upd],%[inc],%[mem] \n\t" // increment and get old value
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// " LAA 2,2,0(3) \n\t" // actually coded instruction
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" .byte 0xeb \n\t" // LAA main opcode
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" .byte 0x22 \n\t" // R1,R3
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" .byte 0x30 \n\t" // R2,disp1
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" .byte 0x00 \n\t" // disp2,disp3
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" .byte 0x00 \n\t" // disp4,disp5
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" .byte 0xf8 \n\t" // LAA minor opcode
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" AGHI 2,-1 \n\t" // calc new value in register
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" LR %[upd],2 \n\t" // move to result register
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//---< outputs >---
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: [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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:
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// : [inc] "a" (inc) // read-only.
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//---< clobbered >---
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: "cc", "r2", "r3"
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);
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} else {
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__asm__ __volatile__ (
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" LLGF %[old],%[mem] \n\t" // get old value
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// LAY not supported by inline assembler
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// "0: LAY %[upd],-1(,%[old]) \n\t" // calc result
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"0: LR %[upd],%[old] \n\t" // calc result
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" AHI %[upd],-1 \n\t"
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" CS %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
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" JNE 0b \n\t" // no success? -> retry
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//---< outputs >---
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: [old] "=&a" (old) // write-only, old counter value
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, [upd] "=&d" (upd) // write-only, updated counter value
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, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
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//---< inputs >---
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336 |
:
|
|
337 |
//---< clobbered >---
|
|
338 |
: "cc"
|
|
339 |
);
|
|
340 |
}
|
|
341 |
}
|
|
342 |
|
|
343 |
inline void Atomic::dec_ptr(volatile intptr_t* dest) {
|
|
344 |
unsigned long old, upd;
|
|
345 |
|
|
346 |
if (VM_Version::has_LoadAndALUAtomicV1()) {
|
|
347 |
__asm__ __volatile__ (
|
|
348 |
" LGHI 2,-1 \n\t" // load increment
|
|
349 |
" LA 3,%[mem] \n\t" // force data address into ARG2
|
|
350 |
// " LAAG %[upd],%[inc],%[mem] \n\t" // increment and get old value
|
|
351 |
// " LAAG 2,2,0(3) \n\t" // actually coded instruction
|
|
352 |
" .byte 0xeb \n\t" // LAA main opcode
|
|
353 |
" .byte 0x22 \n\t" // R1,R3
|
|
354 |
" .byte 0x30 \n\t" // R2,disp1
|
|
355 |
" .byte 0x00 \n\t" // disp2,disp3
|
|
356 |
" .byte 0x00 \n\t" // disp4,disp5
|
|
357 |
" .byte 0xe8 \n\t" // LAA minor opcode
|
|
358 |
" AGHI 2,-1 \n\t" // calc new value in register
|
|
359 |
" LR %[upd],2 \n\t" // move to result register
|
|
360 |
//---< outputs >---
|
|
361 |
: [upd] "=&d" (upd) // write-only, updated counter value
|
|
362 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
|
|
363 |
//---< inputs >---
|
|
364 |
:
|
|
365 |
// : [inc] "a" (inc) // read-only.
|
|
366 |
//---< clobbered >---
|
|
367 |
: "cc", "r2", "r3"
|
|
368 |
);
|
|
369 |
} else {
|
|
370 |
__asm__ __volatile__ (
|
|
371 |
" LG %[old],%[mem] \n\t" // get old value
|
|
372 |
// LAY not supported by inline assembler
|
|
373 |
// "0: LAY %[upd],-1(,%[old]) \n\t" // calc result
|
|
374 |
"0: LGR %[upd],%[old] \n\t" // calc result
|
|
375 |
" AGHI %[upd],-1 \n\t"
|
|
376 |
" CSG %[old],%[upd],%[mem] \n\t" // try to xchg res with mem
|
|
377 |
" JNE 0b \n\t" // no success? -> retry
|
|
378 |
//---< outputs >---
|
|
379 |
: [old] "=&a" (old) // write-only, old counter value
|
|
380 |
, [upd] "=&d" (upd) // write-only, updated counter value
|
|
381 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
|
|
382 |
//---< inputs >---
|
|
383 |
:
|
|
384 |
//---< clobbered >---
|
|
385 |
: "cc"
|
|
386 |
);
|
|
387 |
}
|
|
388 |
}
|
|
389 |
|
|
390 |
inline void Atomic::dec_ptr(volatile void* dest) {
|
|
391 |
dec_ptr((volatile intptr_t*)dest);
|
|
392 |
}
|
|
393 |
|
|
394 |
//-------------
|
|
395 |
// Atomic::xchg
|
|
396 |
//-------------
|
|
397 |
// These methods force the value in memory to be replaced by the new value passed
|
|
398 |
// in as argument.
|
|
399 |
//
|
|
400 |
// The value in memory is replaced by using a compare-and-swap instruction. The
|
|
401 |
// instruction is retried as often as required. This makes sure that the new
|
|
402 |
// value can be seen, at least for a very short period of time, by other CPUs.
|
|
403 |
//
|
|
404 |
// If we would use a normal "load(old value) store(new value)" sequence,
|
|
405 |
// the new value could be lost unnoticed, due to a store(new value) from
|
|
406 |
// another thread.
|
|
407 |
//
|
|
408 |
// The return value is the (unchanged) value from memory as it was when the
|
|
409 |
// replacement succeeded.
|
|
410 |
inline jint Atomic::xchg (jint xchg_val, volatile jint* dest) {
|
|
411 |
unsigned int old;
|
|
412 |
|
|
413 |
__asm__ __volatile__ (
|
|
414 |
" LLGF %[old],%[mem] \n\t" // get old value
|
|
415 |
"0: CS %[old],%[upd],%[mem] \n\t" // try to xchg upd with mem
|
|
416 |
" JNE 0b \n\t" // no success? -> retry
|
|
417 |
//---< outputs >---
|
|
418 |
: [old] "=&d" (old) // write-only, prev value irrelevant
|
|
419 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
|
|
420 |
//---< inputs >---
|
|
421 |
: [upd] "d" (xchg_val) // read-only, value to be written to memory
|
|
422 |
//---< clobbered >---
|
|
423 |
: "cc"
|
|
424 |
);
|
|
425 |
|
|
426 |
return (jint)old;
|
|
427 |
}
|
|
428 |
|
|
429 |
inline intptr_t Atomic::xchg_ptr(intptr_t xchg_val, volatile intptr_t* dest) {
|
|
430 |
unsigned long old;
|
|
431 |
|
|
432 |
__asm__ __volatile__ (
|
|
433 |
" LG %[old],%[mem] \n\t" // get old value
|
|
434 |
"0: CSG %[old],%[upd],%[mem] \n\t" // try to xchg upd with mem
|
|
435 |
" JNE 0b \n\t" // no success? -> retry
|
|
436 |
//---< outputs >---
|
|
437 |
: [old] "=&d" (old) // write-only, init from memory
|
|
438 |
, [mem] "+Q" (*dest) // read/write, memory to be updated atomically
|
|
439 |
//---< inputs >---
|
|
440 |
: [upd] "d" (xchg_val) // read-only, value to be written to memory
|
|
441 |
//---< clobbered >---
|
|
442 |
: "cc"
|
|
443 |
);
|
|
444 |
|
|
445 |
return (intptr_t)old;
|
|
446 |
}
|
|
447 |
|
|
448 |
inline void *Atomic::xchg_ptr(void *exchange_value, volatile void *dest) {
|
|
449 |
return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest);
|
|
450 |
}
|
|
451 |
|
|
452 |
//----------------
|
|
453 |
// Atomic::cmpxchg
|
|
454 |
//----------------
|
|
455 |
// These methods compare the value in memory with a given compare value.
|
|
456 |
// If both values compare equal, the value in memory is replaced with
|
|
457 |
// the exchange value.
|
|
458 |
//
|
|
459 |
// The value in memory is compared and replaced by using a compare-and-swap
|
|
460 |
// instruction. The instruction is NOT retried (one shot only).
|
|
461 |
//
|
|
462 |
// The return value is the (unchanged) value from memory as it was when the
|
|
463 |
// compare-and-swap instruction completed. A successful exchange operation
|
|
464 |
// is indicated by (return value == compare_value). If unsuccessful, a new
|
|
465 |
// exchange value can be calculated based on the return value which is the
|
|
466 |
// latest contents of the memory location.
|
|
467 |
//
|
|
468 |
// Inspecting the return value is the only way for the caller to determine
|
|
469 |
// if the compare-and-swap instruction was successful:
|
|
470 |
// - If return value and compare value compare equal, the compare-and-swap
|
|
471 |
// instruction was successful and the value in memory was replaced by the
|
|
472 |
// exchange value.
|
|
473 |
// - If return value and compare value compare unequal, the compare-and-swap
|
|
474 |
// instruction was not successful. The value in memory was left unchanged.
|
|
475 |
//
|
|
476 |
// The s390 processors always fence before and after the csg instructions.
|
|
477 |
// Thus we ignore the memory ordering argument. The docu says: "A serialization
|
|
478 |
// function is performed before the operand is fetched and again after the
|
|
479 |
// operation is completed."
|
|
480 |
|
|
481 |
jint Atomic::cmpxchg(jint xchg_val, volatile jint* dest, jint cmp_val, cmpxchg_memory_order unused) {
|
|
482 |
unsigned long old;
|
|
483 |
|
|
484 |
__asm__ __volatile__ (
|
|
485 |
" CS %[old],%[upd],%[mem] \n\t" // Try to xchg upd with mem.
|
|
486 |
// outputs
|
|
487 |
: [old] "=&d" (old) // Write-only, prev value irrelevant.
|
|
488 |
, [mem] "+Q" (*dest) // Read/write, memory to be updated atomically.
|
|
489 |
// inputs
|
|
490 |
: [upd] "d" (xchg_val)
|
|
491 |
, "0" (cmp_val) // Read-only, initial value for [old] (operand #0).
|
|
492 |
// clobbered
|
|
493 |
: "cc"
|
|
494 |
);
|
|
495 |
|
|
496 |
return (jint)old;
|
|
497 |
}
|
|
498 |
|
|
499 |
jlong Atomic::cmpxchg(jlong xchg_val, volatile jlong* dest, jlong cmp_val, cmpxchg_memory_order unused) {
|
|
500 |
unsigned long old;
|
|
501 |
|
|
502 |
__asm__ __volatile__ (
|
|
503 |
" CSG %[old],%[upd],%[mem] \n\t" // Try to xchg upd with mem.
|
|
504 |
// outputs
|
|
505 |
: [old] "=&d" (old) // Write-only, prev value irrelevant.
|
|
506 |
, [mem] "+Q" (*dest) // Read/write, memory to be updated atomically.
|
|
507 |
// inputs
|
|
508 |
: [upd] "d" (xchg_val)
|
|
509 |
, "0" (cmp_val) // Read-only, initial value for [old] (operand #0).
|
|
510 |
// clobbered
|
|
511 |
: "cc"
|
|
512 |
);
|
|
513 |
|
|
514 |
return (jlong)old;
|
|
515 |
}
|
|
516 |
|
|
517 |
void* Atomic::cmpxchg_ptr(void *xchg_val, volatile void* dest, void* cmp_val, cmpxchg_memory_order unused) {
|
|
518 |
return (void*)cmpxchg((jlong)xchg_val, (volatile jlong*)dest, (jlong)cmp_val, unused);
|
|
519 |
}
|
|
520 |
|
|
521 |
intptr_t Atomic::cmpxchg_ptr(intptr_t xchg_val, volatile intptr_t* dest, intptr_t cmp_val, cmpxchg_memory_order unused) {
|
|
522 |
return (intptr_t)cmpxchg((jlong)xchg_val, (volatile jlong*)dest, (jlong)cmp_val, unused);
|
|
523 |
}
|
|
524 |
|
|
525 |
inline jlong Atomic::load(volatile jlong* src) { return *src; }
|
|
526 |
|
|
527 |
#endif // OS_CPU_LINUX_S390_VM_ATOMIC_LINUX_S390_INLINE_HPP
|