10565
|
1 |
/*
|
|
2 |
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
|
|
3 |
* Copyright 2007, 2008, 2009 Red Hat, Inc.
|
|
4 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
|
5 |
*
|
|
6 |
* This code is free software; you can redistribute it and/or modify it
|
|
7 |
* under the terms of the GNU General Public License version 2 only, as
|
|
8 |
* published by the Free Software Foundation.
|
|
9 |
*
|
|
10 |
* This code is distributed in the hope that it will be useful, but WITHOUT
|
|
11 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
12 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
13 |
* version 2 for more details (a copy is included in the LICENSE file that
|
|
14 |
* accompanied this code).
|
|
15 |
*
|
|
16 |
* You should have received a copy of the GNU General Public License version
|
|
17 |
* 2 along with this work; if not, write to the Free Software Foundation,
|
|
18 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
|
19 |
*
|
|
20 |
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
|
21 |
* or visit www.oracle.com if you need additional information or have any
|
|
22 |
* questions.
|
|
23 |
*
|
|
24 |
*/
|
|
25 |
|
|
26 |
#ifndef OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP
|
|
27 |
#define OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP
|
|
28 |
|
|
29 |
#include "runtime/orderAccess.hpp"
|
|
30 |
#include "vm_version_zero.hpp"
|
|
31 |
|
|
32 |
#ifdef ARM
|
|
33 |
|
|
34 |
/*
|
|
35 |
* ARM Kernel helper for memory barrier.
|
|
36 |
* Using __asm __volatile ("":::"memory") does not work reliable on ARM
|
|
37 |
* and gcc __sync_synchronize(); implementation does not use the kernel
|
|
38 |
* helper for all gcc versions so it is unreliable to use as well.
|
|
39 |
*/
|
|
40 |
typedef void (__kernel_dmb_t) (void);
|
|
41 |
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
|
|
42 |
|
|
43 |
#define FULL_MEM_BARRIER __kernel_dmb()
|
|
44 |
#define READ_MEM_BARRIER __kernel_dmb()
|
|
45 |
#define WRITE_MEM_BARRIER __kernel_dmb()
|
|
46 |
|
|
47 |
#else // ARM
|
|
48 |
|
|
49 |
#define FULL_MEM_BARRIER __sync_synchronize()
|
|
50 |
|
|
51 |
#ifdef PPC
|
|
52 |
|
|
53 |
#ifdef __NO_LWSYNC__
|
|
54 |
#define READ_MEM_BARRIER __asm __volatile ("sync":::"memory")
|
|
55 |
#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
|
|
56 |
#else
|
|
57 |
#define READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
|
|
58 |
#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
|
|
59 |
#endif
|
|
60 |
|
|
61 |
#else // PPC
|
|
62 |
|
|
63 |
#define READ_MEM_BARRIER __asm __volatile ("":::"memory")
|
|
64 |
#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
|
|
65 |
|
|
66 |
#endif // PPC
|
|
67 |
|
|
68 |
#endif // ARM
|
|
69 |
|
|
70 |
|
|
71 |
inline void OrderAccess::loadload() { acquire(); }
|
|
72 |
inline void OrderAccess::storestore() { release(); }
|
|
73 |
inline void OrderAccess::loadstore() { acquire(); }
|
|
74 |
inline void OrderAccess::storeload() { fence(); }
|
|
75 |
|
|
76 |
inline void OrderAccess::acquire() {
|
|
77 |
READ_MEM_BARRIER;
|
|
78 |
}
|
|
79 |
|
|
80 |
inline void OrderAccess::release() {
|
|
81 |
WRITE_MEM_BARRIER;
|
|
82 |
}
|
|
83 |
|
|
84 |
inline void OrderAccess::fence() {
|
|
85 |
FULL_MEM_BARRIER;
|
|
86 |
}
|
|
87 |
|
|
88 |
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; }
|
|
89 |
inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; }
|
|
90 |
inline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; }
|
|
91 |
inline jlong OrderAccess::load_acquire(volatile jlong* p) {
|
|
92 |
jlong tmp;
|
|
93 |
os::atomic_copy64(p, &tmp);
|
|
94 |
acquire();
|
|
95 |
return tmp;
|
|
96 |
}
|
|
97 |
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; }
|
|
98 |
inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; }
|
|
99 |
inline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; }
|
|
100 |
inline julong OrderAccess::load_acquire(volatile julong* p) {
|
|
101 |
julong tmp;
|
|
102 |
os::atomic_copy64(p, &tmp);
|
|
103 |
acquire();
|
|
104 |
return tmp;
|
|
105 |
}
|
|
106 |
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; }
|
|
107 |
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) {
|
|
108 |
jdouble tmp;
|
|
109 |
os::atomic_copy64(p, &tmp);
|
|
110 |
acquire();
|
|
111 |
return tmp;
|
|
112 |
}
|
|
113 |
|
|
114 |
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) {
|
|
115 |
intptr_t data = *p;
|
|
116 |
acquire();
|
|
117 |
return data;
|
|
118 |
}
|
|
119 |
inline void* OrderAccess::load_ptr_acquire(volatile void* p) {
|
|
120 |
void *data = *(void* volatile *)p;
|
|
121 |
acquire();
|
|
122 |
return data;
|
|
123 |
}
|
|
124 |
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) {
|
|
125 |
void *data = *(void* const volatile *)p;
|
|
126 |
acquire();
|
|
127 |
return data;
|
|
128 |
}
|
|
129 |
|
|
130 |
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; }
|
|
131 |
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; }
|
|
132 |
inline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; }
|
|
133 |
inline void OrderAccess::release_store(volatile jlong* p, jlong v)
|
|
134 |
{ release(); os::atomic_copy64(&v, p); }
|
|
135 |
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; }
|
|
136 |
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; }
|
|
137 |
inline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; }
|
|
138 |
inline void OrderAccess::release_store(volatile julong* p, julong v)
|
|
139 |
{ release(); os::atomic_copy64(&v, p); }
|
|
140 |
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; }
|
|
141 |
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v)
|
|
142 |
{ release(); os::atomic_copy64(&v, p); }
|
|
143 |
|
|
144 |
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; }
|
|
145 |
inline void OrderAccess::release_store_ptr(volatile void* p, void* v)
|
|
146 |
{ release(); *(void* volatile *)p = v; }
|
|
147 |
|
|
148 |
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
|
|
149 |
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
|
|
150 |
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
|
|
151 |
inline void OrderAccess::store_fence(jlong* p, jlong v) { os::atomic_copy64(&v, p); fence(); }
|
|
152 |
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
|
|
153 |
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
|
|
154 |
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
|
|
155 |
inline void OrderAccess::store_fence(julong* p, julong v) { os::atomic_copy64(&v, p); fence(); }
|
|
156 |
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
|
|
157 |
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { os::atomic_copy64(&v, p); fence(); }
|
|
158 |
|
|
159 |
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
|
|
160 |
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
|
|
161 |
|
|
162 |
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); }
|
|
163 |
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); }
|
|
164 |
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); }
|
|
165 |
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
|
|
166 |
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); }
|
|
167 |
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); }
|
|
168 |
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); }
|
|
169 |
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); }
|
|
170 |
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); }
|
|
171 |
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); }
|
|
172 |
|
|
173 |
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); }
|
|
174 |
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); }
|
|
175 |
|
|
176 |
#endif // OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP
|