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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_S390_VM_MACROASSEMBLER_S390_INLINE_HPP
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#define CPU_S390_VM_MACROASSEMBLER_S390_INLINE_HPP
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#include "asm/assembler.inline.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/codeBuffer.hpp"
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#include "code/codeCache.hpp"
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#include "runtime/thread.hpp"
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// Simplified shift operations for single register operands, constant shift amount.
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inline void MacroAssembler::lshift(Register r, int places, bool is_DW) {
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if (is_DW) {
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z_sllg(r, r, places);
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} else {
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z_sll(r, places);
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}
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}
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inline void MacroAssembler::rshift(Register r, int places, bool is_DW) {
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if (is_DW) {
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z_srlg(r, r, places);
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} else {
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z_srl(r, places);
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}
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}
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// *((int8_t*)(dst)) |= imm8
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inline void MacroAssembler::or2mem_8(Address& dst, int64_t imm8) {
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if (Displacement::is_shortDisp(dst.disp())) {
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z_oi(dst, imm8);
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} else {
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z_oiy(dst, imm8);
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}
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}
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inline int MacroAssembler::store_const(const Address &dest, long imm, Register scratch, bool is_long) {
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unsigned int lm = is_long ? 8 : 4;
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unsigned int lc = is_long ? 8 : 4;
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return store_const(dest, imm, lm, lc, scratch);
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}
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// Do not rely on add2reg* emitter.
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// Depending on CmdLine switches and actual parameter values,
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// the generated code may alter the condition code, which is counter-intuitive
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// to the semantics of the "load address" (LA/LAY) instruction.
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// Generic address loading d <- base(a) + index(a) + disp(a)
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inline void MacroAssembler::load_address(Register d, const Address &a) {
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if (Displacement::is_shortDisp(a.disp())) {
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z_la(d, a.disp(), a.indexOrR0(), a.baseOrR0());
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} else if (Displacement::is_validDisp(a.disp())) {
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z_lay(d, a.disp(), a.indexOrR0(), a.baseOrR0());
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} else {
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guarantee(false, "displacement = " SIZE_FORMAT_HEX ", out of range for LA/LAY", a.disp());
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}
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}
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inline void MacroAssembler::load_const(Register t, void* x) {
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load_const(t, (long)x);
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}
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// Load a 64 bit constant encoded by a `Label'.
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// Works for bound as well as unbound labels. For unbound labels, the
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// code will become patched as soon as the label gets bound.
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inline void MacroAssembler::load_const(Register t, Label& L) {
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load_const(t, target(L));
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}
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inline void MacroAssembler::load_const(Register t, const AddressLiteral& a) {
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assert(t != Z_R0, "R0 not allowed");
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// First relocate (we don't change the offset in the RelocationHolder,
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// just pass a.rspec()), then delegate to load_const(Register, long).
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relocate(a.rspec());
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load_const(t, (long)a.value());
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}
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inline void MacroAssembler::load_const_optimized(Register t, long x) {
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(void) load_const_optimized_rtn_len(t, x, true);
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}
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inline void MacroAssembler::load_const_optimized(Register t, void* a) {
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load_const_optimized(t, (long)a);
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}
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inline void MacroAssembler::load_const_optimized(Register t, Label& L) {
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load_const_optimized(t, target(L));
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}
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inline void MacroAssembler::load_const_optimized(Register t, const AddressLiteral& a) {
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assert(t != Z_R0, "R0 not allowed");
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assert((relocInfo::relocType)a.rspec().reloc()->type() == relocInfo::none,
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"cannot relocate optimized load_consts");
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load_const_optimized(t, a.value());
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}
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inline void MacroAssembler::set_oop(jobject obj, Register d) {
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load_const(d, allocate_oop_address(obj));
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}
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inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
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load_const(d, constant_oop_address(obj));
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}
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// Adds MetaData constant md to TOC and loads it from there.
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// md is added to the oop_recorder, but no relocation is added.
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inline bool MacroAssembler::set_metadata_constant(Metadata* md, Register d) {
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AddressLiteral a = constant_metadata_address(md);
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return load_const_from_toc(d, a, d); // Discards the relocation.
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}
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inline bool MacroAssembler::is_call_pcrelative_short(unsigned long inst) {
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return is_equal(inst, BRAS_ZOPC); // off 16, len 16
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}
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inline bool MacroAssembler::is_call_pcrelative_long(unsigned long inst) {
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return is_equal(inst, BRASL_ZOPC); // off 16, len 32
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}
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inline bool MacroAssembler::is_branch_pcrelative_short(unsigned long inst) {
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// Branch relative, 16-bit offset.
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return is_equal(inst, BRC_ZOPC); // off 16, len 16
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}
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inline bool MacroAssembler::is_branch_pcrelative_long(unsigned long inst) {
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// Branch relative, 32-bit offset.
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return is_equal(inst, BRCL_ZOPC); // off 16, len 32
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}
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inline bool MacroAssembler::is_compareandbranch_pcrelative_short(unsigned long inst) {
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// Compare and branch relative, 16-bit offset.
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return is_equal(inst, CRJ_ZOPC, CMPBRANCH_MASK) || is_equal(inst, CGRJ_ZOPC, CMPBRANCH_MASK) ||
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is_equal(inst, CIJ_ZOPC, CMPBRANCH_MASK) || is_equal(inst, CGIJ_ZOPC, CMPBRANCH_MASK) ||
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is_equal(inst, CLRJ_ZOPC, CMPBRANCH_MASK) || is_equal(inst, CLGRJ_ZOPC, CMPBRANCH_MASK) ||
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is_equal(inst, CLIJ_ZOPC, CMPBRANCH_MASK) || is_equal(inst, CLGIJ_ZOPC, CMPBRANCH_MASK);
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}
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inline bool MacroAssembler::is_branchoncount_pcrelative_short(unsigned long inst) {
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// Branch relative on count, 16-bit offset.
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return is_equal(inst, BRCT_ZOPC) || is_equal(inst, BRCTG_ZOPC); // off 16, len 16
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}
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inline bool MacroAssembler::is_branchonindex32_pcrelative_short(unsigned long inst) {
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// Branch relative on index (32bit), 16-bit offset.
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return is_equal(inst, BRXH_ZOPC) || is_equal(inst, BRXLE_ZOPC); // off 16, len 16
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}
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inline bool MacroAssembler::is_branchonindex64_pcrelative_short(unsigned long inst) {
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// Branch relative on index (64bit), 16-bit offset.
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return is_equal(inst, BRXHG_ZOPC) || is_equal(inst, BRXLG_ZOPC); // off 16, len 16
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}
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inline bool MacroAssembler::is_branchonindex_pcrelative_short(unsigned long inst) {
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return is_branchonindex32_pcrelative_short(inst) ||
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is_branchonindex64_pcrelative_short(inst);
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}
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inline bool MacroAssembler::is_branch_pcrelative16(unsigned long inst) {
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return is_branch_pcrelative_short(inst) ||
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is_compareandbranch_pcrelative_short(inst) ||
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is_branchoncount_pcrelative_short(inst) ||
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is_branchonindex_pcrelative_short(inst);
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}
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inline bool MacroAssembler::is_branch_pcrelative32(unsigned long inst) {
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return is_branch_pcrelative_long(inst);
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}
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inline bool MacroAssembler::is_branch_pcrelative(unsigned long inst) {
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return is_branch_pcrelative16(inst) ||
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is_branch_pcrelative32(inst);
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}
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inline bool MacroAssembler::is_load_pcrelative_long(unsigned long inst) {
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// Load relative, 32-bit offset.
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return is_equal(inst, LRL_ZOPC, REL_LONG_MASK) || is_equal(inst, LGRL_ZOPC, REL_LONG_MASK); // off 16, len 32
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}
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inline bool MacroAssembler::is_misc_pcrelative_long(unsigned long inst) {
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// Load address, execute relative, 32-bit offset.
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return is_equal(inst, LARL_ZOPC, REL_LONG_MASK) || is_equal(inst, EXRL_ZOPC, REL_LONG_MASK); // off 16, len 32
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}
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inline bool MacroAssembler::is_pcrelative_short(unsigned long inst) {
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return is_branch_pcrelative16(inst) ||
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is_call_pcrelative_short(inst);
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}
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inline bool MacroAssembler::is_pcrelative_long(unsigned long inst) {
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return is_branch_pcrelative32(inst) ||
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is_call_pcrelative_long(inst) ||
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is_load_pcrelative_long(inst) ||
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is_misc_pcrelative_long(inst);
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}
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inline bool MacroAssembler::is_load_pcrelative_long(address iLoc) {
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unsigned long inst;
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unsigned int len = get_instruction(iLoc, &inst);
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return (len == 6) && is_load_pcrelative_long(inst);
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}
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inline bool MacroAssembler::is_pcrelative_short(address iLoc) {
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unsigned long inst;
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unsigned int len = get_instruction(iLoc, &inst);
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return ((len == 4) || (len == 6)) && is_pcrelative_short(inst);
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}
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inline bool MacroAssembler::is_pcrelative_long(address iLoc) {
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unsigned long inst;
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unsigned int len = get_instruction(iLoc, &inst);
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return (len == 6) && is_pcrelative_long(inst);
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}
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// Dynamic TOC. Test for any pc-relative instruction.
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inline bool MacroAssembler::is_pcrelative_instruction(address iloc) {
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unsigned long inst;
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get_instruction(iloc, &inst);
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return is_pcrelative_short(inst) ||
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is_pcrelative_long(inst);
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}
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inline bool MacroAssembler::is_load_addr_pcrel(address a) {
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return is_equal(a, LARL_ZOPC, LARL_MASK);
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}
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// Save the return pc in the register that should be stored as the return pc
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// in the current frame (default is R14).
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inline void MacroAssembler::save_return_pc(Register pc) {
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z_stg(pc, _z_abi16(return_pc), Z_SP);
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}
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inline void MacroAssembler::restore_return_pc() {
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z_lg(Z_R14, _z_abi16(return_pc), Z_SP);
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}
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// Call a function with given entry.
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inline address MacroAssembler::call(Register function_entry) {
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assert(function_entry != Z_R0, "function_entry cannot be Z_R0");
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Assembler::z_basr(Z_R14, function_entry);
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_last_calls_return_pc = pc();
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return _last_calls_return_pc;
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}
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// Call a C function via a function entry.
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inline address MacroAssembler::call_c(Register function_entry) {
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return call(function_entry);
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}
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// Call a stub function via a function descriptor, but don't save TOC before
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// call, don't setup TOC and ENV for call, and don't restore TOC after call
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inline address MacroAssembler::call_stub(Register function_entry) {
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return call_c(function_entry);
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}
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inline address MacroAssembler::call_stub(address function_entry) {
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return call_c(function_entry);
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}
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// Get the pc where the last emitted call will return to.
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inline address MacroAssembler::last_calls_return_pc() {
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return _last_calls_return_pc;
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}
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inline void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) {
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set_last_Java_frame(last_Java_sp, last_Java_pc, true);
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}
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inline void MacroAssembler::set_last_Java_frame_static(Register last_Java_sp, Register last_Java_pc) {
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set_last_Java_frame(last_Java_sp, last_Java_pc, false);
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}
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inline void MacroAssembler::reset_last_Java_frame(void) {
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reset_last_Java_frame(true);
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}
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inline void MacroAssembler::reset_last_Java_frame_static(void) {
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reset_last_Java_frame(false);
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}
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inline void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1) {
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set_top_ijava_frame_at_SP_as_last_Java_frame(sp, tmp1, true);
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}
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inline void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame_static(Register sp, Register tmp1) {
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set_top_ijava_frame_at_SP_as_last_Java_frame(sp, tmp1, true);
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}
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#endif // CPU_S390_VM_MACROASSEMBLER_S390_INLINE_HPP
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