/*

 * Copyright (c) 2005, 2009, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

# include "incls/_precompiled.incl"

# include "incls/_c1_LIRGenerator_x86.cpp.incl"

#ifdef ASSERT

#define __ gen()->lir(__FILE__, __LINE__)->

#else

#define __ gen()->lir()->

#endif

// Item will be loaded into a byte register; Intel only

void LIRItem::load_byte_item() {

  load_item();

  LIR_Opr res = result();

  if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {

    // make sure that it is a byte register

    assert(!value()->type()->is_float() && !value()->type()->is_double(),

           "can't load floats in byte register");

    LIR_Opr reg = _gen->rlock_byte(T_BYTE);

    __ move(res, reg);

    _result = reg;

  }

}

void LIRItem::load_nonconstant() {

  LIR_Opr r = value()->operand();

  if (r->is_constant()) {

    _result = r;

  } else {

    load_item();

  }

}

//--------------------------------------------------------------

//               LIRGenerator

//--------------------------------------------------------------

LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::rax_oop_opr; }

LIR_Opr LIRGenerator::exceptionPcOpr()  { return FrameMap::rdx_opr; }

LIR_Opr LIRGenerator::divInOpr()        { return FrameMap::rax_opr; }

LIR_Opr LIRGenerator::divOutOpr()       { return FrameMap::rax_opr; }

LIR_Opr LIRGenerator::remOutOpr()       { return FrameMap::rdx_opr; }

LIR_Opr LIRGenerator::shiftCountOpr()   { return FrameMap::rcx_opr; }

LIR_Opr LIRGenerator::syncTempOpr()     { return FrameMap::rax_opr; }

LIR_Opr LIRGenerator::getThreadTemp()   { return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {

  LIR_Opr opr;

  switch (type->tag()) {

    case intTag:     opr = FrameMap::rax_opr;          break;

    case objectTag:  opr = FrameMap::rax_oop_opr;      break;

    case longTag:    opr = FrameMap::long0_opr;        break;

    case floatTag:   opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr  : FrameMap::fpu0_float_opr;  break;

    case doubleTag:  opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr;  break;

    case addressTag:

    default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;

  }

  assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");

  return opr;

}

LIR_Opr LIRGenerator::rlock_byte(BasicType type) {

  LIR_Opr reg = new_register(T_INT);

  set_vreg_flag(reg, LIRGenerator::byte_reg);

  return reg;

}

//--------- loading items into registers --------------------------------

// i486 instructions can inline constants

bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {

  if (type == T_SHORT || type == T_CHAR) {

    // there is no immediate move of word values in asembler_i486.?pp

    return false;

  }

  Constant* c = v->as_Constant();

  if (c && c->state() == NULL) {

    // constants of any type can be stored directly, except for

    // unloaded object constants.

    return true;

  }

  return false;

}

bool LIRGenerator::can_inline_as_constant(Value v) const {

  if (v->type()->tag() == longTag) return false;

  return v->type()->tag() != objectTag ||

    (v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());

}

bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {

  if (c->type() == T_LONG) return false;

  return c->type() != T_OBJECT || c->as_jobject() == NULL;

}

LIR_Opr LIRGenerator::safepoint_poll_register() {

  return LIR_OprFact::illegalOpr;

}

LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,

                                            int shift, int disp, BasicType type) {

  assert(base->is_register(), "must be");

  if (index->is_constant()) {

    return new LIR_Address(base,

                           (index->as_constant_ptr()->as_jint() << shift) + disp,

                           type);

  } else {

    return new LIR_Address(base, index, (LIR_Address::Scale)shift, disp, type);

  }

}

LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,

                                              BasicType type, bool needs_card_mark) {

  int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);

  LIR_Address* addr;

  if (index_opr->is_constant()) {

    int elem_size = type2aelembytes(type);

    addr = new LIR_Address(array_opr,

                           offset_in_bytes + index_opr->as_jint() * elem_size, type);

  } else {

#ifdef _LP64

    if (index_opr->type() == T_INT) {

      LIR_Opr tmp = new_register(T_LONG);

      __ convert(Bytecodes::_i2l, index_opr, tmp);

      index_opr = tmp;

    }

#endif // _LP64

    addr =  new LIR_Address(array_opr,

                            index_opr,

                            LIR_Address::scale(type),

                            offset_in_bytes, type);

  }

  if (needs_card_mark) {

    // This store will need a precise card mark, so go ahead and

    // compute the full adddres instead of computing once for the

    // store and again for the card mark.

    LIR_Opr tmp = new_pointer_register();

    __ leal(LIR_OprFact::address(addr), tmp);

    return new LIR_Address(tmp, type);

  } else {

    return addr;

  }

}

void LIRGenerator::increment_counter(address counter, int step) {

  LIR_Opr pointer = new_pointer_register();

  __ move(LIR_OprFact::intptrConst(counter), pointer);

  LIR_Address* addr = new LIR_Address(pointer, T_INT);

  increment_counter(addr, step);

}

void LIRGenerator::increment_counter(LIR_Address* addr, int step) {

  __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr);

}

void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {

  __ cmp_mem_int(condition, base, disp, c, info);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {

  __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {

  __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);

}

bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {

  if (tmp->is_valid()) {

    if (is_power_of_2(c + 1)) {

      __ move(left, tmp);

      __ shift_left(left, log2_intptr(c + 1), left);

      __ sub(left, tmp, result);

      return true;

    } else if (is_power_of_2(c - 1)) {

      __ move(left, tmp);

      __ shift_left(left, log2_intptr(c - 1), left);

      __ add(left, tmp, result);

      return true;

    }

  }

  return false;

}

void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {

  BasicType type = item->type();

  __ store(item, new LIR_Address(FrameMap::rsp_opr, in_bytes(offset_from_sp), type));

}

//----------------------------------------------------------------------

//             visitor functions

//----------------------------------------------------------------------

void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {

  assert(x->is_root(),"");

  bool needs_range_check = true;

  bool use_length = x->length() != NULL;

  bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;

  bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||

                                         !get_jobject_constant(x->value())->is_null_object());

  LIRItem array(x->array(), this);

  LIRItem index(x->index(), this);

  LIRItem value(x->value(), this);

  LIRItem length(this);

  array.load_item();

  index.load_nonconstant();

  if (use_length) {

    needs_range_check = x->compute_needs_range_check();

    if (needs_range_check) {

      length.set_instruction(x->length());

      length.load_item();

    }

  }

  if (needs_store_check) {

    value.load_item();

  } else {

    value.load_for_store(x->elt_type());

  }

  set_no_result(x);

  // the CodeEmitInfo must be duplicated for each different

  // LIR-instruction because spilling can occur anywhere between two

  // instructions and so the debug information must be different

  CodeEmitInfo* range_check_info = state_for(x);

  CodeEmitInfo* null_check_info = NULL;

  if (x->needs_null_check()) {

    null_check_info = new CodeEmitInfo(range_check_info);

  }

  // emit array address setup early so it schedules better

  LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);

  if (GenerateRangeChecks && needs_range_check) {

    if (use_length) {

      __ cmp(lir_cond_belowEqual, length.result(), index.result());

      __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));

    } else {

      array_range_check(array.result(), index.result(), null_check_info, range_check_info);

      // range_check also does the null check

      null_check_info = NULL;

    }

  }

  if (GenerateArrayStoreCheck && needs_store_check) {

    LIR_Opr tmp1 = new_register(objectType);

    LIR_Opr tmp2 = new_register(objectType);

    LIR_Opr tmp3 = new_register(objectType);

    CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);

    __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info);

  }

  if (obj_store) {

    // Needs GC write barriers.

    pre_barrier(LIR_OprFact::address(array_addr), false, NULL);

    __ move(value.result(), array_addr, null_check_info);

    // Seems to be a precise

    post_barrier(LIR_OprFact::address(array_addr), value.result());

  } else {

    __ move(value.result(), array_addr, null_check_info);

  }

}

void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {

  assert(x->is_root(),"");

  LIRItem obj(x->obj(), this);

  obj.load_item();

  set_no_result(x);

  // "lock" stores the address of the monitor stack slot, so this is not an oop

  LIR_Opr lock = new_register(T_INT);

  // Need a scratch register for biased locking on x86

  LIR_Opr scratch = LIR_OprFact::illegalOpr;

  if (UseBiasedLocking) {

    scratch = new_register(T_INT);

  }

  CodeEmitInfo* info_for_exception = NULL;

  if (x->needs_null_check()) {

    info_for_exception = state_for(x, x->lock_stack_before());

  }

  // this CodeEmitInfo must not have the xhandlers because here the

  // object is already locked (xhandlers expect object to be unlocked)

  CodeEmitInfo* info = state_for(x, x->state(), true);

  monitor_enter(obj.result(), lock, syncTempOpr(), scratch,

                        x->monitor_no(), info_for_exception, info);

}

void LIRGenerator::do_MonitorExit(MonitorExit* x) {

  assert(x->is_root(),"");

  LIRItem obj(x->obj(), this);

  obj.dont_load_item();

  LIR_Opr lock = new_register(T_INT);

  LIR_Opr obj_temp = new_register(T_INT);

  set_no_result(x);

  monitor_exit(obj_temp, lock, syncTempOpr(), x->monitor_no());

}

// _ineg, _lneg, _fneg, _dneg

void LIRGenerator::do_NegateOp(NegateOp* x) {

  LIRItem value(x->x(), this);

  value.set_destroys_register();

  value.load_item();

  LIR_Opr reg = rlock(x);

  __ negate(value.result(), reg);

  set_result(x, round_item(reg));

}

// for  _fadd, _fmul, _fsub, _fdiv, _frem

//      _dadd, _dmul, _dsub, _ddiv, _drem

void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {

  LIRItem left(x->x(),  this);

  LIRItem right(x->y(), this);

  LIRItem* left_arg  = &left;

  LIRItem* right_arg = &right;

  assert(!left.is_stack() || !right.is_stack(), "can't both be memory operands");

  bool must_load_both = (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem);

  if (left.is_register() || x->x()->type()->is_constant() || must_load_both) {

    left.load_item();

  } else {

    left.dont_load_item();

  }

  // do not load right operand if it is a constant.  only 0 and 1 are

  // loaded because there are special instructions for loading them

  // without memory access (not needed for SSE2 instructions)

  bool must_load_right = false;

  if (right.is_constant()) {

    LIR_Const* c = right.result()->as_constant_ptr();

    assert(c != NULL, "invalid constant");

    assert(c->type() == T_FLOAT || c->type() == T_DOUBLE, "invalid type");

    if (c->type() == T_FLOAT) {

      must_load_right = UseSSE < 1 && (c->is_one_float() || c->is_zero_float());

    } else {

      must_load_right = UseSSE < 2 && (c->is_one_double() || c->is_zero_double());

    }

  }

  if (must_load_both) {

    // frem and drem destroy also right operand, so move it to a new register

    right.set_destroys_register();

    right.load_item();

  } else if (right.is_register() || must_load_right) {

    right.load_item();

  } else {

    right.dont_load_item();

  }

  LIR_Opr reg = rlock(x);

  LIR_Opr tmp = LIR_OprFact::illegalOpr;

  if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) {

    tmp = new_register(T_DOUBLE);

  }

  if ((UseSSE >= 1 && x->op() == Bytecodes::_frem) || (UseSSE >= 2 && x->op() == Bytecodes::_drem)) {

    // special handling for frem and drem: no SSE instruction, so must use FPU with temporary fpu stack slots

    LIR_Opr fpu0, fpu1;

    if (x->op() == Bytecodes::_frem) {

      fpu0 = LIR_OprFact::single_fpu(0);

      fpu1 = LIR_OprFact::single_fpu(1);

    } else {

      fpu0 = LIR_OprFact::double_fpu(0);

      fpu1 = LIR_OprFact::double_fpu(1);

    }

    __ move(right.result(), fpu1); // order of left and right operand is important!

    __ move(left.result(), fpu0);

    __ rem (fpu0, fpu1, fpu0);

    __ move(fpu0, reg);

  } else {

    arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp);

  }

  set_result(x, round_item(reg));

}

// for  _ladd, _lmul, _lsub, _ldiv, _lrem

void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {

  if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem ) {

    // long division is implemented as a direct call into the runtime

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    // the check for division by zero destroys the right operand

    right.set_destroys_register();

    BasicTypeList signature(2);

    signature.append(T_LONG);

    signature.append(T_LONG);

    CallingConvention* cc = frame_map()->c_calling_convention(&signature);

    // check for division by zero (destroys registers of right operand!)

    CodeEmitInfo* info = state_for(x);

    const LIR_Opr result_reg = result_register_for(x->type());

    left.load_item_force(cc->at(1));

    right.load_item();

    __ move(right.result(), cc->at(0));

    __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));

    __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));

    address entry;

    switch (x->op()) {

    case Bytecodes::_lrem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem);

      break; // check if dividend is 0 is done elsewhere

    case Bytecodes::_ldiv:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv);

      break; // check if dividend is 0 is done elsewhere

    case Bytecodes::_lmul:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul);

      break;

    default:

      ShouldNotReachHere();

    }

    LIR_Opr result = rlock_result(x);

    __ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args());

    __ move(result_reg, result);

  } else if (x->op() == Bytecodes::_lmul) {

    // missing test if instr is commutative and if we should swap

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    // right register is destroyed by the long mul, so it must be

    // copied to a new register.

    right.set_destroys_register();

    left.load_item();

    right.load_item();

    LIR_Opr reg = FrameMap::long0_opr;

    arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);

    LIR_Opr result = rlock_result(x);

    __ move(reg, result);

  } else {

    // missing test if instr is commutative and if we should swap

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    left.load_item();

    // don't load constants to save register

    right.load_nonconstant();

    rlock_result(x);

    arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);

  }

}

// for: _iadd, _imul, _isub, _idiv, _irem

void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {

  if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {

    // The requirements for division and modulo

    // input : rax,: dividend                         min_int

    //         reg: divisor   (may not be rax,/rdx)   -1

    //

    // output: rax,: quotient  (= rax, idiv reg)       min_int

    //         rdx: remainder (= rax, irem reg)       0

    // rax, and rdx will be destroyed

    // Note: does this invalidate the spec ???