author | vlivanov |
Wed, 24 Jul 2019 10:50:40 +0300 | |
changeset 57574 | 6a159c6c23cc |
parent 53244 | 9807daeb47c4 |
child 57583 | aad50831e169 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2016 SAP SE. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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// Major contributions by AHa, JL, LS |
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#ifndef CPU_S390_NATIVEINST_S390_HPP |
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#define CPU_S390_NATIVEINST_S390_HPP |
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#include "asm/macroAssembler.hpp" |
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#include "runtime/icache.hpp" |
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#include "runtime/os.hpp" |
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class NativeCall; |
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class NativeFarCall; |
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class NativeMovConstReg; |
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class NativeJump; |
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#ifndef COMPILER2 |
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class NativeGeneralJump; |
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class NativeMovRegMem; |
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#endif |
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class NativeInstruction; |
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NativeCall* nativeCall_before(address return_address); |
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NativeCall* nativeCall_at(address instr); |
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NativeFarCall* nativeFarCall_before(address return_address); |
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NativeFarCall* nativeFarCall_at(address instr); |
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NativeMovConstReg* nativeMovConstReg_at(address address); |
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NativeMovConstReg* nativeMovConstReg_before(address address); |
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NativeJump* nativeJump_at(address address); |
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#ifndef COMPILER2 |
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NativeMovRegMem* nativeMovRegMem_at (address address); |
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NativeGeneralJump* nativeGeneralJump_at(address address); |
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#endif |
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NativeInstruction* nativeInstruction_at(address address); |
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// We have interface for the following instructions: |
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// - NativeInstruction |
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// - NativeCall |
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// - NativeFarCall |
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// - NativeMovConstReg |
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// - NativeMovRegMem |
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// - NativeJump |
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// - NativeGeneralJump |
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// - NativeIllegalInstruction |
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// The base class for different kinds of native instruction abstractions. |
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// Provides the primitive operations to manipulate code relative to this. |
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//------------------------------------- |
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// N a t i v e I n s t r u c t i o n |
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//------------------------------------- |
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class NativeInstruction { |
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friend class Relocation; |
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public: |
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enum z_specific_constants { |
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nop_instruction_size = 2 |
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}; |
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bool is_illegal(); |
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// Bcrl is currently the only accepted instruction here. |
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bool is_jump(); |
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// We use an illtrap for marking a method as not_entrant or zombie. |
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bool is_sigill_zombie_not_entrant(); |
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bool is_safepoint_poll() { |
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// Is the current instruction a POTENTIAL read access to the polling page? |
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// The instruction's current arguments are not checked! |
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return MacroAssembler::is_load_from_polling_page(addr_at(0)); |
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} |
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address get_poll_address(void *ucontext) { |
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// Extract poll address from instruction and ucontext. |
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return MacroAssembler::get_poll_address(addr_at(0), ucontext); |
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} |
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uint get_poll_register() { |
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// Extract poll register from instruction. |
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return MacroAssembler::get_poll_register(addr_at(0)); |
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} |
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public: |
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// The output of __ breakpoint_trap(). |
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static int illegal_instruction(); |
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// The address of the currently processed instruction. |
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address instruction_address() const { return addr_at(0); } |
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protected: |
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address addr_at(int offset) const { return address(this) + offset; } |
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// z/Architecture terminology |
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// halfword = 2 bytes |
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// word = 4 bytes |
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// doubleword = 8 bytes |
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unsigned short halfword_at(int offset) const { return *(unsigned short*)addr_at(offset); } |
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int word_at(int offset) const { return *(jint*)addr_at(offset); } |
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long long_at(int offset) const { return *(jlong*)addr_at(offset); } |
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void set_halfword_at(int offset, short i); // Deals with I-cache. |
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void set_word_at(int offset, int i); // Deals with I-cache. |
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void set_jlong_at(int offset, jlong i); // Deals with I-cache. |
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void set_addr_at(int offset, address x); // Deals with I-cache. |
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void print() const; |
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void print(const char* msg) const; |
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void dump() const; |
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void dump(const unsigned int range) const; |
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void dump(const unsigned int range, const char* msg) const; |
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public: |
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void verify(); |
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// unit test stuff |
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static void test() {} // Override for testing. |
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friend NativeInstruction* nativeInstruction_at(address address) { |
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NativeInstruction* inst = (NativeInstruction*)address; |
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#ifdef ASSERT |
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inst->verify(); |
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#endif |
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return inst; |
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} |
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}; |
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//--------------------------------------------------- |
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// N a t i v e I l l e g a l I n s t r u c t i o n |
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//--------------------------------------------------- |
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class NativeIllegalInstruction: public NativeInstruction { |
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public: |
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enum z_specific_constants { |
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instruction_size = 2 |
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}; |
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// Insert illegal opcode at specific address. |
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static void insert(address code_pos); |
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}; |
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//----------------------- |
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// N a t i v e C a l l |
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//----------------------- |
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// The NativeCall is an abstraction for accessing/manipulating call |
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// instructions. It is used to manipulate inline caches, primitive & |
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// dll calls, etc. |
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// A native call, as defined by this abstraction layer, consists of |
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// all instructions required to set up for and actually make the call. |
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// |
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// On z/Architecture, there exist three different forms of native calls: |
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// 1) Call with pc-relative address, 1 instruction |
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// The location of the target function is encoded as relative address |
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// in the call instruction. The short form (BRAS) allows for a |
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// 16-bit signed relative address (in 2-byte units). The long form |
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// (BRASL) allows for a 32-bit signed relative address (in 2-byte units). |
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// 2) Call with immediate address, 3 or 5 instructions. |
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// The location of the target function is given by an immediate |
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// constant which is loaded into a (scratch) register. Depending on |
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// the hardware capabilities, this takes 2 or 4 instructions. |
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// The call itself is then a "call by register"(BASR) instruction. |
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// 3) Call with address from constant pool, 2(3) instructions (with dynamic TOC) |
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// The location of the target function is stored in the constant pool |
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// during compilation. From there it is loaded into a (scratch) register. |
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// The call itself is then a "call by register"(BASR) instruction. |
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// |
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// When initially generating a call, the compiler uses form 2) (not |
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// patchable, target address constant, e.g. runtime calls) or 3) (patchable, |
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// target address might eventually get relocated). Later in the process, |
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// a call could be transformed into form 1) (also patchable) during ShortenBranches. |
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// |
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// If a call is/has to be patchable, the instruction sequence generated for it |
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// has to be constant in length. Excessive space, created e.g. by ShortenBranches, |
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// is allocated to lower addresses and filled with nops. That is necessary to |
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// keep the return address constant, no matter what form the call has. |
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// Methods dealing with such calls have "patchable" as part of their name. |
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class NativeCall: public NativeInstruction { |
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public: |
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static int get_IC_pos_in_java_to_interp_stub() { |
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return 0; |
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} |
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enum z_specific_constants { |
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instruction_size = 18, // Used in shared code for calls with reloc_info: |
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// value correct if !has_long_displacement_fast(). |
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call_far_pcrelative_displacement_offset = 4, // Includes 2 bytes for the nop. |
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call_far_pcrelative_displacement_alignment = 4 |
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}; |
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// Maximum size (in bytes) of a call to an absolute address. |
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// Used when emitting call to deopt handler blob, which is a |
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// "load_const_call". The code pattern is: |
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// tmpReg := load_const(address); (* depends on CPU ArchLvl, but is otherwise constant *) |
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// call(tmpReg); (* basr, 2 bytes *) |
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static unsigned int max_instruction_size() { |
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return MacroAssembler::load_const_size() + MacroAssembler::call_byregister_size(); |
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} |
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// address instruction_address() const { return addr_at(0); } |
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// For the ordering of the checks see note at nativeCall_before. |
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address next_instruction_address() const { |
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address iaddr = instruction_address(); |
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if (MacroAssembler::is_load_const_call(iaddr)) { |
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// Form 2): load_const, BASR |
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return addr_at(MacroAssembler::load_const_call_size()); |
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} |
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if (MacroAssembler::is_load_const_from_toc_call(iaddr)) { |
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// Form 3): load_const_from_toc (LARL+LG/LGRL), BASR. |
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return addr_at(MacroAssembler::load_const_from_toc_call_size()); |
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} |
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if (MacroAssembler::is_call_far_pcrelative(iaddr)) { |
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// Form 1): NOP, BRASL |
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// The BRASL (Branch Relative And Save Long) is patched into the space created |
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// by the load_const_from_toc_call sequence (typically (LARL-LG)/LGRL - BASR. |
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// The BRASL must be positioned such that it's end is FW (4-byte) aligned (for atomic patching). |
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// It is achieved by aligning the end of the entire sequence on a 4byte boundary, by inserting |
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// a nop, if required, at the very beginning of the instruction sequence. The nop needs to |
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// be accounted for when calculating the next instruction address. The alignment takes place |
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// already when generating the original instruction sequence. The alignment requirement |
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// makes the size depend on location. |
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// The return address of the call must always be at the end of the instruction sequence. |
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// Inserting the extra alignment nop (or anything else) at the end is not an option. |
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// The patched-in brasl instruction is prepended with a nop to make it easier to |
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// distinguish from a load_const_from_toc_call sequence. |
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return addr_at(MacroAssembler::call_far_pcrelative_size()); |
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} |
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((NativeCall*)iaddr)->print(); |
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guarantee(false, "Not a NativeCall site"); |
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return NULL; |
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} |
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address return_address() const { |
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return next_instruction_address(); |
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} |
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address destination() const; |
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void set_destination_mt_safe(address dest); |
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void verify_alignment() {} // Yet another real do nothing guy :) |
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void verify(); |
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// unit test stuff |
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static void test(); |
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// Creation. |
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friend NativeCall* nativeCall_at(address instr) { |
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NativeCall* call; |
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// Make sure not to return garbage. |
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if (NativeCall::is_call_at(instr)) { |
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call = (NativeCall*)instr; |
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} else { |
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call = (NativeCall*)instr; |
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call->print(); |
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guarantee(false, "Not a NativeCall site"); |
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} |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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// This is a very tricky function to implement. It involves stepping |
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// backwards in the instruction stream. On architectures with variable |
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// instruction length, this is a risky endeavor. From the return address, |
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// you do not know how far to step back to be at a location (your starting |
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// point) that will eventually bring you back to the return address. |
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// Furthermore, it may happen that there are multiple starting points. |
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// |
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// With only a few possible (allowed) code patterns, the risk is lower but |
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// does not diminish completely. Experience shows that there are code patterns |
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// which look like a load_const_from_toc_call @(return address-8), but in |
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// fact are a call_far_pcrelative @(return address-6). The other way around |
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// is possible as well, but was not knowingly observed so far. |
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// |
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// The unpredictability is caused by the pc-relative address field in both |
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// the call_far_pcrelative (BASR) and the load_const_from_toc (LGRL) |
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// instructions. This field can contain an arbitrary bit pattern. |
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// |
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// Here is a real-world example: |
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// Mnemonics: <not a valid sequence> LGRL r10,<addr> BASR r14,r10 |
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// Hex code: eb01 9008 007a c498 ffff c4a8 c0e5 ffc1 0dea |
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// Mnemonics: AGSI <mem>,I8 LGRL r9,<addr> BRASL r14,<addr> correct |
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// |
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// If you first check for a load_const_from_toc_call @(-8), you will find |
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// a false positive. In this example, it is obviously false, because the |
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// preceding bytes do not form a valid instruction pattern. If you first |
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// check for call_far_pcrelative @(-6), you get a true positive - in this |
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// case. |
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// |
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// The following remedy has been implemented/enforced: |
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// 1) Everywhere, the permissible code patterns are checked in the same |
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// sequence: Form 2) - Form 3) - Form 1). |
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// 2) The call_far_pcrelative, which would ideally be just one BRASL |
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// instruction, is always prepended with a NOP. This measure avoids |
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// ambiguities with load_const_from_toc_call. |
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friend NativeCall* nativeCall_before(address return_address) { |
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NativeCall *call = NULL; |
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// Make sure not to return garbage |
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address instp = return_address - MacroAssembler::load_const_call_size(); |
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if (MacroAssembler::is_load_const_call(instp)) { // Form 2) |
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call = (NativeCall*)(instp); // load_const + basr |
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} else { |
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instp = return_address - MacroAssembler::load_const_from_toc_call_size(); |
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if (MacroAssembler::is_load_const_from_toc_call(instp)) { // Form 3) |
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call = (NativeCall*)(instp); // load_const_from_toc + basr |
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} else { |
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instp = return_address - MacroAssembler::call_far_pcrelative_size(); |
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if (MacroAssembler::is_call_far_pcrelative(instp)) { // Form 1) |
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call = (NativeCall*)(instp); // brasl (or nop + brasl) |
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} else { |
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call = (NativeCall*)(instp); |
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call->print(); |
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guarantee(false, "Not a NativeCall site"); |
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} |
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} |
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} |
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356 |
#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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362 |
// Ordering of checks 2) 3) 1) is relevant! |
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static bool is_call_at(address a) { |
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// Check plain instruction sequence. Do not care about filler or alignment nops. |
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365 |
bool b = MacroAssembler::is_load_const_call(a) || // load_const + basr |
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MacroAssembler::is_load_const_from_toc_call(a) || // load_const_from_toc + basr |
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MacroAssembler::is_call_far_pcrelative(a); // nop + brasl |
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return b; |
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} |
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371 |
// Ordering of checks 2) 3) 1) is relevant! |
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372 |
static bool is_call_before(address a) { |
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// check plain instruction sequence. Do not care about filler or alignment nops. |
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bool b = MacroAssembler::is_load_const_call( a - MacroAssembler::load_const_call_size()) || // load_const + basr |
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MacroAssembler::is_load_const_from_toc_call(a - MacroAssembler::load_const_from_toc_call_size()) || // load_const_from_toc + basr |
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MacroAssembler::is_call_far_pcrelative( a - MacroAssembler::call_far_pcrelative_size()); // nop+brasl |
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return b; |
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378 |
} |
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379 |
||
380 |
static bool is_call_to(address instr, address target) { |
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381 |
// Check whether there is a `NativeCall' at the address `instr' |
|
382 |
// calling to the address `target'. |
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383 |
return is_call_at(instr) && target == ((NativeCall *)instr)->destination(); |
|
384 |
} |
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385 |
||
386 |
bool is_pcrelative() { |
|
387 |
return MacroAssembler::is_call_far_pcrelative((address)this); |
|
388 |
} |
|
389 |
}; |
|
390 |
||
391 |
//----------------------------- |
|
392 |
// N a t i v e F a r C a l l |
|
393 |
//----------------------------- |
|
394 |
||
395 |
// The NativeFarCall is an abstraction for accessing/manipulating native |
|
396 |
// call-anywhere instructions. |
|
397 |
// Used to call native methods which may be loaded anywhere in the address |
|
398 |
// space, possibly out of reach of a call instruction. |
|
399 |
||
400 |
// Refer to NativeCall for a description of the supported call forms. |
|
401 |
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402 |
class NativeFarCall: public NativeInstruction { |
|
403 |
||
404 |
public: |
|
405 |
// We use MacroAssembler::call_far_patchable() for implementing a |
|
406 |
// call-anywhere instruction. |
|
407 |
||
408 |
static int instruction_size() { return MacroAssembler::call_far_patchable_size(); } |
|
409 |
static int return_address_offset() { return MacroAssembler::call_far_patchable_ret_addr_offset(); } |
|
410 |
||
411 |
// address instruction_address() const { return addr_at(0); } |
|
412 |
||
413 |
address next_instruction_address() const { |
|
414 |
return addr_at(instruction_size()); |
|
415 |
} |
|
416 |
||
417 |
address return_address() const { |
|
418 |
return addr_at(return_address_offset()); |
|
419 |
} |
|
420 |
||
421 |
// Returns the NativeFarCall's destination. |
|
422 |
address destination(); |
|
423 |
||
424 |
// Sets the NativeCall's destination, not necessarily mt-safe. |
|
425 |
// Used when relocating code. |
|
426 |
void set_destination(address dest, int toc_offset); |
|
427 |
||
428 |
// Checks whether instr points at a NativeFarCall instruction. |
|
429 |
static bool is_far_call_at(address instr) { |
|
430 |
// Use compound inspection function which, in addition to instruction sequence, |
|
431 |
// also checks for expected nops and for instruction alignment. |
|
432 |
return MacroAssembler::is_call_far_patchable_at(instr); |
|
433 |
} |
|
434 |
||
435 |
// Does the NativeFarCall implementation use a pc-relative encoding |
|
436 |
// of the call destination? |
|
437 |
// Used when relocating code. |
|
438 |
bool is_pcrelative() { |
|
439 |
address iaddr = (address)this; |
|
440 |
assert(is_far_call_at(iaddr), "unexpected call type"); |
|
441 |
return MacroAssembler::is_call_far_patchable_pcrelative_at(iaddr); |
|
442 |
} |
|
443 |
||
444 |
void verify(); |
|
445 |
||
446 |
// Unit tests |
|
447 |
static void test(); |
|
448 |
||
449 |
// Instantiates a NativeFarCall object starting at the given instruction |
|
450 |
// address and returns the NativeFarCall object. |
|
451 |
inline friend NativeFarCall* nativeFarCall_at(address instr) { |
|
452 |
NativeFarCall* call = (NativeFarCall*)instr; |
|
453 |
#ifdef ASSERT |
|
454 |
call->verify(); |
|
455 |
#endif |
|
456 |
return call; |
|
457 |
} |
|
458 |
}; |
|
459 |
||
460 |
||
461 |
//------------------------------------- |
|
462 |
// N a t i v e M o v C o n s t R e g |
|
463 |
//------------------------------------- |
|
464 |
||
465 |
// An interface for accessing/manipulating native set_oop imm, reg instructions. |
|
466 |
// (Used to manipulate inlined data references, etc.) |
|
467 |
||
468 |
// A native move of a constant into a register, as defined by this abstraction layer, |
|
469 |
// deals with instruction sequences that load "quasi constant" oops into registers |
|
470 |
// for addressing. For multiple causes, those "quasi constant" oops eventually need |
|
471 |
// to be changed (i.e. patched). The reason is quite simple: objects might get moved |
|
472 |
// around in storage. Pc-relative oop addresses have to be patched also if the |
|
473 |
// reference location is moved. That happens when executable code is relocated. |
|
474 |
||
475 |
class NativeMovConstReg: public NativeInstruction { |
|
476 |
public: |
|
477 |
||
478 |
enum z_specific_constants { |
|
479 |
instruction_size = 10 // Used in shared code for calls with reloc_info. |
|
480 |
}; |
|
481 |
||
482 |
// address instruction_address() const { return addr_at(0); } |
|
483 |
||
484 |
// The current instruction might be located at an offset. |
|
485 |
address next_instruction_address(int offset = 0) const; |
|
486 |
||
487 |
// (The [set_]data accessor respects oop_type relocs also.) |
|
488 |
intptr_t data() const; |
|
489 |
||
490 |
// Patch data in code stream. |
|
491 |
address set_data_plain(intptr_t x, CodeBlob *code); |
|
492 |
// Patch data in code stream and oop pool if necessary. |
|
493 |
void set_data(intptr_t x); |
|
494 |
||
495 |
// Patch narrow oop constant in code stream. |
|
496 |
void set_narrow_oop(intptr_t data); |
|
497 |
void set_narrow_klass(intptr_t data); |
|
498 |
void set_pcrel_addr(intptr_t addr, CompiledMethod *nm = NULL, bool copy_back_to_oop_pool=false); |
|
499 |
void set_pcrel_data(intptr_t data, CompiledMethod *nm = NULL, bool copy_back_to_oop_pool=false); |
|
500 |
||
501 |
void verify(); |
|
502 |
||
503 |
// unit test stuff |
|
504 |
static void test(); |
|
505 |
||
506 |
// Creation. |
|
507 |
friend NativeMovConstReg* nativeMovConstReg_at(address address) { |
|
508 |
NativeMovConstReg* test = (NativeMovConstReg*)address; |
|
509 |
#ifdef ASSERT |
|
510 |
test->verify(); |
|
511 |
#endif |
|
512 |
return test; |
|
513 |
} |
|
514 |
}; |
|
515 |
||
516 |
||
517 |
#ifdef COMPILER1 |
|
518 |
//--------------------------------- |
|
519 |
// N a t i v e M o v R e g M e m |
|
520 |
//--------------------------------- |
|
521 |
||
522 |
// Interface to manipulate a code sequence that performs a memory access (load/store). |
|
523 |
// The code is the patchable version of memory accesses generated by |
|
524 |
// LIR_Assembler::reg2mem() and LIR_Assembler::mem2reg(). |
|
525 |
// |
|
526 |
// Loading the offset for the mem access is target of the manipulation. |
|
527 |
// |
|
528 |
// The instruction sequence looks like this: |
|
529 |
// iihf %r1,$bits1 ; load offset for mem access |
|
530 |
// iilf %r1,$bits2 |
|
531 |
// [compress oop] ; optional, load only |
|
532 |
// load/store %r2,0(%r1,%r2) ; memory access |
|
533 |
||
534 |
class NativeMovRegMem; |
|
535 |
inline NativeMovRegMem* nativeMovRegMem_at (address address); |
|
536 |
class NativeMovRegMem: public NativeInstruction { |
|
537 |
public: |
|
538 |
intptr_t offset() const { |
|
539 |
return nativeMovConstReg_at(addr_at(0))->data(); |
|
540 |
} |
|
541 |
void set_offset(intptr_t x) { |
|
542 |
nativeMovConstReg_at(addr_at(0))->set_data(x); |
|
543 |
} |
|
544 |
void add_offset_in_bytes(intptr_t radd_offset) { |
|
545 |
set_offset(offset() + radd_offset); |
|
546 |
} |
|
547 |
void verify(); |
|
548 |
||
549 |
private: |
|
550 |
friend inline NativeMovRegMem* nativeMovRegMem_at(address address) { |
|
551 |
NativeMovRegMem* test = (NativeMovRegMem*)address; |
|
552 |
#ifdef ASSERT |
|
553 |
test->verify(); |
|
554 |
#endif |
|
555 |
return test; |
|
556 |
} |
|
557 |
}; |
|
558 |
#endif // COMPILER1 |
|
559 |
||
560 |
||
561 |
//----------------------- |
|
562 |
// N a t i v e J u m p |
|
563 |
//----------------------- |
|
564 |
||
565 |
||
566 |
// An interface for accessing/manipulating native jumps |
|
567 |
class NativeJump: public NativeInstruction { |
|
568 |
public: |
|
569 |
enum z_constants { |
|
570 |
instruction_size = 2 // Size of z_illtrap(). |
|
571 |
}; |
|
572 |
||
573 |
// Maximum size (in bytes) of a jump to an absolute address. |
|
574 |
// Used when emitting branch to an exception handler which is a "load_const_optimized_branch". |
|
575 |
// Thus, a pessimistic estimate is obtained when using load_const. |
|
576 |
// code pattern is: |
|
577 |
// tmpReg := load_const(address); (* varying size *) |
|
578 |
// jumpTo(tmpReg); (* bcr, 2 bytes *) |
|
579 |
// |
|
580 |
static unsigned int max_instruction_size() { |
|
581 |
return MacroAssembler::load_const_size() + MacroAssembler::jump_byregister_size(); |
|
582 |
} |
|
583 |
||
584 |
||
585 |
// address instruction_address() const { return addr_at(0); } |
|
586 |
||
587 |
address jump_destination() const { |
|
588 |
return (address)nativeMovConstReg_at(instruction_address())->data(); |
|
589 |
} |
|
590 |
||
591 |
void set_jump_destination(address dest) { |
|
592 |
nativeMovConstReg_at(instruction_address())->set_data(((intptr_t)dest)); |
|
593 |
} |
|
594 |
||
595 |
// Creation |
|
596 |
friend NativeJump* nativeJump_at(address address) { |
|
597 |
NativeJump* jump = (NativeJump*)address; |
|
598 |
#ifdef ASSERT |
|
599 |
jump->verify(); |
|
600 |
#endif |
|
601 |
return jump; |
|
602 |
} |
|
603 |
||
604 |
static bool is_jump_at(address a) { |
|
605 |
int off = 0; |
|
606 |
bool b = (MacroAssembler::is_load_const_from_toc(a+off) && |
|
607 |
Assembler::is_z_br(*(short*)(a+off + MacroAssembler::load_const_from_toc_size()))); |
|
608 |
b = b || (MacroAssembler::is_load_const(a+off) && |
|
609 |
Assembler::is_z_br(*(short*)(a+off + MacroAssembler::load_const_size()))); |
|
610 |
return b; |
|
611 |
} |
|
612 |
||
613 |
void verify(); |
|
614 |
||
615 |
// Unit testing stuff |
|
616 |
static void test(); |
|
617 |
||
618 |
// Insertion of native jump instruction. |
|
619 |
static void insert(address code_pos, address entry); |
|
620 |
||
621 |
// MT-safe insertion of native jump at verified method entry. |
|
622 |
static void check_verified_entry_alignment(address entry, address verified_entry) { } |
|
623 |
||
624 |
static void patch_verified_entry(address entry, address verified_entry, address dest); |
|
625 |
}; |
|
626 |
||
627 |
//------------------------------------- |
|
628 |
// N a t i v e G e n e r a l J u m p |
|
629 |
//------------------------------------- |
|
630 |
||
631 |
// Despite the name, handles only simple branches. |
|
632 |
// On ZARCH_64 BRCL only. |
|
633 |
class NativeGeneralJump; |
|
634 |
inline NativeGeneralJump* nativeGeneralJump_at(address address); |
|
635 |
class NativeGeneralJump: public NativeInstruction { |
|
636 |
public: |
|
637 |
enum ZARCH_specific_constants { |
|
638 |
instruction_size = 6 |
|
639 |
}; |
|
640 |
||
641 |
address instruction_address() const { return addr_at(0); } |
|
642 |
address jump_destination() const { return addr_at(0) + MacroAssembler::get_pcrel_offset(addr_at(0)); } |
|
643 |
||
644 |
// Creation |
|
645 |
friend inline NativeGeneralJump* nativeGeneralJump_at(address addr) { |
|
646 |
NativeGeneralJump* jump = (NativeGeneralJump*)(addr); |
|
647 |
#ifdef ASSERT |
|
648 |
jump->verify(); |
|
649 |
#endif |
|
650 |
return jump; |
|
651 |
} |
|
652 |
||
653 |
// Insertion of native general jump instruction. |
|
654 |
static void insert_unconditional(address code_pos, address entry); |
|
655 |
||
656 |
void set_jump_destination(address dest) { |
|
657 |
Unimplemented(); |
|
658 |
// set_word_at(MacroAssembler::call_far_pcrelative_size()-4, Assembler::z_pcrel_off(dest, addr_at(0))); |
|
659 |
} |
|
660 |
||
661 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
662 |
||
663 |
void verify() PRODUCT_RETURN; |
|
664 |
}; |
|
665 |
||
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
52460
diff
changeset
|
666 |
#endif // CPU_S390_NATIVEINST_S390_HPP |