src/hotspot/cpu/arm/gc/g1/g1BarrierSetAssembler_arm.cpp
author eosterlund
Thu, 26 Apr 2018 20:42:43 +0200
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child 49938 2c2a722a2c0c
permissions -rw-r--r--
8201543: Modularize C1 GC barriers Reviewed-by: pliden, rbackman, rkennke
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/*
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 * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "gc/g1/g1BarrierSet.hpp"
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#include "gc/g1/g1BarrierSetAssembler.hpp"
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#include "gc/g1/g1CardTable.hpp"
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#include "gc/g1/heapRegion.hpp"
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#include "interpreter/interp_masm.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/thread.hpp"
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#include "utilities/macros.hpp"
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#ifdef COMPILER1
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#include "c1/c1_LIRAssembler.hpp"
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#include "c1/c1_MacroAssembler.hpp"
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#include "gc/g1/c1/g1BarrierSetC1.hpp"
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#endif
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#define __ masm->
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#ifdef PRODUCT
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#define BLOCK_COMMENT(str) /* nothing */
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#else
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#define BLOCK_COMMENT(str) __ block_comment(str)
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#endif
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators,
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                                                            Register addr, Register count, int callee_saved_regs) {
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  bool dest_uninitialized = (decorators & AS_DEST_NOT_INITIALIZED) != 0;
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  if (!dest_uninitialized) {
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    assert( addr->encoding() < callee_saved_regs, "addr must be saved");
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    assert(count->encoding() < callee_saved_regs, "count must be saved");
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    BLOCK_COMMENT("PreBarrier");
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#ifdef AARCH64
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    callee_saved_regs = align_up(callee_saved_regs, 2);
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    for (int i = 0; i < callee_saved_regs; i += 2) {
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      __ raw_push(as_Register(i), as_Register(i+1));
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    }
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#else
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    RegisterSet saved_regs = RegisterSet(R0, as_Register(callee_saved_regs-1));
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    __ push(saved_regs | R9ifScratched);
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#endif // AARCH64
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    if (addr != R0) {
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      assert_different_registers(count, R0);
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      __ mov(R0, addr);
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    }
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#ifdef AARCH64
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    __ zero_extend(R1, count, 32); // G1BarrierSet::write_ref_array_pre_*_entry takes size_t
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#else
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    if (count != R1) {
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      __ mov(R1, count);
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    }
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#endif // AARCH64
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    if (UseCompressedOops) {
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      __ call(CAST_FROM_FN_PTR(address, G1BarrierSet::write_ref_array_pre_narrow_oop_entry));
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    } else {
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      __ call(CAST_FROM_FN_PTR(address, G1BarrierSet::write_ref_array_pre_oop_entry));
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    }
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#ifdef AARCH64
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    for (int i = callee_saved_regs - 2; i >= 0; i -= 2) {
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      __ raw_pop(as_Register(i), as_Register(i+1));
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    }
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#else
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    __ pop(saved_regs | R9ifScratched);
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#endif // AARCH64
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  }
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}
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void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
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                                                             Register addr, Register count, Register tmp) {
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  BLOCK_COMMENT("G1PostBarrier");
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  if (addr != R0) {
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    assert_different_registers(count, R0);
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    __ mov(R0, addr);
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  }
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#ifdef AARCH64
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  __ zero_extend(R1, count, 32); // G1BarrierSet::write_ref_array_post_entry takes size_t
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#else
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  if (count != R1) {
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    __ mov(R1, count);
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  }
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#if R9_IS_SCRATCHED
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  // Safer to save R9 here since callers may have been written
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  // assuming R9 survives. This is suboptimal but is not in
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  // general worth optimizing for the few platforms where R9
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  // is scratched. Note that the optimization might not be to
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  // difficult for this particular call site.
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  __ push(R9);
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#endif // !R9_IS_SCRATCHED
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#endif // !AARCH64
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  __ call(CAST_FROM_FN_PTR(address, G1BarrierSet::write_ref_array_post_entry));
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#ifndef AARCH64
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#if R9_IS_SCRATCHED
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  __ pop(R9);
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#endif // !R9_IS_SCRATCHED
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#endif // !AARCH64
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}
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#ifdef COMPILER1
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#undef __
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#define __ ce->masm()->
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void G1BarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub) {
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  G1BarrierSetC1* bs = (G1BarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1();
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  // At this point we know that marking is in progress.
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  // If do_load() is true then we have to emit the
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  // load of the previous value; otherwise it has already
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  // been loaded into _pre_val.
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  __ bind(*stub->entry());
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  assert(stub->pre_val()->is_register(), "Precondition.");
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  Register pre_val_reg = stub->pre_val()->as_register();
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  if (stub->do_load()) {
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    ce->mem2reg(stub->addr(), stub->pre_val(), T_OBJECT, stub->patch_code(), stub->info(), false /*wide*/, false /*unaligned*/);
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  }
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  __ cbz(pre_val_reg, *stub->continuation());
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  ce->verify_reserved_argument_area_size(1);
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  __ str(pre_val_reg, Address(SP));
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  __ call(bs->pre_barrier_c1_runtime_code_blob()->code_begin(), relocInfo::runtime_call_type);
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  __ b(*stub->continuation());
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}
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   157
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void G1BarrierSetAssembler::gen_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub) {
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  G1BarrierSetC1* bs = (G1BarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1();
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  __ bind(*stub->entry());
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  assert(stub->addr()->is_register(), "Precondition.");
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  assert(stub->new_val()->is_register(), "Precondition.");
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  Register new_val_reg = stub->new_val()->as_register();
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  __ cbz(new_val_reg, *stub->continuation());
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  ce->verify_reserved_argument_area_size(1);
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  __ str(stub->addr()->as_pointer_register(), Address(SP));
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  __ call(bs->post_barrier_c1_runtime_code_blob()->code_begin(), relocInfo::runtime_call_type);
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  __ b(*stub->continuation());
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}
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#undef __
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#define __ sasm->
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   173
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void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm) {
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  // Input:
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  // - pre_val pushed on the stack
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  __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
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  BarrierSet* bs = BarrierSet::barrier_set();
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  if (bs->kind() != BarrierSet::G1BarrierSet) {
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    __ mov(R0, (int)id);
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    __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
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    __ should_not_reach_here();
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    break;
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  }
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  // save at least the registers that need saving if the runtime is called
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#ifdef AARCH64
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  __ raw_push(R0, R1);
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  __ raw_push(R2, R3);
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  const int nb_saved_regs = 4;
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#else // AARCH64
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  const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
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  const int nb_saved_regs = 6;
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  assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
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  __ push(saved_regs);
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#endif // AARCH64
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  const Register r_pre_val_0  = R0; // must be R0, to be ready for the runtime call
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  const Register r_index_1    = R1;
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  const Register r_buffer_2   = R2;
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   203
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  Address queue_active(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset()));
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  Address queue_index(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_index_offset()));
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  Address buffer(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_buffer_offset()));
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  Label done;
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  Label runtime;
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  // Is marking still active?
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  assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
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  __ ldrb(R1, queue_active);
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  __ cbz(R1, done);
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  __ ldr(r_index_1, queue_index);
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  __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
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  __ ldr(r_buffer_2, buffer);
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   219
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  __ subs(r_index_1, r_index_1, wordSize);
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  __ b(runtime, lt);
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   222
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  __ str(r_index_1, queue_index);
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  __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
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  __ bind(done);
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   227
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#ifdef AARCH64
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  __ raw_pop(R2, R3);
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  __ raw_pop(R0, R1);
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#else // AARCH64
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  __ pop(saved_regs);
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#endif // AARCH64
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   234
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  __ ret();
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  __ bind(runtime);
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   238
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  __ save_live_registers();
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  assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
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  __ mov(c_rarg1, Rthread);
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  __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
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   244
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  __ restore_live_registers_without_return();
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  __ b(done);
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}
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   249
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void G1BarrierSetAssembler::generate_c1_post_barrier_runtime_stub(StubAssembler* sasm) {
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  // Input:
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  // - store_addr, pushed on the stack
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   253
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  __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
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  BarrierSet* bs = BarrierSet::barrier_set();
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  if (bs->kind() != BarrierSet::G1BarrierSet) {
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    __ mov(R0, (int)id);
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    __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
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    __ should_not_reach_here();
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    break;
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  }
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   263
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  Label done;
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  Label recheck;
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  Label runtime;
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   267
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  Address queue_index(Rthread, in_bytes(G1ThreadLocalData::dirty_card_queue_index_offset()));
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  Address buffer(Rthread, in_bytes(G1ThreadLocalData::dirty_card_queue_buffer_offset()));
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  AddressLiteral cardtable(ci_card_table_address_as<address>(), relocInfo::none);
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  // save at least the registers that need saving if the runtime is called
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#ifdef AARCH64
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  __ raw_push(R0, R1);
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  __ raw_push(R2, R3);
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  const int nb_saved_regs = 4;
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#else // AARCH64
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  const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
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  const int nb_saved_regs = 6;
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  assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
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  __ push(saved_regs);
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   283
#endif // AARCH64
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   284
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  const Register r_card_addr_0 = R0; // must be R0 for the slow case
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  const Register r_obj_0 = R0;
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  const Register r_card_base_1 = R1;
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  const Register r_tmp2 = R2;
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  const Register r_index_2 = R2;
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  const Register r_buffer_3 = R3;
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  const Register tmp1 = Rtemp;
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   292
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  __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
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  // Note: there is a comment in x86 code about not using
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   295
  // ExternalAddress / lea, due to relocation not working
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  // properly for that address. Should be OK for arm, where we
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  // explicitly specify that 'cardtable' has a relocInfo::none
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   298
  // type.
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   299
  __ lea(r_card_base_1, cardtable);
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  __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTable::card_shift));
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  // first quick check without barrier
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  __ ldrb(r_tmp2, Address(r_card_addr_0));
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  __ cmp(r_tmp2, (int)G1CardTable::g1_young_card_val());
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  __ b(recheck, ne);
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  __ bind(done);
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#ifdef AARCH64
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  __ raw_pop(R2, R3);
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  __ raw_pop(R0, R1);
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#else // AARCH64
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  __ pop(saved_regs);
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#endif // AARCH64
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  __ ret();
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  __ bind(recheck);
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  __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
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  // reload card state after the barrier that ensures the stored oop was visible
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  __ ldrb(r_tmp2, Address(r_card_addr_0));
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  assert(CardTable::dirty_card_val() == 0, "adjust this code");
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  __ cbz(r_tmp2, done);
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  // storing region crossing non-NULL, card is clean.
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  // dirty card and log.
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  assert(0 == (int)CardTable::dirty_card_val(), "adjust this code");
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  if ((ci_card_table_address_as<intptr_t>() & 0xff) == 0) {
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    // Card table is aligned so the lowest byte of the table address base is zero.
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    __ strb(r_card_base_1, Address(r_card_addr_0));
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  } else {
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    __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
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  }
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  __ ldr(r_index_2, queue_index);
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  __ ldr(r_buffer_3, buffer);
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  __ subs(r_index_2, r_index_2, wordSize);
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  __ b(runtime, lt); // go to runtime if now negative
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  __ str(r_index_2, queue_index);
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  __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
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  __ b(done);
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  __ bind(runtime);
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  __ save_live_registers();
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  assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
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  __ mov(c_rarg1, Rthread);
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  __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
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  __ restore_live_registers_without_return();
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  __ b(done);
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}
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#undef __
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#endif // COMPILER1