author | darcy |
Tue, 12 Nov 2019 10:45:23 -0800 | |
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/* |
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* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef OS_CPU_SOLARIS_SPARC_ORDERACCESS_SOLARIS_SPARC_HPP |
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#define OS_CPU_SOLARIS_SPARC_ORDERACCESS_SOLARIS_SPARC_HPP |
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// Included in orderAccess.hpp header file. |
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// Compiler version last used for testing: solaris studio 12u3 |
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// Please update this information when this file changes |
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// Implementation of class OrderAccess. |
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// Assume TSO. |
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// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions |
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inline void compiler_barrier() { |
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__asm__ volatile ("" : : : "memory"); |
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} |
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inline void OrderAccess::loadload() { compiler_barrier(); } |
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inline void OrderAccess::storestore() { compiler_barrier(); } |
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inline void OrderAccess::loadstore() { compiler_barrier(); } |
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inline void OrderAccess::storeload() { fence(); } |
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inline void OrderAccess::acquire() { compiler_barrier(); } |
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inline void OrderAccess::release() { compiler_barrier(); } |
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inline void OrderAccess::fence() { |
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__asm__ volatile ("membar #StoreLoad" : : : "memory"); |
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} |
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inline void OrderAccess::cross_modify_fence() { } |
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#endif // OS_CPU_SOLARIS_SPARC_ORDERACCESS_SOLARIS_SPARC_HPP |