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/*
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* Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_ARM_VM_VMREG_ARM_HPP
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#define CPU_ARM_VM_VMREG_ARM_HPP
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inline bool is_Register() {
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return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
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}
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inline bool is_FloatRegister() {
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return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
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}
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inline Register as_Register() {
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assert(is_Register(), "must be");
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assert(is_concrete(), "concrete register expected");
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return ::as_Register(value() >> ConcreteRegisterImpl::log_vmregs_per_gpr);
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}
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inline FloatRegister as_FloatRegister() {
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assert(is_FloatRegister(), "must be");
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assert(is_concrete(), "concrete register expected");
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return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> ConcreteRegisterImpl::log_vmregs_per_fpr);
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}
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inline bool is_concrete() {
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if (is_Register()) {
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return ((value() & right_n_bits(ConcreteRegisterImpl::log_vmregs_per_gpr)) == 0);
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} else if (is_FloatRegister()) {
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return (((value() - ConcreteRegisterImpl::max_gpr) & right_n_bits(ConcreteRegisterImpl::log_vmregs_per_fpr)) == 0);
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} else {
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return false;
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}
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}
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#endif // CPU_ARM_VM_VMREG_ARM_HPP
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