/*

 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_X86_VM_ASSEMBLER_X86_HPP

#define CPU_X86_VM_ASSEMBLER_X86_HPP

#include "asm/register.hpp"

#include "vm_version_x86.hpp"

class BiasedLockingCounters;

// Contains all the definitions needed for x86 assembly code generation.

// Calling convention

class Argument VALUE_OBJ_CLASS_SPEC {

 public:

  enum {

#ifdef _LP64

#ifdef _WIN64

    n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)

    n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )

#else

    n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)

    n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )

#endif // _WIN64

    n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...

    n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...

#else

    n_register_parameters = 0   // 0 registers used to pass arguments

#endif // _LP64

  };

};

#ifdef _LP64

// Symbolically name the register arguments used by the c calling convention.

// Windows is different from linux/solaris. So much for standards...

#ifdef _WIN64

REGISTER_DECLARATION(Register, c_rarg0, rcx);

REGISTER_DECLARATION(Register, c_rarg1, rdx);

REGISTER_DECLARATION(Register, c_rarg2, r8);

REGISTER_DECLARATION(Register, c_rarg3, r9);

REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);

#else

REGISTER_DECLARATION(Register, c_rarg0, rdi);

REGISTER_DECLARATION(Register, c_rarg1, rsi);

REGISTER_DECLARATION(Register, c_rarg2, rdx);

REGISTER_DECLARATION(Register, c_rarg3, rcx);

REGISTER_DECLARATION(Register, c_rarg4, r8);

REGISTER_DECLARATION(Register, c_rarg5, r9);

REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);

REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);

REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);

REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);

REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);

#endif // _WIN64

// Symbolically name the register arguments used by the Java calling convention.

// We have control over the convention for java so we can do what we please.

// What pleases us is to offset the java calling convention so that when

// we call a suitable jni method the arguments are lined up and we don't

// have to do little shuffling. A suitable jni method is non-static and a

// small number of arguments (two fewer args on windows)

//

//        |-------------------------------------------------------|

//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |

//        |-------------------------------------------------------|

//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)

//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux

//        |-------------------------------------------------------|

//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |

//        |-------------------------------------------------------|

REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);

REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);

REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);

// Windows runs out of register args here

#ifdef _WIN64

REGISTER_DECLARATION(Register, j_rarg3, rdi);

REGISTER_DECLARATION(Register, j_rarg4, rsi);

#else

REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);

REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);

#endif /* _WIN64 */

REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);

REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);

REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);

REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);

REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);

REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);

REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile

REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile

REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved

REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved

#else

// rscratch1 will apear in 32bit code that is dead but of course must compile

// Using noreg ensures if the dead code is incorrectly live and executed it

// will cause an assertion failure

#define rscratch1 noreg

#define rscratch2 noreg

#endif // _LP64

// JSR 292 fixed register usages:

REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);

// Address is an abstraction used to represent a memory location

// using any of the amd64 addressing modes with one object.

//

// Note: A register location is represented via a Register, not

//       via an address for efficiency & simplicity reasons.

class ArrayAddress;

class Address VALUE_OBJ_CLASS_SPEC {

 public:

  enum ScaleFactor {

    no_scale = -1,

    times_1  =  0,

    times_2  =  1,

    times_4  =  2,

    times_8  =  3,

    times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)

  };

  static ScaleFactor times(int size) {

    assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");

    if (size == 8)  return times_8;

    if (size == 4)  return times_4;

    if (size == 2)  return times_2;

    return times_1;

  }

  static int scale_size(ScaleFactor scale) {

    assert(scale != no_scale, "");

    assert(((1 << (int)times_1) == 1 &&

            (1 << (int)times_2) == 2 &&

            (1 << (int)times_4) == 4 &&

            (1 << (int)times_8) == 8), "");

    return (1 << (int)scale);

  }

 private:

  Register         _base;

  Register         _index;

  ScaleFactor      _scale;

  int              _disp;

  RelocationHolder _rspec;

  // Easily misused constructors make them private

  // %%% can we make these go away?

  NOT_LP64(Address(address loc, RelocationHolder spec);)

  Address(int disp, address loc, relocInfo::relocType rtype);

  Address(int disp, address loc, RelocationHolder spec);

 public:

 int disp() { return _disp; }

  // creation

  Address()

    : _base(noreg),

      _index(noreg),

      _scale(no_scale),

      _disp(0) {

  }

  // No default displacement otherwise Register can be implicitly

  // converted to 0(Register) which is quite a different animal.

  Address(Register base, int disp)

    : _base(base),

      _index(noreg),

      _scale(no_scale),

      _disp(disp) {

  }

  Address(Register base, Register index, ScaleFactor scale, int disp = 0)

    : _base (base),

      _index(index),

      _scale(scale),

      _disp (disp) {

    assert(!index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

  Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)

    : _base (base),

      _index(index.register_or_noreg()),

      _scale(scale),

      _disp (disp + (index.constant_or_zero() * scale_size(scale))) {

    if (!index.is_register())  scale = Address::no_scale;

    assert(!_index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

  Address plus_disp(int disp) const {

    Address a = (*this);

    a._disp += disp;

    return a;

  }

  Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {

    Address a = (*this);

    a._disp += disp.constant_or_zero() * scale_size(scale);

    if (disp.is_register()) {

      assert(!a.index()->is_valid(), "competing indexes");

      a._index = disp.as_register();

      a._scale = scale;

    }

    return a;

  }

  bool is_same_address(Address a) const {

    // disregard _rspec

    return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;

  }

  // The following two overloads are used in connection with the

  // ByteSize type (see sizes.hpp).  They simplify the use of

  // ByteSize'd arguments in assembly code. Note that their equivalent

  // for the optimized build are the member functions with int disp

  // argument since ByteSize is mapped to an int type in that case.

  //

  // Note: DO NOT introduce similar overloaded functions for WordSize

  // arguments as in the optimized mode, both ByteSize and WordSize

  // are mapped to the same type and thus the compiler cannot make a

  // distinction anymore (=> compiler errors).

#ifdef ASSERT

  Address(Register base, ByteSize disp)

    : _base(base),

      _index(noreg),

      _scale(no_scale),

      _disp(in_bytes(disp)) {

  }

  Address(Register base, Register index, ScaleFactor scale, ByteSize disp)

    : _base(base),

      _index(index),

      _scale(scale),

      _disp(in_bytes(disp)) {

    assert(!index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

  Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)

    : _base (base),

      _index(index.register_or_noreg()),

      _scale(scale),

      _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {

    if (!index.is_register())  scale = Address::no_scale;

    assert(!_index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

#endif // ASSERT

  // accessors

  bool        uses(Register reg) const { return _base == reg || _index == reg; }

  Register    base()             const { return _base;  }

  Register    index()            const { return _index; }

  ScaleFactor scale()            const { return _scale; }

  int         disp()             const { return _disp;  }

  // Convert the raw encoding form into the form expected by the constructor for

  // Address.  An index of 4 (rsp) corresponds to having no index, so convert

  // that to noreg for the Address constructor.

  static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);

  static Address make_array(ArrayAddress);

 private:

  bool base_needs_rex() const {

    return _base != noreg && _base->encoding() >= 8;

  }

  bool index_needs_rex() const {

    return _index != noreg &&_index->encoding() >= 8;

  }

  relocInfo::relocType reloc() const { return _rspec.type(); }

  friend class Assembler;

  friend class MacroAssembler;

  friend class LIR_Assembler; // base/index/scale/disp

};

//

// AddressLiteral has been split out from Address because operands of this type

// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out

// the few instructions that need to deal with address literals are unique and the

// MacroAssembler does not have to implement every instruction in the Assembler

// in order to search for address literals that may need special handling depending

// on the instruction and the platform. As small step on the way to merging i486/amd64

// directories.

//

class AddressLiteral VALUE_OBJ_CLASS_SPEC {

  friend class ArrayAddress;

  RelocationHolder _rspec;

  // Typically we use AddressLiterals we want to use their rval

  // However in some situations we want the lval (effect address) of the item.

  // We provide a special factory for making those lvals.

  bool _is_lval;

  // If the target is far we'll need to load the ea of this to

  // a register to reach it. Otherwise if near we can do rip

  // relative addressing.

  address          _target;

 protected:

  // creation

  AddressLiteral()

    : _is_lval(false),

      _target(NULL)

  {}

  public:

  AddressLiteral(address target, relocInfo::relocType rtype);

  AddressLiteral(address target, RelocationHolder const& rspec)

    : _rspec(rspec),

      _is_lval(false),

      _target(target)

  {}

  AddressLiteral addr() {

    AddressLiteral ret = *this;

    ret._is_lval = true;

    return ret;

  }

 private:

  address target() { return _target; }

  bool is_lval() { return _is_lval; }

  relocInfo::relocType reloc() const { return _rspec.type(); }

  const RelocationHolder& rspec() const { return _rspec; }

  friend class Assembler;

  friend class MacroAssembler;

  friend class Address;

  friend class LIR_Assembler;

};

// Convience classes

class RuntimeAddress: public AddressLiteral {

  public:

  RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}

};

class ExternalAddress: public AddressLiteral {

 private:

  static relocInfo::relocType reloc_for_target(address target) {

    // Sometimes ExternalAddress is used for values which aren't

    // exactly addresses, like the card table base.

    // external_word_type can't be used for values in the first page

    // so just skip the reloc in that case.

    return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;

  }

 public:

  ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}

};

class InternalAddress: public AddressLiteral {

  public:

  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}

};

// x86 can do array addressing as a single operation since disp can be an absolute

// address amd64 can't. We create a class that expresses the concept but does extra

// magic on amd64 to get the final result

class ArrayAddress VALUE_OBJ_CLASS_SPEC {

  private:

  AddressLiteral _base;

  Address        _index;

  public:

  ArrayAddress() {};

  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};

  AddressLiteral base() { return _base; }

  Address index() { return _index; }

};

const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);

// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction

// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write

// is what you get. The Assembler is generating code into a CodeBuffer.

class Assembler : public AbstractAssembler  {

  friend class AbstractAssembler; // for the non-virtual hack

  friend class LIR_Assembler; // as_Address()

  friend class StubGenerator;

 public:

  enum Condition {                     // The x86 condition codes used for conditional jumps/moves.

    zero          = 0x4,

    notZero       = 0x5,

    equal         = 0x4,

    notEqual      = 0x5,

    less          = 0xc,

    lessEqual     = 0xe,

    greater       = 0xf,

    greaterEqual  = 0xd,

    below         = 0x2,

    belowEqual    = 0x6,

    above         = 0x7,

    aboveEqual    = 0x3,

    overflow      = 0x0,

    noOverflow    = 0x1,

    carrySet      = 0x2,

    carryClear    = 0x3,

    negative      = 0x8,

    positive      = 0x9,

    parity        = 0xa,

    noParity      = 0xb

  };

  enum Prefix {

    // segment overrides

    CS_segment = 0x2e,

    SS_segment = 0x36,

    DS_segment = 0x3e,

    ES_segment = 0x26,

    FS_segment = 0x64,

    GS_segment = 0x65,

    REX        = 0x40,

    REX_B      = 0x41,

    REX_X      = 0x42,

    REX_XB     = 0x43,

    REX_R      = 0x44,

    REX_RB     = 0x45,

    REX_RX     = 0x46,

    REX_RXB    = 0x47,

    REX_W      = 0x48,

    REX_WB     = 0x49,

    REX_WX     = 0x4A,

    REX_WXB    = 0x4B,

    REX_WR     = 0x4C,

    REX_WRB    = 0x4D,

    REX_WRX    = 0x4E,

    REX_WRXB   = 0x4F,

    VEX_3bytes = 0xC4,

    VEX_2bytes = 0xC5

  };

  enum VexPrefix {

    VEX_B = 0x20,

    VEX_X = 0x40,

    VEX_R = 0x80,

    VEX_W = 0x80

  };

  enum VexSimdPrefix {

    VEX_SIMD_NONE = 0x0,

    VEX_SIMD_66   = 0x1,