/*

 * Copyright 2005-2008 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

# include "incls/_precompiled.incl"

# include "incls/_c1_LIRGenerator_sparc.cpp.incl"

#ifdef ASSERT

#define __ gen()->lir(__FILE__, __LINE__)->

#else

#define __ gen()->lir()->

#endif

void LIRItem::load_byte_item() {

  // byte loads use same registers as other loads

  load_item();

}

void LIRItem::load_nonconstant() {

  LIR_Opr r = value()->operand();

  if (_gen->can_inline_as_constant(value())) {

    if (!r->is_constant()) {

      r = LIR_OprFact::value_type(value()->type());

    }

    _result = r;

  } else {

    load_item();

  }

}

//--------------------------------------------------------------

//               LIRGenerator

//--------------------------------------------------------------

LIR_Opr LIRGenerator::exceptionOopOpr()              { return FrameMap::Oexception_opr;  }

LIR_Opr LIRGenerator::exceptionPcOpr()               { return FrameMap::Oissuing_pc_opr; }

LIR_Opr LIRGenerator::syncTempOpr()                  { return new_register(T_OBJECT); }

LIR_Opr LIRGenerator::getThreadTemp()                { return rlock_callee_saved(T_INT); }

LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {

  LIR_Opr opr;

  switch (type->tag()) {

  case intTag:     opr = callee ? FrameMap::I0_opr      : FrameMap::O0_opr;       break;

  case objectTag:  opr = callee ? FrameMap::I0_oop_opr  : FrameMap::O0_oop_opr;   break;

  case longTag:    opr = callee ? FrameMap::in_long_opr : FrameMap::out_long_opr; break;

  case floatTag:   opr = FrameMap::F0_opr;                                        break;

  case doubleTag:  opr = FrameMap::F0_double_opr;                                 break;

  case addressTag:

  default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;

  }

  assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");

  return opr;

}

LIR_Opr LIRGenerator::rlock_callee_saved(BasicType type) {

  LIR_Opr reg = new_register(type);

  set_vreg_flag(reg, callee_saved);

  return reg;

}

LIR_Opr LIRGenerator::rlock_byte(BasicType type) {

  return new_register(T_INT);

}

//--------- loading items into registers --------------------------------

// SPARC cannot inline all constants

bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {

  if (v->type()->as_IntConstant() != NULL) {

    return v->type()->as_IntConstant()->value() == 0;

  } else if (v->type()->as_LongConstant() != NULL) {

    return v->type()->as_LongConstant()->value() == 0L;

  } else if (v->type()->as_ObjectConstant() != NULL) {

    return v->type()->as_ObjectConstant()->value()->is_null_object();

  } else {

    return false;

  }

}

// only simm13 constants can be inlined

bool LIRGenerator:: can_inline_as_constant(Value i) const {

  if (i->type()->as_IntConstant() != NULL) {

    return Assembler::is_simm13(i->type()->as_IntConstant()->value());

  } else {

    return can_store_as_constant(i, as_BasicType(i->type()));

  }

}

bool LIRGenerator:: can_inline_as_constant(LIR_Const* c) const {

  if (c->type() == T_INT) {

    return Assembler::is_simm13(c->as_jint());

  }

  return false;

}

LIR_Opr LIRGenerator::safepoint_poll_register() {

  return new_register(T_INT);

}

LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,

                                            int shift, int disp, BasicType type) {

  assert(base->is_register(), "must be");

  // accumulate fixed displacements

  if (index->is_constant()) {

    disp += index->as_constant_ptr()->as_jint() << shift;

    index = LIR_OprFact::illegalOpr;

  }

  if (index->is_register()) {

    // apply the shift and accumulate the displacement

    if (shift > 0) {

      LIR_Opr tmp = new_register(T_INT);

      __ shift_left(index, shift, tmp);

      index = tmp;

    }

    if (disp != 0) {

      LIR_Opr tmp = new_register(T_INT);

      if (Assembler::is_simm13(disp)) {

        __ add(tmp, LIR_OprFact::intConst(disp), tmp);

        index = tmp;

      } else {

        __ move(LIR_OprFact::intConst(disp), tmp);

        __ add(tmp, index, tmp);

        index = tmp;

      }

      disp = 0;

    }

  } else if (disp != 0 && !Assembler::is_simm13(disp)) {

    // index is illegal so replace it with the displacement loaded into a register

    index = new_register(T_INT);

    __ move(LIR_OprFact::intConst(disp), index);

    disp = 0;

  }

  // at this point we either have base + index or base + displacement

  if (disp == 0) {

    return new LIR_Address(base, index, type);

  } else {

    assert(Assembler::is_simm13(disp), "must be");

    return new LIR_Address(base, disp, type);

  }

}

LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,

                                              BasicType type, bool needs_card_mark) {

  int elem_size = type2aelembytes(type);

  int shift = exact_log2(elem_size);

  LIR_Opr base_opr;

  int offset = arrayOopDesc::base_offset_in_bytes(type);

  if (index_opr->is_constant()) {

    int i = index_opr->as_constant_ptr()->as_jint();

    int array_offset = i * elem_size;

    if (Assembler::is_simm13(array_offset + offset)) {

      base_opr = array_opr;

      offset = array_offset + offset;

    } else {

      base_opr = new_pointer_register();

      if (Assembler::is_simm13(array_offset)) {

        __ add(array_opr, LIR_OprFact::intptrConst(array_offset), base_opr);

      } else {

        __ move(LIR_OprFact::intptrConst(array_offset), base_opr);

        __ add(base_opr, array_opr, base_opr);

      }

    }

  } else {

#ifdef _LP64

    if (index_opr->type() == T_INT) {

      LIR_Opr tmp = new_register(T_LONG);

      __ convert(Bytecodes::_i2l, index_opr, tmp);

      index_opr = tmp;

    }

#endif

    base_opr = new_pointer_register();

    assert (index_opr->is_register(), "Must be register");

    if (shift > 0) {

      __ shift_left(index_opr, shift, base_opr);

      __ add(base_opr, array_opr, base_opr);

    } else {

      __ add(index_opr, array_opr, base_opr);

    }

  }

  if (needs_card_mark) {

    LIR_Opr ptr = new_pointer_register();

    __ add(base_opr, LIR_OprFact::intptrConst(offset), ptr);

    return new LIR_Address(ptr, 0, type);

  } else {

    return new LIR_Address(base_opr, offset, type);

  }

}

void LIRGenerator::increment_counter(address counter, int step) {

  LIR_Opr pointer = new_pointer_register();

  __ move(LIR_OprFact::intptrConst(counter), pointer);

  LIR_Address* addr = new LIR_Address(pointer, 0, T_INT);

  increment_counter(addr, step);

}

void LIRGenerator::increment_counter(LIR_Address* addr, int step) {

  LIR_Opr temp = new_register(T_INT);

  __ move(addr, temp);

  LIR_Opr c = LIR_OprFact::intConst(step);

  if (Assembler::is_simm13(step)) {

    __ add(temp, c, temp);

  } else {

    LIR_Opr temp2 = new_register(T_INT);

    __ move(c, temp2);

    __ add(temp, temp2, temp);

  }

  __ move(temp, addr);

}

void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {

  LIR_Opr o7opr = FrameMap::O7_opr;

  __ load(new LIR_Address(base, disp, T_INT), o7opr, info);

  __ cmp(condition, o7opr, c);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {

  LIR_Opr o7opr = FrameMap::O7_opr;

  __ load(new LIR_Address(base, disp, type), o7opr, info);

  __ cmp(condition, reg, o7opr);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {

  LIR_Opr o7opr = FrameMap::O7_opr;

  __ load(new LIR_Address(base, disp, type), o7opr, info);

  __ cmp(condition, reg, o7opr);

}

bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {

  assert(left != result, "should be different registers");

  if (is_power_of_2(c + 1)) {

    __ shift_left(left, log2_intptr(c + 1), result);

    __ sub(result, left, result);

    return true;

  } else if (is_power_of_2(c - 1)) {

    __ shift_left(left, log2_intptr(c - 1), result);

    __ add(result, left, result);

    return true;

  }

  return false;

}

void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {

  BasicType t = item->type();

  LIR_Opr sp_opr = FrameMap::SP_opr;

  if ((t == T_LONG || t == T_DOUBLE) &&

      ((in_bytes(offset_from_sp) - STACK_BIAS) % 8 != 0)) {

    __ unaligned_move(item, new LIR_Address(sp_opr, in_bytes(offset_from_sp), t));

  } else {

    __ move(item, new LIR_Address(sp_opr, in_bytes(offset_from_sp), t));

  }

}

//----------------------------------------------------------------------

//             visitor functions

//----------------------------------------------------------------------

void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {

  assert(x->is_root(),"");

  bool needs_range_check = true;

  bool use_length = x->length() != NULL;

  bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;

  bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||

                                         !get_jobject_constant(x->value())->is_null_object());

  LIRItem array(x->array(), this);

  LIRItem index(x->index(), this);

  LIRItem value(x->value(), this);

  LIRItem length(this);

  array.load_item();

  index.load_nonconstant();

  if (use_length) {

    needs_range_check = x->compute_needs_range_check();

    if (needs_range_check) {

      length.set_instruction(x->length());

      length.load_item();

    }

  }

  if (needs_store_check) {

    value.load_item();

  } else {

    value.load_for_store(x->elt_type());

  }

  set_no_result(x);

  // the CodeEmitInfo must be duplicated for each different

  // LIR-instruction because spilling can occur anywhere between two

  // instructions and so the debug information must be different

  CodeEmitInfo* range_check_info = state_for(x);

  CodeEmitInfo* null_check_info = NULL;

  if (x->needs_null_check()) {

    null_check_info = new CodeEmitInfo(range_check_info);

  }

  // emit array address setup early so it schedules better

  LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);

  if (GenerateRangeChecks && needs_range_check) {

    if (use_length) {

      __ cmp(lir_cond_belowEqual, length.result(), index.result());

      __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));

    } else {

      array_range_check(array.result(), index.result(), null_check_info, range_check_info);

      // range_check also does the null check

      null_check_info = NULL;

    }

  }

  if (GenerateArrayStoreCheck && needs_store_check) {

    LIR_Opr tmp1 = FrameMap::G1_opr;

    LIR_Opr tmp2 = FrameMap::G3_opr;

    LIR_Opr tmp3 = FrameMap::G5_opr;

    CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);

    __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info);

  }

  if (obj_store) {

    // Needs GC write barriers.

    pre_barrier(LIR_OprFact::address(array_addr), false, NULL);

  }

  __ move(value.result(), array_addr, null_check_info);

  if (obj_store) {

    // Is this precise?

    post_barrier(LIR_OprFact::address(array_addr), value.result());

  }

}

void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {

  assert(x->is_root(),"");

  LIRItem obj(x->obj(), this);

  obj.load_item();

  set_no_result(x);

  LIR_Opr lock    = FrameMap::G1_opr;

  LIR_Opr scratch = FrameMap::G3_opr;

  LIR_Opr hdr     = FrameMap::G4_opr;

  CodeEmitInfo* info_for_exception = NULL;

  if (x->needs_null_check()) {

    info_for_exception = state_for(x, x->lock_stack_before());

  }

  // this CodeEmitInfo must not have the xhandlers because here the

  // object is already locked (xhandlers expects object to be unlocked)

  CodeEmitInfo* info = state_for(x, x->state(), true);

  monitor_enter(obj.result(), lock, hdr, scratch, x->monitor_no(), info_for_exception, info);

}

void LIRGenerator::do_MonitorExit(MonitorExit* x) {

  assert(x->is_root(),"");

  LIRItem obj(x->obj(), this);

  obj.dont_load_item();

  set_no_result(x);

  LIR_Opr lock      = FrameMap::G1_opr;

  LIR_Opr hdr       = FrameMap::G3_opr;

  LIR_Opr obj_temp  = FrameMap::G4_opr;

  monitor_exit(obj_temp, lock, hdr, x->monitor_no());

}

// _ineg, _lneg, _fneg, _dneg

void LIRGenerator::do_NegateOp(NegateOp* x) {

  LIRItem value(x->x(), this);

  value.load_item();

  LIR_Opr reg = rlock_result(x);

  __ negate(value.result(), reg);

}

// for  _fadd, _fmul, _fsub, _fdiv, _frem

//      _dadd, _dmul, _dsub, _ddiv, _drem

void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {

  switch (x->op()) {

  case Bytecodes::_fadd:

  case Bytecodes::_fmul:

  case Bytecodes::_fsub:

  case Bytecodes::_fdiv:

  case Bytecodes::_dadd:

  case Bytecodes::_dmul:

  case Bytecodes::_dsub:

  case Bytecodes::_ddiv: {

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    left.load_item();

    right.load_item();

    rlock_result(x);

    arithmetic_op_fpu(x->op(), x->operand(), left.result(), right.result(), x->is_strictfp());

  }

  break;

  case Bytecodes::_frem:

  case Bytecodes::_drem: {

    address entry;

    switch (x->op()) {

    case Bytecodes::_frem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::frem);

      break;

    case Bytecodes::_drem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::drem);

      break;

    default:

      ShouldNotReachHere();

    }

    LIR_Opr result = call_runtime(x->x(), x->y(), entry, x->type(), NULL);

    set_result(x, result);

  }

  break;

  default: ShouldNotReachHere();

  }

}

// for  _ladd, _lmul, _lsub, _ldiv, _lrem

void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {

  switch (x->op()) {

  case Bytecodes::_lrem:

  case Bytecodes::_lmul:

  case Bytecodes::_ldiv: {

    if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem) {

      LIRItem right(x->y(), this);

      right.load_item();

      CodeEmitInfo* info = state_for(x);

      LIR_Opr item = right.result();

      assert(item->is_register(), "must be");

      __ cmp(lir_cond_equal, item, LIR_OprFact::longConst(0));

      __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));

    }

    address entry;

    switch (x->op()) {

    case Bytecodes::_lrem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem);

      break; // check if dividend is 0 is done elsewhere

    case Bytecodes::_ldiv:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv);

      break; // check if dividend is 0 is done elsewhere

    case Bytecodes::_lmul:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul);

      break;

    default:

      ShouldNotReachHere();

    }

    // order of arguments to runtime call is reversed.

    LIR_Opr result = call_runtime(x->y(), x->x(), entry, x->type(), NULL);

    set_result(x, result);

    break;

  }

  case Bytecodes::_ladd:

  case Bytecodes::_lsub: {

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    left.load_item();

    right.load_item();

    rlock_result(x);

    arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);

    break;

  }

  default: ShouldNotReachHere();

  }

}

// Returns if item is an int constant that can be represented by a simm13

static bool is_simm13(LIR_Opr item) {

  if (item->is_constant() && item->type() == T_INT) {

    return Assembler::is_simm13(item->as_constant_ptr()->as_jint());

  } else {