/*

 * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

class BiasedLockingCounters;

// <sys/trap.h> promises that the system will not use traps 16-31

#define ST_RESERVED_FOR_USER_0 0x10

/* Written: David Ungar 4/19/97 */

// Contains all the definitions needed for sparc assembly code generation.

// Register aliases for parts of the system:

// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe

// across context switches in V8+ ABI.  Of course, there are no 64 bit regs

// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.

// g2-g4 are scratch registers called "application globals".  Their

// meaning is reserved to the "compilation system"--which means us!

// They are are not supposed to be touched by ordinary C code, although

// highly-optimized C code might steal them for temps.  They are safe

// across thread switches, and the ABI requires that they be safe

// across function calls.

//

// g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered

// across func calls, and V8+ also allows g5 to be clobbered across

// func calls.  Also, g1 and g5 can get touched while doing shared

// library loading.

//

// We must not touch g7 (it is the thread-self register) and g6 is

// reserved for certain tools.  g0, of course, is always zero.

//

// (Sources:  SunSoft Compilers Group, thread library engineers.)

// %%%% The interpreter should be revisited to reduce global scratch regs.

// This global always holds the current JavaThread pointer:

REGISTER_DECLARATION(Register, G2_thread , G2);

REGISTER_DECLARATION(Register, G6_heapbase , G6);

// The following globals are part of the Java calling convention:

REGISTER_DECLARATION(Register, G5_method             , G5);

REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);

REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);

// The following globals are used for the new C1 & interpreter calling convention:

REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument

// This local is used to preserve G2_thread in the interpreter and in stubs:

REGISTER_DECLARATION(Register, L7_thread_cache , L7);

// These globals are used as scratch registers in the interpreter:

REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch

REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME

REGISTER_DECLARATION(Register, G3_scratch    , G3);

REGISTER_DECLARATION(Register, G4_scratch    , G4);

// These globals are used as short-lived scratch registers in the compiler:

REGISTER_DECLARATION(Register, Gtemp  , G5);

// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,

// because a single patchable "set" instruction (NativeMovConstReg,

// or NativeMovConstPatching for compiler1) instruction

// serves to set up either quantity, depending on whether the compiled

// call site is an inline cache or is megamorphic.  See the function

// CompiledIC::set_to_megamorphic.

//

// On the other hand, G5_inline_cache_klass must differ from G5_method,

// because both registers are needed for an inline cache that calls

// an interpreted method.

//

// Note that G5_method is only the method-self for the interpreter,

// and is logically unrelated to G5_megamorphic_method.

//

// Invariants on G2_thread (the JavaThread pointer):

//  - it should not be used for any other purpose anywhere

//  - it must be re-initialized by StubRoutines::call_stub()

//  - it must be preserved around every use of call_VM

// We can consider using g2/g3/g4 to cache more values than the

// JavaThread, such as the card-marking base or perhaps pointers into

// Eden.  It's something of a waste to use them as scratch temporaries,

// since they are not supposed to be volatile.  (Of course, if we find

// that Java doesn't benefit from application globals, then we can just

// use them as ordinary temporaries.)

//

// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,

// it makes sense to use them routinely for procedure linkage,

// whenever the On registers are not applicable.  Examples:  G5_method,

// G5_inline_cache_klass, and a double handful of miscellaneous compiler

// stubs.  This means that compiler stubs, etc., should be kept to a

// maximum of two or three G-register arguments.

// stub frames

REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself

// Interpreter frames

#ifdef CC_INTERP

REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer

REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch

REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)

REGISTER_DECLARATION(Register, L2_scratch       , L2);

REGISTER_DECLARATION(Register, L3_scratch       , L3);

REGISTER_DECLARATION(Register, L4_scratch       , L4);

REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses

REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses

REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache

REGISTER_DECLARATION(Register, O5_savedSP       , O5);

REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply

                                                       // a copy SP, so in 64-bit it's a biased value.  The bias

                                                       // is added and removed as needed in the frame code.

// Interface to signature handler

REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler

REGISTER_DECLARATION(Register, Lmethod          , L6); // methodOop when calling signature handler

#else

REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer

REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode

REGISTER_DECLARATION(Register, Lmethod          , L2);

REGISTER_DECLARATION(Register, Llocals          , L3);

REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler

                                                       // must match Llocals in asm interpreter

REGISTER_DECLARATION(Register, Lmonitors        , L4);

REGISTER_DECLARATION(Register, Lbyte_code       , L5);

// When calling out from the interpreter we record SP so that we can remove any extra stack

// space allocated during adapter transitions. This register is only live from the point

// of the call until we return.

REGISTER_DECLARATION(Register, Llast_SP         , L5);

REGISTER_DECLARATION(Register, Lscratch         , L5);

REGISTER_DECLARATION(Register, Lscratch2        , L6);

REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache

REGISTER_DECLARATION(Register, O5_savedSP       , O5);

REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply

                                                       // a copy SP, so in 64-bit it's a biased value.  The bias

                                                       // is added and removed as needed in the frame code.

REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables

REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode

REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data

#endif /* CC_INTERP */

// NOTE: Lscratch2 and LcpoolCache point to the same registers in

//       the interpreter code. If Lscratch2 needs to be used for some

//       purpose than LcpoolCache should be restore after that for

//       the interpreter to work right

// (These assignments must be compatible with L7_thread_cache; see above.)

// Since Lbcp points into the middle of the method object,

// it is temporarily converted into a "bcx" during GC.

// Exception processing

// These registers are passed into exception handlers.

// All exception handlers require the exception object being thrown.

// In addition, an nmethod's exception handler must be passed

// the address of the call site within the nmethod, to allow

// proper selection of the applicable catch block.

// (Interpreter frames use their own bcp() for this purpose.)

//

// The Oissuing_pc value is not always needed.  When jumping to a

// handler that is known to be interpreted, the Oissuing_pc value can be

// omitted.  An actual catch block in compiled code receives (from its

// nmethod's exception handler) the thrown exception in the Oexception,

// but it doesn't need the Oissuing_pc.

//

// If an exception handler (either interpreted or compiled)

// discovers there is no applicable catch block, it updates

// the Oissuing_pc to the continuation PC of its own caller,

// pops back to that caller's stack frame, and executes that

// caller's exception handler.  Obviously, this process will

// iterate until the control stack is popped back to a method

// containing an applicable catch block.  A key invariant is

// that the Oissuing_pc value is always a value local to

// the method whose exception handler is currently executing.

//

// Note:  The issuing PC value is __not__ a raw return address (I7 value).

// It is a "return pc", the address __following__ the call.

// Raw return addresses are converted to issuing PCs by frame::pc(),

// or by stubs.  Issuing PCs can be used directly with PC range tables.

//

REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown

REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from

// These must occur after the declarations above

#ifndef DONT_USE_REGISTER_DEFINES

#define Gthread             AS_REGISTER(Register, Gthread)

#define Gmethod             AS_REGISTER(Register, Gmethod)

#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)

#define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)

#define Gargs               AS_REGISTER(Register, Gargs)

#define Lthread_cache       AS_REGISTER(Register, Lthread_cache)

#define Gframe_size         AS_REGISTER(Register, Gframe_size)

#define Gtemp               AS_REGISTER(Register, Gtemp)

#ifdef CC_INTERP

#define Lstate              AS_REGISTER(Register, Lstate)

#define Lesp                AS_REGISTER(Register, Lesp)

#define L1_scratch          AS_REGISTER(Register, L1_scratch)

#define Lmirror             AS_REGISTER(Register, Lmirror)

#define L2_scratch          AS_REGISTER(Register, L2_scratch)

#define L3_scratch          AS_REGISTER(Register, L3_scratch)

#define L4_scratch          AS_REGISTER(Register, L4_scratch)

#define Lscratch            AS_REGISTER(Register, Lscratch)

#define Lscratch2           AS_REGISTER(Register, Lscratch2)

#define L7_scratch          AS_REGISTER(Register, L7_scratch)

#define Ostate              AS_REGISTER(Register, Ostate)

#else

#define Lesp                AS_REGISTER(Register, Lesp)

#define Lbcp                AS_REGISTER(Register, Lbcp)

#define Lmethod             AS_REGISTER(Register, Lmethod)

#define Llocals             AS_REGISTER(Register, Llocals)

#define Lmonitors           AS_REGISTER(Register, Lmonitors)

#define Lbyte_code          AS_REGISTER(Register, Lbyte_code)

#define Lscratch            AS_REGISTER(Register, Lscratch)

#define Lscratch2           AS_REGISTER(Register, Lscratch2)

#define LcpoolCache         AS_REGISTER(Register, LcpoolCache)

#endif /* ! CC_INTERP */

#define Lentry_args         AS_REGISTER(Register, Lentry_args)

#define I5_savedSP          AS_REGISTER(Register, I5_savedSP)

#define O5_savedSP          AS_REGISTER(Register, O5_savedSP)

#define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)

#define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)

#define IdispatchTables     AS_REGISTER(Register, IdispatchTables)

#define Oexception          AS_REGISTER(Register, Oexception)

#define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)

#endif

// Address is an abstraction used to represent a memory location.

//

// Note: A register location is represented via a Register, not

//       via an address for efficiency & simplicity reasons.

class Address VALUE_OBJ_CLASS_SPEC {

 private:

  Register              _base;

#ifdef _LP64

  int                   _hi32;          // bits 63::32

  int                   _low32;         // bits 31::0

#endif

  int                   _hi;

  int                   _disp;

  RelocationHolder      _rspec;

  RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {

    switch (rt) {

    case relocInfo::external_word_type:

      return external_word_Relocation::spec(a);

    case relocInfo::internal_word_type:

      return internal_word_Relocation::spec(a);

#ifdef _LP64

    case relocInfo::opt_virtual_call_type:

      return opt_virtual_call_Relocation::spec();

    case relocInfo::static_call_type:

      return static_call_Relocation::spec();

    case relocInfo::runtime_call_type:

      return runtime_call_Relocation::spec();

#endif

    case relocInfo::none:

      return RelocationHolder();

    default:

      ShouldNotReachHere();

      return RelocationHolder();

    }

  }

 public:

  Address(Register b, address a, relocInfo::relocType rt = relocInfo::none)

    : _rspec(rspec_from_rtype(rt, a))

  {

    _base  = b;

#ifdef _LP64

    _hi32  = (intptr_t)a >> 32;    // top 32 bits in 64 bit word

    _low32 = (intptr_t)a & ~0;     // low 32 bits in 64 bit word

#endif

    _hi    = (intptr_t)a & ~0x3ff; // top    22 bits in low word

    _disp  = (intptr_t)a &  0x3ff; // bottom 10 bits

  }

  Address(Register b, address a, RelocationHolder const& rspec)

    : _rspec(rspec)

  {

    _base  = b;

#ifdef _LP64

    _hi32  = (intptr_t)a >> 32;    // top 32 bits in 64 bit word

    _low32 = (intptr_t)a & ~0;     // low 32 bits in 64 bit word

#endif

    _hi    = (intptr_t)a & ~0x3ff; // top    22 bits

    _disp  = (intptr_t)a &  0x3ff; // bottom 10 bits

  }

  Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder())

    : _rspec(rspec)

  {

    _base  = b;

#ifdef _LP64

// [RGV] Put in Assert to force me to check usage of this constructor

     assert( h == 0, "Check usage of this constructor" );

    _hi32  = h;

    _low32 = d;

    _hi    = h;

    _disp  = d;

#else

    _hi    = h;

    _disp  = d;

#endif

  }

  Address()

    : _rspec(RelocationHolder())

  {

    _base  = G0;

#ifdef _LP64

    _hi32  = 0;

    _low32 = 0;

#endif

    _hi    = 0;

    _disp  = 0;

  }

  // fancier constructors

  enum addr_type {

    extra_in_argument,  // in the In registers

    extra_out_argument  // in the Outs

  };

  Address( addr_type, int );

  // accessors

  Register               base() const { return _base; }

#ifdef _LP64

  int                   hi32()  const { return _hi32; }

  int                   low32() const { return _low32; }

#endif

  int                      hi() const { return _hi;  }

  int                    disp() const { return _disp; }

#ifdef _LP64

  intptr_t              value() const { return ((intptr_t)_hi32 << 32) |

                                                (intptr_t)(uint32_t)_low32; }

#else

  int                   value() const { return _hi | _disp; }

#endif

  const relocInfo::relocType  rtype() { return _rspec.type(); }

  const RelocationHolder&     rspec() { return _rspec; }

  RelocationHolder      rspec(int offset) const {

    return offset == 0 ? _rspec : _rspec.plus(offset);

  }

  inline bool is_simm13(int offset = 0);  // check disp+offset for overflow

  Address split_disp() const {            // deal with disp overflow

    Address a = (*this);

    int hi_disp = _disp & ~0x3ff;

    if (hi_disp != 0) {

      a._disp -= hi_disp;

      a._hi   += hi_disp;

    }

    return a;

  }

  Address after_save() const {

    Address a = (*this);

    a._base = a._base->after_save();

    return a;

  }

  Address after_restore() const {

    Address a = (*this);

    a._base = a._base->after_restore();

    return a;

  }

  friend class Assembler;

};

inline Address RegisterImpl::address_in_saved_window() const {

   return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));

}

// Argument is an abstraction used to represent an outgoing

// actual argument or an incoming formal parameter, whether

// it resides in memory or in a register, in a manner consistent

// with the SPARC Application Binary Interface, or ABI.  This is

// often referred to as the native or C calling convention.

class Argument VALUE_OBJ_CLASS_SPEC {

 private:

  int _number;

  bool _is_in;

 public:

#ifdef _LP64

  enum {

    n_register_parameters = 6,          // only 6 registers may contain integer parameters

    n_float_register_parameters = 16    // Can have up to 16 floating registers

  };

#else

  enum {

    n_register_parameters = 6           // only 6 registers may contain integer parameters

  };

#endif

  // creation

  Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}

  int  number() const  { return _number;  }

  bool is_in()  const  { return _is_in;   }

  bool is_out() const  { return !is_in(); }

  Argument successor() const  { return Argument(number() + 1, is_in()); }

  Argument as_in()     const  { return Argument(number(), true ); }

  Argument as_out()    const  { return Argument(number(), false); }

  // locating register-based arguments:

  bool is_register() const { return _number < n_register_parameters; }

#ifdef _LP64

  // locating Floating Point register-based arguments:

  bool is_float_register() const { return _number < n_float_register_parameters; }

  FloatRegister as_float_register() const {

    assert(is_float_register(), "must be a register argument");

    return as_FloatRegister(( number() *2 ) + 1);

  }

  FloatRegister as_double_register() const {

    assert(is_float_register(), "must be a register argument");

    return as_FloatRegister(( number() *2 ));

  }

#endif

  Register as_register() const {

    assert(is_register(), "must be a register argument");

    return is_in() ? as_iRegister(number()) : as_oRegister(number());

  }

  // locating memory-based arguments

  Address as_address() const {

    assert(!is_register(), "must be a memory argument");

    return address_in_frame();

  }

  // When applied to a register-based argument, give the corresponding address

  // into the 6-word area "into which callee may store register arguments"

  // (This is a different place than the corresponding register-save area location.)

  Address address_in_frame() const {

    return Address( is_in()   ? Address::extra_in_argument

                              : Address::extra_out_argument,

                    _number );

  }

  // debugging

  const char* name() const;

  friend class Assembler;

};

// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction

// level; i.e., what you write

// is what you get. The Assembler is generating code into a CodeBuffer.

class Assembler : public AbstractAssembler  {

 protected:

  static void print_instruction(int inst);

  static int  patched_branch(int dest_pos, int inst, int inst_pos);

  static int  branch_destination(int inst, int pos);

  friend class AbstractAssembler;

  // code patchers need various routines like inv_wdisp()

  friend class NativeInstruction;

  friend class NativeGeneralJump;

  friend class Relocation;

  friend class Label;

 public:

  // op carries format info; see page 62 & 267

  enum ops {

    call_op   = 1, // fmt 1

    branch_op = 0, // also sethi (fmt2)

    arith_op  = 2, // fmt 3, arith & misc

    ldst_op   = 3  // fmt 3, load/store

  };

  enum op2s {

    bpr_op2   = 3,