author | chegar |
Wed, 16 Dec 2015 12:17:03 +0000 | |
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child 35071 | a0910b1d3e0d |
child 35112 | b3c4347bb751 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP |
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#define CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP |
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const int StackAlignmentInBytes = 16; |
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#define SUPPORTS_NATIVE_CX8 |
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// The expected size in bytes of a cache line, used to pad data structures. |
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#if defined(TIERED) |
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#ifdef _LP64 |
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// tiered, 64-bit, large machine |
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#define DEFAULT_CACHE_LINE_SIZE 128 |
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#else |
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// tiered, 32-bit, medium machine |
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#define DEFAULT_CACHE_LINE_SIZE 64 |
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#endif |
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#elif defined(COMPILER1) |
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// pure C1, 32-bit, small machine |
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// i486 was the last Intel chip with 16-byte cache line size |
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#define DEFAULT_CACHE_LINE_SIZE 32 |
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#elif defined(COMPILER2) || defined(SHARK) |
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#ifdef _LP64 |
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// pure C2, 64-bit, large machine |
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#define DEFAULT_CACHE_LINE_SIZE 128 |
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#else |
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// pure C2, 32-bit, medium machine |
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#define DEFAULT_CACHE_LINE_SIZE 64 |
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#endif |
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#endif |
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#if defined(COMPILER2) && !defined(JAVASE_EMBEDDED) |
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// Include Restricted Transactional Memory lock eliding optimization |
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#define INCLUDE_RTM_OPT 1 |
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#endif |
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#endif // CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP |