//

// Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

// ARM Architecture Description File

//----------DEFINITION BLOCK---------------------------------------------------

// Define name --> value mappings to inform the ADLC of an integer valued name

// Current support includes integer values in the range [0, 0x7FFFFFFF]

// Format:

//        int_def  <name>         ( <int_value>, <expression>);

// Generated Code in ad_<arch>.hpp

//        #define  <name>   (<expression>)

//        // value == <int_value>

// Generated code in ad_<arch>.cpp adlc_verification()

//        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");

//

definitions %{

// The default cost (of an ALU instruction).

  int_def DEFAULT_COST      (    100,     100);

  int_def HUGE_COST         (1000000, 1000000);

// Memory refs are twice as expensive as run-of-the-mill.

  int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);

// Branches are even more expensive.

  int_def BRANCH_COST       (    300, DEFAULT_COST * 3);

  int_def CALL_COST         (    300, DEFAULT_COST * 3);

%}

//----------SOURCE BLOCK-------------------------------------------------------

// This is a block of C++ code which provides values, functions, and

// definitions necessary in the rest of the architecture description

source_hpp %{

// Header information of the source block.

// Method declarations/definitions which are used outside

// the ad-scope can conveniently be defined here.

//

// To keep related declarations/definitions/uses close together,

// we switch between source %{ }% and source_hpp %{ }% freely as needed.

// Does destination need to be loaded in a register then passed to a

// branch instruction?

extern bool maybe_far_call(const CallNode *n);

extern bool maybe_far_call(const MachCallNode *n);

static inline bool cache_reachable() {

  return MacroAssembler::_cache_fully_reachable();

}

#define ldr_32 ldr

#define str_32 str

#define tst_32 tst

#define teq_32 teq

#if 1

extern bool PrintOptoAssembly;

#endif

class c2 {

public:

  static OptoRegPair return_value(int ideal_reg);

};

class CallStubImpl {

  //--------------------------------------------------------------

  //---<  Used for optimization in Compile::Shorten_branches  >---

  //--------------------------------------------------------------

 public:

  // Size of call trampoline stub.

  static uint size_call_trampoline() {

    return 0; // no call trampolines on this platform

  }

  // number of relocations needed by a call trampoline stub

  static uint reloc_call_trampoline() {

    return 0; // no call trampolines on this platform

  }

};

class HandlerImpl {

 public:

  static int emit_exception_handler(CodeBuffer &cbuf);

  static int emit_deopt_handler(CodeBuffer& cbuf);

  static uint size_exception_handler() {

    return ( 3 * 4 );

  }

  static uint size_deopt_handler() {

    return ( 9 * 4 );

  }

};

%}

source %{

#define __ _masm.

static FloatRegister reg_to_FloatRegister_object(int register_encoding);

static Register reg_to_register_object(int register_encoding);

// ****************************************************************************

// REQUIRED FUNCTIONALITY

// Indicate if the safepoint node needs the polling page as an input.

// Since ARM does not have absolute addressing, it does.

bool SafePointNode::needs_polling_address_input() {

  return true;

}

// emit an interrupt that is caught by the debugger (for debugging compiler)

void emit_break(CodeBuffer &cbuf) {

  MacroAssembler _masm(&cbuf);

  __ breakpoint();

}

#ifndef PRODUCT

void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {

  st->print("TA");

}

#endif

void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

  emit_break(cbuf);

}

uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {

  return MachNode::size(ra_);

}

void emit_nop(CodeBuffer &cbuf) {

  MacroAssembler _masm(&cbuf);

  __ nop();

}

void emit_call_reloc(CodeBuffer &cbuf, const MachCallNode *n, MachOper *m, RelocationHolder const& rspec) {

  int ret_addr_offset0 = n->as_MachCall()->ret_addr_offset();

  int call_site_offset = cbuf.insts()->mark_off();

  MacroAssembler _masm(&cbuf);

  __ set_inst_mark(); // needed in emit_to_interp_stub() to locate the call

  address target = (address)m->method();

  assert(n->as_MachCall()->entry_point() == target, "sanity");

  assert(maybe_far_call(n) == !__ reachable_from_cache(target), "sanity");

  assert(cache_reachable() == __ cache_fully_reachable(), "sanity");

  assert(target != NULL, "need real address");

  int ret_addr_offset = -1;

  if (rspec.type() == relocInfo::runtime_call_type) {

    __ call(target, rspec);

    ret_addr_offset = __ offset();

  } else {

    // scratches Rtemp

    ret_addr_offset = __ patchable_call(target, rspec, true);

  }

  assert(ret_addr_offset - call_site_offset == ret_addr_offset0, "fix ret_addr_offset()");

}

//=============================================================================

// REQUIRED FUNCTIONALITY for encoding

void emit_lo(CodeBuffer &cbuf, int val) {  }

void emit_hi(CodeBuffer &cbuf, int val) {  }

//=============================================================================

const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();

int Compile::ConstantTable::calculate_table_base_offset() const {

  int offset = -(size() / 2);

  // flds, fldd: 8-bit  offset multiplied by 4: +/- 1024

  // ldr, ldrb : 12-bit offset:                 +/- 4096

  if (!Assembler::is_simm10(offset)) {

    offset = Assembler::min_simm10();

  }

  return offset;

}

bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }

void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {

  ShouldNotReachHere();

}

void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

  Compile* C = ra_->C;

  Compile::ConstantTable& constant_table = C->constant_table();

  MacroAssembler _masm(&cbuf);

  Register r = as_Register(ra_->get_encode(this));

  CodeSection* consts_section = __ code()->consts();

  int consts_size = consts_section->align_at_start(consts_section->size());

  assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);

  // Materialize the constant table base.

  address baseaddr = consts_section->start() + -(constant_table.table_base_offset());

  RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);

  __ mov_address(r, baseaddr, rspec);

}

uint MachConstantBaseNode::size(PhaseRegAlloc*) const {

  return 8;

}

#ifndef PRODUCT

void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

  char reg[128];

  ra_->dump_register(this, reg);

  st->print("MOV_SLOW    &constanttable,%s\t! constant table base", reg);

}

#endif

#ifndef PRODUCT

void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

  Compile* C = ra_->C;

  for (int i = 0; i < OptoPrologueNops; i++) {

    st->print_cr("NOP"); st->print("\t");

  }

  size_t framesize = C->frame_size_in_bytes();

  assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

  int bangsize = C->bang_size_in_bytes();

  // Remove two words for return addr and rbp,

  framesize -= 2*wordSize;

  bangsize -= 2*wordSize;

  // Calls to C2R adapters often do not accept exceptional returns.

  // We require that their callers must bang for them.  But be careful, because

  // some VM calls (such as call site linkage) can use several kilobytes of

  // stack.  But the stack safety zone should account for that.

  // See bugs 4446381, 4468289, 4497237.

  if (C->need_stack_bang(bangsize)) {

    st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");

  }

  st->print_cr("PUSH   R_FP|R_LR_LR"); st->print("\t");

  if (framesize != 0) {

    st->print   ("SUB    R_SP, R_SP, " SIZE_FORMAT,framesize);

  }

}

#endif

void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

  Compile* C = ra_->C;

  MacroAssembler _masm(&cbuf);

  for (int i = 0; i < OptoPrologueNops; i++) {

    __ nop();

  }

  size_t framesize = C->frame_size_in_bytes();

  assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

  int bangsize = C->bang_size_in_bytes();

  // Remove two words for return addr and fp,

  framesize -= 2*wordSize;

  bangsize -= 2*wordSize;

  // Calls to C2R adapters often do not accept exceptional returns.

  // We require that their callers must bang for them.  But be careful, because

  // some VM calls (such as call site linkage) can use several kilobytes of

  // stack.  But the stack safety zone should account for that.

  // See bugs 4446381, 4468289, 4497237.

  if (C->need_stack_bang(bangsize)) {

    __ arm_stack_overflow_check(bangsize, Rtemp);

  }

  __ raw_push(FP, LR);

  if (framesize != 0) {

    __ sub_slow(SP, SP, framesize);

  }

  // offset from scratch buffer is not valid

  if (strcmp(cbuf.name(), "Compile::Fill_buffer") == 0) {

    C->set_frame_complete( __ offset() );

  }

  if (C->has_mach_constant_base_node()) {

    // NOTE: We set the table base offset here because users might be

    // emitted before MachConstantBaseNode.

    Compile::ConstantTable& constant_table = C->constant_table();

    constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());

  }

}

uint MachPrologNode::size(PhaseRegAlloc *ra_) const {

  return MachNode::size(ra_);

}

int MachPrologNode::reloc() const {

  return 10; // a large enough number

}

//=============================================================================

#ifndef PRODUCT

void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

  Compile* C = ra_->C;

  size_t framesize = C->frame_size_in_bytes();

  framesize -= 2*wordSize;

  if (framesize != 0) {

    st->print("ADD    R_SP, R_SP, " SIZE_FORMAT "\n\t",framesize);

  }

  st->print("POP    R_FP|R_LR_LR");

  if (do_polling() && ra_->C->is_method_compilation()) {

    st->print("\n\t");

    st->print("MOV    Rtemp, #PollAddr\t! Load Polling address\n\t");

    st->print("LDR    Rtemp,[Rtemp]\t!Poll for Safepointing");

  }

}

#endif

void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

  MacroAssembler _masm(&cbuf);

  Compile* C = ra_->C;

  size_t framesize = C->frame_size_in_bytes();

  framesize -= 2*wordSize;

  if (framesize != 0) {

    __ add_slow(SP, SP, framesize);

  }

  __ raw_pop(FP, LR);

  // If this does safepoint polling, then do it here

  if (do_polling() && ra_->C->is_method_compilation()) {

    // mov_slow here is usually one or two instruction

    __ mov_address(Rtemp, (address)os::get_polling_page());

    __ relocate(relocInfo::poll_return_type);

    __ ldr(Rtemp, Address(Rtemp));

  }

}

uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {

  return MachNode::size(ra_);

}

int MachEpilogNode::reloc() const {

  return 16; // a large enough number

}

const Pipeline * MachEpilogNode::pipeline() const {

  return MachNode::pipeline_class();

}

int MachEpilogNode::safepoint_offset() const {

  assert( do_polling(), "no return for this epilog node");

  //  return MacroAssembler::size_of_sethi(os::get_polling_page());

  Unimplemented();

  return 0;

}

//=============================================================================

// Figure out which register class each belongs in: rc_int, rc_float, rc_stack

enum RC { rc_bad, rc_int, rc_float, rc_stack };

static enum RC rc_class( OptoReg::Name reg ) {

  if (!OptoReg::is_valid(reg)) return rc_bad;

  if (OptoReg::is_stack(reg)) return rc_stack;

  VMReg r = OptoReg::as_VMReg(reg);

  if (r->is_Register()) return rc_int;

  assert(r->is_FloatRegister(), "must be");

  return rc_float;

}

static inline bool is_iRegLd_memhd(OptoReg::Name src_first, OptoReg::Name src_second, int offset) {

  int rlo = Matcher::_regEncode[src_first];

  int rhi = Matcher::_regEncode[src_second];

  if (!((rlo&1)==0 && (rlo+1 == rhi))) {

    tty->print_cr("CAUGHT BAD LDRD/STRD");

  }

  return (rlo&1)==0 && (rlo+1 == rhi) && is_memoryHD(offset);

}

uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,

                                        PhaseRegAlloc *ra_,

                                        bool do_size,

                                        outputStream* st ) const {

  // Get registers to move

  OptoReg::Name src_second = ra_->get_reg_second(in(1));

  OptoReg::Name src_first = ra_->get_reg_first(in(1));

  OptoReg::Name dst_second = ra_->get_reg_second(this );

  OptoReg::Name dst_first = ra_->get_reg_first(this );

  enum RC src_second_rc = rc_class(src_second);

  enum RC src_first_rc = rc_class(src_first);

  enum RC dst_second_rc = rc_class(dst_second);

  enum RC dst_first_rc = rc_class(dst_first);

  assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );

  // Generate spill code!

  int size = 0;

  if (src_first == dst_first && src_second == dst_second)

    return size;            // Self copy, no move

#ifdef TODO

  if (bottom_type()->isa_vect() != NULL) {

  }

#endif

  // Shared code does not expect instruction set capability based bailouts here.

  // Handle offset unreachable bailout with minimal change in shared code.

  // Bailout only for real instruction emit.

  // This requires a single comment change in shared code. ( see output.cpp "Normal" instruction case )

  MacroAssembler _masm(cbuf);

  // --------------------------------------

  // Check for mem-mem move.  Load into unused float registers and fall into

  // the float-store case.

  if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {

    int offset = ra_->reg2offset(src_first);

    if (cbuf && !is_memoryfp(offset)) {

      ra_->C->record_method_not_compilable("unable to handle large constant offsets");

      return 0;

    } else {

      if (src_second_rc != rc_bad) {

        assert((src_first&1)==0 && src_first+1 == src_second, "pair of registers must be aligned/contiguous");

        src_first     = OptoReg::Name(R_mem_copy_lo_num);

        src_second    = OptoReg::Name(R_mem_copy_hi_num);

        src_first_rc  = rc_float;

        src_second_rc = rc_float;

        if (cbuf) {

          __ ldr_double(Rmemcopy, Address(SP, offset));

        } else if (!do_size) {

          st->print(LDR_DOUBLE "   R_%s,[R_SP + #%d]\t! spill",OptoReg::regname(src_first),offset);

        }

      } else {

        src_first     = OptoReg::Name(R_mem_copy_lo_num);

        src_first_rc  = rc_float;

        if (cbuf) {

          __ ldr_float(Rmemcopy, Address(SP, offset));

        } else if (!do_size) {

          st->print(LDR_FLOAT "   R_%s,[R_SP + #%d]\t! spill",OptoReg::regname(src_first),offset);

        }

      }

      size += 4;

    }

  }

  if (src_second_rc == rc_stack && dst_second_rc == rc_stack) {

    Unimplemented();

  }

  // --------------------------------------

  // Check for integer reg-reg copy

  if (src_first_rc == rc_int && dst_first_rc == rc_int) {

    // Else normal reg-reg copy

    assert( src_second != dst_first, "smashed second before evacuating it" );

    if (cbuf) {

      __ mov(reg_to_register_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[src_first]));

#ifndef PRODUCT

    } else if (!do_size) {

      st->print("MOV    R_%s, R_%s\t# spill",

                Matcher::regName[dst_first],

                Matcher::regName[src_first]);

#endif

    }

    size += 4;

  }

  // Check for integer store

  if (src_first_rc == rc_int && dst_first_rc == rc_stack) {

    int offset = ra_->reg2offset(dst_first);

    if (cbuf && !is_memoryI(offset)) {

      ra_->C->record_method_not_compilable("unable to handle large constant offsets");

      return 0;

    } else {

      if (src_second_rc != rc_bad && is_iRegLd_memhd(src_first, src_second, offset)) {

        assert((src_first&1)==0 && src_first+1 == src_second, "pair of registers must be aligned/contiguous");

        if (cbuf) {

          __ str_64(reg_to_register_object(Matcher::_regEncode[src_first]), Address(SP, offset));

#ifndef PRODUCT

        } else if (!do_size) {

          if (size != 0) st->print("\n\t");

          st->print(STR_64 "   R_%s,[R_SP + #%d]\t! spill",OptoReg::regname(src_first), offset);

#endif

        }

        return size + 4;

      } else {

        if (cbuf) {

          __ str_32(reg_to_register_object(Matcher::_regEncode[src_first]), Address(SP, offset));

#ifndef PRODUCT

        } else if (!do_size) {

          if (size != 0) st->print("\n\t");

          st->print(STR_32 "   R_%s,[R_SP + #%d]\t! spill",OptoReg::regname(src_first), offset);

#endif

        }

      }

    }

    size += 4;

  }

  // Check for integer load

  if (dst_first_rc == rc_int && src_first_rc == rc_stack) {

    int offset = ra_->reg2offset(src_first);

    if (cbuf && !is_memoryI(offset)) {

      ra_->C->record_method_not_compilable("unable to handle large constant offsets");

      return 0;