/*

 * Copyright (c) 2005, 2016, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2014, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_FrameMap.hpp"

#include "c1/c1_Instruction.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_LIRGenerator.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArray.hpp"

#include "ci/ciObjArrayKlass.hpp"

#include "ci/ciTypeArrayKlass.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "vmreg_aarch64.inline.hpp"

#ifdef ASSERT

#define __ gen()->lir(__FILE__, __LINE__)->

#else

#define __ gen()->lir()->

#endif

// Item will be loaded into a byte register; Intel only

void LIRItem::load_byte_item() {

  load_item();

}

void LIRItem::load_nonconstant() {

  LIR_Opr r = value()->operand();

  if (r->is_constant()) {

    _result = r;

  } else {

    load_item();

  }

}

//--------------------------------------------------------------

//               LIRGenerator

//--------------------------------------------------------------

LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::r0_oop_opr; }

LIR_Opr LIRGenerator::exceptionPcOpr()  { return FrameMap::r3_opr; }

LIR_Opr LIRGenerator::divInOpr()        { Unimplemented(); return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::divOutOpr()       { Unimplemented(); return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::remOutOpr()       { Unimplemented(); return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::shiftCountOpr()   { Unimplemented(); return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::syncLockOpr()     { return new_register(T_INT); }

LIR_Opr LIRGenerator::syncTempOpr()     { return FrameMap::r0_opr; }

LIR_Opr LIRGenerator::getThreadTemp()   { return LIR_OprFact::illegalOpr; }

LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {

  LIR_Opr opr;

  switch (type->tag()) {

    case intTag:     opr = FrameMap::r0_opr;          break;

    case objectTag:  opr = FrameMap::r0_oop_opr;      break;

    case longTag:    opr = FrameMap::long0_opr;        break;

    case floatTag:   opr = FrameMap::fpu0_float_opr;  break;

    case doubleTag:  opr = FrameMap::fpu0_double_opr;  break;

    case addressTag:

    default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;

  }

  assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");

  return opr;

}

LIR_Opr LIRGenerator::rlock_byte(BasicType type) {

  LIR_Opr reg = new_register(T_INT);

  set_vreg_flag(reg, LIRGenerator::byte_reg);

  return reg;

}

//--------- loading items into registers --------------------------------

bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {

  if (v->type()->as_IntConstant() != NULL) {

    return v->type()->as_IntConstant()->value() == 0L;

  } else if (v->type()->as_LongConstant() != NULL) {

    return v->type()->as_LongConstant()->value() == 0L;

  } else if (v->type()->as_ObjectConstant() != NULL) {

    return v->type()->as_ObjectConstant()->value()->is_null_object();

  } else {

    return false;

  }

}

bool LIRGenerator::can_inline_as_constant(Value v) const {

  // FIXME: Just a guess

  if (v->type()->as_IntConstant() != NULL) {

    return Assembler::operand_valid_for_add_sub_immediate(v->type()->as_IntConstant()->value());

  } else if (v->type()->as_LongConstant() != NULL) {

    return v->type()->as_LongConstant()->value() == 0L;

  } else if (v->type()->as_ObjectConstant() != NULL) {

    return v->type()->as_ObjectConstant()->value()->is_null_object();

  } else {

    return false;

  }

}

bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const { return false; }

LIR_Opr LIRGenerator::safepoint_poll_register() {

  return LIR_OprFact::illegalOpr;

}

LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,

                                            int shift, int disp, BasicType type) {

  assert(base->is_register(), "must be");

  intx large_disp = disp;

  // accumulate fixed displacements

  if (index->is_constant()) {

    large_disp += (intx)(index->as_constant_ptr()->as_jint()) << shift;

    index = LIR_OprFact::illegalOpr;

  }

  if (index->is_register()) {

    // apply the shift and accumulate the displacement

    if (shift > 0) {

      LIR_Opr tmp = new_pointer_register();

      __ shift_left(index, shift, tmp);

      index = tmp;

    }

    if (large_disp != 0) {

      LIR_Opr tmp = new_pointer_register();

      if (Assembler::operand_valid_for_add_sub_immediate(large_disp)) {

        __ add(tmp, tmp, LIR_OprFact::intptrConst(large_disp));

        index = tmp;

      } else {

        __ move(tmp, LIR_OprFact::intptrConst(large_disp));

        __ add(tmp, index, tmp);

        index = tmp;

      }

      large_disp = 0;

    }

  } else if (large_disp != 0 && !Address::offset_ok_for_immed(large_disp, shift)) {

    // index is illegal so replace it with the displacement loaded into a register

    index = new_pointer_register();

    __ move(LIR_OprFact::intptrConst(large_disp), index);

    large_disp = 0;

  }

  // at this point we either have base + index or base + displacement

  if (large_disp == 0) {

    return new LIR_Address(base, index, type);

  } else {

    assert(Address::offset_ok_for_immed(large_disp, 0), "must be");

    return new LIR_Address(base, large_disp, type);

  }

}

LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,

                                              BasicType type, bool needs_card_mark) {

  int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);

  int elem_size = type2aelembytes(type);

  int shift = exact_log2(elem_size);

  LIR_Address* addr;

  if (index_opr->is_constant()) {

    addr = new LIR_Address(array_opr,

                           offset_in_bytes + (intx)(index_opr->as_jint()) * elem_size, type);

  } else {

    if (offset_in_bytes) {

      LIR_Opr tmp = new_pointer_register();

      __ add(array_opr, LIR_OprFact::intConst(offset_in_bytes), tmp);

      array_opr = tmp;

      offset_in_bytes = 0;

    }

    addr =  new LIR_Address(array_opr,

                            index_opr,

                            LIR_Address::scale(type),

                            offset_in_bytes, type);

  }

  if (needs_card_mark) {

    // This store will need a precise card mark, so go ahead and

    // compute the full adddres instead of computing once for the

    // store and again for the card mark.

    LIR_Opr tmp = new_pointer_register();

    __ leal(LIR_OprFact::address(addr), tmp);

    return new LIR_Address(tmp, type);

  } else {

    return addr;

  }

}

LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {

  LIR_Opr r;

  if (type == T_LONG) {

    r = LIR_OprFact::longConst(x);

    if (!Assembler::operand_valid_for_logical_immediate(false, x)) {

      LIR_Opr tmp = new_register(type);

      __ move(r, tmp);

      return tmp;

    }

  } else if (type == T_INT) {

    r = LIR_OprFact::intConst(x);

    if (!Assembler::operand_valid_for_logical_immediate(true, x)) {

      // This is all rather nasty.  We don't know whether our constant

      // is required for a logical or an arithmetic operation, wo we

      // don't know what the range of valid values is!!

      LIR_Opr tmp = new_register(type);

      __ move(r, tmp);

      return tmp;

    }

  } else {

    ShouldNotReachHere();

    r = NULL;  // unreachable

  }

  return r;

}

void LIRGenerator::increment_counter(address counter, BasicType type, int step) {

  LIR_Opr pointer = new_pointer_register();

  __ move(LIR_OprFact::intptrConst(counter), pointer);

  LIR_Address* addr = new LIR_Address(pointer, type);

  increment_counter(addr, step);

}

void LIRGenerator::increment_counter(LIR_Address* addr, int step) {

  LIR_Opr imm = NULL;

  switch(addr->type()) {

  case T_INT:

    imm = LIR_OprFact::intConst(step);

    break;

  case T_LONG:

    imm = LIR_OprFact::longConst(step);

    break;

  default:

    ShouldNotReachHere();

  }

  LIR_Opr reg = new_register(addr->type());

  __ load(addr, reg);

  __ add(reg, imm, reg);

  __ store(reg, addr);

}

void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {

  LIR_Opr reg = new_register(T_INT);

  __ load(generate_address(base, disp, T_INT), reg, info);

  __ cmp(condition, reg, LIR_OprFact::intConst(c));

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {

  LIR_Opr reg1 = new_register(T_INT);

  __ load(generate_address(base, disp, type), reg1, info);

  __ cmp(condition, reg, reg1);

}

bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {

  if (is_power_of_2(c - 1)) {

    __ shift_left(left, exact_log2(c - 1), tmp);

    __ add(tmp, left, result);

    return true;

  } else if (is_power_of_2(c + 1)) {

    __ shift_left(left, exact_log2(c + 1), tmp);

    __ sub(tmp, left, result);

    return true;

  } else {

    return false;

  }

}

void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {

  BasicType type = item->type();

  __ store(item, new LIR_Address(FrameMap::sp_opr, in_bytes(offset_from_sp), type));

}

//----------------------------------------------------------------------

//             visitor functions

//----------------------------------------------------------------------

void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {

  assert(x->is_pinned(),"");

  bool needs_range_check = x->compute_needs_range_check();

  bool use_length = x->length() != NULL;

  bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;

  bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||

                                         !get_jobject_constant(x->value())->is_null_object() ||

                                         x->should_profile());

  LIRItem array(x->array(), this);

  LIRItem index(x->index(), this);

  LIRItem value(x->value(), this);

  LIRItem length(this);

  array.load_item();

  index.load_nonconstant();

  if (use_length && needs_range_check) {

    length.set_instruction(x->length());

    length.load_item();

  }

  if (needs_store_check || x->check_boolean()) {

    value.load_item();

  } else {

    value.load_for_store(x->elt_type());

  }

  set_no_result(x);

  // the CodeEmitInfo must be duplicated for each different

  // LIR-instruction because spilling can occur anywhere between two

  // instructions and so the debug information must be different

  CodeEmitInfo* range_check_info = state_for(x);

  CodeEmitInfo* null_check_info = NULL;

  if (x->needs_null_check()) {

    null_check_info = new CodeEmitInfo(range_check_info);

  }

  // emit array address setup early so it schedules better

  // FIXME?  No harm in this on aarch64, and it might help

  LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);

  if (GenerateRangeChecks && needs_range_check) {

    if (use_length) {

      __ cmp(lir_cond_belowEqual, length.result(), index.result());

      __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));

    } else {

      array_range_check(array.result(), index.result(), null_check_info, range_check_info);

      // range_check also does the null check

      null_check_info = NULL;

    }

  }

  if (GenerateArrayStoreCheck && needs_store_check) {

    LIR_Opr tmp1 = new_register(objectType);

    LIR_Opr tmp2 = new_register(objectType);

    LIR_Opr tmp3 = new_register(objectType);

    CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);

    __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info, x->profiled_method(), x->profiled_bci());

  }

  if (obj_store) {

    // Needs GC write barriers.

    pre_barrier(LIR_OprFact::address(array_addr), LIR_OprFact::illegalOpr /* pre_val */,

                true /* do_load */, false /* patch */, NULL);

    __ move(value.result(), array_addr, null_check_info);

    // Seems to be a precise

    post_barrier(LIR_OprFact::address(array_addr), value.result());

  } else {

    LIR_Opr result = maybe_mask_boolean(x, array.result(), value.result(), null_check_info);

    __ move(result, array_addr, null_check_info);

  }

}

void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.load_item();

  set_no_result(x);

  // "lock" stores the address of the monitor stack slot, so this is not an oop

  LIR_Opr lock = new_register(T_INT);

  // Need a scratch register for biased locking

  LIR_Opr scratch = LIR_OprFact::illegalOpr;

  if (UseBiasedLocking) {

    scratch = new_register(T_INT);

  }

  CodeEmitInfo* info_for_exception = NULL;

  if (x->needs_null_check()) {

    info_for_exception = state_for(x);

  }

  // this CodeEmitInfo must not have the xhandlers because here the

  // object is already locked (xhandlers expect object to be unlocked)

  CodeEmitInfo* info = state_for(x, x->state(), true);

  monitor_enter(obj.result(), lock, syncTempOpr(), scratch,

                        x->monitor_no(), info_for_exception, info);

}

void LIRGenerator::do_MonitorExit(MonitorExit* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.dont_load_item();

  LIR_Opr lock = new_register(T_INT);

  LIR_Opr obj_temp = new_register(T_INT);

  set_no_result(x);

  monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no());

}

void LIRGenerator::do_NegateOp(NegateOp* x) {

  LIRItem from(x->x(), this);

  from.load_item();

  LIR_Opr result = rlock_result(x);

  __ negate (from.result(), result);

}

// for  _fadd, _fmul, _fsub, _fdiv, _frem

//      _dadd, _dmul, _dsub, _ddiv, _drem

void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {

  if (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem) {

    // float remainder is implemented as a direct call into the runtime

    LIRItem right(x->x(), this);

    LIRItem left(x->y(), this);

    BasicTypeList signature(2);

    if (x->op() == Bytecodes::_frem) {

      signature.append(T_FLOAT);

      signature.append(T_FLOAT);

    } else {

      signature.append(T_DOUBLE);

      signature.append(T_DOUBLE);

    }

    CallingConvention* cc = frame_map()->c_calling_convention(&signature);

    const LIR_Opr result_reg = result_register_for(x->type());

    left.load_item_force(cc->at(1));

    right.load_item();

    __ move(right.result(), cc->at(0));

    address entry;

    if (x->op() == Bytecodes::_frem) {

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::frem);

    } else {

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::drem);

    }

    LIR_Opr result = rlock_result(x);

    __ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args());

    __ move(result_reg, result);

    return;

  }

  LIRItem left(x->x(),  this);

  LIRItem right(x->y(), this);

  LIRItem* left_arg  = &left;

  LIRItem* right_arg = &right;

  // Always load right hand side.

  right.load_item();

  if (!left.is_register())

    left.load_item();

  LIR_Opr reg = rlock(x);

  LIR_Opr tmp = LIR_OprFact::illegalOpr;

  if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) {

    tmp = new_register(T_DOUBLE);

  }

  arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), NULL);

  set_result(x, round_item(reg));

}

// for  _ladd, _lmul, _lsub, _ldiv, _lrem

void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {

  // missing test if instr is commutative and if we should swap

  LIRItem left(x->x(), this);

  LIRItem right(x->y(), this);

  if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem) {

    // the check for division by zero destroys the right operand

    right.set_destroys_register();

    // check for division by zero (destroys registers of right operand!)

    CodeEmitInfo* info = state_for(x);

    left.load_item();

    right.load_item();

    __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));

    __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));

    rlock_result(x);

    switch (x->op()) {

    case Bytecodes::_lrem:

      __ rem (left.result(), right.result(), x->operand());

      break;

    case Bytecodes::_ldiv: