8202993: Add support for x86 testptr/testq with register and address
Reviewed-by: kvn, neliasso
--- a/src/hotspot/cpu/x86/assembler_x86.cpp Mon May 14 15:42:59 2018 +0200
+++ b/src/hotspot/cpu/x86/assembler_x86.cpp Mon May 14 15:43:00 2018 +0200
@@ -8981,6 +8981,13 @@
emit_arith(0x85, 0xC0, dst, src);
}
+void Assembler::testq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_int8((unsigned char)0x85);
+ emit_operand(dst, src);
+}
+
void Assembler::xaddq(Address dst, Register src) {
InstructionMark im(this);
prefixq(dst, src);
--- a/src/hotspot/cpu/x86/assembler_x86.hpp Mon May 14 15:42:59 2018 +0200
+++ b/src/hotspot/cpu/x86/assembler_x86.hpp Mon May 14 15:43:00 2018 +0200
@@ -1813,6 +1813,7 @@
void testq(Register dst, int32_t imm32);
void testq(Register dst, Register src);
+ void testq(Register dst, Address src);
// BMI - count trailing zeros
void tzcntl(Register dst, Register src);
--- a/src/hotspot/cpu/x86/macroAssembler_x86.hpp Mon May 14 15:42:59 2018 +0200
+++ b/src/hotspot/cpu/x86/macroAssembler_x86.hpp Mon May 14 15:43:00 2018 +0200
@@ -836,6 +836,7 @@
void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
+ void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
void testptr(Register src1, Register src2);
void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }