8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
Summary: aarch64: add prefetch for write prior to ldxr/stxr loops.
Reviewed-by: aph
Contributed-by: felix.yang@linaro.org
--- a/hotspot/src/cpu/aarch64/vm/aarch64.ad Sat Feb 20 15:15:35 2016 +0000
+++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad Sat Mar 05 22:22:37 2016 +0800
@@ -4683,6 +4683,7 @@
__ br(Assembler::EQ, cont);
} else {
Label retry_load;
+ __ prfm(Address(oop), PSTL1STRM);
__ bind(retry_load);
__ ldaxr(tmp, oop);
__ cmp(tmp, disp_hdr);
@@ -4737,6 +4738,7 @@
__ cmp(rscratch1, disp_hdr);
} else {
Label retry_load, fail;
+ __ prfm(Address(tmp), PSTL1STRM);
__ bind(retry_load);
__ ldaxr(rscratch1, tmp);
__ cmp(disp_hdr, rscratch1);
@@ -4830,6 +4832,7 @@
__ cmp(tmp, box);
} else {
Label retry_load;
+ __ prfm(Address(oop), PSTL1STRM);
__ bind(retry_load);
__ ldxr(tmp, oop);
__ cmp(box, tmp);
--- a/hotspot/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Sat Feb 20 15:15:35 2016 +0000
+++ b/hotspot/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Sat Mar 05 22:22:37 2016 +0800
@@ -1565,6 +1565,7 @@
Label retry_load, nope;
// flush and load exclusive from the memory location
// and fail if it is not what we expect
+ __ prfm(Address(addr), PSTL1STRM);
__ bind(retry_load);
__ ldaxrw(rscratch1, addr);
__ cmpw(rscratch1, cmpval);
@@ -1590,6 +1591,7 @@
Label retry_load, nope;
// flush and load exclusive from the memory location
// and fail if it is not what we expect
+ __ prfm(Address(addr), PSTL1STRM);
__ bind(retry_load);
__ ldaxr(rscratch1, addr);
__ cmp(rscratch1, cmpval);
@@ -3170,6 +3172,7 @@
}
Label again;
__ lea(tmp, addr);
+ __ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*add)(rscratch1, dst, inc);
@@ -3189,6 +3192,7 @@
assert_different_registers(obj, addr.base(), tmp, rscratch2, dst);
Label again;
__ lea(tmp, addr);
+ __ prfm(Address(tmp), PSTL1STRM);
__ bind(again);
(_masm->*lda)(dst, tmp);
(_masm->*stl)(rscratch2, obj, tmp);
--- a/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Sat Feb 20 15:15:35 2016 +0000
+++ b/hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Sat Mar 05 22:22:37 2016 +0800
@@ -1638,6 +1638,7 @@
void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
Label retry_load;
+ prfm(Address(counter_addr), PSTL1STRM);
bind(retry_load);
// flush and load exclusive from the memory location
ldxrw(tmp, counter_addr);
@@ -2078,7 +2079,7 @@
membar(AnyAny);
} else {
Label retry_load, nope;
-
+ prfm(Address(addr), PSTL1STRM);
bind(retry_load);
// flush and load exclusive from the memory location
// and fail if it is not what we expect
@@ -2114,7 +2115,7 @@
membar(AnyAny);
} else {
Label retry_load, nope;
-
+ prfm(Address(addr), PSTL1STRM);
bind(retry_load);
// flush and load exclusive from the memory location
// and fail if it is not what we expect
@@ -2149,6 +2150,7 @@
} else {
BLOCK_COMMENT("cmpxchg {");
Label retry_load, done;
+ prfm(Address(addr), PSTL1STRM);
bind(retry_load);
load_exclusive(tmp, addr, size, acquire);
if (size == xword)
@@ -2177,6 +2179,7 @@
result = different(prev, incr, addr) ? prev : rscratch2; \
\
Label retry_load; \
+ prfm(Address(addr), PSTL1STRM); \
bind(retry_load); \
LDXR(result, addr); \
OP(rscratch1, result, incr); \
@@ -2199,6 +2202,7 @@
result = different(prev, newv, addr) ? prev : rscratch2; \
\
Label retry_load; \
+ prfm(Address(addr), PSTL1STRM); \
bind(retry_load); \
LDXR(result, addr); \
STXR(rscratch1, newv, addr); \
--- a/hotspot/src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp Sat Feb 20 15:15:35 2016 +0000
+++ b/hotspot/src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp Sat Mar 05 22:22:37 2016 +0800
@@ -1984,6 +1984,7 @@
__ push(rscratch3);
Label L;
__ mov(rscratch2, (address) &BytecodeCounter::_counter_value);
+ __ prfm(Address(rscratch2), PSTL1STRM);
__ bind(L);
__ ldxr(rscratch1, rscratch2);
__ add(rscratch1, rscratch1, 1);