--- a/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Sat May 14 15:34:30 2016 -0700
+++ b/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Thu May 19 11:01:38 2016 -0700
@@ -4767,6 +4767,7 @@
   assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
   Register end = count;
   int cache_line_size = VM_Version::prefetch_data_size();
+  assert(cache_line_size > 0, "cache line size should be known for this code");
   // Minimum count when BIS zeroing can be used since
   // it needs membar which is expensive.
   int block_zero_size  = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);

--- a/hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp	Sat May 14 15:34:30 2016 -0700
+++ b/hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu May 19 11:01:38 2016 -0700
@@ -49,7 +49,7 @@
   AllocatePrefetchDistance = allocate_prefetch_distance();
   AllocatePrefetchStyle    = allocate_prefetch_style();
 
-  if (!has_blk_init()) {
+  if (!has_blk_init() || cache_line_size <= 0) {
     if (AllocatePrefetchInstr == 1) {
       warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
@@ -87,7 +87,7 @@
       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
     }
     if (is_niagara_plus()) {
-      if (has_blk_init() && UseTLAB &&
+      if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
         // Use BIS instruction for TLAB allocation prefetch.
         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);