Merge jdk7-b35
authorduke
Wed, 05 Jul 2017 16:41:01 +0200
changeset 1112 6d909d5803e3
parent 1111 a98b896e5485 (diff)
parent 1052 12555bdf3bc6 (current diff)
child 1113 72886a1ae398
child 1114 36e263d543a6
child 1115 aa80c2c69d03
child 1118 6efdce669cb9
child 1121 3a0cf5cbc50e
child 1126 2ec4685584f3
child 1130 e1831d987443
child 1141 bca37d1ebb75
child 1150 972c77670265
child 1166 f2bfef4df8d0
child 1195 fb3ef7625578
child 1197 d4350a8e64e9
child 1200 3ebe122b58a9
child 1202 5a725d2f0daa
child 1204 fd485442ceb2
child 1207 7719d3506f1a
child 1394 43b4b8b54e65
Merge
--- a/.hgtags-top-repo	Wed Jul 05 16:40:32 2017 +0200
+++ b/.hgtags-top-repo	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 3300a35a0bd56d695b92fe0b34f03ebbfc939064 jdk7-b31
 64da805be725721bf2004e7409a0d7a16fc8ddbc jdk7-b32
 bb1ef4ee3d2c8cbf43a37d372325a7952be590b9 jdk7-b33
+46a989ab932992b2084b946eeb322fa99b9fee6c jdk7-b34
--- a/corba/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/corba/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 ef6af34d75a7b44e77083f1d4ee47631fa09d3b4 jdk7-b31
 80a0f46a6203e727012bd579fe38a609b83decce jdk7-b32
 6a5b9d2f8b20de54e3bfe33cd12bd0793caedc4e jdk7-b33
+0a812b9824e5d17b073765d1505594b49ff88a10 jdk7-b34
--- a/hotspot/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 9c2ecc2ffb125f14fab3857fe7689598956348a0 jdk7-b31
 b727c32788a906c04839516ae7443a085185a300 jdk7-b32
 585535ec8a14adafa6bfea65d6975e29094c8cec jdk7-b33
+5251a9cd8eb8743eee647365bee1c8afdc131556 jdk7-b34
--- a/hotspot/agent/make/build-pkglist	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/agent/make/build-pkglist	Wed Jul 05 16:41:01 2017 +0200
@@ -8,4 +8,4 @@
 SED=$MKS_HOME/sed
 SORT=$MKS_HOME/sort
 
-$CD ../src/share/classes; $FIND sun/jvm/hotspot \( -name SCCS -prune \) -o -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
+$CD ../src/share/classes; $FIND sun/jvm/hotspot com/sun/java/swing -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
--- a/hotspot/make/hotspot_version	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/hotspot_version	Wed Jul 05 16:41:01 2017 +0200
@@ -35,7 +35,7 @@
 
 HS_MAJOR_VER=14
 HS_MINOR_VER=0
-HS_BUILD_NUMBER=03
+HS_BUILD_NUMBER=04
 
 JDK_MAJOR_VER=1
 JDK_MINOR_VER=7
--- a/hotspot/make/linux/makefiles/sa.make	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/linux/makefiles/sa.make	Wed Jul 05 16:41:01 2017 +0200
@@ -41,8 +41,9 @@
 SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
 
 # gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
 
 SA_CLASSDIR = $(GENERATED)/saclasses
 
@@ -58,7 +59,7 @@
 	   $(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
 	fi
 
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
 	$(QUIETLY) echo "Making $@"
 	$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
 	  echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -72,9 +73,18 @@
 	$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
 	  mkdir -p $(SA_CLASSDIR);        \
 	fi
-	$(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+
+	$(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+	$(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+
 	$(QUIETLY) $(REMOTE) $(COMPILE.RMIC)  -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
 	$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+	$(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+	$(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
 	$(QUIETLY) $(REMOTE) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
 	$(QUIETLY) $(REMOTE) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
 	$(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext
--- a/hotspot/make/sa.files	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/sa.files	Wed Jul 05 16:41:01 2017 +0200
@@ -33,40 +33,23 @@
 
 AGENT_SRC_DIR = $(AGENT_DIR)/src/share/classes
 
-AGENT_ALLFILES = \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/DebugServer.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HelloWorld.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotAgent.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotSolarisVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotTypeDataBase.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/LinuxVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/ObjectHistogram.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/RMIHelper.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/StackTrace.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/TestDebugger.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/Win32VtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Immediate.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ImmediateOrRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Operand.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCArgument.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisterType.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86RegisterPart.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/BugSpotAgent.java \
+# Splitted the set of files into two sets because on linux plaform
+# listing or compiling all the files results in 'Argument list too long' error.
+
+AGENT_FILES1 = \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/tree/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/c1/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/code/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/compiler/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/x86/*.java \
@@ -75,7 +58,6 @@
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/sparc/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/x86/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dummy/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/ia64/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/amd64/*.java \
@@ -107,7 +89,10 @@
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/jdi/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/livejvm/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/memory/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java 
+
+
+AGENT_FILES2 = \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/amd64/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/ia64/*.java \
@@ -127,7 +112,17 @@
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/x86/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/jcore/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/soql/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/types/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/types/basic/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/*.java \
 $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/memo/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/action/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/classbrowser/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/table/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/tree/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/treetable/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/action/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/ui/*.java
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/make/solaris/makefiles/reorder_COMPILER1_amd64	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,5450 @@
+data = R0x2000;
+text = LOAD ?RXO;
+
+
+# Test Null
+text: .text%__cplus_fini_at_exit: CCrti.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: arguments.o;
+text: .text%__1cQAgentLibraryList2t6M_v_: arguments.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable.o;
+text: .text%__1cFRInfo2t6M_v_: c1_AllocTable.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_AllocTable_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Canonicalizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Canonicalizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeStubs_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeStubs_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compilation.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Compilation.o;
+text: .text%__1cMelapsedTimer2t6M_v_: c1_Compilation.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compiler.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Compiler.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_GraphBuilder.o;
+text: .text%__1cFRInfo2t6M_v_: c1_GraphBuilder.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_IR.o;
+text: .text%__1cFRInfo2t6M_v_: c1_IR.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Instruction.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Instruction.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_InstructionPrinter.o;
+text: .text%__1cFRInfo2t6M_v_: c1_InstructionPrinter.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Items.o;
+text: .text%__1cIHintItem2t6MpnJValueType_i_v_: c1_Items.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Items_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIR.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIR.o;
+text: .text%__1cLLIR_OprFactHillegal6F_pnLLIR_OprDesc__: c1_LIR.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIROptimizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIROptimizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Loops.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Loops.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_MacroAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_MacroAssembler_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Optimizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Optimizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RInfo.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_RInfo.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RInfo_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Runtime1.o;
+text: .text%__1cIiEntries2t6M_v_;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Runtime1_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ScanBlocks.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ScanBlocks.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueMap.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueMap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueSet.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueSet.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueStack.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueStack.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: codeBlob.o;
+text: .text%__1cFRInfo2t6M_v_: codeBlob.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: codeCache.o;
+text: .text%__1cICHeapObj2n6FI_pv_;
+text: .text%__1cCosGmalloc6FI_pv_;
+text: .text%__1cICodeHeap2t6M_v_;
+text: .text%__1cMVirtualSpace2t6M_v_;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: compilationPolicy.o;
+text: .text%__1cMelapsedTimer2t6M_v_: compilationPolicy.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: compileBroker.o;
+text: .text%__1cMelapsedTimer2t6M_v_: compileBroker.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: compiledIC.o;
+text: .text%__1cFRInfo2t6M_v_: compiledIC.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: deoptimization.o;
+text: .text%__1cFRInfo2t6M_v_: deoptimization.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: fprofiler.o;
+text: .text%__1cMelapsedTimer2t6M_v_: fprofiler.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: frame.o;
+text: .text%__1cFRInfo2t6M_v_: frame.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: frame_x86.o;
+text: .text%__1cFRInfo2t6M_v_: frame_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: genCollectedHeap.o;
+text: .text%__1cTAssertIsPermClosure2t6M_v_: genCollectedHeap.o;
+text: .text%__1cRAlwaysTrueClosure2t6M_v_: genCollectedHeap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: generateOopMap.o;
+text: .text%__1cNCellTypeStateLmake_bottom6F_0_: generateOopMap.o;
+text: .text%__1cNCellTypeStateImake_any6Fi_0_: generateOopMap.o;
+text: .text%__1cNCellTypeStateImake_top6F_0_: generateOopMap.o;
+text: .text%__1cMelapsedTimer2t6M_v_: generateOopMap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: interpreter.o;
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+text: .text%__1cMLinkResolverOresolve_method6FrnMmethodHandle_rnLKlassHandle_nSconstantPoolHandle_ipnGThread__v_;
+text: .text%__1cKCompiledICZcompute_monomorphic_entry6FnMmethodHandle_nLKlassHandle_iirnOCompiledICInfo_pnGThread__v_;
+text: .text%__1cKCompiledIC2t6MpnKNativeCall__v_;
+text: .text%__1cXvirtual_call_RelocationIparse_ic6FrpnICodeBlob_rpC5rppnHoopDesc_pi_nNRelocIterator__;
+text: .text%__1cKCompiledICIis_clean6kM_i_;
+text: .text%__1cKCompiledICOic_destination6kM_pC_;
+text: .text%__1cKCompiledICWis_in_transition_state6kM_i_;
+text: .text%__1cRInlineCacheBufferIcontains6FpC_i_;
+text: .text%__1cKCompiledICSset_to_monomorphic6MrknOCompiledICInfo__v_;
+text: .text%__1cSCompiledStaticCallSset_to_interpreted6MnMmethodHandle_pC_v_;
+text: .text%__1cSCompiledStaticCallJfind_stub6M_pC_;
+text: .text%__1cNRelocIteratorEnext6M_i_: compiledIC.o;
+text: .text%__1cPBoundRelocationLunpack_data6MnJrelocInfoJrelocType__v_: compiledIC.o;
+text: .text%__1cbBopt_virtual_call_RelocationLstatic_stub6M_pC_;
+text: .text%__1cKNativeCallXset_destination_mt_safe6MpC_v_;
+text: .text%__1cNnmethodLocker2T6M_v_;
+text: .text%__1cNmethodOopDescTverified_code_entry6M_pC_;
+text: .text%jni_GetByteArrayRegion: jni.o;
+text: .text%JVM_DefineClassWithSource;
+text: .text%__1cXjvm_define_class_common6FpnHJNIEnv__pkcpnI_jobject_pkWi53pnGThread__pnH_jclass__: jvm.o;
+text: .text%__1cQSystemDictionaryTresolve_from_stream6FnMsymbolHandle_nGHandle_2pnPClassFileStream_pnGThread__pnMklassOopDesc__;
+text: .text%__1cPClassFileParserbDverify_legal_method_signature6MnMsymbolHandle_1pnGThread__i_;
+text: .text%__1cPClassFileParserZskip_over_field_signature6MpciIpnGThread__1_;
+text: .text%__1cPClassFileParserXverify_legal_class_name6MnMsymbolHandle_pnGThread__v_;
+text: .text%__1cQput_after_lookup6FnMsymbolHandle_0ppnLNameSigHash__i_;
+text: .text%__1cEhash6Fpkc1_I_;
+text: .text%__1cKDictionarybAis_valid_protection_domain6MiInMsymbolHandle_nGHandle_2_i_;
+text: .text%__1cPDictionaryEntrybAcontains_protection_domain6kMpnHoopDesc__i_;
+text: .text%__1cQSystemDictionarybAvalidate_protection_domain6FnTinstanceKlassHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cKDictionaryVadd_protection_domain6MiInTinstanceKlassHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cPDictionaryEntryVadd_protection_domain6MpnHoopDesc__v_;
+text: .text%__1cUverify_byte_codes_fn6F_pv_: verifier.o;
+text: .text%JVM_GetClassCPEntriesCount;
+text: .text%JVM_GetClassCPTypes;
+text: .text%JVM_GetClassNameUTF;
+text: .text%JVM_ReleaseUTF;
+text: .text%JVM_FindClassFromClass;
+text: .text%jni_IsSameObject: jni.o;
+text: .text%JVM_GetClassFieldsCount;
+text: .text%JVM_GetClassMethodsCount;
+text: .text%JVM_GetMethodIxModifiers;
+text: .text%JVM_GetMethodIxByteCodeLength;
+text: .text%JVM_GetMethodIxByteCode;
+text: .text%JVM_GetMethodIxExceptionTableLength;
+text: .text%JVM_GetMethodIxLocalsCount;
+text: .text%JVM_GetMethodIxArgsSize;
+text: .text%JVM_GetMethodIxSignatureUTF;
+text: .text%JVM_GetMethodIxMaxStack;
+text: .text%JVM_GetMethodIxExceptionsCount;
+text: .text%JVM_GetMethodIxExceptionIndexes;
+text: .text%JVM_GetCPMethodNameUTF;
+text: .text%JVM_GetCPMethodClassNameUTF;
+text: .text%jni_NewLocalRef: jni.o;
+text: .text%JVM_GetCPMethodModifiers;
+text: .text%JVM_IsConstructorIx;
+text: .text%JVM_GetCPMethodSignatureUTF;
+text: .text%jni_DeleteGlobalRef: jni.o;
+text: .text%__1cQSystemDictionaryVadd_loader_constraint6FnMsymbolHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cVLoaderConstraintTableJadd_entry6MnMsymbolHandle_pnMklassOopDesc_nGHandle_34pnGThread__i_;
+text: .text%__1cVLoaderConstraintTableJnew_entry6MIpnNsymbolOopDesc_pnMklassOopDesc_ii_pnVLoaderConstraintEntry__;
+text: .text%jni_ToReflectedMethod: jni.o;
+text: .text%__1cKReflectionKnew_method6FnMmethodHandle_iipnGThread__pnHoopDesc__;
+text: .text%__1cNSignatureInfoIdo_array6Mii_v_: reflection.o;
+text: .text%__1cYjava_lang_reflect_MethodGcreate6FpnGThread__nGHandle__;
+text: .text%__1cYjava_lang_reflect_MethodJset_clazz6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodIset_slot6FpnHoopDesc_i_v_;
+text: .text%__1cYjava_lang_reflect_MethodIset_name6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodPset_return_type6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodTset_parameter_types6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodTset_exception_types6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodNset_modifiers6FpnHoopDesc_i_v_;
+text: .text%__1cYjava_lang_reflect_MethodThas_signature_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodVhas_annotations_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodPset_annotations6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodbFhas_parameter_annotations_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodZset_parameter_annotations6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodbChas_annotation_default_field6F_i_;
+text: .text%__1cNmethodOopDescSannotation_default6kM_pnQtypeArrayOopDesc__;
+text: .text%__1cYjava_lang_reflect_MethodWset_annotation_default6FpnHoopDesc_2_v_;
+text: .text%jni_CallIntMethod: jni.o;
+text: .text%jni_CallStaticVoidMethod: jni.o;
+text: .text%jni_DetachCurrentThread;
+text: .text%__1cKJavaThreadEexit6Mi_v_;
+text: .text%__1cQjava_lang_ThreadLthreadGroup6FpnHoopDesc__2_;
+text: .text%JVM_MonitorNotifyAll;
+text: .text%__1cNThreadServiceWcurrent_thread_exiting6FpnKJavaThread__v_;
+text: .text%__1cLensure_join6FpnKJavaThread__v_: thread.o;
+text: .text%__1cQjava_lang_ThreadNset_stillborn6FpnHoopDesc__v_;
+text: .text%__1cKJavaThreadYremove_stack_guard_pages6M_v_;
+text: .text%__1cWThreadLocalAllocBufferFclear6M_v_;
+text: .text%__1cHThreadsGremove6FpnKJavaThread__v_;
+text: .text%__1cNThreadServiceNremove_thread6FpnKJavaThread_i_v_;
+text: .text%__SLIP.DELETER__A: thread.o;
+text: .text%__1cKJavaThread2T6M_v_;
+text: .text%__1cGParker2T6M_v_;
+text: .text%__1cHMonitor2T6M_v_;
+text: .text%__1cFMutex2T6M_v_;
+text: .text%lwp_cond_destroy: os_solaris.o;
+text: .text%lwp_mutex_destroy: os_solaris.o;
+text: .text%__1cUThreadSafepointStateHdestroy6FpnKJavaThread__v_;
+text: .text%__1cUThreadSafepointState2T6M_v_;
+text: .text%__1cGThread2T5B6M_v_;
+text: .text%__1cCosLfree_thread6FpnIOSThread__v_;
+text: .text%__1cIOSThread2T6M_v_;
+text: .text%__1cIOSThreadKpd_destroy6M_v_;
+text: .text%jni_DestroyJavaVM;
+text: .text%jni_AttachCurrentThread;
+text: .text%attach_current_thread: jni.o;
+text: .text%__1cCosWcreate_attached_thread6FpnGThread__i_;
+text: .text%__1cKJavaThreadSallocate_threadObj6MnGHandle_pcipnGThread__v_;
+text: .text%__1cHThreadsKdestroy_vm6F_i_;
+text: .text%__1cKJavaThreadVinvoke_shutdown_hooks6M_v_;
+text: .text%__1cLbefore_exit6FpnKJavaThread__v_;
+text: .text%__1cNWatcherThreadEstop6F_v_;
+text: .text%__1cLStatSamplerJdisengage6F_v_;
+text: .text%__1cMPeriodicTaskJdisenroll6M_v_;
+text: .text%__1cMPeriodicTask2T5B6M_v_;
+text: .text%__1cMPeriodicTaskLis_enrolled6kM_i_;
+text: .text%__1cLStatSamplerHdestroy6F_v_;
+text: .text%__1cMPerfDataList2T6M_v_;
+text: .text%__1cLJvmtiExportNpost_vm_death6F_v_;
+text: .text%__1cUJvmtiEventControllerIvm_death6F_v_;
+text: .text%__1cCosXterminate_signal_thread6F_v_;
+text: .text%__1cCosNsigexitnum_pd6F_i_;
+text: .text%__1cCosNsignal_notify6Fi_v_;
+text: .text%__1cQprint_statistics6F_v_;
+text: .text%__1cFVTuneEexit6F_v_;
+text: .text%__1cIVMThreadXwait_for_vm_thread_exit6F_v_;
+text: .text%__1cUSafepointSynchronizeFbegin6F_v_;
+text: .text%__1cORuntimeServiceWrecord_safepoint_begin6F_v_;
+text: .text%__1cJTimeStampSticks_since_update6kM_x_;
+text: .text%__1cTAbstractInterpreterRnotice_safepoints6F_v_;
+text: .text%__1cKcopy_table6FppC1i_v_: interpreter.o;
+text: .text%__1cUSafepointSynchronizeFblock6FpnKJavaThread__v_;
+text: .text%__1cCosRcurrent_thread_id6F_i_;
+text: .text%__1cJttyLockerbCbreak_tty_lock_for_safepoint6Fi_v_;
+text: .text%__1cCosbCmake_polling_page_unreadable6F_v_;
+text: .text%__1cUThreadSafepointStateXexamine_state_of_thread6Mi_v_;
+text: .text%__1cUSafepointSynchronizeOsafepoint_safe6FpnKJavaThread_nPJavaThreadState__i_;
+text: .text%__1cUThreadSafepointStateMroll_forward6Mn0AMsuspend_type_pnHnmethod_i_v_;
+text: .text%__1cORuntimeServicebDrecord_safepoint_synchronized6F_v_;
+text: .text%__1cUSafepointSynchronizeQdo_cleanup_tasks6F_v_;
+text: .text%__1cSObjectSynchronizerVdeflate_idle_monitors6F_v_;
+text: .text%__1cNObjectMonitorHis_busy6kM_i_;
+text: .text%__1cRInlineCacheBufferUupdate_inline_caches6F_v_;
+text: .text%__1cMCounterDecayFdecay6F_v_;
+text: .text%__1cQSystemDictionaryRnumber_of_classes6F_i_;
+text: .text%__1cQSystemDictionaryStry_get_next_class6F_pnMklassOopDesc__;
+text: .text%__1cKDictionaryStry_get_next_class6M_pnMklassOopDesc__;
+text: .text%__1cNinstanceKlassKmethods_do6MpFpnNmethodOopDesc__v_v_;
+text: .text%__1cJdo_method6FpnNmethodOopDesc__v_: recompilationMonitor.o;
+text: .text%__1cONMethodSweeperFsweep6F_v_;
+text: .text%__1cNCompileBrokerQset_should_block6F_v_;
+text: .text%__1cHVM_ExitbJwait_for_threads_in_native_to_block6F_i_;
+text: .text%__1cURecompilationMonitorbFstop_recompilation_monitor_task6F_v_;
+text: .text%__1cIVMThreadHdestroy6F_v_;
+text: .text%__SLIP.DELETER__A: vmThread.o;
+text: .text%__1cSThreadLocalStorageRpd_invalidate_all6F_v_;
+text: .text%__1cHVM_ExitNset_vm_exited6F_i_;
+text: .text%__1cMexit_globals6F_v_;
+text: .text%__1cVverificationType_exit6F_v_;
+text: .text%__1cQVerificationTypeIfinalize6F_v_;
+text: .text%__1cPperfMemory_exit6F_v_;
+text: .text%__1cPPerfDataManagerHdestroy6F_v_;
+text: .text%__1cIPerfData2T6M_v_;
+text: .text%__1cKPerfMemoryHdestroy6F_v_;
+text: .text%__1cKPerfMemoryUdelete_memory_region6F_v_;
+text: .text%__1cUdelete_shared_memory6FpcI_v_: perfMemory_solaris.o;
+text: .text%__1cLremove_file6Fpkc_v_: perfMemory_solaris.o;
+text: .text%__1cMostream_exit6F_v_;
+text: .text%__SLIP.DELETER__C: ostream.o;
+text: .text%__SLIP.FINAL__A: c1_Items.o;
+# Test Exit
+text: .text%__1cPSignatureStreamHis_done6kM_i_;
+text: .text%JVM_Halt;
+text: .text%__1cHvm_exit6Fi_v_;
+text: .text%__1cIVMThreadHexecute6FpnMVM_Operation__v_;
+text: .text%__1cMVM_OperationNdoit_prologue6M_i_: vm_operations.o;
+text: .text%__1cGThreadMget_priority6Fkpk0_nOThreadPriority__;
+text: .text%__1cCosMget_priority6FkpknGThread_rnOThreadPriority__nIOSReturn__;
+text: .text%__1cCosTget_native_priority6FkpknGThread_pi_nIOSReturn__;
+text: .text%__1cMVM_OperationSset_calling_thread6MpnGThread_nOThreadPriority__v_;
+text: .text%__1cMVM_OperationPevaluation_mode6kM_n0AEMode__: vm_operations.o;
+text: .text%__1cMVM_OperationSis_cheap_allocated6kM_i_: vm_operations.o;
+text: .text%__1cQVMOperationQdDueueDadd6MpnMVM_Operation__i_;
+text: .text%__1cQVMOperationQdDueueOqueue_add_back6MipnMVM_Operation__v_;
+text: .text%__1cQVMOperationQdDueueGinsert6MpnMVM_Operation_2_v_;
+text: .text%__1cQVMOperationQdDueueGunlink6MpnMVM_Operation__v_;
+text: .text%__1cHVM_ExitEname6kM_pkc_: vm_operations.o;
+text: .text%__1cJEventMark2t6MpkcE_v_: vmThread.o;
+text: .text%__1cCosJyield_all6Fi_v_;
+text: .text%__1cGThreadRis_Watcher_thread6kM_i_: vmThread.o;
+text: .text%__1cSInterpreterRuntimeMat_safepoint6FpnKJavaThread__v_;
+text: .text%__1cIVMThreadSevaluate_operation6MpnMVM_Operation__v_;
+text: .text%__1cMVM_OperationIevaluate6M_v_;
+text: .text%__1cHVM_ExitEdoit6M_v_;
+# Test Hello
+text: .text%JVM_GetCPFieldSignatureUTF;
+text: .text%JVM_Write;
+text: .text%__1cDhpiFwrite6FipkvI_I_: jvm.o;
+# Test Sleep
+text: .text%JVM_GetMethodIxExceptionTableEntry;
+text: .text%JVM_GetCPClassNameUTF;
+text: .text%JVM_Sleep;
+text: .text%__1cCosHSolarisTsetup_interruptible6F_pnKJavaThread__;
+text: .text%__1cCosHSolarisTsetup_interruptible6FpnKJavaThread__v_;
+text: .text%__1cUSafepointSynchronizeRis_cleanup_needed6F_i_;
+text: .text%__1cRInlineCacheBufferIis_empty6F_i_;
+text: .text%__1cCosHSolarisVcleanup_interruptible6FpnKJavaThread__v_;
+text: .text%__1cCosOunguard_memory6FpcI_i_;
+# Test IntToString
+text: .text%__1cQChunkPoolCleanerEtask6M_v_: allocation.o;
+text: .text%__1cJChunkPoolMfree_all_but6MI_v_: allocation.o;
+# Test LoadToolkit
+text: .text%JVM_GetClassContext;
+text: .text%__1cNCollectedHeapMobj_allocate6FnLKlassHandle_ipnGThread__pnHoopDesc__: jvm.o;
+text: .text%jni_IsAssignableFrom: jni.o;
+text: .text%__1cOGenerateOopMapGdo_ldc6Mii_v_;
+text: .text%__1cQComputeCallStackIdo_array6Mii_v_: generateOopMap.o;
+text: .text%__1cMGraphBuilderNload_constant6M_v_;
+text: .text%__1cQciBytecodeStreamMget_constant6kM_nKciConstant__;
+text: .text%__1cQciBytecodeStreamSget_constant_index6kM_i_;
+text: .text%__1cFciEnvVget_constant_by_index6MpnPciInstanceKlass_i_nKciConstant__;
+text: .text%__1cFciEnvbAget_constant_by_index_impl6MpnPciInstanceKlass_i_nKciConstant__;
+text: .text%__1cMLinkResolverbBresolve_static_call_or_null6FnLKlassHandle_nMsymbolHandle_21_nMmethodHandle__;
+text: .text%__1cLInstructionMas_LoadLocal6M_pnJLoadLocal__: c1_Canonicalizer.o;
+text: .text%__1cTsort_by_start_block6FppnELoop_2_i_: c1_Loops.o;
+text: .text%__1cILIR_ListLcall_static6MpnLLIR_OprDesc_pCpnMCodeEmitInfo_pnOStaticCallStub__v_: c1_LIREmitter.o;
+text: .text%__1cLLIR_EmitterLcmp_mem_int6MnMLIR_OpBranchNLIR_Condition_nFRInfo_iipnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListLcmp_mem_int6MnMLIR_OpBranchNLIR_Condition_nFRInfo_iipnMCodeEmitInfo__v_;
+text: .text%__1cJValueTypeLas_VoidType6M_pnIVoidType__: c1_Canonicalizer.o;
+text: .text%__1cILIR_ListHint2reg6MinFRInfo__v_: c1_LIREmitter.o;
+text: .text%__1cWstatic_call_RelocationEtype6M_nJrelocInfoJrelocType__: relocInfo.o;
+text: .text%__1cRComputeEntryStackIdo_array6Mii_v_: generateOopMap.o;
+text: .text%__1cKValueStackEpush6MpnJValueType_pnLInstruction__v_: c1_Optimizer.o;
+text: .text%__1cEIfOpPinput_values_do6MpFppnLInstruction__v_v_: c1_Instruction.o;
+text: .text%__1cEIfOpFvisit6MpnSInstructionVisitor__v_: c1_Instruction.o;
+text: .text%__1cQNullCheckVisitorHdo_IfOp6MpnEIfOp__v_;
+text: .text%__1cIValueGenHdo_IfOp6MpnEIfOp__v_;
+text: .text%__1cLLIR_EmitterLifop_phase16MnLInstructionJCondition_pnLLIR_OprDesc_4_v_;
+text: .text%__1cLLIR_EmitterLifop_phase26MnFRInfo_pnLLIR_OprDesc_3nLInstructionJCondition__v_;
+text: .text%__1cILIR_ListGbranch6MnMLIR_OpBranchNLIR_Condition_pnFLabel__v_;
+text: .text%__1cRLIR_PeepholeStateUstart_forward_branch6MpnFLabel__v_;
+text: .text%__1cOGenerateOopMapMdo_checkcast6M_v_;
+text: .text%__1cMGraphBuilderLinstance_of6Mi_v_;
+text: .text%__1cKInstanceOfFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cJTypeCheckIcan_trap6kM_i_: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderOdirect_compare6MpnHciKlass__i_;
+text: .text%__1cKInstanceOfNas_InstanceOf6M_p0_: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderKcheck_cast6Mi_v_;
+text: .text%__1cJCheckCastFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cJValueTypeKas_IntType6M_pnHIntType__: c1_ValueType.o;
+text: .text%__1cJTypeCheckPinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cQNullCheckVisitorMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cIValueGenNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeGenerator_x86.o;
+text: .text%__1cLLIR_EmitterNinstanceof_op6MpnLLIR_OprDesc_2pnHciKlass_nFRInfo_5ipnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListKinstanceof6MpnLLIR_OprDesc_2pnHciKlass_22ipnMCodeEmitInfo__v_;
+text: .text%__1cPLIR_OpTypeCheck2t6MnILIR_Code_pnLLIR_OprDesc_3pnHciKlass_33ipnMCodeEmitInfo_7pnICodeStub__v_;
+text: .text%__1cIValueGenMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cILIR_ListJcheckcast6MpnLLIR_OprDesc_2pnHciKlass_22ipnMCodeEmitInfo_6pnICodeStub__v_;
+text: .text%__1cILIR_ListJsafepoint6MnFRInfo_pnMCodeEmitInfo__v_: c1_CodeGenerator_x86.o;
+text: .text%__1cPLIR_OpTypeCheckFvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cTSimpleExceptionStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cPLIR_OpTypeCheckJemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerQemit_opTypeCheck6MpnPLIR_OpTypeCheck__v_;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_LIROptimizer.o;
+text: .text%__1cIintArrayIindex_of6kMki_i_: c1_LIROptimizer.o;
+text: .text%__1cNLIR_AssemblerQemit_opTypeCheck6MpnPLIR_OpTypeCheck__v_;
+text: .text%__1cIciObjectIencoding6M_pnI_jobject__;
+text: .text%__1cJAssemblerEcmpl6MnHAddress_pnI_jobject__v_;
+text: .text%__1cTSimpleExceptionStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cTSimpleExceptionStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cJLoadFieldIis_equal6kMpnLInstruction__i_: c1_Instruction.o;
+text: .text%__1cJLoadFieldMas_LoadField6M_p0_: c1_Instruction.o;
+text: .text%__1cDPhiPinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cDPhiFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorGdo_Phi6MpnDPhi__v_;
+text: .text%__1cLInstructionIas_Local6M_pnFLocal__: c1_GraphBuilder.o;
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+text: .text%__1cHciKlassMaccess_flags6M_i_;
+text: .text%__1cILIR_ListPallocate_object6MnFRInfo_111ii1pnICodeStub__v_;
+text: .text%__1cLLIR_EmitterOmembar_release6M_v_;
+text: .text%__1cLLIR_EmitterGmembar6M_v_;
+text: .text%__1cIValueGenRdo_NewObjectArray6MpnONewObjectArray__v_;
+text: .text%__1cLLIR_EmitterQnew_object_array6MnFRInfo_pnHciKlass_pnLLIR_OprDesc_11111pnMCodeEmitInfo_7_v_;
+text: .text%__1cSNewObjectArrayStub2t6MnFRInfo_11pnMCodeEmitInfo__v_;
+text: .text%__1cPciObjArrayKlassEmake6FpnHciKlass__p0_;
+text: .text%__1cPciObjArrayKlassJmake_impl6FpnHciKlass__p0_;
+text: .text%__1cLLIR_EmitterOmembar_acquire6M_v_;
+text: .text%__1cIValueGenKdo_ShiftOp6MpnHShiftOp__v_;
+text: .text%__1cIValueGenPshiftCountRInfo6F_nFRInfo__;
+text: .text%__1cLLIR_EmitterIshift_op6MnJBytecodesECode_nFRInfo_pnLLIR_OprDesc_53_v_;
+text: .text%__1cILIR_ListKshift_left6MnFRInfo_i1_v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListKlogical_or6MnFRInfo_pnLLIR_OprDesc_1_v_: c1_LIREmitter.o;
+text: .text%__1cOLIR_OpAllocObjFvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cSNewObjectArrayStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cOLIR_OpAllocObjJemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerOemit_alloc_obj6MpnOLIR_OpAllocObj__v_;
+text: .text%__1cNLIR_AssemblerOemit_alloc_obj6MpnOLIR_OpAllocObj__v_;
+text: .text%__1cRC1_MacroAssemblerPallocate_object6MpnMRegisterImpl_22ii2rnFLabel__v_;
+text: .text%__1cNLIR_AssemblerOmembar_release6M_v_;
+text: .text%__1cNLIR_AssemblerGmembar6M_v_;
+text: .text%__1cSNewObjectArrayStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cNLIR_AssemblerOmembar_acquire6M_v_;
+text: .text%__1cEBaseHas_Base6M_p0_: c1_IR.o;
+text: .text%__1cNLIR_AssemblerOemit_osr_entry6MpnHIRScope_ipnFLabel_i_v_;
+text: .text%__1cSNewObjectArrayStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cNinstanceKlassPadd_osr_nmethod6MpnHnmethod__v_;
+text: .text%__1cUGenericGrowableArrayLraw_at_grow6MipknEGrET__pv_;
+text: .text%__1cNSignatureInfoIdo_short6M_v_: bytecode.o;
+text: .text%jni_MonitorEnter: jni.o;
+text: .text%__1cSObjectSynchronizerJjni_enter6FnGHandle_pnGThread__v_;
+text: .text%jni_MonitorExit: jni.o;
+text: .text%__1cSObjectSynchronizerIjni_exit6FpnHoopDesc_pnGThread__v_;
+text: .text%jni_CallVoidMethod: jni.o;
+text: .text%__1cXJNI_ArgumentPusherVaArgHget_int6M_v_: jni.o;
+text: .text%jni_CallStaticBooleanMethodV: jni.o;
+text: .text%JVM_GetStackTraceDepth;
+text: .text%__1cTjava_lang_ThrowableVget_stack_trace_depth6FpnHoopDesc_pnGThread__i_;
+text: .text%__1cTjava_lang_ThrowableJbacktrace6FpnHoopDesc__2_;
+text: .text%JVM_GetStackTraceElement;
+text: .text%__1cTjava_lang_ThrowableXget_stack_trace_element6FpnHoopDesc_ipnGThread__2_;
+text: .text%__1cbBjava_lang_StackTraceElementGcreate6FnMmethodHandle_ipnGThread__pnHoopDesc__;
+text: .text%__1cbBjava_lang_StackTraceElementNset_className6FpnHoopDesc_2_v_;
+text: .text%__1cbBjava_lang_StackTraceElementOset_methodName6FpnHoopDesc_2_v_;
+text: .text%__1cbBjava_lang_StackTraceElementMset_fileName6FpnHoopDesc_2_v_;
+text: .text%__1cNmethodOopDescUline_number_from_bci6kMi_i_;
+text: .text%__1cbECompressedLineNumberReadStream2t6MpC_v_;
+text: .text%__1cbECompressedLineNumberReadStreamJread_pair6M_i_;
+text: .text%__1cUCompressedReadStreamIread_int6M_i_: methodOop.o;
+text: .text%__1cbBjava_lang_StackTraceElementOset_lineNumber6FpnHoopDesc_i_v_;
+text: .text%__1cFKlassNoop_is_method6kM_i_: typeArrayKlass.o;
+text: .text%__1cFKlassRoop_is_methodData6kM_i_: typeArrayKlass.o;
+text: .text%__1cIciObjectOis_null_object6kM_i_: ciObjectFactory.o;
+text: .text%__1cNObjectMonitorJnotifyAll6MpnGThread__v_;
+text: .text%__1cNObjectMonitorREntryQdDueue_insert6MpnMObjectWaiter_i_v_;
+text: .text%__1cNObjectMonitorbAEntryQdDueue_SelectSuccessor6M_pnMObjectWaiter__;
+text: .text%__1cLServiceUtilLvisible_oop6FpnHoopDesc__i_: objectMonitor_solaris.o;
+text: .text%__1cNObjectMonitorGEnterI6MpnGThread__v_;
+text: .text%JVM_EnableCompiler;
+text: .text%__1cCosHSolarisFEventEpark6Mx_i_: objectMonitor_solaris.o;
+text: .text%__1cJStubQdDueueKremove_all6M_v_;
+text: .text%__1cJStubQdDueueMremove_first6Mi_v_;
+text: .text%__1cJStubQdDueueMremove_first6M_v_;
+text: .text%__1cPICStubInterfaceIfinalize6MpnEStub__v_: icBuffer.o;
+text: .text%__1cGICStubIfinalize6M_v_;
+text: .text%__1cGICStubKcached_oop6kM_pnHoopDesc__;
+text: .text%__1cRInlineCacheBufferUic_buffer_cached_oop6FpC_pnHoopDesc__;
+text: .text%__1cKCompiledICOset_cached_oop6MpnHoopDesc__v_;
+text: .text%__1cOoop_RelocationSfix_oop_relocation6M_v_;
+text: .text%__1cGICStubLdestination6kM_pC_;
+text: .text%__1cRInlineCacheBufferVic_buffer_entry_point6FpC_1_;
+text: .text%__1cPICStubInterfaceEsize6kMpnEStub__i_: icBuffer.o;
+text: .text%__1cUSafepointSynchronizeDend6F_v_;
+text: .text%__1cCosbAmake_polling_page_readable6F_v_;
+text: .text%__1cTAbstractInterpreterRignore_safepoints6F_v_;
+text: .text%__1cGThreadQunboost_priority6Fp0_v_;
+text: .text%__1cUThreadSafepointStateHrestart6M_v_;
+text: .text%__1cORuntimeServiceUrecord_safepoint_end6F_v_;
+text: .text%__1cKJavaThreadbScheck_safepoint_and_suspend_for_native_trans6Fp0_v_;
+# Test LoadFrame
+text: .text%__1cNObjectMonitorGenter26MpnGThread__v_;
+text: .text%__1cICompilerPsupports_native6M_i_: c1_Compiler.o;
+text: .text%__1cLCompilationVcompile_native_method6MpnLCodeOffsets__i_;
+text: .text%__1cIciMethodMnative_entry6M_pC_;
+text: .text%__1cLCompilationUemit_code_for_native6MpCpnLCodeOffsets__v_;
+text: .text%__1cLCompilationXemit_code_prolog_native6MpnIFrameMap__v_;
+text: .text%__1cNLIR_AssemblerRemit_method_entry6MpnLLIR_Emitter_pnHIRScope__v_;
+text: .text%__1cOMacroAssemblerHfat_nop6M_v_;
+text: .text%__1cNLIR_AssemblerQemit_native_call6MpCpnMCodeEmitInfo__v_;
+text: .text%__1cMCodeEmitInfobGcreate_oop_map_for_own_signature6M_pnGOopMap__;
+text: .text%__1cNLIR_AssemblerXemit_native_method_exit6MpnMCodeEmitInfo__v_;
+text: .text%__1cNSignatureInfoHdo_char6M_v_: reflection.o;
+text: .text%__1cNSignatureInfoHdo_bool6M_v_: reflection.o;
+text: .text%jni_CallObjectMethodV: jni.o;
+text: .text%jni_SetObjectField: jni.o;
+text: .text%jni_IsInstanceOf: jni.o;
+text: .text%jni_GetStaticObjectField: jni.o;
+text: .text%__1cbCTwoGenerationCollectorPolicybMshould_try_older_generation_allocation6kMI_i_;
+text: .text%__1cQGenCollectedHeapSattempt_allocation6MIiii_pnIHeapWord__;
+text: .text%__1cQDefNewGenerationIallocate6MIii_pnIHeapWord__: defNewGeneration.o;
+text: .text%__1cKGenerationInext_gen6kM_p0_;
+text: .text%__1cKGenerationYallocation_limit_reached6MpnFSpace_pnIHeapWord_I_4_: tenuredGeneration.o;
+text: .text%__1cQDefNewGenerationTallocate_from_space6MI_pnIHeapWord__;
+text: .text%__1cPVM_GC_OperationNdoit_prologue6M_i_;
+text: .text%__1cPVM_GC_OperationZacquire_pending_list_lock6M_v_;
+text: .text%__1cQinstanceRefKlassZacquire_pending_list_lock6FpnJBasicLock__v_;
+text: .text%__1cXjava_lang_ref_ReferenceWpending_list_lock_addr6F_ppnHoopDesc__;
+text: .text%__1cPVM_GC_OperationQgc_count_changed6kM_i_;
+text: .text%__1cbAVM_GenCollectForAllocationEname6kM_pkc_: vm_operations.o;
+text: .text%__1cbAVM_GenCollectForAllocationEdoit6M_v_;
+text: .text%__1cNJvmtiGCMarker2t6Mi_v_;
+text: .text%__1cQGenCollectedHeapZsatisfy_failed_allocation6MIiipi_pnIHeapWord__;
+text: .text%__1cbCTwoGenerationCollectorPolicyZsatisfy_failed_allocation6MIiipi_pnIHeapWord__;
+text: .text%__1cQGenCollectedHeapNdo_collection6MiiIiiipi_v_;
+text: .text%__1cXTraceMemoryManagerStats2t6Mi_v_;
+text: .text%__1cNMemoryServiceIgc_begin6Fi_v_;
+text: .text%__1cPGCMemoryManagerIgc_begin6M_v_;
+text: .text%__1cKManagementJtimestamp6F_x_;
+text: .text%__1cKGCStatInfoMset_gc_usage6MinLMemoryUsage_i_v_;
+text: .text%__1cTContiguousSpacePoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cTContiguousSpacePoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cbBSurvivorContiguousSpacePoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cbBSurvivorContiguousSpacePoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cOGenerationPoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cOGenerationPoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cQGenCollectedHeapLgc_prologue6Mi_v_;
+text: .text%__1cNCollectedHeapbFaccumulate_statistics_all_tlabs6M_v_;
+text: .text%__1cWThreadLocalAllocBufferbFaccumulate_statistics_before_gc6F_v_;
+text: .text%__1cWThreadLocalAllocBufferVaccumulate_statistics6MIi_v_;
+text: .text%__1cPGlobalTLABStatsHpublish6M_v_;
+text: .text%__1cQGenCollectedHeapTensure_parseability6M_v_;
+text: .text%__1cNCollectedHeapTensure_parseability6M_v_;
+text: .text%__1cNCollectedHeapOfill_all_tlabs6M_v_;
+text: .text%__1cQGenCollectedHeapSgeneration_iterate6Mpn0AKGenClosure_i_v_;
+text: .text%__1cbCGenEnsureParseabilityClosureNdo_generation6MpnKGeneration__v_: genCollectedHeap.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: defNewGeneration.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: tenuredGeneration.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: compactingPermGenGen.o;
+text: .text%__1cSAllocationProfilerViterate_since_last_gc6F_v_;
+text: .text%__1cUGenGCPrologueClosureNdo_generation6MpnKGeneration__v_: genCollectedHeap.o;
+text: .text%__1cQDefNewGenerationLgc_prologue6Mi_v_: defNewGeneration.o;
+text: .text%__1cRTenuredGenerationLgc_prologue6Mi_v_;
+text: .text%__1cKGenerationLgc_prologue6Mi_v_: compactingPermGenGen.o;
+text: .text%__1cKGenerationOshould_collect6MiIii_i_: defNewGeneration.o;
+text: .text%__1cQDefNewGenerationKshort_name6kM_pkc_: defNewGeneration.o;
+text: .text%__1cKGenerationIcounters6M_pnRCollectorCounters__: defNewGeneration.o;
+text: .text%__1cQGenCollectedHeapKsave_marks6M_v_;
+text: .text%__1cQDefNewGenerationKsave_marks6M_v_;
+text: .text%__1cbCOneContigSpaceCardGenerationKsave_marks6M_v_;
+text: .text%__1cQDefNewGenerationHcollect6MiiIii_v_;
+text: .text%__1cQDefNewGenerationbAcollection_attempt_is_safe6M_i_;
+text: .text%__1cRTenuredGenerationZpromotion_attempt_is_safe6kMIi_i_;
+text: .text%__1cKGenerationYmax_contiguous_available6kM_I_;
+text: .text%__1cbCOneContigSpaceCardGenerationUcontiguous_available6kM_I_;
+text: .text%__1cQDefNewGenerationbIinit_assuming_no_promotion_failure6M_v_;
+text: .text%__1cQDefNewGenerationOIsAliveClosure2t6MpnKGeneration__v_;
+text: .text%__1cSScanWeakRefClosure2t6MpnQDefNewGeneration__v_;
+text: .text%__1cLCardTableRSbGprepare_for_younger_refs_iterate6Mi_v_;
+text: .text%__1cULRUCurrentHeapPolicy2t6M_v_;
+text: .text%__1cPCollectorPolicyPis_train_policy6M_i_: collectorPolicy.o;
+text: .text%__1cPFastScanClosure2t6MpnQDefNewGeneration_i_v_;
+text: .text%__1cQDefNewGenerationbCFastEvacuateFollowersClosure2t6MpnQGenCollectedHeap_ip0pnPFastScanClosure_6_v_;
+text: .text%__1cQGenCollectedHeapUprocess_strong_roots6Miiin0ATClassScanningOption_pnQOopsInGenClosure_3_v_;
+text: .text%__1cKSharedHeapbAchange_strong_roots_parity6M_v_;
+text: .text%__1cMSubTasksDonePis_task_claimed6Mi_i_;
+text: .text%__1cIUniverseHoops_do6FpnKOopClosure_i_v_;
+text: .text%__1cPFastScanClosureGdo_oop6MppnHoopDesc__v_: defNewGeneration.o;
+text: .text%__1cQDefNewGenerationWcopy_to_survivor_space6MpnHoopDesc_p2_2_;
+text: .text%__1cKJNIHandlesHoops_do6FpnKOopClosure__v_;
+text: .text%__1cOJNIHandleBlockHoops_do6MpnKOopClosure__v_;
+text: .text%__1cHThreadsHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKJavaThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cGThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cKHandleAreaHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNchunk_oops_do6FpnKOopClosure_pnFChunk_pc_I_: handles.o;
+text: .text%__1cQStackFrameStream2t6MpnKJavaThread_i_v_;
+text: .text%__1cFframeQoops_do_internal6MpnKOopClosure_pnLRegisterMap_i_v_;
+text: .text%__1cFframeToops_interpreted_do6MpnKOopClosure_pknLRegisterMap_i_v_;
+text: .text%__1cFframeVinterpreter_frame_bci6kM_i_;
+text: .text%__1cFframebDinterpreter_frame_monitor_end6kM_pnPBasicObjectLock__;
+text: .text%__1cFframebFinterpreter_frame_monitor_begin6kM_pnPBasicObjectLock__;
+text: .text%__1cRInterpreterOopMap2t6M_v_;
+text: .text%__1cRInterpreterOopMapKinitialize6M_v_;
+text: .text%__1cNmethodOopDescImask_for6MipnRInterpreterOopMap__v_;
+text: .text%__1cNinstanceKlassImask_for6MnMmethodHandle_ipnRInterpreterOopMap__v_;
+text: .text%__1cLOopMapCache2t6M_v_;
+text: .text%__1cLOopMapCacheGlookup6MnMmethodHandle_ipnRInterpreterOopMap__v_;
+text: .text%__1cLOopMapCacheIentry_at6kMi_pnQOopMapCacheEntry__;
+text: .text%__1cRInterpreterOopMapIis_empty6M_i_;
+text: .text%__1cQOopMapCacheEntryEfill6MnMmethodHandle_i_v_;
+text: .text%__1cQOopMapCacheEntryFflush6M_v_;
+text: .text%__1cQOopMapCacheEntryTdeallocate_bit_mask6M_v_;
+text: .text%__1cQOopMapCacheEntryPfill_for_native6M_v_;
+text: .text%__1cQOopMapCacheEntryRallocate_bit_mask6M_v_;
+text: .text%__1cTMaskFillerForNative2t6MnMmethodHandle_pIi_v_: oopMapCache.o;
+text: .text%__1cNFingerprinterLfingerprint6M_X_: oopMapCache.o;
+text: .text%__1cTMaskFillerForNativeLpass_object6M_v_: oopMapCache.o;
+text: .text%__1cRInterpreterOopMapNresource_copy6MpnQOopMapCacheEntry__v_;
+text: .text%__1cRInterpreterOopMapLiterate_oop6MpnNOffsetClosure__v_;
+text: .text%__1cXInterpreterFrameClosureJoffset_do6Mi_v_: frame.o;
+text: .text%__1cRInterpreterOopMap2T6M_v_;
+text: .text%__1cTOopMapForCacheEntry2t6MnMmethodHandle_ipnQOopMapCacheEntry__v_;
+text: .text%__1cTOopMapForCacheEntryLcompute_map6MpnGThread__v_;
+text: .text%__1cTOopMapForCacheEntryRpossible_gc_point6MpnOBytecodeStream__i_;
+text: .text%__1cTOopMapForCacheEntryOreport_results6kM_i_: oopMapCache.o;
+text: .text%__1cOGenerateOopMapVresult_for_basicblock6Mi_v_;
+text: .text%__1cTOopMapForCacheEntryZfill_stackmap_for_opcodes6MpnOBytecodeStream_pnNCellTypeState_4i_v_;
+text: .text%__1cQOopMapCacheEntryIset_mask6MpnNCellTypeState_2i_v_;
+text: .text%__1cFframeNoops_entry_do6MpnKOopClosure_pknLRegisterMap__v_;
+text: .text%__1cPJavaCallWrapperHoops_do6MpnKOopClosure__v_;
+text: .text%__1cXNativeSignatureIteratorHdo_long6M_v_: oopMapCache.o;
+text: .text%__1cTMaskFillerForNativeJpass_long6M_v_: oopMapCache.o;
+text: .text%__1cFframebHnext_monitor_in_interpreter_frame6kMpnPBasicObjectLock__2_;
+text: .text%__1cOGenerateOopMapPdo_monitorenter6Mi_v_;
+text: .text%__1cOGenerateOopMapXreplace_all_CTS_matches6MnNCellTypeState_1_v_;
+text: .text%__1cOGenerateOopMapMmonitor_push6MnNCellTypeState__v_;
+text: .text%__1cQComputeCallStackHdo_bool6M_v_: generateOopMap.o;
+text: .text%__1cQComputeCallStackHdo_long6M_v_: generateOopMap.o;
+text: .text%__1cOGenerateOopMapOdo_monitorexit6Mi_v_;
+text: .text%__1cOGenerateOopMapLmonitor_pop6M_nNCellTypeState__;
+text: .text%__1cRComputeEntryStackHdo_long6M_v_: generateOopMap.o;
+text: .text%__1cPBytecode_invokeIis_valid6kM_i_: frame.o;
+text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: oopMapCache.o;
+text: .text%__1cFframebDoops_interpreted_arguments_do6MnMsymbolHandle_ipnKOopClosure__v_;
+text: .text%__1cRArgumentOopFinderDset6MinJBasicType__v_: frame.o;
+text: .text%__1cIVMThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQVMOperationQdDueueHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQVMOperationQdDueueNqueue_oops_do6MipnKOopClosure__v_;
+text: .text%__1cSObjectSynchronizerHoops_do6FpnKOopClosure__v_;
+text: .text%__1cMFlatProfilerHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKManagementHoops_do6FpnKOopClosure__v_;
+text: .text%__1cNMemoryServiceHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKMemoryPoolHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNMemoryManagerHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNThreadServiceHoops_do6FpnKOopClosure__v_;
+text: .text%__1cLJvmtiExportHoops_do6FpnKOopClosure__v_;
+text: .text%__1cXJvmtiCurrentBreakpointsHoops_do6FpnKOopClosure__v_;
+text: .text%__1cbGJvmtiVMObjectAllocEventCollectorXoops_do_for_all_threads6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryHoops_do6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryRpreloaded_oops_do6FpnKOopClosure__v_;
+text: .text%__1cKDictionaryHoops_do6MpnKOopClosure__v_;
+text: .text%__1cPDictionaryEntrybDprotection_domain_set_oops_do6MpnKOopClosure__v_: dictionary.o;
+text: .text%__1cQPlaceholderTableHoops_do6MpnKOopClosure__v_;
+text: .text%__1cVLoaderConstraintTableHoops_do6MpnKOopClosure__v_;
+text: .text%__1cUCompactingPermGenGenUyounger_refs_iterate6MpnQOopsInGenClosure__v_;
+text: .text%__1cbCOneContigSpaceCardGenerationUyounger_refs_iterate6MpnQOopsInGenClosure__v_;
+text: .text%__1cKGenerationbDyounger_refs_in_space_iterate6MpnFSpace_pnQOopsInGenClosure__v_;
+text: .text%__1cLCardTableRSbDyounger_refs_in_space_iterate6MpnFSpace_pnQOopsInGenClosure__v_;
+text: .text%__1cPContiguousSpaceLnew_dcto_cl6MpnKOopClosure_nRCardTableModRefBSOPrecisionStyle_pnIHeapWord__pnVDirtyCardToOopClosure__;
+text: .text%__1cPContiguousSpaceZused_region_at_save_marks6kM_nJMemRegion__: space.o;
+text: .text%__1cRCardTableModRefBSWnon_clean_card_iterate6MpnFSpace_nJMemRegion_pnVDirtyCardToOopClosure_pnQMemRegionClosure_i_v_;
+text: .text%__1cRCardTableModRefBSbBnon_clean_card_iterate_work6MnJMemRegion_pnQMemRegionClosure_i_v_;
+text: .text%__1cJMemRegionMintersection6kMk0_0_;
+text: .text%__1cYClearNoncleanCardWrapperMdo_MemRegion6MnJMemRegion__v_: cardTableRS.o;
+text: .text%__1cYClearNoncleanCardWrapperKclear_card6MpW_i_: cardTableRS.o;
+text: .text%__1cVDirtyCardToOopClosureMdo_MemRegion6MnJMemRegion__v_;
+text: .text%__1cWOffsetTableContigSpaceLblock_start6kMpkv_pnIHeapWord__: space.o;
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+text: .text%__1cILIR_ListKround32bit6MnFRInfo_i_v_: c1_LIREmitter.o;
+text: .text%__1cIValueGenOspill_register6MnFRInfo__v_;
+text: .text%__1cIRegAllocTget_value_for_rinfo6kMnFRInfo__pnLInstruction__;
+text: .text%__1cLGetValueForGdo_cpu6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cIValueGenKdivInRInfo6F_nFRInfo__;
+text: .text%__1cIValueGenLremOutRInfo6F_nFRInfo__;
+text: .text%__1cMArithmeticOpKlock_stack6kM_pnKValueStack__: c1_Instruction.o;
+text: .text%__1cLLIR_EmitterParithmetic_idiv6MnJBytecodesECode_pnLLIR_OprDesc_44nFRInfo_pnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListEirem6MnFRInfo_111pnMCodeEmitInfo__v_;
+text: .text%__1cHLIR_Op3Fvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cHLIR_Op3Jemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerIemit_op36MpnHLIR_Op3__v_;
+text: .text%__1cNLIR_AssemblerIfpu_push6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimEpush6Mi_v_;
+text: .text%__1cNLIR_AssemblerKfpu_on_tos6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimPoffset_from_tos6kMi_i_;
+text: .text%__1cIintArrayIindex_of6kMki_i_: c1_FrameMap_x86.o;
+text: .text%__1cNLIR_AssemblerHfpu_pop6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimDpop6Mi_i_;
+text: .text%__1cNLIR_AssemblerKround32_op6MpnLLIR_OprDesc_2_v_;
+text: .text%__1cJAssemblerGfist_s6MnHAddress__v_;
+text: .text%__1cNLIR_AssemblerJreset_FPU6M_v_;
+text: .text%__1cNLIR_AssemblerIemit_op36MpnHLIR_Op3__v_;
+text: .text%__1cNLIR_AssemblerParithmetic_idiv6MnILIR_Code_pnLLIR_OprDesc_333pnMCodeEmitInfo__v_;
+text: .text%__1cNLIR_AssemblerXadd_debug_info_for_div06MipnMCodeEmitInfo__v_;
+text: .text%__1cNDivByZeroStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cNDivByZeroStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cIciObjectSis_obj_array_klass6M_i_: ciTypeArrayKlass.o;
+text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_GraphBuilder.o;
+text: .text%__1cLInstructionKas_ShiftOp6M_pnHShiftOp__: c1_Instruction.o;
+text: .text%__1cILIR_ListLlogical_xor6MnFRInfo_pnLLIR_OprDesc_1_v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListUunsigned_shift_right6MnFRInfo_i1_v_: c1_LIREmitter.o;
+text: .text%__1cIRuntime1Ohandle_ic_miss6FpnKJavaThread_pnHoopDesc__pC_;
+text: .text%__1cNSharedRuntimeVhandle_ic_miss_helper6FpnKJavaThread_pnGThread__nMmethodHandle__;
+text: .text%__1cbEJvmtiDynamicCodeEventCollector2t6M_v_;
+text: .text%__1cKCompiledICOis_megamorphic6kM_i_;
+text: .text%__1cLVtableStubsOis_entry_point6FpC_i_;
+text: .text%__1cKCompiledICSset_to_megamorphic6MpnICallInfo_nJBytecodesECode_pnGThread__v_;
+text: .text%__1cLVtableStubsLcreate_stub6FiipnNmethodOopDesc__pC_;
+text: .text%__1cLVtableStubsGlookup6Fiii_pnKVtableStub__;
+text: .text%__1cLVtableStubsScreate_vtable_stub6Fii_pnKVtableStub__;
+text: .text%__1cKVtableStubSpd_code_size_limit6Fi_i_;
+text: .text%__1cKVtableStub2n6FIi_pv_;
+text: .text%__1cKVtableStubRpd_code_alignment6F_i_;
+text: .text%__1cLVtableStubsFenter6FiiipnKVtableStub__v_;
+text: .text%__1cGEventsDlog6FpkcE_v_: compiledIC.o;
+text: .text%__1cbEJvmtiDynamicCodeEventCollector2T6M_v_;
+text: .text%Unsafe_EnsureClassInitialized;
+text: .text%Unsafe_StaticFieldOffset;
+text: .text%Unsafe_StaticFieldBaseFromField;
+text: .text%Unsafe_GetIntVolatile;
+text: .text%__1cUBytecode_tableswitchGlength6M_i_: generateOopMap.o;
+text: .text%__1cUBytecode_tableswitchOdest_offset_at6kMi_i_;
+text: .text%__1cUBytecode_tableswitchGlength6M_i_: c1_GraphBuilder.o;
+text: .text%__1cLInstructionKas_ShiftOp6M_pnHShiftOp__: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderMtable_switch6M_v_;
+text: .text%__1cLTableSwitchFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cLInstructionJas_Return6M_pnGReturn__: c1_GraphBuilder.o;
+text: .text%__1cGSwitchPinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cIValueGenOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cIValueGenVsetup_phis_for_switch6MpnEItem_pnKValueStack__v_;
+text: .text%__1cLLIR_EmitterOtableswitch_op6MpnLLIR_OprDesc_ipnKBlockBegin__v_;
+text: .text%__1cWstatic_call_RelocationLstatic_stub6M_pC_;
+text: .text%__1cSCompiledStaticCallMset_to_clean6M_v_;
+# Test JHello
+text: .text%__1cYjava_lang_reflect_MethodNset_signature6FpnHoopDesc_2_v_;
+text: .text%JVM_InitializeSocketLibrary;
+text: .text%__1cDhpiZinitialize_socket_library6F_i_;
+text: .text%JVM_Socket;
+text: .text%Unsafe_PageSize;
+text: .text%__1cNFingerprinterHdo_byte6M_v_: dump.o;
+text: .text%__1cXNativeSignatureIteratorHdo_byte6M_v_: interpreterRuntime.o;
+text: .text%Unsafe_SetMemory;
+text: .text%__1cECopyQpd_fill_to_words6FpnIHeapWord_II_v_: unsafe.o;
+text: .text%__1cNSharedRuntimeElrem6Fxx_x_;
+text: .text%Unsafe_DefineClass1;
+text: .text%__1cSUnsafe_DefineClass6FpnHJNIEnv__pnI_jstring_pnL_jbyteArray_iipnI_jobject_7_pnH_jclass__: unsafe.o;
+text: .text%JVM_DefineClass;
+text: .text%__1cPClassFileParserXverify_unqualified_name6MpcIi_i_;
+text: .text%__1cVLoaderConstraintTableYextend_loader_constraint6MpnVLoaderConstraintEntry_nGHandle_pnMklassOopDesc__v_;
+text: .text%__1cVLoaderConstraintTablebHensure_loader_constraint_capacity6MpnVLoaderConstraintEntry_i_v_;
+text: .text%__1cIciObjectIis_klass6M_i_: ciInstance.o;
+text: .text%__1cQInstanceConstantIencoding6kM_pnI_jobject__;
+text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_Instruction.o;
+text: .text%__1cILIR_ListQunwind_exception6MnFRInfo_1pnMCodeEmitInfo__v_: c1_CodeGenerator.o;
+text: .text%__1cIRuntime1Tprimitive_arraycopy6FpnIHeapWord_2i_v_;
+text: .text%__1cRComputeEntryStackHdo_char6M_v_: generateOopMap.o;
+text: .text%jni_NewDirectByteBuffer;
+text: .text%__1cbDinitializeDirectBufferSupport6FpnHJNIEnv___i_: jni.o;
+text: .text%lookupDirectBufferClasses: jni.o;
+text: .text%__1cJlookupOne6FpnHJNIEnv__pkcpnGThread__pnH_jclass__: jni.o;
+text: .text%__1cHJNIEnv_JNewObject6MpnH_jclass_pnK_jmethodID_E_pnI_jobject__: jni.o;
+text: .text%jni_GetDoubleArrayRegion: jni.o;
+text: .text%__1cNSignatureInfoJdo_double6M_v_: bytecode.o;
+text: .text%__1cXJNI_ArgumentPusherVaArgJget_float6M_v_: jni.o;
+text: .text%__1cQComputeCallStackHdo_byte6M_v_: generateOopMap.o;
+text: .text%__1cFKlassQup_cast_abstract6M_p0_;
+text: .text%__1cRComputeEntryStackHdo_byte6M_v_: generateOopMap.o;
+text: .text%__1cNSharedRuntimeDd2i6Fd_i_;
+text: .text%__1cSInterpreterRuntimeWslow_signature_handler6FpnKJavaThread_pnNmethodOopDesc_pi5_pC_;
+text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerLpass_object6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorIdo_array6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorGdo_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerIpass_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorHdo_bool6M_v_: interpreterRT_x86.o;
+text: .text%jni_GetFloatArrayRegion: jni.o;
+text: .text%jni_GetCharArrayRegion: jni.o;
+text: .text%jni_SetFloatField: jni.o;
+text: .text%jni_NewFloatArray: jni.o;
+text: .text%jni_SetFloatArrayRegion: jni.o;
+# SwingSet
+text: .text%JVM_GetFieldIxModifiers;
+text: .text%JVM_GetCPFieldClassNameUTF;
+text: .text%JVM_GetCPFieldModifiers;
+text: .text%__1cPClassFileParserUverify_constantvalue6MiinSconstantPoolHandle_pnGThread__v_;
+text: .text%__1cXjava_lang_ref_ReferenceOset_discovered6FpnHoopDesc_2_v_;
+text: .text%__1cMStoreIndexedPother_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%JVM_MonitorNotify;
+text: .text%__1cSObjectSynchronizerGnotify6FnGHandle_pnGThread__v_;
+text: .text%__1cKValueStackElock6MpnHIRScope_pnLInstruction__i_;
+text: .text%__1cKValueStackGunlock6M_i_;
+text: .text%__1cLLIR_EmitterVmonitorenter_at_entry6MnFRInfo_pnMCodeEmitInfo__v_;
+text: .text%__1cLLIR_EmitterNmonitor_enter6MnFRInfo_111ipnMCodeEmitInfo_3_v_;
+text: .text%__1cQMonitorEnterStub2t6MnFRInfo_1pnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListbAload_stack_address_monitor6MinFRInfo__v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListLlock_object6MnFRInfo_111pnICodeStub_pnMCodeEmitInfo__v_;
+text: .text%__1cIValueGenNsyncTempRInfo6F_nFRInfo__;
+text: .text%__1cLLIR_EmitterQreturn_op_prolog6Mi_v_;
+text: .text%__1cLLIR_EmitterMmonitor_exit6MnFRInfo_11i_v_;
+text: .text%__1cILIR_ListNunlock_object6MnFRInfo_11pnICodeStub__v_;
+text: .text%__1cKLIR_OpLockFvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cQMonitorEnterStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cKLIR_OpLockJemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerJemit_lock6MpnKLIR_OpLock__v_;
+text: .text%__1cNLIR_AssemblerPmonitor_address6MinFRInfo__v_;
+text: .text%__1cIFrameMapbEaddress_for_monitor_lock_index6kMi_nHAddress__;
+text: .text%__1cIFrameMapbAfp_offset_for_monitor_lock6kMi_i_;
+text: .text%__1cNLIR_AssemblerJemit_lock6MpnKLIR_OpLock__v_;
+text: .text%__1cRC1_MacroAssemblerLlock_object6MpnMRegisterImpl_22rnFLabel__v_;
+text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cIFrameMapWmonitor_object_regname6kMi_nHOptoRegEName__;
+text: .text%__1cIFrameMapbCfp_offset_for_monitor_object6kMi_i_;
+text: .text%__1cMCodeEmitInfobHlocation_for_monitor_object_index6Mi_nILocation__;
+text: .text%__1cIFrameMapbHlocation_for_monitor_object_index6kMipnILocation__i_;
+text: .text%__1cMCodeEmitInfobFlocation_for_monitor_lock_index6Mi_nILocation__;
+text: .text%__1cIFrameMapbFlocation_for_monitor_lock_index6kMipnILocation__i_;
+text: .text%__1cMMonitorValue2t6MpnKScopeValue_nILocation__v_;
+text: .text%__1cMMonitorValueIwrite_on6MpnUDebugInfoWriteStream__v_;
+text: .text%__1cRC1_MacroAssemblerNunlock_object6MpnMRegisterImpl_22rnFLabel__v_;
+text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
+text: .text%__1cQMonitorEnterStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cNLIR_AssemblerRload_receiver_reg6MpnMRegisterImpl__v_;
+text: .text%__1cNLIR_AssemblerLmonitorexit6MnFRInfo_1pnMRegisterImpl_i3_v_;
+text: .text%__1cPMonitorExitStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%jni_NewIntArray: jni.o;
+text: .text%__1cNCollectedHeapYlarge_typearray_allocate6FnLKlassHandle_iipnGThread__pnHoopDesc__: typeArrayKlass.o;
+text: .text%__1cFKlassUoop_oop_iterate_nv_m6MpnHoopDesc_pnQFilteringClosure_nJMemRegion__i_: objArrayKlassKlass.o;
+text: .text%__1cSobjArrayKlassKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
+text: .text%__1cQinstanceRefKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_;
+text: .text%__1cRTenuredGenerationKshort_name6kM_pkc_: tenuredGeneration.o;
+text: .text%__1cKGenerationIcounters6M_pnRCollectorCounters__: tenuredGeneration.o;
+text: .text%__1cRTenuredGenerationHcollect6MiiIii_v_;
+text: .text%__1cRTenuredGenerationbJretire_alloc_buffers_before_full_gc6M_v_;
+text: .text%__1cbCOneContigSpaceCardGenerationHcollect6MiiIii_v_;
+text: .text%__1cMGenMarkSweepTinvoke_at_safepoint6FipnSReferenceProcessor_i_v_;
+text: .text%__1cJCodeCacheLgc_prologue6F_v_;
+text: .text%__1cHThreadsLgc_prologue6F_v_;
+text: .text%__1cKJavaThreadLgc_prologue6M_v_;
+text: .text%__1cKJavaThreadJframes_do6MpFpnFframe_pknLRegisterMap__v_v_;
+text: .text%__1cRframe_gc_prologue6FpnFframe_pknLRegisterMap__v_: thread.o;
+text: .text%__1cFframeLgc_prologue6M_v_;
+text: .text%__1cQGenCollectedHeapRsave_used_regions6Mii_v_;
+text: .text%__1cKGenerationQsave_used_region6M_v_: tenuredGeneration.o;
+text: .text%__1cbCOneContigSpaceCardGenerationLused_region6kM_nJMemRegion__;
+text: .text%__1cPContiguousSpaceLused_region6kM_nJMemRegion__: space.o;
+text: .text%__1cKGenerationQsave_used_region6M_v_: defNewGeneration.o;
+text: .text%__1cKGenerationLused_region6kM_nJMemRegion__: defNewGeneration.o;
+text: .text%__1cKGenerationQsave_used_region6M_v_: compactingPermGenGen.o;
+text: .text%__1cMGenMarkSweepPallocate_stacks6F_v_;
+text: .text%__1cQGenCollectedHeapOgather_scratch6MpnKGeneration_I_pnMScratchBlock__;
+text: .text%__1cQDefNewGenerationScontribute_scratch6MrpnMScratchBlock_pnKGeneration_I_v_;
+text: .text%__1cKGenerationScontribute_scratch6MrpnMScratchBlock_p0I_v_: tenuredGeneration.o;
+text: .text%__1cRsort_scratch_list6FrpnMScratchBlock__v_: genCollectedHeap.o;
+text: .text%__1cVremoveSmallestScratch6FppnMScratchBlock__1_: genCollectedHeap.o;
+text: .text%__1cMGenMarkSweepRmark_sweep_phase16Firii_v_;
+text: .text%__1cJEventMark2t6MpkcE_v_: genMarkSweep.o;
+text: .text%__1cJMarkSweepRFollowRootClosureGdo_oop6MppnHoopDesc__v_: markSweep.o;
+text: .text%__1cJMarkSweepLfollow_root6FppnHoopDesc__v_;
+text: .text%__1cParrayKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cLklassVtableToop_follow_contents6M_v_;
+text: .text%__1cJMarkSweepO_mark_and_push6FppnHoopDesc__v_;
+text: .text%__1cKklassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cJMarkSweepXrevisit_weak_klass_link6FpnFKlass__v_;
+text: .text%__1cJMarkSweepMfollow_stack6F_v_;
+text: .text%__1cNinstanceKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cSinstanceKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cNinstanceKlassUfollow_static_fields6M_v_;
+text: .text%__1cLklassItableToop_follow_contents6M_v_;
+text: .text%__1cJMarkSweepNpreserve_mark6FpnHoopDesc_pnLmarkOopDesc__v_;
+text: .text%__1cLsymbolKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cOtypeArrayKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cMjniIdMapBaseHoops_do6MpnKOopClosure__v_;
+text: .text%__1cIjniIdMapHoops_do6MpnKOopClosure__v_;
+text: .text%__1cJMarkSweepSMarkAndPushClosureGdo_oop6MppnHoopDesc__v_: markSweep.o;
+text: .text%__1cNobjArrayKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cJMarkSweepPmark_and_follow6FppnHoopDesc__v_;
+text: .text%__1cSobjArrayKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cRconstantPoolKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cWconstantPoolCacheKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cWConstantPoolCacheEntryPfollow_contents6M_v_;
+text: .text%__1cLmethodKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cQconstMethodKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cQinstanceRefKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cFJNIidHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryValways_strong_oops_do6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryYalways_strong_classes_do6FpnKOopClosure__v_;
+text: .text%__1cKDictionaryYalways_strong_classes_do6MpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryPplaceholders_do6FpnKOopClosure__v_;
+text: .text%__1cVLoaderConstraintTableYalways_strong_classes_do6MpnKOopClosure__v_;
+text: .text%__1cJvmSymbolsHoops_do6FpnKOopClosure_i_v_;
+text: .text%__1cJMarkSweepOIsAliveClosureLdo_object_b6MpnHoopDesc__i_: markSweep.o;
+text: .text%__1cJMarkSweepQKeepAliveClosureGdo_oop6MppnHoopDesc__v_;
+text: .text%__1cJMarkSweepSFollowStackClosureHdo_void6M_v_: markSweep.o;
+text: .text%__1cQSystemDictionaryMdo_unloading6FpnRBoolObjectClosure_pnKOopClosure__i_;
+text: .text%__1cKDictionaryMdo_unloading6MpnRBoolObjectClosure_pnKOopClosure__i_;
+text: .text%__1cVLoaderConstraintTableYpurge_loader_constraints6MpnRBoolObjectClosure__v_;
+text: .text%__1cJCodeCacheMdo_unloading6FpnRBoolObjectClosure_pnKOopClosure_iri_v_;
+text: .text%__1cJCodeCacheFfirst6F_pnICodeBlob__;
+text: .text%__1cICodeHeapLfirst_block6kM_pnJHeapBlock__;
+text: .text%__1cICodeHeapJnext_free6kMpnJHeapBlock__pv_;
+text: .text%__1cJCodeCacheFalive6FpnICodeBlob__2_;
+text: .text%__1cKBufferBlobIis_alive6kM_i_: codeBlob.o;
+text: .text%__1cKBufferBlobbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_: codeBlob.o;
+text: .text%__1cJCodeCacheEnext6FpnICodeBlob__2_;
+text: .text%__1cICodeHeapLblock_start6kMpv_pnJHeapBlock__;
+text: .text%__1cICodeHeapKnext_block6kMpnJHeapBlock__2_;
+text: .text%__1cNSingletonBlobIis_alive6kM_i_: codeBlob.o;
+text: .text%__1cNSingletonBlobbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_: codeBlob.o;
+text: .text%__1cLRuntimeStubIis_alive6kM_i_: codeBlob.o;
+text: .text%__1cLRuntimeStubbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_: codeBlob.o;
+text: .text%__1cHnmethodIis_alive6kM_i_: nmethod.o;
+text: .text%__1cHnmethodbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_;
+text: .text%__1cHnmethodOis_not_entrant6kM_i_: nmethod.o;
+text: .text%__1cHnmethodbHfollow_root_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_ppnHoopDesc_iri_v_;
+text: .text%__1cOoop_RelocationJoop_value6M_pnHoopDesc__;
+text: .text%__1cVcompiledICHolderKlassSoop_being_unloaded6MpnRBoolObjectClosure_pnHoopDesc__i_;
+text: .text%__1cVcompiledICHolderKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cJMarkSweepXfollow_weak_klass_links6F_v_;
+text: .text%__1cFKlassXfollow_weak_klass_links6MpnRBoolObjectClosure_pnKOopClosure__v_;
+text: .text%__1cNinstanceKlassXfollow_weak_klass_links6MpnRBoolObjectClosure_pnKOopClosure__v_;
+text: .text%__1cJHashtableGunlink6MpnRBoolObjectClosure__v_;
+text: .text%__1cMGenMarkSweepRmark_sweep_phase26F_v_;
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--- a/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486	Wed Jul 05 16:41:01 2017 +0200
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+text: .text%__1cICodeStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
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+text: .text%__1cOStaticCallStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
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+text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler_x86.o;
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-text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_i486.o;
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+text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
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 text: .text%__1cIFrameMapbAfp_offset_for_monitor_lock6kMi_i_;
 text: .text%__1cNLIR_AssemblerJemit_lock6MpnKLIR_OpLock__v_;
 text: .text%__1cRC1_MacroAssemblerLlock_object6MpnMRegisterImpl_22rnFLabel__v_;
-text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_i486.o;
+text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
 text: .text%__1cIFrameMapWmonitor_object_regname6kMi_nHOptoRegEName__;
 text: .text%__1cIFrameMapbCfp_offset_for_monitor_object6kMi_i_;
 text: .text%__1cMCodeEmitInfobHlocation_for_monitor_object_index6Mi_nILocation__;
@@ -4925,7 +4925,7 @@
 text: .text%__1cMMonitorValue2t6MpnKScopeValue_nILocation__v_;
 text: .text%__1cMMonitorValueIwrite_on6MpnUDebugInfoWriteStream__v_;
 text: .text%__1cRC1_MacroAssemblerNunlock_object6MpnMRegisterImpl_22rnFLabel__v_;
-text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_i486.o;
+text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
 text: .text%__1cQMonitorEnterStubJemit_code6MpnNLIR_Assembler__v_;
 text: .text%__1cNLIR_AssemblerRload_receiver_reg6MpnMRegisterImpl__v_;
 text: .text%__1cNLIR_AssemblerLmonitorexit6MnFRInfo_1pnMRegisterImpl_i3_v_;
@@ -5168,7 +5168,7 @@
 text: .text%__1cCosHrealloc6FpvI_1_;
 text: .text%Unsafe_GetNativeFloat;
 text: .text%__1cIValueGenQdo_currentThread6MpnJIntrinsic__v_;
-text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_i486.o;
+text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_x86.o;
 text: .text%__1cNLIR_AssemblerKget_thread6MpnLLIR_OprDesc__v_;
 text: .text%__1cIValueGenSload_item_patching6MpnHIRScope_ipnEItem_pnKValueStack_pnOExceptionScope__v_;
 text: .text%__1cEItemUget_jobject_constant6kM_pnIciObject__;
@@ -5246,7 +5246,7 @@
 text: .text%__1cFframeLnmethods_do6M_v_;
 text: .text%__1cFframeVnmethods_code_blob_do6M_v_;
 text: .text%__1cILIR_ListEidiv6MnFRInfo_i11pnMCodeEmitInfo__v_;
-text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_x86.o;
 text: .text%__1cONMethodSweeperPprocess_nmethod6FpnHnmethod__v_;
 text: .text%__1cHnmethodPis_locked_by_vm6kM_i_: nmethod.o;
 text: .text%__1cHnmethodLis_unloaded6kM_i_: nmethod.o;
@@ -5423,13 +5423,13 @@
 text: .text%__1cLLIR_EmitterOget_raw_unsafe6MnFRInfo_pnLLIR_OprDesc_3inJBasicType__v_;
 text: .text%__1cILIR_ListMload_mem_reg6MpnLLIR_Address_nFRInfo_nJBasicType_pnMCodeEmitInfo_nHLIR_Op1NLIR_PatchCode__v_;
 text: .text%__1cIValueGenPdo_LookupSwitch6MpnMLookupSwitch__v_;
-text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_i486.o;
+text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_x86.o;
 text: .text%__1cLLIR_EmitterVlookupswitch_range_op6MpnLLIR_OprDesc_iipnKBlockBegin__v_;
 text: .text%__1cNSharedRuntimeEldiv6Fxx_x_;
 text: .text%Unsafe_GetObjectVolatile;
 text: .text%signalHandler;
 text: .text%JVM_handle_solaris_signal;
-text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_i486.o;
+text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_x86.o;
 text: .text%__1cICodeBlobRis_at_poll_return6MpC_i_;
 text: .text%__1cUSafepointSynchronizebDhandle_polling_page_exception6FpnKJavaThread__pC_;
 text: .text%__1cbCCompiledCodeSafepointHandlerbDhandle_polling_page_exception6M_pC_;
--- a/hotspot/make/solaris/makefiles/sa.make	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/solaris/makefiles/sa.make	Wed Jul 05 16:41:01 2017 +0200
@@ -37,8 +37,9 @@
 SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
 
 # gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
 
 SA_CLASSDIR = $(GENERATED)/saclasses
 
@@ -52,7 +53,7 @@
 	   $(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
 	fi
 
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
 	$(QUIETLY) echo "Making $@";
 	$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
 	   echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -66,9 +67,17 @@
 	$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
 	  mkdir -p $(SA_CLASSDIR);        \
 	fi
-	$(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+	$(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+	$(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+	
 	$(QUIETLY) $(COMPILE.RMIC)  -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
 	$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+	$(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+	$(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
 	$(QUIETLY) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
 	$(QUIETLY) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
 	$(QUIETLY) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.proc.ProcDebuggerLocal
--- a/hotspot/make/windows/makefiles/sa.make	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/make/windows/makefiles/sa.make	Wed Jul 05 16:41:01 2017 +0200
@@ -49,15 +49,22 @@
 
 default::  $(GENERATED)\sa-jdi.jar
 
-$(GENERATED)\sa-jdi.jar: $(AGENT_ALLFILES:/=\) 
+$(GENERATED)\sa-jdi.jar: $(AGENT_FILES1:/=\) $(AGENT_FILES2:/=\)
 	@if not exist $(SA_CLASSDIR) mkdir $(SA_CLASSDIR)
 	@echo ...Building sa-jdi.jar
 	@echo ...$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) ....
-	@$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES:/=\)
+	@$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1:/=\)
+	@$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2:/=\)
 	$(COMPILE_RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
 	$(QUIETLY) echo $(SA_BUILD_VERSION_PROP) > $(SA_PROPERTIES)
 	$(RUN_JAR) cf $@ -C saclasses . 
 	$(RUN_JAR) uf $@ -C $(AGENT_SRC_DIR:/=\) META-INF\services\com.sun.jdi.connect.Connector 
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+	$(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+	$(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+	$(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+	$(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
 	$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.windbg.WindbgDebuggerLocal
 	$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext 
 	$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.ia64.IA64ThreadContext 
--- a/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -956,7 +956,8 @@
     size->load_item();
     store_stack_parameter (size->result(),
                            in_ByteSize(STACK_BIAS +
-                                       (i + frame::memory_parameter_word_sp_offset) * wordSize));
+                                       frame::memory_parameter_word_sp_offset * wordSize +
+                                       i * sizeof(jint)));
   }
 
   // This instruction can be deoptimized in the slow path : use
--- a/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -204,3 +204,9 @@
   NativeInstruction* ni = nativeInstruction_at(x);
   ni->set_long_at(0, u.l);
 }
+
+void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
+
+void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
--- a/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -465,9 +465,7 @@
 
     case T_LONG:
       assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
-#ifdef COMPILER2
 #ifdef _LP64
-        // Can't be tiered (yet)
         if (int_reg < int_reg_max) {
           Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
           regs[i].set2(r->as_VMReg());
@@ -476,11 +474,12 @@
           stk_reg_pairs += 2;
         }
 #else
+#ifdef COMPILER2
         // For 32-bit build, can't pass longs in O-regs because they become
         // I-regs and get trashed.  Use G-regs instead.  G1 and G4 are almost
         // spare and available.  This convention isn't used by the Sparc ABI or
         // anywhere else. If we're tiered then we don't use G-regs because c1
-        // can't deal with them as a "pair".
+        // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
         // G0: zero
         // G1: 1st Long arg
         // G2: global allocated to TLS
@@ -500,7 +499,6 @@
           regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
           stk_reg_pairs += 2;
         }
-#endif // _LP64
 #else // COMPILER2
         if (int_reg_pairs + 1 < int_reg_max) {
           if (is_outgoing) {
@@ -514,6 +512,7 @@
           stk_reg_pairs += 2;
         }
 #endif // COMPILER2
+#endif // _LP64
       break;
 
     case T_FLOAT:
@@ -699,17 +698,16 @@
 // Stores long into offset pointed to by base
 void AdapterGenerator::store_c2i_long(Register r, Register base,
                                       const int st_off, bool is_stack) {
-#ifdef COMPILER2
 #ifdef _LP64
   // In V9, longs are given 2 64-bit slots in the interpreter, but the
   // data is passed in only 1 slot.
   __ stx(r, base, next_arg_slot(st_off));
 #else
+#ifdef COMPILER2
   // Misaligned store of 64-bit data
   __ stw(r, base, arg_slot(st_off));    // lo bits
   __ srlx(r, 32, r);
   __ stw(r, base, next_arg_slot(st_off));  // hi bits
-#endif // _LP64
 #else
   if (is_stack) {
     // Misaligned store of 64-bit data
@@ -721,6 +719,7 @@
     __ stw(r             , base, next_arg_slot(st_off)); // hi bits
   }
 #endif // COMPILER2
+#endif // _LP64
   tag_c2i_arg(frame::TagCategory2, base, st_off, r);
 }
 
@@ -1637,7 +1636,7 @@
     }
   } else if (dst.is_single_phys_reg()) {
     if (src.is_adjacent_aligned_on_stack(2)) {
-      __ ld_long(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
+      __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
     } else {
       // dst is a single reg.
       // Remember lo is low address not msb for stack slots
@@ -1811,7 +1810,6 @@
                                                 VMRegPair *in_regs,
                                                 BasicType ret_type) {
 
-
   // Native nmethod wrappers never take possesion of the oop arguments.
   // So the caller will gc the arguments. The only thing we need an
   // oopMap for is if the call is static
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,7503 @@
+/*
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_x86.cpp.incl"
+
+// Implementation of AddressLiteral
+
+AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
+  _is_lval = false;
+  _target = target;
+  switch (rtype) {
+  case relocInfo::oop_type:
+    // Oops are a special case. Normally they would be their own section
+    // but in cases like icBuffer they are literals in the code stream that
+    // we don't have a section for. We use none so that we get a literal address
+    // which is always patchable.
+    break;
+  case relocInfo::external_word_type:
+    _rspec = external_word_Relocation::spec(target);
+    break;
+  case relocInfo::internal_word_type:
+    _rspec = internal_word_Relocation::spec(target);
+    break;
+  case relocInfo::opt_virtual_call_type:
+    _rspec = opt_virtual_call_Relocation::spec();
+    break;
+  case relocInfo::static_call_type:
+    _rspec = static_call_Relocation::spec();
+    break;
+  case relocInfo::runtime_call_type:
+    _rspec = runtime_call_Relocation::spec();
+    break;
+  case relocInfo::poll_type:
+  case relocInfo::poll_return_type:
+    _rspec = Relocation::spec_simple(rtype);
+    break;
+  case relocInfo::none:
+    break;
+  default:
+    ShouldNotReachHere();
+    break;
+  }
+}
+
+// Implementation of Address
+
+#ifdef _LP64
+
+Address Address::make_array(ArrayAddress adr) {
+  // Not implementable on 64bit machines
+  // Should have been handled higher up the call chain.
+  ShouldNotReachHere();
+  return Address();
+}
+
+// exceedingly dangerous constructor
+Address::Address(int disp, address loc, relocInfo::relocType rtype) {
+  _base  = noreg;
+  _index = noreg;
+  _scale = no_scale;
+  _disp  = disp;
+  switch (rtype) {
+    case relocInfo::external_word_type:
+      _rspec = external_word_Relocation::spec(loc);
+      break;
+    case relocInfo::internal_word_type:
+      _rspec = internal_word_Relocation::spec(loc);
+      break;
+    case relocInfo::runtime_call_type:
+      // HMM
+      _rspec = runtime_call_Relocation::spec();
+      break;
+    case relocInfo::poll_type:
+    case relocInfo::poll_return_type:
+      _rspec = Relocation::spec_simple(rtype);
+      break;
+    case relocInfo::none:
+      break;
+    default:
+      ShouldNotReachHere();
+  }
+}
+#else // LP64
+
+Address Address::make_array(ArrayAddress adr) {
+  AddressLiteral base = adr.base();
+  Address index = adr.index();
+  assert(index._disp == 0, "must not have disp"); // maybe it can?
+  Address array(index._base, index._index, index._scale, (intptr_t) base.target());
+  array._rspec = base._rspec;
+  return array;
+}
+
+// exceedingly dangerous constructor
+Address::Address(address loc, RelocationHolder spec) {
+  _base  = noreg;
+  _index = noreg;
+  _scale = no_scale;
+  _disp  = (intptr_t) loc;
+  _rspec = spec;
+}
+
+#endif // _LP64
+
+
+
+// Convert the raw encoding form into the form expected by the constructor for
+// Address.  An index of 4 (rsp) corresponds to having no index, so convert
+// that to noreg for the Address constructor.
+Address Address::make_raw(int base, int index, int scale, int disp) {
+  bool valid_index = index != rsp->encoding();
+  if (valid_index) {
+    Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
+    return madr;
+  } else {
+    Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
+    return madr;
+  }
+}
+
+// Implementation of Assembler
+
+int AbstractAssembler::code_fill_byte() {
+  return (u_char)'\xF4'; // hlt
+}
+
+// make this go away someday
+void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
+  if (rtype == relocInfo::none)
+        emit_long(data);
+  else  emit_data(data, Relocation::spec_simple(rtype), format);
+}
+
+void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
+  assert(imm_operand == 0, "default format must be immediate in this file");
+  assert(inst_mark() != NULL, "must be inside InstructionMark");
+  if (rspec.type() !=  relocInfo::none) {
+    #ifdef ASSERT
+      check_relocation(rspec, format);
+    #endif
+    // Do not use AbstractAssembler::relocate, which is not intended for
+    // embedded words.  Instead, relocate to the enclosing instruction.
+
+    // hack. call32 is too wide for mask so use disp32
+    if (format == call32_operand)
+      code_section()->relocate(inst_mark(), rspec, disp32_operand);
+    else
+      code_section()->relocate(inst_mark(), rspec, format);
+  }
+  emit_long(data);
+}
+
+static int encode(Register r) {
+  int enc = r->encoding();
+  if (enc >= 8) {
+    enc -= 8;
+  }
+  return enc;
+}
+
+static int encode(XMMRegister r) {
+  int enc = r->encoding();
+  if (enc >= 8) {
+    enc -= 8;
+  }
+  return enc;
+}
+
+void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
+  assert(dst->has_byte_register(), "must have byte register");
+  assert(isByte(op1) && isByte(op2), "wrong opcode");
+  assert(isByte(imm8), "not a byte");
+  assert((op1 & 0x01) == 0, "should be 8bit operation");
+  emit_byte(op1);
+  emit_byte(op2 | encode(dst));
+  emit_byte(imm8);
+}
+
+
+void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
+  assert(isByte(op1) && isByte(op2), "wrong opcode");
+  assert((op1 & 0x01) == 1, "should be 32bit operation");
+  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
+  if (is8bit(imm32)) {
+    emit_byte(op1 | 0x02); // set sign bit
+    emit_byte(op2 | encode(dst));
+    emit_byte(imm32 & 0xFF);
+  } else {
+    emit_byte(op1);
+    emit_byte(op2 | encode(dst));
+    emit_long(imm32);
+  }
+}
+
+// immediate-to-memory forms
+void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
+  assert((op1 & 0x01) == 1, "should be 32bit operation");
+  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
+  if (is8bit(imm32)) {
+    emit_byte(op1 | 0x02); // set sign bit
+    emit_operand(rm, adr, 1);
+    emit_byte(imm32 & 0xFF);
+  } else {
+    emit_byte(op1);
+    emit_operand(rm, adr, 4);
+    emit_long(imm32);
+  }
+}
+
+void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
+  LP64_ONLY(ShouldNotReachHere());
+  assert(isByte(op1) && isByte(op2), "wrong opcode");
+  assert((op1 & 0x01) == 1, "should be 32bit operation");
+  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
+  InstructionMark im(this);
+  emit_byte(op1);
+  emit_byte(op2 | encode(dst));
+  emit_data((intptr_t)obj, relocInfo::oop_type, 0);
+}
+
+
+void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
+  assert(isByte(op1) && isByte(op2), "wrong opcode");
+  emit_byte(op1);
+  emit_byte(op2 | encode(dst) << 3 | encode(src));
+}
+
+
+void Assembler::emit_operand(Register reg, Register base, Register index,
+                             Address::ScaleFactor scale, int disp,
+                             RelocationHolder const& rspec,
+                             int rip_relative_correction) {
+  relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
+
+  // Encode the registers as needed in the fields they are used in
+
+  int regenc = encode(reg) << 3;
+  int indexenc = index->is_valid() ? encode(index) << 3 : 0;
+  int baseenc = base->is_valid() ? encode(base) : 0;
+
+  if (base->is_valid()) {
+    if (index->is_valid()) {
+      assert(scale != Address::no_scale, "inconsistent address");
+      // [base + index*scale + disp]
+      if (disp == 0 && rtype == relocInfo::none  &&
+          base != rbp LP64_ONLY(&& base != r13)) {
+        // [base + index*scale]
+        // [00 reg 100][ss index base]
+        assert(index != rsp, "illegal addressing mode");
+        emit_byte(0x04 | regenc);
+        emit_byte(scale << 6 | indexenc | baseenc);
+      } else if (is8bit(disp) && rtype == relocInfo::none) {
+        // [base + index*scale + imm8]
+        // [01 reg 100][ss index base] imm8
+        assert(index != rsp, "illegal addressing mode");
+        emit_byte(0x44 | regenc);
+        emit_byte(scale << 6 | indexenc | baseenc);
+        emit_byte(disp & 0xFF);
+      } else {
+        // [base + index*scale + disp32]
+        // [10 reg 100][ss index base] disp32
+        assert(index != rsp, "illegal addressing mode");
+        emit_byte(0x84 | regenc);
+        emit_byte(scale << 6 | indexenc | baseenc);
+        emit_data(disp, rspec, disp32_operand);
+      }
+    } else if (base == rsp LP64_ONLY(|| base == r12)) {
+      // [rsp + disp]
+      if (disp == 0 && rtype == relocInfo::none) {
+        // [rsp]
+        // [00 reg 100][00 100 100]
+        emit_byte(0x04 | regenc);
+        emit_byte(0x24);
+      } else if (is8bit(disp) && rtype == relocInfo::none) {
+        // [rsp + imm8]
+        // [01 reg 100][00 100 100] disp8
+        emit_byte(0x44 | regenc);
+        emit_byte(0x24);
+        emit_byte(disp & 0xFF);
+      } else {
+        // [rsp + imm32]
+        // [10 reg 100][00 100 100] disp32
+        emit_byte(0x84 | regenc);
+        emit_byte(0x24);
+        emit_data(disp, rspec, disp32_operand);
+      }
+    } else {
+      // [base + disp]
+      assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
+      if (disp == 0 && rtype == relocInfo::none &&
+          base != rbp LP64_ONLY(&& base != r13)) {
+        // [base]
+        // [00 reg base]
+        emit_byte(0x00 | regenc | baseenc);
+      } else if (is8bit(disp) && rtype == relocInfo::none) {
+        // [base + disp8]
+        // [01 reg base] disp8
+        emit_byte(0x40 | regenc | baseenc);
+        emit_byte(disp & 0xFF);
+      } else {
+        // [base + disp32]
+        // [10 reg base] disp32
+        emit_byte(0x80 | regenc | baseenc);
+        emit_data(disp, rspec, disp32_operand);
+      }
+    }
+  } else {
+    if (index->is_valid()) {
+      assert(scale != Address::no_scale, "inconsistent address");
+      // [index*scale + disp]
+      // [00 reg 100][ss index 101] disp32
+      assert(index != rsp, "illegal addressing mode");
+      emit_byte(0x04 | regenc);
+      emit_byte(scale << 6 | indexenc | 0x05);
+      emit_data(disp, rspec, disp32_operand);
+    } else if (rtype != relocInfo::none ) {
+      // [disp] (64bit) RIP-RELATIVE (32bit) abs
+      // [00 000 101] disp32
+
+      emit_byte(0x05 | regenc);
+      // Note that the RIP-rel. correction applies to the generated
+      // disp field, but _not_ to the target address in the rspec.
+
+      // disp was created by converting the target address minus the pc
+      // at the start of the instruction. That needs more correction here.
+      // intptr_t disp = target - next_ip;
+      assert(inst_mark() != NULL, "must be inside InstructionMark");
+      address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
+      int64_t adjusted = disp;
+      // Do rip-rel adjustment for 64bit
+      LP64_ONLY(adjusted -=  (next_ip - inst_mark()));
+      assert(is_simm32(adjusted),
+             "must be 32bit offset (RIP relative address)");
+      emit_data((int32_t) adjusted, rspec, disp32_operand);
+
+    } else {
+      // 32bit never did this, did everything as the rip-rel/disp code above
+      // [disp] ABSOLUTE
+      // [00 reg 100][00 100 101] disp32
+      emit_byte(0x04 | regenc);
+      emit_byte(0x25);
+      emit_data(disp, rspec, disp32_operand);
+    }
+  }
+}
+
+void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
+                             Address::ScaleFactor scale, int disp,
+                             RelocationHolder const& rspec) {
+  emit_operand((Register)reg, base, index, scale, disp, rspec);
+}
+
+// Secret local extension to Assembler::WhichOperand:
+#define end_pc_operand (_WhichOperand_limit)
+
+address Assembler::locate_operand(address inst, WhichOperand which) {
+  // Decode the given instruction, and return the address of
+  // an embedded 32-bit operand word.
+
+  // If "which" is disp32_operand, selects the displacement portion
+  // of an effective address specifier.
+  // If "which" is imm64_operand, selects the trailing immediate constant.
+  // If "which" is call32_operand, selects the displacement of a call or jump.
+  // Caller is responsible for ensuring that there is such an operand,
+  // and that it is 32/64 bits wide.
+
+  // If "which" is end_pc_operand, find the end of the instruction.
+
+  address ip = inst;
+  bool is_64bit = false;
+
+  debug_only(bool has_disp32 = false);
+  int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
+
+  again_after_prefix:
+  switch (0xFF & *ip++) {
+
+  // These convenience macros generate groups of "case" labels for the switch.
+#define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
+#define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
+             case (x)+4: case (x)+5: case (x)+6: case (x)+7
+#define REP16(x) REP8((x)+0): \
+              case REP8((x)+8)
+
+  case CS_segment:
+  case SS_segment:
+  case DS_segment:
+  case ES_segment:
+  case FS_segment:
+  case GS_segment:
+    // Seems dubious
+    LP64_ONLY(assert(false, "shouldn't have that prefix"));
+    assert(ip == inst+1, "only one prefix allowed");
+    goto again_after_prefix;
+
+  case 0x67:
+  case REX:
+  case REX_B:
+  case REX_X:
+  case REX_XB:
+  case REX_R:
+  case REX_RB:
+  case REX_RX:
+  case REX_RXB:
+    NOT_LP64(assert(false, "64bit prefixes"));
+    goto again_after_prefix;
+
+  case REX_W:
+  case REX_WB:
+  case REX_WX:
+  case REX_WXB:
+  case REX_WR:
+  case REX_WRB:
+  case REX_WRX:
+  case REX_WRXB:
+    NOT_LP64(assert(false, "64bit prefixes"));
+    is_64bit = true;
+    goto again_after_prefix;
+
+  case 0xFF: // pushq a; decl a; incl a; call a; jmp a
+  case 0x88: // movb a, r
+  case 0x89: // movl a, r
+  case 0x8A: // movb r, a
+  case 0x8B: // movl r, a
+  case 0x8F: // popl a
+    debug_only(has_disp32 = true);
+    break;
+
+  case 0x68: // pushq #32
+    if (which == end_pc_operand) {
+      return ip + 4;
+    }
+    assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
+    return ip;                  // not produced by emit_operand
+
+  case 0x66: // movw ... (size prefix)
+    again_after_size_prefix2:
+    switch (0xFF & *ip++) {
+    case REX:
+    case REX_B:
+    case REX_X:
+    case REX_XB:
+    case REX_R:
+    case REX_RB:
+    case REX_RX:
+    case REX_RXB:
+    case REX_W:
+    case REX_WB:
+    case REX_WX:
+    case REX_WXB:
+    case REX_WR:
+    case REX_WRB:
+    case REX_WRX:
+    case REX_WRXB:
+      NOT_LP64(assert(false, "64bit prefix found"));
+      goto again_after_size_prefix2;
+    case 0x8B: // movw r, a
+    case 0x89: // movw a, r
+      debug_only(has_disp32 = true);
+      break;
+    case 0xC7: // movw a, #16
+      debug_only(has_disp32 = true);
+      tail_size = 2;  // the imm16
+      break;
+    case 0x0F: // several SSE/SSE2 variants
+      ip--;    // reparse the 0x0F
+      goto again_after_prefix;
+    default:
+      ShouldNotReachHere();
+    }
+    break;
+
+  case REP8(0xB8): // movl/q r, #32/#64(oop?)
+    if (which == end_pc_operand)  return ip + (is_64bit ? 8 : 4);
+    // these asserts are somewhat nonsensical
+#ifndef _LP64
+    assert(which == imm_operand || which == disp32_operand, "");
+#else
+    assert((which == call32_operand || which == imm_operand) && is_64bit ||
+           which == narrow_oop_operand && !is_64bit, "");
+#endif // _LP64
+    return ip;
+
+  case 0x69: // imul r, a, #32
+  case 0xC7: // movl a, #32(oop?)
+    tail_size = 4;
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    break;
+
+  case 0x0F: // movx..., etc.
+    switch (0xFF & *ip++) {
+    case 0x12: // movlps
+    case 0x28: // movaps
+    case 0x2E: // ucomiss
+    case 0x2F: // comiss
+    case 0x54: // andps
+    case 0x55: // andnps
+    case 0x56: // orps
+    case 0x57: // xorps
+    case 0x6E: // movd
+    case 0x7E: // movd
+    case 0xAE: // ldmxcsr   a
+      // 64bit side says it these have both operands but that doesn't
+      // appear to be true
+      debug_only(has_disp32 = true);
+      break;
+
+    case 0xAD: // shrd r, a, %cl
+    case 0xAF: // imul r, a
+    case 0xBE: // movsbl r, a (movsxb)
+    case 0xBF: // movswl r, a (movsxw)
+    case 0xB6: // movzbl r, a (movzxb)
+    case 0xB7: // movzwl r, a (movzxw)
+    case REP16(0x40): // cmovl cc, r, a
+    case 0xB0: // cmpxchgb
+    case 0xB1: // cmpxchg
+    case 0xC1: // xaddl
+    case 0xC7: // cmpxchg8
+    case REP16(0x90): // setcc a
+      debug_only(has_disp32 = true);
+      // fall out of the switch to decode the address
+      break;
+
+    case 0xAC: // shrd r, a, #8
+      debug_only(has_disp32 = true);
+      tail_size = 1;  // the imm8
+      break;
+
+    case REP16(0x80): // jcc rdisp32
+      if (which == end_pc_operand)  return ip + 4;
+      assert(which == call32_operand, "jcc has no disp32 or imm");
+      return ip;
+    default:
+      ShouldNotReachHere();
+    }
+    break;
+
+  case 0x81: // addl a, #32; addl r, #32
+    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
+    // on 32bit in the case of cmpl, the imm might be an oop
+    tail_size = 4;
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    break;
+
+  case 0x83: // addl a, #8; addl r, #8
+    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    tail_size = 1;
+    break;
+
+  case 0x9B:
+    switch (0xFF & *ip++) {
+    case 0xD9: // fnstcw a
+      debug_only(has_disp32 = true);
+      break;
+    default:
+      ShouldNotReachHere();
+    }
+    break;
+
+  case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
+  case REP4(0x10): // adc...
+  case REP4(0x20): // and...
+  case REP4(0x30): // xor...
+  case REP4(0x08): // or...
+  case REP4(0x18): // sbb...
+  case REP4(0x28): // sub...
+  case 0xF7: // mull a
+  case 0x8D: // lea r, a
+  case 0x87: // xchg r, a
+  case REP4(0x38): // cmp...
+  case 0x85: // test r, a
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    break;
+
+  case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
+  case 0xC6: // movb a, #8
+  case 0x80: // cmpb a, #8
+  case 0x6B: // imul r, a, #8
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    tail_size = 1; // the imm8
+    break;
+
+  case 0xE8: // call rdisp32
+  case 0xE9: // jmp  rdisp32
+    if (which == end_pc_operand)  return ip + 4;
+    assert(which == call32_operand, "call has no disp32 or imm");
+    return ip;
+
+  case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
+  case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
+  case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
+  case 0xDD: // fld_d a; fst_d a; fstp_d a
+  case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
+  case 0xDF: // fild_d a; fistp_d a
+  case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
+  case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
+  case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
+    debug_only(has_disp32 = true);
+    break;
+
+  case 0xF3:                    // For SSE
+  case 0xF2:                    // For SSE2
+    switch (0xFF & *ip++) {
+    case REX:
+    case REX_B:
+    case REX_X:
+    case REX_XB:
+    case REX_R:
+    case REX_RB:
+    case REX_RX:
+    case REX_RXB:
+    case REX_W:
+    case REX_WB:
+    case REX_WX:
+    case REX_WXB:
+    case REX_WR:
+    case REX_WRB:
+    case REX_WRX:
+    case REX_WRXB:
+      NOT_LP64(assert(false, "found 64bit prefix"));
+      ip++;
+    default:
+      ip++;
+    }
+    debug_only(has_disp32 = true); // has both kinds of operands!
+    break;
+
+  default:
+    ShouldNotReachHere();
+
+#undef REP8
+#undef REP16
+  }
+
+  assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
+#ifdef _LP64
+  assert(which != imm_operand, "instruction is not a movq reg, imm64");
+#else
+  // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
+  assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
+#endif // LP64
+  assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
+
+  // parse the output of emit_operand
+  int op2 = 0xFF & *ip++;
+  int base = op2 & 0x07;
+  int op3 = -1;
+  const int b100 = 4;
+  const int b101 = 5;
+  if (base == b100 && (op2 >> 6) != 3) {
+    op3 = 0xFF & *ip++;
+    base = op3 & 0x07;   // refetch the base
+  }
+  // now ip points at the disp (if any)
+
+  switch (op2 >> 6) {
+  case 0:
+    // [00 reg  100][ss index base]
+    // [00 reg  100][00   100  esp]
+    // [00 reg base]
+    // [00 reg  100][ss index  101][disp32]
+    // [00 reg  101]               [disp32]
+
+    if (base == b101) {
+      if (which == disp32_operand)
+        return ip;              // caller wants the disp32
+      ip += 4;                  // skip the disp32
+    }
+    break;
+
+  case 1:
+    // [01 reg  100][ss index base][disp8]
+    // [01 reg  100][00   100  esp][disp8]
+    // [01 reg base]               [disp8]
+    ip += 1;                    // skip the disp8
+    break;
+
+  case 2:
+    // [10 reg  100][ss index base][disp32]
+    // [10 reg  100][00   100  esp][disp32]
+    // [10 reg base]               [disp32]
+    if (which == disp32_operand)
+      return ip;                // caller wants the disp32
+    ip += 4;                    // skip the disp32
+    break;
+
+  case 3:
+    // [11 reg base]  (not a memory addressing mode)
+    break;
+  }
+
+  if (which == end_pc_operand) {
+    return ip + tail_size;
+  }
+
+#ifdef _LP64
+  assert(false, "fix locate_operand");
+#else
+  assert(which == imm_operand, "instruction has only an imm field");
+#endif // LP64
+  return ip;
+}
+
+address Assembler::locate_next_instruction(address inst) {
+  // Secretly share code with locate_operand:
+  return locate_operand(inst, end_pc_operand);
+}
+
+
+#ifdef ASSERT
+void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
+  address inst = inst_mark();
+  assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
+  address opnd;
+
+  Relocation* r = rspec.reloc();
+  if (r->type() == relocInfo::none) {
+    return;
+  } else if (r->is_call() || format == call32_operand) {
+    // assert(format == imm32_operand, "cannot specify a nonzero format");
+    opnd = locate_operand(inst, call32_operand);
+  } else if (r->is_data()) {
+    assert(format == imm_operand || format == disp32_operand
+           LP64_ONLY(|| format == narrow_oop_operand), "format ok");
+    opnd = locate_operand(inst, (WhichOperand)format);
+  } else {
+    assert(format == imm_operand, "cannot specify a format");
+    return;
+  }
+  assert(opnd == pc(), "must put operand where relocs can find it");
+}
+#endif // ASSERT
+
+void Assembler::emit_operand32(Register reg, Address adr) {
+  assert(reg->encoding() < 8, "no extended registers");
+  assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
+               adr._rspec);
+}
+
+void Assembler::emit_operand(Register reg, Address adr,
+                             int rip_relative_correction) {
+  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
+               adr._rspec,
+               rip_relative_correction);
+}
+
+void Assembler::emit_operand(XMMRegister reg, Address adr) {
+  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
+               adr._rspec);
+}
+
+// MMX operations
+void Assembler::emit_operand(MMXRegister reg, Address adr) {
+  assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+}
+
+// work around gcc (3.2.1-7a) bug
+void Assembler::emit_operand(Address adr, MMXRegister reg) {
+  assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+}
+
+
+void Assembler::emit_farith(int b1, int b2, int i) {
+  assert(isByte(b1) && isByte(b2), "wrong opcode");
+  assert(0 <= i &&  i < 8, "illegal stack offset");
+  emit_byte(b1);
+  emit_byte(b2 + i);
+}
+
+
+// Now the Assembler instruction (identical for 32/64 bits)
+
+void Assembler::adcl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xD0, dst, imm32);
+}
+
+void Assembler::adcl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x13);
+  emit_operand(dst, src);
+}
+
+void Assembler::adcl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x13, 0xC0, dst, src);
+}
+
+void Assembler::addl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_arith_operand(0x81, rax, dst, imm32);
+}
+
+void Assembler::addl(Address dst, Register src) {
+  InstructionMark im(this);
+  prefix(dst, src);
+  emit_byte(0x01);
+  emit_operand(src, dst);
+}
+
+void Assembler::addl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xC0, dst, imm32);
+}
+
+void Assembler::addl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x03);
+  emit_operand(dst, src);
+}
+
+void Assembler::addl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x03, 0xC0, dst, src);
+}
+
+void Assembler::addr_nop_4() {
+  // 4 bytes: NOP DWORD PTR [EAX+0]
+  emit_byte(0x0F);
+  emit_byte(0x1F);
+  emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
+  emit_byte(0);    // 8-bits offset (1 byte)
+}
+
+void Assembler::addr_nop_5() {
+  // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
+  emit_byte(0x0F);
+  emit_byte(0x1F);
+  emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
+  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
+  emit_byte(0);    // 8-bits offset (1 byte)
+}
+
+void Assembler::addr_nop_7() {
+  // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
+  emit_byte(0x0F);
+  emit_byte(0x1F);
+  emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
+  emit_long(0);    // 32-bits offset (4 bytes)
+}
+
+void Assembler::addr_nop_8() {
+  // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
+  emit_byte(0x0F);
+  emit_byte(0x1F);
+  emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
+  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
+  emit_long(0);    // 32-bits offset (4 bytes)
+}
+
+void Assembler::addsd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x58);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::addsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x58);
+  emit_operand(dst, src);
+}
+
+void Assembler::addss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x58);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::addss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x58);
+  emit_operand(dst, src);
+}
+
+void Assembler::andl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xE0, dst, imm32);
+}
+
+void Assembler::andl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x23);
+  emit_operand(dst, src);
+}
+
+void Assembler::andl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x23, 0xC0, dst, src);
+}
+
+void Assembler::andpd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x54);
+  emit_operand(dst, src);
+}
+
+void Assembler::bswapl(Register reg) { // bswap
+  int encode = prefix_and_encode(reg->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xC8 | encode);
+}
+
+void Assembler::call(Label& L, relocInfo::relocType rtype) {
+  // suspect disp32 is always good
+  int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
+
+  if (L.is_bound()) {
+    const int long_size = 5;
+    int offs = (int)( target(L) - pc() );
+    assert(offs <= 0, "assembler error");
+    InstructionMark im(this);
+    // 1110 1000 #32-bit disp
+    emit_byte(0xE8);
+    emit_data(offs - long_size, rtype, operand);
+  } else {
+    InstructionMark im(this);
+    // 1110 1000 #32-bit disp
+    L.add_patch_at(code(), locator());
+
+    emit_byte(0xE8);
+    emit_data(int(0), rtype, operand);
+  }
+}
+
+void Assembler::call(Register dst) {
+  // This was originally using a 32bit register encoding
+  // and surely we want 64bit!
+  // this is a 32bit encoding but in 64bit mode the default
+  // operand size is 64bit so there is no need for the
+  // wide prefix. So prefix only happens if we use the
+  // new registers. Much like push/pop.
+  int x = offset();
+  // this may be true but dbx disassembles it as if it
+  // were 32bits...
+  // int encode = prefix_and_encode(dst->encoding());
+  // if (offset() != x) assert(dst->encoding() >= 8, "what?");
+  int encode = prefixq_and_encode(dst->encoding());
+
+  emit_byte(0xFF);
+  emit_byte(0xD0 | encode);
+}
+
+
+void Assembler::call(Address adr) {
+  InstructionMark im(this);
+  prefix(adr);
+  emit_byte(0xFF);
+  emit_operand(rdx, adr);
+}
+
+void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
+  assert(entry != NULL, "call most probably wrong");
+  InstructionMark im(this);
+  emit_byte(0xE8);
+  intptr_t disp = entry - (_code_pos + sizeof(int32_t));
+  assert(is_simm32(disp), "must be 32bit offset (call2)");
+  // Technically, should use call32_operand, but this format is
+  // implied by the fact that we're emitting a call instruction.
+
+  int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
+  emit_data((int) disp, rspec, operand);
+}
+
+void Assembler::cdql() {
+  emit_byte(0x99);
+}
+
+void Assembler::cmovl(Condition cc, Register dst, Register src) {
+  NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x40 | cc);
+  emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::cmovl(Condition cc, Register dst, Address src) {
+  NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x40 | cc);
+  emit_operand(dst, src);
+}
+
+void Assembler::cmpb(Address dst, int imm8) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0x80);
+  emit_operand(rdi, dst, 1);
+  emit_byte(imm8);
+}
+
+void Assembler::cmpl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0x81);
+  emit_operand(rdi, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::cmpl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xF8, dst, imm32);
+}
+
+void Assembler::cmpl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x3B, 0xC0, dst, src);
+}
+
+
+void Assembler::cmpl(Register dst, Address  src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x3B);
+  emit_operand(dst, src);
+}
+
+void Assembler::cmpw(Address dst, int imm16) {
+  InstructionMark im(this);
+  assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
+  emit_byte(0x66);
+  emit_byte(0x81);
+  emit_operand(rdi, dst, 2);
+  emit_word(imm16);
+}
+
+// The 32-bit cmpxchg compares the value at adr with the contents of rax,
+// and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
+// The ZF is set if the compared values were equal, and cleared otherwise.
+void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
+  if (Atomics & 2) {
+     // caveat: no instructionmark, so this isn't relocatable.
+     // Emit a synthetic, non-atomic, CAS equivalent.
+     // Beware.  The synthetic form sets all ICCs, not just ZF.
+     // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
+     cmpl(rax, adr);
+     movl(rax, adr);
+     if (reg != rax) {
+        Label L ;
+        jcc(Assembler::notEqual, L);
+        movl(adr, reg);
+        bind(L);
+     }
+  } else {
+     InstructionMark im(this);
+     prefix(adr, reg);
+     emit_byte(0x0F);
+     emit_byte(0xB1);
+     emit_operand(reg, adr);
+  }
+}
+
+void Assembler::comisd(XMMRegister dst, Address src) {
+  // NOTE: dbx seems to decode this as comiss even though the
+  // 0x66 is there. Strangly ucomisd comes out correct
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  comiss(dst, src);
+}
+
+void Assembler::comiss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x2F);
+  emit_operand(dst, src);
+}
+
+void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xE6);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5B);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttss2sil(Register dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::decl(Address dst) {
+  // Don't use it directly. Use MacroAssembler::decrement() instead.
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0xFF);
+  emit_operand(rcx, dst);
+}
+
+void Assembler::divsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x5E);
+  emit_operand(dst, src);
+}
+
+void Assembler::divsd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::divss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x5E);
+  emit_operand(dst, src);
+}
+
+void Assembler::divss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::emms() {
+  NOT_LP64(assert(VM_Version::supports_mmx(), ""));
+  emit_byte(0x0F);
+  emit_byte(0x77);
+}
+
+void Assembler::hlt() {
+  emit_byte(0xF4);
+}
+
+void Assembler::idivl(Register src) {
+  int encode = prefix_and_encode(src->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xF8 | encode);
+}
+
+void Assembler::imull(Register dst, Register src) {
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xAF);
+  emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::imull(Register dst, Register src, int value) {
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  if (is8bit(value)) {
+    emit_byte(0x6B);
+    emit_byte(0xC0 | encode);
+    emit_byte(value);
+  } else {
+    emit_byte(0x69);
+    emit_byte(0xC0 | encode);
+    emit_long(value);
+  }
+}
+
+void Assembler::incl(Address dst) {
+  // Don't use it directly. Use MacroAssembler::increment() instead.
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0xFF);
+  emit_operand(rax, dst);
+}
+
+void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
+  InstructionMark im(this);
+  relocate(rtype);
+  assert((0 <= cc) && (cc < 16), "illegal cc");
+  if (L.is_bound()) {
+    address dst = target(L);
+    assert(dst != NULL, "jcc most probably wrong");
+
+    const int short_size = 2;
+    const int long_size = 6;
+    intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
+    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
+      // 0111 tttn #8-bit disp
+      emit_byte(0x70 | cc);
+      emit_byte((offs - short_size) & 0xFF);
+    } else {
+      // 0000 1111 1000 tttn #32-bit disp
+      assert(is_simm32(offs - long_size),
+             "must be 32bit offset (call4)");
+      emit_byte(0x0F);
+      emit_byte(0x80 | cc);
+      emit_long(offs - long_size);
+    }
+  } else {
+    // Note: could eliminate cond. jumps to this jump if condition
+    //       is the same however, seems to be rather unlikely case.
+    // Note: use jccb() if label to be bound is very close to get
+    //       an 8-bit displacement
+    L.add_patch_at(code(), locator());
+    emit_byte(0x0F);
+    emit_byte(0x80 | cc);
+    emit_long(0);
+  }
+}
+
+void Assembler::jccb(Condition cc, Label& L) {
+  if (L.is_bound()) {
+    const int short_size = 2;
+    address entry = target(L);
+    assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
+           "Dispacement too large for a short jmp");
+    intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
+    // 0111 tttn #8-bit disp
+    emit_byte(0x70 | cc);
+    emit_byte((offs - short_size) & 0xFF);
+  } else {
+    InstructionMark im(this);
+    L.add_patch_at(code(), locator());
+    emit_byte(0x70 | cc);
+    emit_byte(0);
+  }
+}
+
+void Assembler::jmp(Address adr) {
+  InstructionMark im(this);
+  prefix(adr);
+  emit_byte(0xFF);
+  emit_operand(rsp, adr);
+}
+
+void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
+  if (L.is_bound()) {
+    address entry = target(L);
+    assert(entry != NULL, "jmp most probably wrong");
+    InstructionMark im(this);
+    const int short_size = 2;
+    const int long_size = 5;
+    intptr_t offs = entry - _code_pos;
+    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
+      emit_byte(0xEB);
+      emit_byte((offs - short_size) & 0xFF);
+    } else {
+      emit_byte(0xE9);
+      emit_long(offs - long_size);
+    }
+  } else {
+    // By default, forward jumps are always 32-bit displacements, since
+    // we can't yet know where the label will be bound.  If you're sure that
+    // the forward jump will not run beyond 256 bytes, use jmpb to
+    // force an 8-bit displacement.
+    InstructionMark im(this);
+    relocate(rtype);
+    L.add_patch_at(code(), locator());
+    emit_byte(0xE9);
+    emit_long(0);
+  }
+}
+
+void Assembler::jmp(Register entry) {
+  int encode = prefix_and_encode(entry->encoding());
+  emit_byte(0xFF);
+  emit_byte(0xE0 | encode);
+}
+
+void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
+  InstructionMark im(this);
+  emit_byte(0xE9);
+  assert(dest != NULL, "must have a target");
+  intptr_t disp = dest - (_code_pos + sizeof(int32_t));
+  assert(is_simm32(disp), "must be 32bit offset (jmp)");
+  emit_data(disp, rspec.reloc(), call32_operand);
+}
+
+void Assembler::jmpb(Label& L) {
+  if (L.is_bound()) {
+    const int short_size = 2;
+    address entry = target(L);
+    assert(is8bit((entry - _code_pos) + short_size),
+           "Dispacement too large for a short jmp");
+    assert(entry != NULL, "jmp most probably wrong");
+    intptr_t offs = entry - _code_pos;
+    emit_byte(0xEB);
+    emit_byte((offs - short_size) & 0xFF);
+  } else {
+    InstructionMark im(this);
+    L.add_patch_at(code(), locator());
+    emit_byte(0xEB);
+    emit_byte(0);
+  }
+}
+
+void Assembler::ldmxcsr( Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  prefix(src);
+  emit_byte(0x0F);
+  emit_byte(0xAE);
+  emit_operand(as_Register(2), src);
+}
+
+void Assembler::leal(Register dst, Address src) {
+  InstructionMark im(this);
+#ifdef _LP64
+  emit_byte(0x67); // addr32
+  prefix(src, dst);
+#endif // LP64
+  emit_byte(0x8D);
+  emit_operand(dst, src);
+}
+
+void Assembler::lock() {
+  if (Atomics & 1) {
+     // Emit either nothing, a NOP, or a NOP: prefix
+     emit_byte(0x90) ;
+  } else {
+     emit_byte(0xF0);
+  }
+}
+
+// Serializes memory.
+void Assembler::mfence() {
+    // Memory barriers are only needed on multiprocessors
+  if (os::is_MP()) {
+    if( LP64_ONLY(true ||) VM_Version::supports_sse2() ) {
+      emit_byte( 0x0F );                // MFENCE; faster blows no regs
+      emit_byte( 0xAE );
+      emit_byte( 0xF0 );
+    } else {
+      // All usable chips support "locked" instructions which suffice
+      // as barriers, and are much faster than the alternative of
+      // using cpuid instruction. We use here a locked add [esp],0.
+      // This is conveniently otherwise a no-op except for blowing
+      // flags (which we save and restore.)
+      pushf();                // Save eflags register
+      lock();
+      addl(Address(rsp, 0), 0);// Assert the lock# signal here
+      popf();                 // Restore eflags register
+    }
+  }
+}
+
+void Assembler::mov(Register dst, Register src) {
+  LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void Assembler::movapd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  int dstenc = dst->encoding();
+  int srcenc = src->encoding();
+  emit_byte(0x66);
+  if (dstenc < 8) {
+    if (srcenc >= 8) {
+      prefix(REX_B);
+      srcenc -= 8;
+    }
+  } else {
+    if (srcenc < 8) {
+      prefix(REX_R);
+    } else {
+      prefix(REX_RB);
+      srcenc -= 8;
+    }
+    dstenc -= 8;
+  }
+  emit_byte(0x0F);
+  emit_byte(0x28);
+  emit_byte(0xC0 | dstenc << 3 | srcenc);
+}
+
+void Assembler::movaps(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  int dstenc = dst->encoding();
+  int srcenc = src->encoding();
+  if (dstenc < 8) {
+    if (srcenc >= 8) {
+      prefix(REX_B);
+      srcenc -= 8;
+    }
+  } else {
+    if (srcenc < 8) {
+      prefix(REX_R);
+    } else {
+      prefix(REX_RB);
+      srcenc -= 8;
+    }
+    dstenc -= 8;
+  }
+  emit_byte(0x0F);
+  emit_byte(0x28);
+  emit_byte(0xC0 | dstenc << 3 | srcenc);
+}
+
+void Assembler::movb(Register dst, Address src) {
+  NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
+  InstructionMark im(this);
+  prefix(src, dst, true);
+  emit_byte(0x8A);
+  emit_operand(dst, src);
+}
+
+
+void Assembler::movb(Address dst, int imm8) {
+  InstructionMark im(this);
+   prefix(dst);
+  emit_byte(0xC6);
+  emit_operand(rax, dst, 1);
+  emit_byte(imm8);
+}
+
+
+void Assembler::movb(Address dst, Register src) {
+  assert(src->has_byte_register(), "must have byte register");
+  InstructionMark im(this);
+  prefix(dst, src, true);
+  emit_byte(0x88);
+  emit_operand(src, dst);
+}
+
+void Assembler::movdl(XMMRegister dst, Register src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x6E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdl(Register dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  // swap src/dst to get correct prefix
+  int encode = prefix_and_encode(src->encoding(), dst->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x7E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdqa(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x6F);
+  emit_operand(dst, src);
+}
+
+void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x6F);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdqa(Address dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0x7F);
+  emit_operand(src, dst);
+}
+
+// Uses zero extension on 64bit
+
+void Assembler::movl(Register dst, int32_t imm32) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xB8 | encode);
+  emit_long(imm32);
+}
+
+void Assembler::movl(Register dst, Register src) {
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x8B);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x8B);
+  emit_operand(dst, src);
+}
+
+void Assembler::movl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0xC7);
+  emit_operand(rax, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::movl(Address dst, Register src) {
+  InstructionMark im(this);
+  prefix(dst, src);
+  emit_byte(0x89);
+  emit_operand(src, dst);
+}
+
+// New cpus require to use movsd and movss to avoid partial register stall
+// when loading from memory. But for old Opteron use movlpd instead of movsd.
+// The selection is done in MacroAssembler::movdbl() and movflt().
+void Assembler::movlpd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x12);
+  emit_operand(dst, src);
+}
+
+void Assembler::movq( MMXRegister dst, Address src ) {
+  assert( VM_Version::supports_mmx(), "" );
+  emit_byte(0x0F);
+  emit_byte(0x6F);
+  emit_operand(dst, src);
+}
+
+void Assembler::movq( Address dst, MMXRegister src ) {
+  assert( VM_Version::supports_mmx(), "" );
+  emit_byte(0x0F);
+  emit_byte(0x7F);
+  // workaround gcc (3.2.1-7a) bug
+  // In that version of gcc with only an emit_operand(MMX, Address)
+  // gcc will tail jump and try and reverse the parameters completely
+  // obliterating dst in the process. By having a version available
+  // that doesn't need to swap the args at the tail jump the bug is
+  // avoided.
+  emit_operand(dst, src);
+}
+
+void Assembler::movq(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x7E);
+  emit_operand(dst, src);
+}
+
+void Assembler::movq(Address dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0xD6);
+  emit_operand(src, dst);
+}
+
+void Assembler::movsbl(Register dst, Address src) { // movsxb
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0xBE);
+  emit_operand(dst, src);
+}
+
+void Assembler::movsbl(Register dst, Register src) { // movsxb
+  NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+  emit_byte(0x0F);
+  emit_byte(0xBE);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movsd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x10);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x10);
+  emit_operand(dst, src);
+}
+
+void Assembler::movsd(Address dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0x11);
+  emit_operand(src, dst);
+}
+
+void Assembler::movss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x10);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x10);
+  emit_operand(dst, src);
+}
+
+void Assembler::movss(Address dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0x11);
+  emit_operand(src, dst);
+}
+
+void Assembler::movswl(Register dst, Address src) { // movsxw
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0xBF);
+  emit_operand(dst, src);
+}
+
+void Assembler::movswl(Register dst, Register src) { // movsxw
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xBF);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movw(Address dst, int imm16) {
+  InstructionMark im(this);
+
+  emit_byte(0x66); // switch to 16-bit mode
+  prefix(dst);
+  emit_byte(0xC7);
+  emit_operand(rax, dst, 2);
+  emit_word(imm16);
+}
+
+void Assembler::movw(Register dst, Address src) {
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x8B);
+  emit_operand(dst, src);
+}
+
+void Assembler::movw(Address dst, Register src) {
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(dst, src);
+  emit_byte(0x89);
+  emit_operand(src, dst);
+}
+
+void Assembler::movzbl(Register dst, Address src) { // movzxb
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0xB6);
+  emit_operand(dst, src);
+}
+
+void Assembler::movzbl(Register dst, Register src) { // movzxb
+  NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+  emit_byte(0x0F);
+  emit_byte(0xB6);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movzwl(Register dst, Address src) { // movzxw
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0xB7);
+  emit_operand(dst, src);
+}
+
+void Assembler::movzwl(Register dst, Register src) { // movzxw
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xB7);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::mull(Address src) {
+  InstructionMark im(this);
+  prefix(src);
+  emit_byte(0xF7);
+  emit_operand(rsp, src);
+}
+
+void Assembler::mull(Register src) {
+  int encode = prefix_and_encode(src->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xE0 | encode);
+}
+
+void Assembler::mulsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x59);
+  emit_operand(dst, src);
+}
+
+void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x59);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::mulss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x59);
+  emit_operand(dst, src);
+}
+
+void Assembler::mulss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x59);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::negl(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xD8 | encode);
+}
+
+void Assembler::nop(int i) {
+#ifdef ASSERT
+  assert(i > 0, " ");
+  // The fancy nops aren't currently recognized by debuggers making it a
+  // pain to disassemble code while debugging. If asserts are on clearly
+  // speed is not an issue so simply use the single byte traditional nop
+  // to do alignment.
+
+  for (; i > 0 ; i--) emit_byte(0x90);
+  return;
+
+#endif // ASSERT
+
+  if (UseAddressNop && VM_Version::is_intel()) {
+    //
+    // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
+    //  1: 0x90
+    //  2: 0x66 0x90
+    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
+    //  4: 0x0F 0x1F 0x40 0x00
+    //  5: 0x0F 0x1F 0x44 0x00 0x00
+    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
+    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
+    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+
+    // The rest coding is Intel specific - don't use consecutive address nops
+
+    // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
+    // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
+    // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
+    // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
+
+    while(i >= 15) {
+      // For Intel don't generate consecutive addess nops (mix with regular nops)
+      i -= 15;
+      emit_byte(0x66);   // size prefix
+      emit_byte(0x66);   // size prefix
+      emit_byte(0x66);   // size prefix
+      addr_nop_8();
+      emit_byte(0x66);   // size prefix
+      emit_byte(0x66);   // size prefix
+      emit_byte(0x66);   // size prefix
+      emit_byte(0x90);   // nop
+    }
+    switch (i) {
+      case 14:
+        emit_byte(0x66); // size prefix
+      case 13:
+        emit_byte(0x66); // size prefix
+      case 12:
+        addr_nop_8();
+        emit_byte(0x66); // size prefix
+        emit_byte(0x66); // size prefix
+        emit_byte(0x66); // size prefix
+        emit_byte(0x90); // nop
+        break;
+      case 11:
+        emit_byte(0x66); // size prefix
+      case 10:
+        emit_byte(0x66); // size prefix
+      case 9:
+        emit_byte(0x66); // size prefix
+      case 8:
+        addr_nop_8();
+        break;
+      case 7:
+        addr_nop_7();
+        break;
+      case 6:
+        emit_byte(0x66); // size prefix
+      case 5:
+        addr_nop_5();
+        break;
+      case 4:
+        addr_nop_4();
+        break;
+      case 3:
+        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
+        emit_byte(0x66); // size prefix
+      case 2:
+        emit_byte(0x66); // size prefix
+      case 1:
+        emit_byte(0x90); // nop
+        break;
+      default:
+        assert(i == 0, " ");
+    }
+    return;
+  }
+  if (UseAddressNop && VM_Version::is_amd()) {
+    //
+    // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
+    //  1: 0x90
+    //  2: 0x66 0x90
+    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
+    //  4: 0x0F 0x1F 0x40 0x00
+    //  5: 0x0F 0x1F 0x44 0x00 0x00
+    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
+    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
+    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+
+    // The rest coding is AMD specific - use consecutive address nops
+
+    // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
+    // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
+    // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
+    // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
+    // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
+    //     Size prefixes (0x66) are added for larger sizes
+
+    while(i >= 22) {
+      i -= 11;
+      emit_byte(0x66); // size prefix
+      emit_byte(0x66); // size prefix
+      emit_byte(0x66); // size prefix
+      addr_nop_8();
+    }
+    // Generate first nop for size between 21-12
+    switch (i) {
+      case 21:
+        i -= 1;
+        emit_byte(0x66); // size prefix
+      case 20:
+      case 19:
+        i -= 1;
+        emit_byte(0x66); // size prefix
+      case 18:
+      case 17:
+        i -= 1;
+        emit_byte(0x66); // size prefix
+      case 16:
+      case 15:
+        i -= 8;
+        addr_nop_8();
+        break;
+      case 14:
+      case 13:
+        i -= 7;
+        addr_nop_7();
+        break;
+      case 12:
+        i -= 6;
+        emit_byte(0x66); // size prefix
+        addr_nop_5();
+        break;
+      default:
+        assert(i < 12, " ");
+    }
+
+    // Generate second nop for size between 11-1
+    switch (i) {
+      case 11:
+        emit_byte(0x66); // size prefix
+      case 10:
+        emit_byte(0x66); // size prefix
+      case 9:
+        emit_byte(0x66); // size prefix
+      case 8:
+        addr_nop_8();
+        break;
+      case 7:
+        addr_nop_7();
+        break;
+      case 6:
+        emit_byte(0x66); // size prefix
+      case 5:
+        addr_nop_5();
+        break;
+      case 4:
+        addr_nop_4();
+        break;
+      case 3:
+        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
+        emit_byte(0x66); // size prefix
+      case 2:
+        emit_byte(0x66); // size prefix
+      case 1:
+        emit_byte(0x90); // nop
+        break;
+      default:
+        assert(i == 0, " ");
+    }
+    return;
+  }
+
+  // Using nops with size prefixes "0x66 0x90".
+  // From AMD Optimization Guide:
+  //  1: 0x90
+  //  2: 0x66 0x90
+  //  3: 0x66 0x66 0x90
+  //  4: 0x66 0x66 0x66 0x90
+  //  5: 0x66 0x66 0x90 0x66 0x90
+  //  6: 0x66 0x66 0x90 0x66 0x66 0x90
+  //  7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
+  //  8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
+  //  9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
+  // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
+  //
+  while(i > 12) {
+    i -= 4;
+    emit_byte(0x66); // size prefix
+    emit_byte(0x66);
+    emit_byte(0x66);
+    emit_byte(0x90); // nop
+  }
+  // 1 - 12 nops
+  if(i > 8) {
+    if(i > 9) {
+      i -= 1;
+      emit_byte(0x66);
+    }
+    i -= 3;
+    emit_byte(0x66);
+    emit_byte(0x66);
+    emit_byte(0x90);
+  }
+  // 1 - 8 nops
+  if(i > 4) {
+    if(i > 6) {
+      i -= 1;
+      emit_byte(0x66);
+    }
+    i -= 3;
+    emit_byte(0x66);
+    emit_byte(0x66);
+    emit_byte(0x90);
+  }
+  switch (i) {
+    case 4:
+      emit_byte(0x66);
+    case 3:
+      emit_byte(0x66);
+    case 2:
+      emit_byte(0x66);
+    case 1:
+      emit_byte(0x90);
+      break;
+    default:
+      assert(i == 0, " ");
+  }
+}
+
+void Assembler::notl(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xD0 | encode );
+}
+
+void Assembler::orl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0x81);
+  emit_operand(rcx, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::orl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xC8, dst, imm32);
+}
+
+
+void Assembler::orl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0B);
+  emit_operand(dst, src);
+}
+
+
+void Assembler::orl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x0B, 0xC0, dst, src);
+}
+
+// generic
+void Assembler::pop(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0x58 | encode);
+}
+
+void Assembler::popf() {
+  emit_byte(0x9D);
+}
+
+void Assembler::popl(Address dst) {
+  // NOTE: this will adjust stack by 8byte on 64bits
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0x8F);
+  emit_operand(rax, dst);
+}
+
+void Assembler::prefetch_prefix(Address src) {
+  prefix(src);
+  emit_byte(0x0F);
+}
+
+void Assembler::prefetchnta(Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x18);
+  emit_operand(rax, src); // 0, src
+}
+
+void Assembler::prefetchr(Address src) {
+  NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x0D);
+  emit_operand(rax, src); // 0, src
+}
+
+void Assembler::prefetcht0(Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x18);
+  emit_operand(rcx, src); // 1, src
+}
+
+void Assembler::prefetcht1(Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x18);
+  emit_operand(rdx, src); // 2, src
+}
+
+void Assembler::prefetcht2(Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x18);
+  emit_operand(rbx, src); // 3, src
+}
+
+void Assembler::prefetchw(Address src) {
+  NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
+  InstructionMark im(this);
+  prefetch_prefix(src);
+  emit_byte(0x0D);
+  emit_operand(rcx, src); // 1, src
+}
+
+void Assembler::prefix(Prefix p) {
+  a_byte(p);
+}
+
+void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
+  assert(isByte(mode), "invalid value");
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+  emit_byte(0x66);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x70);
+  emit_byte(0xC0 | encode);
+  emit_byte(mode & 0xFF);
+
+}
+
+void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
+  assert(isByte(mode), "invalid value");
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x70);
+  emit_operand(dst, src);
+  emit_byte(mode & 0xFF);
+}
+
+void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
+  assert(isByte(mode), "invalid value");
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x70);
+  emit_byte(0xC0 | encode);
+  emit_byte(mode & 0xFF);
+}
+
+void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
+  assert(isByte(mode), "invalid value");
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst); // QQ new
+  emit_byte(0x0F);
+  emit_byte(0x70);
+  emit_operand(dst, src);
+  emit_byte(mode & 0xFF);
+}
+
+void Assembler::psrlq(XMMRegister dst, int shift) {
+  // HMM Table D-1 says sse2 or mmx
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+  int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
+  emit_byte(0x66);
+  emit_byte(0x0F);
+  emit_byte(0x73);
+  emit_byte(0xC0 | encode);
+  emit_byte(shift);
+}
+
+void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x60);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::push(int32_t imm32) {
+  // in 64bits we push 64bits onto the stack but only
+  // take a 32bit immediate
+  emit_byte(0x68);
+  emit_long(imm32);
+}
+
+void Assembler::push(Register src) {
+  int encode = prefix_and_encode(src->encoding());
+
+  emit_byte(0x50 | encode);
+}
+
+void Assembler::pushf() {
+  emit_byte(0x9C);
+}
+
+void Assembler::pushl(Address src) {
+  // Note this will push 64bit on 64bit
+  InstructionMark im(this);
+  prefix(src);
+  emit_byte(0xFF);
+  emit_operand(rsi, src);
+}
+
+void Assembler::pxor(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0xEF);
+  emit_operand(dst, src);
+}
+
+void Assembler::pxor(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xEF);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::rcll(Register dst, int imm8) {
+  assert(isShiftCount(imm8), "illegal shift count");
+  int encode = prefix_and_encode(dst->encoding());
+  if (imm8 == 1) {
+    emit_byte(0xD1);
+    emit_byte(0xD0 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xD0 | encode);
+    emit_byte(imm8);
+  }
+}
+
+// copies data from [esi] to [edi] using rcx pointer sized words
+// generic
+void Assembler::rep_mov() {
+  emit_byte(0xF3);
+  // MOVSQ
+  LP64_ONLY(prefix(REX_W));
+  emit_byte(0xA5);
+}
+
+// sets rcx pointer sized words with rax, value at [edi]
+// generic
+void Assembler::rep_set() { // rep_set
+  emit_byte(0xF3);
+  // STOSQ
+  LP64_ONLY(prefix(REX_W));
+  emit_byte(0xAB);
+}
+
+// scans rcx pointer sized words at [edi] for occurance of rax,
+// generic
+void Assembler::repne_scan() { // repne_scan
+  emit_byte(0xF2);
+  // SCASQ
+  LP64_ONLY(prefix(REX_W));
+  emit_byte(0xAF);
+}
+
+#ifdef _LP64
+// scans rcx 4 byte words at [edi] for occurance of rax,
+// generic
+void Assembler::repne_scanl() { // repne_scan
+  emit_byte(0xF2);
+  // SCASL
+  emit_byte(0xAF);
+}
+#endif
+
+void Assembler::ret(int imm16) {
+  if (imm16 == 0) {
+    emit_byte(0xC3);
+  } else {
+    emit_byte(0xC2);
+    emit_word(imm16);
+  }
+}
+
+void Assembler::sahf() {
+#ifdef _LP64
+  // Not supported in 64bit mode
+  ShouldNotReachHere();
+#endif
+  emit_byte(0x9E);
+}
+
+void Assembler::sarl(Register dst, int imm8) {
+  int encode = prefix_and_encode(dst->encoding());
+  assert(isShiftCount(imm8), "illegal shift count");
+  if (imm8 == 1) {
+    emit_byte(0xD1);
+    emit_byte(0xF8 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xF8 | encode);
+    emit_byte(imm8);
+  }
+}
+
+void Assembler::sarl(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xF8 | encode);
+}
+
+void Assembler::sbbl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_arith_operand(0x81, rbx, dst, imm32);
+}
+
+void Assembler::sbbl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xD8, dst, imm32);
+}
+
+
+void Assembler::sbbl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x1B);
+  emit_operand(dst, src);
+}
+
+void Assembler::sbbl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x1B, 0xC0, dst, src);
+}
+
+void Assembler::setb(Condition cc, Register dst) {
+  assert(0 <= cc && cc < 16, "illegal cc");
+  int encode = prefix_and_encode(dst->encoding(), true);
+  emit_byte(0x0F);
+  emit_byte(0x90 | cc);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::shll(Register dst, int imm8) {
+  assert(isShiftCount(imm8), "illegal shift count");
+  int encode = prefix_and_encode(dst->encoding());
+  if (imm8 == 1 ) {
+    emit_byte(0xD1);
+    emit_byte(0xE0 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xE0 | encode);
+    emit_byte(imm8);
+  }
+}
+
+void Assembler::shll(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xE0 | encode);
+}
+
+void Assembler::shrl(Register dst, int imm8) {
+  assert(isShiftCount(imm8), "illegal shift count");
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xC1);
+  emit_byte(0xE8 | encode);
+  emit_byte(imm8);
+}
+
+void Assembler::shrl(Register dst) {
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xE8 | encode);
+}
+
+// copies a single word from [esi] to [edi]
+void Assembler::smovl() {
+  emit_byte(0xA5);
+}
+
+void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
+  // HMM Table D-1 says sse2
+  // NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x51);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::stmxcsr( Address dst) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  prefix(dst);
+  emit_byte(0x0F);
+  emit_byte(0xAE);
+  emit_operand(as_Register(3), dst);
+}
+
+void Assembler::subl(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefix(dst);
+  if (is8bit(imm32)) {
+    emit_byte(0x83);
+    emit_operand(rbp, dst, 1);
+    emit_byte(imm32 & 0xFF);
+  } else {
+    emit_byte(0x81);
+    emit_operand(rbp, dst, 4);
+    emit_long(imm32);
+  }
+}
+
+void Assembler::subl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xE8, dst, imm32);
+}
+
+void Assembler::subl(Address dst, Register src) {
+  InstructionMark im(this);
+  prefix(dst, src);
+  emit_byte(0x29);
+  emit_operand(src, dst);
+}
+
+void Assembler::subl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x2B);
+  emit_operand(dst, src);
+}
+
+void Assembler::subl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x2B, 0xC0, dst, src);
+}
+
+void Assembler::subsd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::subsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x5C);
+  emit_operand(dst, src);
+}
+
+void Assembler::subss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x5C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::subss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF3);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x5C);
+  emit_operand(dst, src);
+}
+
+void Assembler::testb(Register dst, int imm8) {
+  NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
+  (void) prefix_and_encode(dst->encoding(), true);
+  emit_arith_b(0xF6, 0xC0, dst, imm8);
+}
+
+void Assembler::testl(Register dst, int32_t imm32) {
+  // not using emit_arith because test
+  // doesn't support sign-extension of
+  // 8bit operands
+  int encode = dst->encoding();
+  if (encode == 0) {
+    emit_byte(0xA9);
+  } else {
+    encode = prefix_and_encode(encode);
+    emit_byte(0xF7);
+    emit_byte(0xC0 | encode);
+  }
+  emit_long(imm32);
+}
+
+void Assembler::testl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x85, 0xC0, dst, src);
+}
+
+void Assembler::testl(Register dst, Address  src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x85);
+  emit_operand(dst, src);
+}
+
+void Assembler::ucomisd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  ucomiss(dst, src);
+}
+
+void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  ucomiss(dst, src);
+}
+
+void Assembler::ucomiss(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x2E);
+  emit_operand(dst, src);
+}
+
+void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2E);
+  emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::xaddl(Address dst, Register src) {
+  InstructionMark im(this);
+  prefix(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0xC1);
+  emit_operand(src, dst);
+}
+
+void Assembler::xchgl(Register dst, Address src) { // xchg
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x87);
+  emit_operand(dst, src);
+}
+
+void Assembler::xchgl(Register dst, Register src) {
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x87);
+  emit_byte(0xc0 | encode);
+}
+
+void Assembler::xorl(Register dst, int32_t imm32) {
+  prefix(dst);
+  emit_arith(0x81, 0xF0, dst, imm32);
+}
+
+void Assembler::xorl(Register dst, Address src) {
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x33);
+  emit_operand(dst, src);
+}
+
+void Assembler::xorl(Register dst, Register src) {
+  (void) prefix_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x33, 0xC0, dst, src);
+}
+
+void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0x66);
+  xorps(dst, src);
+}
+
+void Assembler::xorpd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0x66);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x57);
+  emit_operand(dst, src);
+}
+
+
+void Assembler::xorps(XMMRegister dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  int encode = prefix_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x57);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::xorps(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  InstructionMark im(this);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x57);
+  emit_operand(dst, src);
+}
+
+#ifndef _LP64
+// 32bit only pieces of the assembler
+
+void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
+  // NO PREFIX AS NEVER 64BIT
+  InstructionMark im(this);
+  emit_byte(0x81);
+  emit_byte(0xF8 | src1->encoding());
+  emit_data(imm32, rspec, 0);
+}
+
+void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
+  // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
+  InstructionMark im(this);
+  emit_byte(0x81);
+  emit_operand(rdi, src1);
+  emit_data(imm32, rspec, 0);
+}
+
+// The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
+// and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
+// into rdx:rax.  The ZF is set if the compared values were equal, and cleared otherwise.
+void Assembler::cmpxchg8(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0x0F);
+  emit_byte(0xc7);
+  emit_operand(rcx, adr);
+}
+
+void Assembler::decl(Register dst) {
+  // Don't use it directly. Use MacroAssembler::decrementl() instead.
+ emit_byte(0x48 | dst->encoding());
+}
+
+#endif // _LP64
+
+// 64bit typically doesn't use the x87 but needs to for the trig funcs
+
+void Assembler::fabs() {
+  emit_byte(0xD9);
+  emit_byte(0xE1);
+}
+
+void Assembler::fadd(int i) {
+  emit_farith(0xD8, 0xC0, i);
+}
+
+void Assembler::fadd_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rax, src);
+}
+
+void Assembler::fadd_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rax, src);
+}
+
+void Assembler::fadda(int i) {
+  emit_farith(0xDC, 0xC0, i);
+}
+
+void Assembler::faddp(int i) {
+  emit_farith(0xDE, 0xC0, i);
+}
+
+void Assembler::fchs() {
+  emit_byte(0xD9);
+  emit_byte(0xE0);
+}
+
+void Assembler::fcom(int i) {
+  emit_farith(0xD8, 0xD0, i);
+}
+
+void Assembler::fcomp(int i) {
+  emit_farith(0xD8, 0xD8, i);
+}
+
+void Assembler::fcomp_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rbx, src);
+}
+
+void Assembler::fcomp_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rbx, src);
+}
+
+void Assembler::fcompp() {
+  emit_byte(0xDE);
+  emit_byte(0xD9);
+}
+
+void Assembler::fcos() {
+  emit_byte(0xD9);
+  emit_byte(0xFF);
+}
+
+void Assembler::fdecstp() {
+  emit_byte(0xD9);
+  emit_byte(0xF6);
+}
+
+void Assembler::fdiv(int i) {
+  emit_farith(0xD8, 0xF0, i);
+}
+
+void Assembler::fdiv_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rsi, src);
+}
+
+void Assembler::fdiv_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rsi, src);
+}
+
+void Assembler::fdiva(int i) {
+  emit_farith(0xDC, 0xF8, i);
+}
+
+// Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
+//       is erroneous for some of the floating-point instructions below.
+
+void Assembler::fdivp(int i) {
+  emit_farith(0xDE, 0xF8, i);                    // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
+}
+
+void Assembler::fdivr(int i) {
+  emit_farith(0xD8, 0xF8, i);
+}
+
+void Assembler::fdivr_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rdi, src);
+}
+
+void Assembler::fdivr_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rdi, src);
+}
+
+void Assembler::fdivra(int i) {
+  emit_farith(0xDC, 0xF0, i);
+}
+
+void Assembler::fdivrp(int i) {
+  emit_farith(0xDE, 0xF0, i);                    // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
+}
+
+void Assembler::ffree(int i) {
+  emit_farith(0xDD, 0xC0, i);
+}
+
+void Assembler::fild_d(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDF);
+  emit_operand32(rbp, adr);
+}
+
+void Assembler::fild_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDB);
+  emit_operand32(rax, adr);
+}
+
+void Assembler::fincstp() {
+  emit_byte(0xD9);
+  emit_byte(0xF7);
+}
+
+void Assembler::finit() {
+  emit_byte(0x9B);
+  emit_byte(0xDB);
+  emit_byte(0xE3);
+}
+
+void Assembler::fist_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDB);
+  emit_operand32(rdx, adr);
+}
+
+void Assembler::fistp_d(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDF);
+  emit_operand32(rdi, adr);
+}
+
+void Assembler::fistp_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDB);
+  emit_operand32(rbx, adr);
+}
+
+void Assembler::fld1() {
+  emit_byte(0xD9);
+  emit_byte(0xE8);
+}
+
+void Assembler::fld_d(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDD);
+  emit_operand32(rax, adr);
+}
+
+void Assembler::fld_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xD9);
+  emit_operand32(rax, adr);
+}
+
+
+void Assembler::fld_s(int index) {
+  emit_farith(0xD9, 0xC0, index);
+}
+
+void Assembler::fld_x(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDB);
+  emit_operand32(rbp, adr);
+}
+
+void Assembler::fldcw(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xd9);
+  emit_operand32(rbp, src);
+}
+
+void Assembler::fldenv(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD9);
+  emit_operand32(rsp, src);
+}
+
+void Assembler::fldlg2() {
+  emit_byte(0xD9);
+  emit_byte(0xEC);
+}
+
+void Assembler::fldln2() {
+  emit_byte(0xD9);
+  emit_byte(0xED);
+}
+
+void Assembler::fldz() {
+  emit_byte(0xD9);
+  emit_byte(0xEE);
+}
+
+void Assembler::flog() {
+  fldln2();
+  fxch();
+  fyl2x();
+}
+
+void Assembler::flog10() {
+  fldlg2();
+  fxch();
+  fyl2x();
+}
+
+void Assembler::fmul(int i) {
+  emit_farith(0xD8, 0xC8, i);
+}
+
+void Assembler::fmul_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rcx, src);
+}
+
+void Assembler::fmul_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rcx, src);
+}
+
+void Assembler::fmula(int i) {
+  emit_farith(0xDC, 0xC8, i);
+}
+
+void Assembler::fmulp(int i) {
+  emit_farith(0xDE, 0xC8, i);
+}
+
+void Assembler::fnsave(Address dst) {
+  InstructionMark im(this);
+  emit_byte(0xDD);
+  emit_operand32(rsi, dst);
+}
+
+void Assembler::fnstcw(Address src) {
+  InstructionMark im(this);
+  emit_byte(0x9B);
+  emit_byte(0xD9);
+  emit_operand32(rdi, src);
+}
+
+void Assembler::fnstsw_ax() {
+  emit_byte(0xdF);
+  emit_byte(0xE0);
+}
+
+void Assembler::fprem() {
+  emit_byte(0xD9);
+  emit_byte(0xF8);
+}
+
+void Assembler::fprem1() {
+  emit_byte(0xD9);
+  emit_byte(0xF5);
+}
+
+void Assembler::frstor(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDD);
+  emit_operand32(rsp, src);
+}
+
+void Assembler::fsin() {
+  emit_byte(0xD9);
+  emit_byte(0xFE);
+}
+
+void Assembler::fsqrt() {
+  emit_byte(0xD9);
+  emit_byte(0xFA);
+}
+
+void Assembler::fst_d(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDD);
+  emit_operand32(rdx, adr);
+}
+
+void Assembler::fst_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xD9);
+  emit_operand32(rdx, adr);
+}
+
+void Assembler::fstp_d(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDD);
+  emit_operand32(rbx, adr);
+}
+
+void Assembler::fstp_d(int index) {
+  emit_farith(0xDD, 0xD8, index);
+}
+
+void Assembler::fstp_s(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xD9);
+  emit_operand32(rbx, adr);
+}
+
+void Assembler::fstp_x(Address adr) {
+  InstructionMark im(this);
+  emit_byte(0xDB);
+  emit_operand32(rdi, adr);
+}
+
+void Assembler::fsub(int i) {
+  emit_farith(0xD8, 0xE0, i);
+}
+
+void Assembler::fsub_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rsp, src);
+}
+
+void Assembler::fsub_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rsp, src);
+}
+
+void Assembler::fsuba(int i) {
+  emit_farith(0xDC, 0xE8, i);
+}
+
+void Assembler::fsubp(int i) {
+  emit_farith(0xDE, 0xE8, i);                    // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
+}
+
+void Assembler::fsubr(int i) {
+  emit_farith(0xD8, 0xE8, i);
+}
+
+void Assembler::fsubr_d(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xDC);
+  emit_operand32(rbp, src);
+}
+
+void Assembler::fsubr_s(Address src) {
+  InstructionMark im(this);
+  emit_byte(0xD8);
+  emit_operand32(rbp, src);
+}
+
+void Assembler::fsubra(int i) {
+  emit_farith(0xDC, 0xE0, i);
+}
+
+void Assembler::fsubrp(int i) {
+  emit_farith(0xDE, 0xE0, i);                    // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
+}
+
+void Assembler::ftan() {
+  emit_byte(0xD9);
+  emit_byte(0xF2);
+  emit_byte(0xDD);
+  emit_byte(0xD8);
+}
+
+void Assembler::ftst() {
+  emit_byte(0xD9);
+  emit_byte(0xE4);
+}
+
+void Assembler::fucomi(int i) {
+  // make sure the instruction is supported (introduced for P6, together with cmov)
+  guarantee(VM_Version::supports_cmov(), "illegal instruction");
+  emit_farith(0xDB, 0xE8, i);
+}
+
+void Assembler::fucomip(int i) {
+  // make sure the instruction is supported (introduced for P6, together with cmov)
+  guarantee(VM_Version::supports_cmov(), "illegal instruction");
+  emit_farith(0xDF, 0xE8, i);
+}
+
+void Assembler::fwait() {
+  emit_byte(0x9B);
+}
+
+void Assembler::fxch(int i) {
+  emit_farith(0xD9, 0xC8, i);
+}
+
+void Assembler::fyl2x() {
+  emit_byte(0xD9);
+  emit_byte(0xF1);
+}
+
+void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format) {
+  InstructionMark im(this);
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xB8 | encode);
+  emit_data((int)imm32, rspec, format);
+}
+
+#ifndef _LP64
+
+void Assembler::incl(Register dst) {
+  // Don't use it directly. Use MacroAssembler::incrementl() instead.
+ emit_byte(0x40 | dst->encoding());
+}
+
+void Assembler::lea(Register dst, Address src) {
+  leal(dst, src);
+}
+
+void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
+  InstructionMark im(this);
+  emit_byte(0xC7);
+  emit_operand(rax, dst);
+  emit_data((int)imm32, rspec, 0);
+}
+
+
+void Assembler::popa() { // 32bit
+  emit_byte(0x61);
+}
+
+void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
+  InstructionMark im(this);
+  emit_byte(0x68);
+  emit_data(imm32, rspec, 0);
+}
+
+void Assembler::pusha() { // 32bit
+  emit_byte(0x60);
+}
+
+void Assembler::set_byte_if_not_zero(Register dst) {
+  emit_byte(0x0F);
+  emit_byte(0x95);
+  emit_byte(0xE0 | dst->encoding());
+}
+
+void Assembler::shldl(Register dst, Register src) {
+  emit_byte(0x0F);
+  emit_byte(0xA5);
+  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
+}
+
+void Assembler::shrdl(Register dst, Register src) {
+  emit_byte(0x0F);
+  emit_byte(0xAD);
+  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
+}
+
+#else // LP64
+
+// 64bit only pieces of the assembler
+// This should only be used by 64bit instructions that can use rip-relative
+// it cannot be used by instructions that want an immediate value.
+
+bool Assembler::reachable(AddressLiteral adr) {
+  int64_t disp;
+  // None will force a 64bit literal to the code stream. Likely a placeholder
+  // for something that will be patched later and we need to certain it will
+  // always be reachable.
+  if (adr.reloc() == relocInfo::none) {
+    return false;
+  }
+  if (adr.reloc() == relocInfo::internal_word_type) {
+    // This should be rip relative and easily reachable.
+    return true;
+  }
+  if (adr.reloc() == relocInfo::virtual_call_type ||
+      adr.reloc() == relocInfo::opt_virtual_call_type ||
+      adr.reloc() == relocInfo::static_call_type ||
+      adr.reloc() == relocInfo::static_stub_type ) {
+    // This should be rip relative within the code cache and easily
+    // reachable until we get huge code caches. (At which point
+    // ic code is going to have issues).
+    return true;
+  }
+  if (adr.reloc() != relocInfo::external_word_type &&
+      adr.reloc() != relocInfo::poll_return_type &&  // these are really external_word but need special
+      adr.reloc() != relocInfo::poll_type &&         // relocs to identify them
+      adr.reloc() != relocInfo::runtime_call_type ) {
+    return false;
+  }
+
+  // Stress the correction code
+  if (ForceUnreachable) {
+    // Must be runtimecall reloc, see if it is in the codecache
+    // Flipping stuff in the codecache to be unreachable causes issues
+    // with things like inline caches where the additional instructions
+    // are not handled.
+    if (CodeCache::find_blob(adr._target) == NULL) {
+      return false;
+    }
+  }
+  // For external_word_type/runtime_call_type if it is reachable from where we
+  // are now (possibly a temp buffer) and where we might end up
+  // anywhere in the codeCache then we are always reachable.
+  // This would have to change if we ever save/restore shared code
+  // to be more pessimistic.
+
+  disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
+  if (!is_simm32(disp)) return false;
+  disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
+  if (!is_simm32(disp)) return false;
+
+  disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
+
+  // Because rip relative is a disp + address_of_next_instruction and we
+  // don't know the value of address_of_next_instruction we apply a fudge factor
+  // to make sure we will be ok no matter the size of the instruction we get placed into.
+  // We don't have to fudge the checks above here because they are already worst case.
+
+  // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
+  // + 4 because better safe than sorry.
+  const int fudge = 12 + 4;
+  if (disp < 0) {
+    disp -= fudge;
+  } else {
+    disp += fudge;
+  }
+  return is_simm32(disp);
+}
+
+void Assembler::emit_data64(jlong data,
+                            relocInfo::relocType rtype,
+                            int format) {
+  if (rtype == relocInfo::none) {
+    emit_long64(data);
+  } else {
+    emit_data64(data, Relocation::spec_simple(rtype), format);
+  }
+}
+
+void Assembler::emit_data64(jlong data,
+                            RelocationHolder const& rspec,
+                            int format) {
+  assert(imm_operand == 0, "default format must be immediate in this file");
+  assert(imm_operand == format, "must be immediate");
+  assert(inst_mark() != NULL, "must be inside InstructionMark");
+  // Do not use AbstractAssembler::relocate, which is not intended for
+  // embedded words.  Instead, relocate to the enclosing instruction.
+  code_section()->relocate(inst_mark(), rspec, format);
+#ifdef ASSERT
+  check_relocation(rspec, format);
+#endif
+  emit_long64(data);
+}
+
+int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
+  if (reg_enc >= 8) {
+    prefix(REX_B);
+    reg_enc -= 8;
+  } else if (byteinst && reg_enc >= 4) {
+    prefix(REX);
+  }
+  return reg_enc;
+}
+
+int Assembler::prefixq_and_encode(int reg_enc) {
+  if (reg_enc < 8) {
+    prefix(REX_W);
+  } else {
+    prefix(REX_WB);
+    reg_enc -= 8;
+  }
+  return reg_enc;
+}
+
+int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
+  if (dst_enc < 8) {
+    if (src_enc >= 8) {
+      prefix(REX_B);
+      src_enc -= 8;
+    } else if (byteinst && src_enc >= 4) {
+      prefix(REX);
+    }
+  } else {
+    if (src_enc < 8) {
+      prefix(REX_R);
+    } else {
+      prefix(REX_RB);
+      src_enc -= 8;
+    }
+    dst_enc -= 8;
+  }
+  return dst_enc << 3 | src_enc;
+}
+
+int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
+  if (dst_enc < 8) {
+    if (src_enc < 8) {
+      prefix(REX_W);
+    } else {
+      prefix(REX_WB);
+      src_enc -= 8;
+    }
+  } else {
+    if (src_enc < 8) {
+      prefix(REX_WR);
+    } else {
+      prefix(REX_WRB);
+      src_enc -= 8;
+    }
+    dst_enc -= 8;
+  }
+  return dst_enc << 3 | src_enc;
+}
+
+void Assembler::prefix(Register reg) {
+  if (reg->encoding() >= 8) {
+    prefix(REX_B);
+  }
+}
+
+void Assembler::prefix(Address adr) {
+  if (adr.base_needs_rex()) {
+    if (adr.index_needs_rex()) {
+      prefix(REX_XB);
+    } else {
+      prefix(REX_B);
+    }
+  } else {
+    if (adr.index_needs_rex()) {
+      prefix(REX_X);
+    }
+  }
+}
+
+void Assembler::prefixq(Address adr) {
+  if (adr.base_needs_rex()) {
+    if (adr.index_needs_rex()) {
+      prefix(REX_WXB);
+    } else {
+      prefix(REX_WB);
+    }
+  } else {
+    if (adr.index_needs_rex()) {
+      prefix(REX_WX);
+    } else {
+      prefix(REX_W);
+    }
+  }
+}
+
+
+void Assembler::prefix(Address adr, Register reg, bool byteinst) {
+  if (reg->encoding() < 8) {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_XB);
+      } else {
+        prefix(REX_B);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_X);
+      } else if (reg->encoding() >= 4 ) {
+        prefix(REX);
+      }
+    }
+  } else {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_RXB);
+      } else {
+        prefix(REX_RB);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_RX);
+      } else {
+        prefix(REX_R);
+      }
+    }
+  }
+}
+
+void Assembler::prefixq(Address adr, Register src) {
+  if (src->encoding() < 8) {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_WXB);
+      } else {
+        prefix(REX_WB);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_WX);
+      } else {
+        prefix(REX_W);
+      }
+    }
+  } else {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_WRXB);
+      } else {
+        prefix(REX_WRB);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_WRX);
+      } else {
+        prefix(REX_WR);
+      }
+    }
+  }
+}
+
+void Assembler::prefix(Address adr, XMMRegister reg) {
+  if (reg->encoding() < 8) {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_XB);
+      } else {
+        prefix(REX_B);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_X);
+      }
+    }
+  } else {
+    if (adr.base_needs_rex()) {
+      if (adr.index_needs_rex()) {
+        prefix(REX_RXB);
+      } else {
+        prefix(REX_RB);
+      }
+    } else {
+      if (adr.index_needs_rex()) {
+        prefix(REX_RX);
+      } else {
+        prefix(REX_R);
+      }
+    }
+  }
+}
+
+void Assembler::adcq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xD0, dst, imm32);
+}
+
+void Assembler::adcq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x13);
+  emit_operand(dst, src);
+}
+
+void Assembler::adcq(Register dst, Register src) {
+  (int) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x13, 0xC0, dst, src);
+}
+
+void Assembler::addq(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_arith_operand(0x81, rax, dst,imm32);
+}
+
+void Assembler::addq(Address dst, Register src) {
+  InstructionMark im(this);
+  prefixq(dst, src);
+  emit_byte(0x01);
+  emit_operand(src, dst);
+}
+
+void Assembler::addq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xC0, dst, imm32);
+}
+
+void Assembler::addq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x03);
+  emit_operand(dst, src);
+}
+
+void Assembler::addq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x03, 0xC0, dst, src);
+}
+
+void Assembler::andq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xE0, dst, imm32);
+}
+
+void Assembler::andq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x23);
+  emit_operand(dst, src);
+}
+
+void Assembler::andq(Register dst, Register src) {
+  (int) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x23, 0xC0, dst, src);
+}
+
+void Assembler::bswapq(Register reg) {
+  int encode = prefixq_and_encode(reg->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xC8 | encode);
+}
+
+void Assembler::cdqq() {
+  prefix(REX_W);
+  emit_byte(0x99);
+}
+
+void Assembler::clflush(Address adr) {
+  prefix(adr);
+  emit_byte(0x0F);
+  emit_byte(0xAE);
+  emit_operand(rdi, adr);
+}
+
+void Assembler::cmovq(Condition cc, Register dst, Register src) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x40 | cc);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cmovq(Condition cc, Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x40 | cc);
+  emit_operand(dst, src);
+}
+
+void Assembler::cmpq(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0x81);
+  emit_operand(rdi, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::cmpq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xF8, dst, imm32);
+}
+
+void Assembler::cmpq(Address dst, Register src) {
+  InstructionMark im(this);
+  prefixq(dst, src);
+  emit_byte(0x3B);
+  emit_operand(src, dst);
+}
+
+void Assembler::cmpq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x3B, 0xC0, dst, src);
+}
+
+void Assembler::cmpq(Register dst, Address  src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x3B);
+  emit_operand(dst, src);
+}
+
+void Assembler::cmpxchgq(Register reg, Address adr) {
+  InstructionMark im(this);
+  prefixq(adr, reg);
+  emit_byte(0x0F);
+  emit_byte(0xB1);
+  emit_operand(reg, adr);
+}
+
+void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2A);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  emit_byte(0xF2);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttss2siq(Register dst, XMMRegister src) {
+  NOT_LP64(assert(VM_Version::supports_sse(), ""));
+  emit_byte(0xF3);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x2C);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::decl(Register dst) {
+  // Don't use it directly. Use MacroAssembler::decrementl() instead.
+  // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xFF);
+  emit_byte(0xC8 | encode);
+}
+
+void Assembler::decq(Register dst) {
+  // Don't use it directly. Use MacroAssembler::decrementq() instead.
+  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xFF);
+  emit_byte(0xC8 | encode);
+}
+
+void Assembler::decq(Address dst) {
+  // Don't use it directly. Use MacroAssembler::decrementq() instead.
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0xFF);
+  emit_operand(rcx, dst);
+}
+
+void Assembler::fxrstor(Address src) {
+  prefixq(src);
+  emit_byte(0x0F);
+  emit_byte(0xAE);
+  emit_operand(as_Register(1), src);
+}
+
+void Assembler::fxsave(Address dst) {
+  prefixq(dst);
+  emit_byte(0x0F);
+  emit_byte(0xAE);
+  emit_operand(as_Register(0), dst);
+}
+
+void Assembler::idivq(Register src) {
+  int encode = prefixq_and_encode(src->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xF8 | encode);
+}
+
+void Assembler::imulq(Register dst, Register src) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0xAF);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::imulq(Register dst, Register src, int value) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  if (is8bit(value)) {
+    emit_byte(0x6B);
+    emit_byte(0xC0 | encode);
+    emit_byte(value);
+  } else {
+    emit_byte(0x69);
+    emit_byte(0xC0 | encode);
+    emit_long(value);
+  }
+}
+
+void Assembler::incl(Register dst) {
+  // Don't use it directly. Use MacroAssembler::incrementl() instead.
+  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
+  int encode = prefix_and_encode(dst->encoding());
+  emit_byte(0xFF);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::incq(Register dst) {
+  // Don't use it directly. Use MacroAssembler::incrementq() instead.
+  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xFF);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::incq(Address dst) {
+  // Don't use it directly. Use MacroAssembler::incrementq() instead.
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0xFF);
+  emit_operand(rax, dst);
+}
+
+void Assembler::lea(Register dst, Address src) {
+  leaq(dst, src);
+}
+
+void Assembler::leaq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x8D);
+  emit_operand(dst, src);
+}
+
+void Assembler::mov64(Register dst, int64_t imm64) {
+  InstructionMark im(this);
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xB8 | encode);
+  emit_long64(imm64);
+}
+
+void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
+  InstructionMark im(this);
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xB8 | encode);
+  emit_data64(imm64, rspec);
+}
+
+void Assembler::movdq(XMMRegister dst, Register src) {
+  // table D-1 says MMX/SSE2
+  NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
+  emit_byte(0x66);
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x6E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdq(Register dst, XMMRegister src) {
+  // table D-1 says MMX/SSE2
+  NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
+  emit_byte(0x66);
+  // swap src/dst to get correct prefix
+  int encode = prefixq_and_encode(src->encoding(), dst->encoding());
+  emit_byte(0x0F);
+  emit_byte(0x7E);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movq(Register dst, Register src) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x8B);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::movq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x8B);
+  emit_operand(dst, src);
+}
+
+void Assembler::movq(Address dst, Register src) {
+  InstructionMark im(this);
+  prefixq(dst, src);
+  emit_byte(0x89);
+  emit_operand(src, dst);
+}
+
+void Assembler::movslq(Register dst, int32_t imm32) {
+  // dbx shows movslq(rcx, 3) as movq     $0x0000000049000000,(%rbx)
+  // and movslq(r8, 3); as movl     $0x0000000048000000,(%rbx)
+  // as a result we shouldn't use until tested at runtime...
+  ShouldNotReachHere();
+  InstructionMark im(this);
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xC7 | encode);
+  emit_long(imm32);
+}
+
+void Assembler::movslq(Address dst, int32_t imm32) {
+  assert(is_simm32(imm32), "lost bits");
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0xC7);
+  emit_operand(rax, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::movslq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x63);
+  emit_operand(dst, src);
+}
+
+void Assembler::movslq(Register dst, Register src) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x63);
+  emit_byte(0xC0 | encode);
+}
+
+void Assembler::negq(Register dst) {
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xD8 | encode);
+}
+
+void Assembler::notq(Register dst) {
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xF7);
+  emit_byte(0xD0 | encode);
+}
+
+void Assembler::orq(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0x81);
+  emit_operand(rcx, dst, 4);
+  emit_long(imm32);
+}
+
+void Assembler::orq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xC8, dst, imm32);
+}
+
+void Assembler::orq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x0B);
+  emit_operand(dst, src);
+}
+
+void Assembler::orq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x0B, 0xC0, dst, src);
+}
+
+void Assembler::popa() { // 64bit
+  movq(r15, Address(rsp, 0));
+  movq(r14, Address(rsp, wordSize));
+  movq(r13, Address(rsp, 2 * wordSize));
+  movq(r12, Address(rsp, 3 * wordSize));
+  movq(r11, Address(rsp, 4 * wordSize));
+  movq(r10, Address(rsp, 5 * wordSize));
+  movq(r9,  Address(rsp, 6 * wordSize));
+  movq(r8,  Address(rsp, 7 * wordSize));
+  movq(rdi, Address(rsp, 8 * wordSize));
+  movq(rsi, Address(rsp, 9 * wordSize));
+  movq(rbp, Address(rsp, 10 * wordSize));
+  // skip rsp
+  movq(rbx, Address(rsp, 12 * wordSize));
+  movq(rdx, Address(rsp, 13 * wordSize));
+  movq(rcx, Address(rsp, 14 * wordSize));
+  movq(rax, Address(rsp, 15 * wordSize));
+
+  addq(rsp, 16 * wordSize);
+}
+
+void Assembler::popq(Address dst) {
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_byte(0x8F);
+  emit_operand(rax, dst);
+}
+
+void Assembler::pusha() { // 64bit
+  // we have to store original rsp.  ABI says that 128 bytes
+  // below rsp are local scratch.
+  movq(Address(rsp, -5 * wordSize), rsp);
+
+  subq(rsp, 16 * wordSize);
+
+  movq(Address(rsp, 15 * wordSize), rax);
+  movq(Address(rsp, 14 * wordSize), rcx);
+  movq(Address(rsp, 13 * wordSize), rdx);
+  movq(Address(rsp, 12 * wordSize), rbx);
+  // skip rsp
+  movq(Address(rsp, 10 * wordSize), rbp);
+  movq(Address(rsp, 9 * wordSize), rsi);
+  movq(Address(rsp, 8 * wordSize), rdi);
+  movq(Address(rsp, 7 * wordSize), r8);
+  movq(Address(rsp, 6 * wordSize), r9);
+  movq(Address(rsp, 5 * wordSize), r10);
+  movq(Address(rsp, 4 * wordSize), r11);
+  movq(Address(rsp, 3 * wordSize), r12);
+  movq(Address(rsp, 2 * wordSize), r13);
+  movq(Address(rsp, wordSize), r14);
+  movq(Address(rsp, 0), r15);
+}
+
+void Assembler::pushq(Address src) {
+  InstructionMark im(this);
+  prefixq(src);
+  emit_byte(0xFF);
+  emit_operand(rsi, src);
+}
+
+void Assembler::rclq(Register dst, int imm8) {
+  assert(isShiftCount(imm8 >> 1), "illegal shift count");
+  int encode = prefixq_and_encode(dst->encoding());
+  if (imm8 == 1) {
+    emit_byte(0xD1);
+    emit_byte(0xD0 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xD0 | encode);
+    emit_byte(imm8);
+  }
+}
+void Assembler::sarq(Register dst, int imm8) {
+  assert(isShiftCount(imm8 >> 1), "illegal shift count");
+  int encode = prefixq_and_encode(dst->encoding());
+  if (imm8 == 1) {
+    emit_byte(0xD1);
+    emit_byte(0xF8 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xF8 | encode);
+    emit_byte(imm8);
+  }
+}
+
+void Assembler::sarq(Register dst) {
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xF8 | encode);
+}
+void Assembler::sbbq(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefixq(dst);
+  emit_arith_operand(0x81, rbx, dst, imm32);
+}
+
+void Assembler::sbbq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xD8, dst, imm32);
+}
+
+void Assembler::sbbq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x1B);
+  emit_operand(dst, src);
+}
+
+void Assembler::sbbq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x1B, 0xC0, dst, src);
+}
+
+void Assembler::shlq(Register dst, int imm8) {
+  assert(isShiftCount(imm8 >> 1), "illegal shift count");
+  int encode = prefixq_and_encode(dst->encoding());
+  if (imm8 == 1) {
+    emit_byte(0xD1);
+    emit_byte(0xE0 | encode);
+  } else {
+    emit_byte(0xC1);
+    emit_byte(0xE0 | encode);
+    emit_byte(imm8);
+  }
+}
+
+void Assembler::shlq(Register dst) {
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xE0 | encode);
+}
+
+void Assembler::shrq(Register dst, int imm8) {
+  assert(isShiftCount(imm8 >> 1), "illegal shift count");
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xC1);
+  emit_byte(0xE8 | encode);
+  emit_byte(imm8);
+}
+
+void Assembler::shrq(Register dst) {
+  int encode = prefixq_and_encode(dst->encoding());
+  emit_byte(0xD3);
+  emit_byte(0xE8 | encode);
+}
+
+void Assembler::sqrtsd(XMMRegister dst, Address src) {
+  NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+  InstructionMark im(this);
+  emit_byte(0xF2);
+  prefix(src, dst);
+  emit_byte(0x0F);
+  emit_byte(0x51);
+  emit_operand(dst, src);
+}
+
+void Assembler::subq(Address dst, int32_t imm32) {
+  InstructionMark im(this);
+  prefixq(dst);
+  if (is8bit(imm32)) {
+    emit_byte(0x83);
+    emit_operand(rbp, dst, 1);
+    emit_byte(imm32 & 0xFF);
+  } else {
+    emit_byte(0x81);
+    emit_operand(rbp, dst, 4);
+    emit_long(imm32);
+  }
+}
+
+void Assembler::subq(Register dst, int32_t imm32) {
+  (void) prefixq_and_encode(dst->encoding());
+  emit_arith(0x81, 0xE8, dst, imm32);
+}
+
+void Assembler::subq(Address dst, Register src) {
+  InstructionMark im(this);
+  prefixq(dst, src);
+  emit_byte(0x29);
+  emit_operand(src, dst);
+}
+
+void Assembler::subq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x2B);
+  emit_operand(dst, src);
+}
+
+void Assembler::subq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x2B, 0xC0, dst, src);
+}
+
+void Assembler::testq(Register dst, int32_t imm32) {
+  // not using emit_arith because test
+  // doesn't support sign-extension of
+  // 8bit operands
+  int encode = dst->encoding();
+  if (encode == 0) {
+    prefix(REX_W);
+    emit_byte(0xA9);
+  } else {
+    encode = prefixq_and_encode(encode);
+    emit_byte(0xF7);
+    emit_byte(0xC0 | encode);
+  }
+  emit_long(imm32);
+}
+
+void Assembler::testq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x85, 0xC0, dst, src);
+}
+
+void Assembler::xaddq(Address dst, Register src) {
+  InstructionMark im(this);
+  prefixq(dst, src);
+  emit_byte(0x0F);
+  emit_byte(0xC1);
+  emit_operand(src, dst);
+}
+
+void Assembler::xchgq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x87);
+  emit_operand(dst, src);
+}
+
+void Assembler::xchgq(Register dst, Register src) {
+  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_byte(0x87);
+  emit_byte(0xc0 | encode);
+}
+
+void Assembler::xorq(Register dst, Register src) {
+  (void) prefixq_and_encode(dst->encoding(), src->encoding());
+  emit_arith(0x33, 0xC0, dst, src);
+}
+
+void Assembler::xorq(Register dst, Address src) {
+  InstructionMark im(this);
+  prefixq(src, dst);
+  emit_byte(0x33);
+  emit_operand(dst, src);
+}
+
+#endif // !LP64
+
+static Assembler::Condition reverse[] = {
+    Assembler::noOverflow     /* overflow      = 0x0 */ ,
+    Assembler::overflow       /* noOverflow    = 0x1 */ ,
+    Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
+    Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
+    Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
+    Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
+    Assembler::above          /* belowEqual    = 0x6 */ ,
+    Assembler::belowEqual     /* above         = 0x7 */ ,
+    Assembler::positive       /* negative      = 0x8 */ ,
+    Assembler::negative       /* positive      = 0x9 */ ,
+    Assembler::noParity       /* parity        = 0xa */ ,
+    Assembler::parity         /* noParity      = 0xb */ ,
+    Assembler::greaterEqual   /* less          = 0xc */ ,
+    Assembler::less           /* greaterEqual  = 0xd */ ,
+    Assembler::greater        /* lessEqual     = 0xe */ ,
+    Assembler::lessEqual      /* greater       = 0xf, */
+
+};
+
+
+// Implementation of MacroAssembler
+
+// First all the versions that have distinct versions depending on 32/64 bit
+// Unless the difference is trivial (1 line or so).
+
+#ifndef _LP64
+
+// 32bit versions
+
+Address MacroAssembler::as_Address(AddressLiteral adr) {
+  return Address(adr.target(), adr.rspec());
+}
+
+Address MacroAssembler::as_Address(ArrayAddress adr) {
+  return Address::make_array(adr);
+}
+
+int MacroAssembler::biased_locking_enter(Register lock_reg,
+                                         Register obj_reg,
+                                         Register swap_reg,
+                                         Register tmp_reg,
+                                         bool swap_reg_contains_mark,
+                                         Label& done,
+                                         Label* slow_case,
+                                         BiasedLockingCounters* counters) {
+  assert(UseBiasedLocking, "why call this otherwise?");
+  assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
+  assert_different_registers(lock_reg, obj_reg, swap_reg);
+
+  if (PrintBiasedLockingStatistics && counters == NULL)
+    counters = BiasedLocking::counters();
+
+  bool need_tmp_reg = false;
+  if (tmp_reg == noreg) {
+    need_tmp_reg = true;
+    tmp_reg = lock_reg;
+  } else {
+    assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
+  }
+  assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
+  Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
+  Address klass_addr     (obj_reg, oopDesc::klass_offset_in_bytes());
+  Address saved_mark_addr(lock_reg, 0);
+
+  // Biased locking
+  // See whether the lock is currently biased toward our thread and
+  // whether the epoch is still valid
+  // Note that the runtime guarantees sufficient alignment of JavaThread
+  // pointers to allow age to be placed into low bits
+  // First check to see whether biasing is even enabled for this object
+  Label cas_label;
+  int null_check_offset = -1;
+  if (!swap_reg_contains_mark) {
+    null_check_offset = offset();
+    movl(swap_reg, mark_addr);
+  }
+  if (need_tmp_reg) {
+    push(tmp_reg);
+  }
+  movl(tmp_reg, swap_reg);
+  andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
+  cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
+  if (need_tmp_reg) {
+    pop(tmp_reg);
+  }
+  jcc(Assembler::notEqual, cas_label);
+  // The bias pattern is present in the object's header. Need to check
+  // whether the bias owner and the epoch are both still current.
+  // Note that because there is no current thread register on x86 we
+  // need to store off the mark word we read out of the object to
+  // avoid reloading it and needing to recheck invariants below. This
+  // store is unfortunate but it makes the overall code shorter and
+  // simpler.
+  movl(saved_mark_addr, swap_reg);
+  if (need_tmp_reg) {
+    push(tmp_reg);
+  }
+  get_thread(tmp_reg);
+  xorl(swap_reg, tmp_reg);
+  if (swap_reg_contains_mark) {
+    null_check_offset = offset();
+  }
+  movl(tmp_reg, klass_addr);
+  xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+  andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
+  if (need_tmp_reg) {
+    pop(tmp_reg);
+  }
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address)counters->biased_lock_entry_count_addr()));
+  }
+  jcc(Assembler::equal, done);
+
+  Label try_revoke_bias;
+  Label try_rebias;
+
+  // At this point we know that the header has the bias pattern and
+  // that we are not the bias owner in the current epoch. We need to
+  // figure out more details about the state of the header in order to
+  // know what operations can be legally performed on the object's
+  // header.
+
+  // If the low three bits in the xor result aren't clear, that means
+  // the prototype header is no longer biased and we have to revoke
+  // the bias on this object.
+  testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
+  jcc(Assembler::notZero, try_revoke_bias);
+
+  // Biasing is still enabled for this data type. See whether the
+  // epoch of the current bias is still valid, meaning that the epoch
+  // bits of the mark word are equal to the epoch bits of the
+  // prototype header. (Note that the prototype header's epoch bits
+  // only change at a safepoint.) If not, attempt to rebias the object
+  // toward the current thread. Note that we must be absolutely sure
+  // that the current epoch is invalid in order to do this because
+  // otherwise the manipulations it performs on the mark word are
+  // illegal.
+  testl(swap_reg, markOopDesc::epoch_mask_in_place);
+  jcc(Assembler::notZero, try_rebias);
+
+  // The epoch of the current bias is still valid but we know nothing
+  // about the owner; it might be set or it might be clear. Try to
+  // acquire the bias of the object using an atomic operation. If this
+  // fails we will go in to the runtime to revoke the object's bias.
+  // Note that we first construct the presumed unbiased header so we
+  // don't accidentally blow away another thread's valid bias.
+  movl(swap_reg, saved_mark_addr);
+  andl(swap_reg,
+       markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
+  if (need_tmp_reg) {
+    push(tmp_reg);
+  }
+  get_thread(tmp_reg);
+  orl(tmp_reg, swap_reg);
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+  if (need_tmp_reg) {
+    pop(tmp_reg);
+  }
+  // If the biasing toward our thread failed, this means that
+  // another thread succeeded in biasing it toward itself and we
+  // need to revoke that bias. The revocation will occur in the
+  // interpreter runtime in the slow case.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
+  }
+  if (slow_case != NULL) {
+    jcc(Assembler::notZero, *slow_case);
+  }
+  jmp(done);
+
+  bind(try_rebias);
+  // At this point we know the epoch has expired, meaning that the
+  // current "bias owner", if any, is actually invalid. Under these
+  // circumstances _only_, we are allowed to use the current header's
+  // value as the comparison value when doing the cas to acquire the
+  // bias in the current epoch. In other words, we allow transfer of
+  // the bias from one thread to another directly in this situation.
+  //
+  // FIXME: due to a lack of registers we currently blow away the age
+  // bits in this situation. Should attempt to preserve them.
+  if (need_tmp_reg) {
+    push(tmp_reg);
+  }
+  get_thread(tmp_reg);
+  movl(swap_reg, klass_addr);
+  orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+  movl(swap_reg, saved_mark_addr);
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+  if (need_tmp_reg) {
+    pop(tmp_reg);
+  }
+  // If the biasing toward our thread failed, then another thread
+  // succeeded in biasing it toward itself and we need to revoke that
+  // bias. The revocation will occur in the runtime in the slow case.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
+  }
+  if (slow_case != NULL) {
+    jcc(Assembler::notZero, *slow_case);
+  }
+  jmp(done);
+
+  bind(try_revoke_bias);
+  // The prototype mark in the klass doesn't have the bias bit set any
+  // more, indicating that objects of this data type are not supposed
+  // to be biased any more. We are going to try to reset the mark of
+  // this object to the prototype value and fall through to the
+  // CAS-based locking scheme. Note that if our CAS fails, it means
+  // that another thread raced us for the privilege of revoking the
+  // bias of this particular object, so it's okay to continue in the
+  // normal locking code.
+  //
+  // FIXME: due to a lack of registers we currently blow away the age
+  // bits in this situation. Should attempt to preserve them.
+  movl(swap_reg, saved_mark_addr);
+  if (need_tmp_reg) {
+    push(tmp_reg);
+  }
+  movl(tmp_reg, klass_addr);
+  movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+  if (need_tmp_reg) {
+    pop(tmp_reg);
+  }
+  // Fall through to the normal CAS-based lock, because no matter what
+  // the result of the above CAS, some thread must have succeeded in
+  // removing the bias bit from the object's header.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
+  }
+
+  bind(cas_label);
+
+  return null_check_offset;
+}
+void MacroAssembler::call_VM_leaf_base(address entry_point,
+                                       int number_of_arguments) {
+  call(RuntimeAddress(entry_point));
+  increment(rsp, number_of_arguments * wordSize);
+}
+
+void MacroAssembler::cmpoop(Address src1, jobject obj) {
+  cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::cmpoop(Register src1, jobject obj) {
+  cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::extend_sign(Register hi, Register lo) {
+  // According to Intel Doc. AP-526, "Integer Divide", p.18.
+  if (VM_Version::is_P6() && hi == rdx && lo == rax) {
+    cdql();
+  } else {
+    movl(hi, lo);
+    sarl(hi, 31);
+  }
+}
+
+void MacroAssembler::fat_nop() {
+  // A 5 byte nop that is safe for patching (see patch_verified_entry)
+  emit_byte(0x26); // es:
+  emit_byte(0x2e); // cs:
+  emit_byte(0x64); // fs:
+  emit_byte(0x65); // gs:
+  emit_byte(0x90);
+}
+
+void MacroAssembler::jC2(Register tmp, Label& L) {
+  // set parity bit if FPU flag C2 is set (via rax)
+  save_rax(tmp);
+  fwait(); fnstsw_ax();
+  sahf();
+  restore_rax(tmp);
+  // branch
+  jcc(Assembler::parity, L);
+}
+
+void MacroAssembler::jnC2(Register tmp, Label& L) {
+  // set parity bit if FPU flag C2 is set (via rax)
+  save_rax(tmp);
+  fwait(); fnstsw_ax();
+  sahf();
+  restore_rax(tmp);
+  // branch
+  jcc(Assembler::noParity, L);
+}
+
+// 32bit can do a case table jump in one instruction but we no longer allow the base
+// to be installed in the Address class
+void MacroAssembler::jump(ArrayAddress entry) {
+  jmp(as_Address(entry));
+}
+
+// Note: y_lo will be destroyed
+void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
+  // Long compare for Java (semantics as described in JVM spec.)
+  Label high, low, done;
+
+  cmpl(x_hi, y_hi);
+  jcc(Assembler::less, low);
+  jcc(Assembler::greater, high);
+  // x_hi is the return register
+  xorl(x_hi, x_hi);
+  cmpl(x_lo, y_lo);
+  jcc(Assembler::below, low);
+  jcc(Assembler::equal, done);
+
+  bind(high);
+  xorl(x_hi, x_hi);
+  increment(x_hi);
+  jmp(done);
+
+  bind(low);
+  xorl(x_hi, x_hi);
+  decrementl(x_hi);
+
+  bind(done);
+}
+
+void MacroAssembler::lea(Register dst, AddressLiteral src) {
+    mov_literal32(dst, (int32_t)src.target(), src.rspec());
+}
+
+void MacroAssembler::lea(Address dst, AddressLiteral adr) {
+  // leal(dst, as_Address(adr));
+  // see note in movl as to why we must use a move
+  mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
+}
+
+void MacroAssembler::leave() {
+  mov(rsp, rbp);
+  pop(rbp);
+}
+
+void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
+  // Multiplication of two Java long values stored on the stack
+  // as illustrated below. Result is in rdx:rax.
+  //
+  // rsp ---> [  ??  ] \               \
+  //            ....    | y_rsp_offset  |
+  //          [ y_lo ] /  (in bytes)    | x_rsp_offset
+  //          [ y_hi ]                  | (in bytes)
+  //            ....                    |
+  //          [ x_lo ]                 /
+  //          [ x_hi ]
+  //            ....
+  //
+  // Basic idea: lo(result) = lo(x_lo * y_lo)
+  //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
+  Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
+  Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
+  Label quick;
+  // load x_hi, y_hi and check if quick
+  // multiplication is possible
+  movl(rbx, x_hi);
+  movl(rcx, y_hi);
+  movl(rax, rbx);
+  orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
+  jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
+  // do full multiplication
+  // 1st step
+  mull(y_lo);                                    // x_hi * y_lo
+  movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
+  // 2nd step
+  movl(rax, x_lo);
+  mull(rcx);                                     // x_lo * y_hi
+  addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
+  // 3rd step
+  bind(quick);                                   // note: rbx, = 0 if quick multiply!
+  movl(rax, x_lo);
+  mull(y_lo);                                    // x_lo * y_lo
+  addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
+}
+
+void MacroAssembler::lneg(Register hi, Register lo) {
+  negl(lo);
+  adcl(hi, 0);
+  negl(hi);
+}
+
+void MacroAssembler::lshl(Register hi, Register lo) {
+  // Java shift left long support (semantics as described in JVM spec., p.305)
+  // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
+  // shift value is in rcx !
+  assert(hi != rcx, "must not use rcx");
+  assert(lo != rcx, "must not use rcx");
+  const Register s = rcx;                        // shift count
+  const int      n = BitsPerWord;
+  Label L;
+  andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
+  cmpl(s, n);                                    // if (s < n)
+  jcc(Assembler::less, L);                       // else (s >= n)
+  movl(hi, lo);                                  // x := x << n
+  xorl(lo, lo);
+  // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
+  bind(L);                                       // s (mod n) < n
+  shldl(hi, lo);                                 // x := x << s
+  shll(lo);
+}
+
+
+void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
+  // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
+  // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
+  assert(hi != rcx, "must not use rcx");
+  assert(lo != rcx, "must not use rcx");
+  const Register s = rcx;                        // shift count
+  const int      n = BitsPerWord;
+  Label L;
+  andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
+  cmpl(s, n);                                    // if (s < n)
+  jcc(Assembler::less, L);                       // else (s >= n)
+  movl(lo, hi);                                  // x := x >> n
+  if (sign_extension) sarl(hi, 31);
+  else                xorl(hi, hi);
+  // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
+  bind(L);                                       // s (mod n) < n
+  shrdl(lo, hi);                                 // x := x >> s
+  if (sign_extension) sarl(hi);
+  else                shrl(hi);
+}
+
+void MacroAssembler::movoop(Register dst, jobject obj) {
+  mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::movoop(Address dst, jobject obj) {
+  mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::movptr(Register dst, AddressLiteral src) {
+  if (src.is_lval()) {
+    mov_literal32(dst, (intptr_t)src.target(), src.rspec());
+  } else {
+    movl(dst, as_Address(src));
+  }
+}
+
+void MacroAssembler::movptr(ArrayAddress dst, Register src) {
+  movl(as_Address(dst), src);
+}
+
+void MacroAssembler::movptr(Register dst, ArrayAddress src) {
+  movl(dst, as_Address(src));
+}
+
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Address dst, intptr_t src) {
+  movl(dst, src);
+}
+
+
+void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
+  movsd(dst, as_Address(src));
+}
+
+void MacroAssembler::pop_callee_saved_registers() {
+  pop(rcx);
+  pop(rdx);
+  pop(rdi);
+  pop(rsi);
+}
+
+void MacroAssembler::pop_fTOS() {
+  fld_d(Address(rsp, 0));
+  addl(rsp, 2 * wordSize);
+}
+
+void MacroAssembler::push_callee_saved_registers() {
+  push(rsi);
+  push(rdi);
+  push(rdx);
+  push(rcx);
+}
+
+void MacroAssembler::push_fTOS() {
+  subl(rsp, 2 * wordSize);
+  fstp_d(Address(rsp, 0));
+}
+
+
+void MacroAssembler::pushoop(jobject obj) {
+  push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+
+void MacroAssembler::pushptr(AddressLiteral src) {
+  if (src.is_lval()) {
+    push_literal32((int32_t)src.target(), src.rspec());
+  } else {
+    pushl(as_Address(src));
+  }
+}
+
+void MacroAssembler::set_word_if_not_zero(Register dst) {
+  xorl(dst, dst);
+  set_byte_if_not_zero(dst);
+}
+
+static void pass_arg0(MacroAssembler* masm, Register arg) {
+  masm->push(arg);
+}
+
+static void pass_arg1(MacroAssembler* masm, Register arg) {
+  masm->push(arg);
+}
+
+static void pass_arg2(MacroAssembler* masm, Register arg) {
+  masm->push(arg);
+}
+
+static void pass_arg3(MacroAssembler* masm, Register arg) {
+  masm->push(arg);
+}
+
+#ifndef PRODUCT
+extern "C" void findpc(intptr_t x);
+#endif
+
+void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
+  // In order to get locks to work, we need to fake a in_VM state
+  JavaThread* thread = JavaThread::current();
+  JavaThreadState saved_state = thread->thread_state();
+  thread->set_thread_state(_thread_in_vm);
+  if (ShowMessageBoxOnError) {
+    JavaThread* thread = JavaThread::current();
+    JavaThreadState saved_state = thread->thread_state();
+    thread->set_thread_state(_thread_in_vm);
+    if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
+      ttyLocker ttyl;
+      BytecodeCounter::print();
+    }
+    // To see where a verify_oop failed, get $ebx+40/X for this frame.
+    // This is the value of eip which points to where verify_oop will return.
+    if (os::message_box(msg, "Execution stopped, print registers?")) {
+      ttyLocker ttyl;
+      tty->print_cr("eip = 0x%08x", eip);
+#ifndef PRODUCT
+      tty->cr();
+      findpc(eip);
+      tty->cr();
+#endif
+      tty->print_cr("rax, = 0x%08x", rax);
+      tty->print_cr("rbx, = 0x%08x", rbx);
+      tty->print_cr("rcx = 0x%08x", rcx);
+      tty->print_cr("rdx = 0x%08x", rdx);
+      tty->print_cr("rdi = 0x%08x", rdi);
+      tty->print_cr("rsi = 0x%08x", rsi);
+      tty->print_cr("rbp, = 0x%08x", rbp);
+      tty->print_cr("rsp = 0x%08x", rsp);
+      BREAKPOINT;
+    }
+  } else {
+    ttyLocker ttyl;
+    ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
+    assert(false, "DEBUG MESSAGE");
+  }
+  ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
+}
+
+void MacroAssembler::stop(const char* msg) {
+  ExternalAddress message((address)msg);
+  // push address of message
+  pushptr(message.addr());
+  { Label L; call(L, relocInfo::none); bind(L); }     // push eip
+  pusha();                                           // push registers
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
+  hlt();
+}
+
+void MacroAssembler::warn(const char* msg) {
+  push_CPU_state();
+
+  ExternalAddress message((address) msg);
+  // push address of message
+  pushptr(message.addr());
+
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
+  addl(rsp, wordSize);       // discard argument
+  pop_CPU_state();
+}
+
+#else // _LP64
+
+// 64 bit versions
+
+Address MacroAssembler::as_Address(AddressLiteral adr) {
+  // amd64 always does this as a pc-rel
+  // we can be absolute or disp based on the instruction type
+  // jmp/call are displacements others are absolute
+  assert(!adr.is_lval(), "must be rval");
+  assert(reachable(adr), "must be");
+  return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
+
+}
+
+Address MacroAssembler::as_Address(ArrayAddress adr) {
+  AddressLiteral base = adr.base();
+  lea(rscratch1, base);
+  Address index = adr.index();
+  assert(index._disp == 0, "must not have disp"); // maybe it can?
+  Address array(rscratch1, index._index, index._scale, index._disp);
+  return array;
+}
+
+int MacroAssembler::biased_locking_enter(Register lock_reg,
+                                         Register obj_reg,
+                                         Register swap_reg,
+                                         Register tmp_reg,
+                                         bool swap_reg_contains_mark,
+                                         Label& done,
+                                         Label* slow_case,
+                                         BiasedLockingCounters* counters) {
+  assert(UseBiasedLocking, "why call this otherwise?");
+  assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
+  assert(tmp_reg != noreg, "tmp_reg must be supplied");
+  assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
+  assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
+  Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
+  Address saved_mark_addr(lock_reg, 0);
+
+  if (PrintBiasedLockingStatistics && counters == NULL)
+    counters = BiasedLocking::counters();
+
+  // Biased locking
+  // See whether the lock is currently biased toward our thread and
+  // whether the epoch is still valid
+  // Note that the runtime guarantees sufficient alignment of JavaThread
+  // pointers to allow age to be placed into low bits
+  // First check to see whether biasing is even enabled for this object
+  Label cas_label;
+  int null_check_offset = -1;
+  if (!swap_reg_contains_mark) {
+    null_check_offset = offset();
+    movq(swap_reg, mark_addr);
+  }
+  movq(tmp_reg, swap_reg);
+  andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
+  cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
+  jcc(Assembler::notEqual, cas_label);
+  // The bias pattern is present in the object's header. Need to check
+  // whether the bias owner and the epoch are both still current.
+  load_prototype_header(tmp_reg, obj_reg);
+  orq(tmp_reg, r15_thread);
+  xorq(tmp_reg, swap_reg);
+  andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
+  }
+  jcc(Assembler::equal, done);
+
+  Label try_revoke_bias;
+  Label try_rebias;
+
+  // At this point we know that the header has the bias pattern and
+  // that we are not the bias owner in the current epoch. We need to
+  // figure out more details about the state of the header in order to
+  // know what operations can be legally performed on the object's
+  // header.
+
+  // If the low three bits in the xor result aren't clear, that means
+  // the prototype header is no longer biased and we have to revoke
+  // the bias on this object.
+  testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
+  jcc(Assembler::notZero, try_revoke_bias);
+
+  // Biasing is still enabled for this data type. See whether the
+  // epoch of the current bias is still valid, meaning that the epoch
+  // bits of the mark word are equal to the epoch bits of the
+  // prototype header. (Note that the prototype header's epoch bits
+  // only change at a safepoint.) If not, attempt to rebias the object
+  // toward the current thread. Note that we must be absolutely sure
+  // that the current epoch is invalid in order to do this because
+  // otherwise the manipulations it performs on the mark word are
+  // illegal.
+  testq(tmp_reg, markOopDesc::epoch_mask_in_place);
+  jcc(Assembler::notZero, try_rebias);
+
+  // The epoch of the current bias is still valid but we know nothing
+  // about the owner; it might be set or it might be clear. Try to
+  // acquire the bias of the object using an atomic operation. If this
+  // fails we will go in to the runtime to revoke the object's bias.
+  // Note that we first construct the presumed unbiased header so we
+  // don't accidentally blow away another thread's valid bias.
+  andq(swap_reg,
+       markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
+  movq(tmp_reg, swap_reg);
+  orq(tmp_reg, r15_thread);
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgq(tmp_reg, Address(obj_reg, 0));
+  // If the biasing toward our thread failed, this means that
+  // another thread succeeded in biasing it toward itself and we
+  // need to revoke that bias. The revocation will occur in the
+  // interpreter runtime in the slow case.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
+  }
+  if (slow_case != NULL) {
+    jcc(Assembler::notZero, *slow_case);
+  }
+  jmp(done);
+
+  bind(try_rebias);
+  // At this point we know the epoch has expired, meaning that the
+  // current "bias owner", if any, is actually invalid. Under these
+  // circumstances _only_, we are allowed to use the current header's
+  // value as the comparison value when doing the cas to acquire the
+  // bias in the current epoch. In other words, we allow transfer of
+  // the bias from one thread to another directly in this situation.
+  //
+  // FIXME: due to a lack of registers we currently blow away the age
+  // bits in this situation. Should attempt to preserve them.
+  load_prototype_header(tmp_reg, obj_reg);
+  orq(tmp_reg, r15_thread);
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgq(tmp_reg, Address(obj_reg, 0));
+  // If the biasing toward our thread failed, then another thread
+  // succeeded in biasing it toward itself and we need to revoke that
+  // bias. The revocation will occur in the runtime in the slow case.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
+  }
+  if (slow_case != NULL) {
+    jcc(Assembler::notZero, *slow_case);
+  }
+  jmp(done);
+
+  bind(try_revoke_bias);
+  // The prototype mark in the klass doesn't have the bias bit set any
+  // more, indicating that objects of this data type are not supposed
+  // to be biased any more. We are going to try to reset the mark of
+  // this object to the prototype value and fall through to the
+  // CAS-based locking scheme. Note that if our CAS fails, it means
+  // that another thread raced us for the privilege of revoking the
+  // bias of this particular object, so it's okay to continue in the
+  // normal locking code.
+  //
+  // FIXME: due to a lack of registers we currently blow away the age
+  // bits in this situation. Should attempt to preserve them.
+  load_prototype_header(tmp_reg, obj_reg);
+  if (os::is_MP()) {
+    lock();
+  }
+  cmpxchgq(tmp_reg, Address(obj_reg, 0));
+  // Fall through to the normal CAS-based lock, because no matter what
+  // the result of the above CAS, some thread must have succeeded in
+  // removing the bias bit from the object's header.
+  if (counters != NULL) {
+    cond_inc32(Assembler::zero,
+               ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
+  }
+
+  bind(cas_label);
+
+  return null_check_offset;
+}
+
+void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
+  Label L, E;
+
+#ifdef _WIN64
+  // Windows always allocates space for it's register args
+  assert(num_args <= 4, "only register arguments supported");
+  subq(rsp,  frame::arg_reg_save_area_bytes);
+#endif
+
+  // Align stack if necessary
+  testl(rsp, 15);
+  jcc(Assembler::zero, L);
+
+  subq(rsp, 8);
+  {
+    call(RuntimeAddress(entry_point));
+  }
+  addq(rsp, 8);
+  jmp(E);
+
+  bind(L);
+  {
+    call(RuntimeAddress(entry_point));
+  }
+
+  bind(E);
+
+#ifdef _WIN64
+  // restore stack pointer
+  addq(rsp, frame::arg_reg_save_area_bytes);
+#endif
+
+}
+
+void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
+  assert(!src2.is_lval(), "should use cmpptr");
+
+  if (reachable(src2)) {
+    cmpq(src1, as_Address(src2));
+  } else {
+    lea(rscratch1, src2);
+    Assembler::cmpq(src1, Address(rscratch1, 0));
+  }
+}
+
+int MacroAssembler::corrected_idivq(Register reg) {
+  // Full implementation of Java ldiv and lrem; checks for special
+  // case as described in JVM spec., p.243 & p.271.  The function
+  // returns the (pc) offset of the idivl instruction - may be needed
+  // for implicit exceptions.
+  //
+  //         normal case                           special case
+  //
+  // input : rax: dividend                         min_long
+  //         reg: divisor   (may not be eax/edx)   -1
+  //
+  // output: rax: quotient  (= rax idiv reg)       min_long
+  //         rdx: remainder (= rax irem reg)       0
+  assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
+  static const int64_t min_long = 0x8000000000000000;
+  Label normal_case, special_case;
+
+  // check for special case
+  cmp64(rax, ExternalAddress((address) &min_long));
+  jcc(Assembler::notEqual, normal_case);
+  xorl(rdx, rdx); // prepare rdx for possible special case (where
+                  // remainder = 0)
+  cmpq(reg, -1);
+  jcc(Assembler::equal, special_case);
+
+  // handle normal case
+  bind(normal_case);
+  cdqq();
+  int idivq_offset = offset();
+  idivq(reg);
+
+  // normal and special case exit
+  bind(special_case);
+
+  return idivq_offset;
+}
+
+void MacroAssembler::decrementq(Register reg, int value) {
+  if (value == min_jint) { subq(reg, value); return; }
+  if (value <  0) { incrementq(reg, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { decq(reg) ; return; }
+  /* else */      { subq(reg, value)       ; return; }
+}
+
+void MacroAssembler::decrementq(Address dst, int value) {
+  if (value == min_jint) { subq(dst, value); return; }
+  if (value <  0) { incrementq(dst, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { decq(dst) ; return; }
+  /* else */      { subq(dst, value)       ; return; }
+}
+
+void MacroAssembler::fat_nop() {
+  // A 5 byte nop that is safe for patching (see patch_verified_entry)
+  // Recommened sequence from 'Software Optimization Guide for the AMD
+  // Hammer Processor'
+  emit_byte(0x66);
+  emit_byte(0x66);
+  emit_byte(0x90);
+  emit_byte(0x66);
+  emit_byte(0x90);
+}
+
+void MacroAssembler::incrementq(Register reg, int value) {
+  if (value == min_jint) { addq(reg, value); return; }
+  if (value <  0) { decrementq(reg, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { incq(reg) ; return; }
+  /* else */      { addq(reg, value)       ; return; }
+}
+
+void MacroAssembler::incrementq(Address dst, int value) {
+  if (value == min_jint) { addq(dst, value); return; }
+  if (value <  0) { decrementq(dst, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { incq(dst) ; return; }
+  /* else */      { addq(dst, value)       ; return; }
+}
+
+// 32bit can do a case table jump in one instruction but we no longer allow the base
+// to be installed in the Address class
+void MacroAssembler::jump(ArrayAddress entry) {
+  lea(rscratch1, entry.base());
+  Address dispatch = entry.index();
+  assert(dispatch._base == noreg, "must be");
+  dispatch._base = rscratch1;
+  jmp(dispatch);
+}
+
+void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
+  ShouldNotReachHere(); // 64bit doesn't use two regs
+  cmpq(x_lo, y_lo);
+}
+
+void MacroAssembler::lea(Register dst, AddressLiteral src) {
+    mov_literal64(dst, (intptr_t)src.target(), src.rspec());
+}
+
+void MacroAssembler::lea(Address dst, AddressLiteral adr) {
+  mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
+  movptr(dst, rscratch1);
+}
+
+void MacroAssembler::leave() {
+  // %%% is this really better? Why not on 32bit too?
+  emit_byte(0xC9); // LEAVE
+}
+
+void MacroAssembler::lneg(Register hi, Register lo) {
+  ShouldNotReachHere(); // 64bit doesn't use two regs
+  negq(lo);
+}
+
+void MacroAssembler::movoop(Register dst, jobject obj) {
+  mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::movoop(Address dst, jobject obj) {
+  mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
+  movq(dst, rscratch1);
+}
+
+void MacroAssembler::movptr(Register dst, AddressLiteral src) {
+  if (src.is_lval()) {
+    mov_literal64(dst, (intptr_t)src.target(), src.rspec());
+  } else {
+    if (reachable(src)) {
+      movq(dst, as_Address(src));
+    } else {
+      lea(rscratch1, src);
+      movq(dst, Address(rscratch1,0));
+    }
+  }
+}
+
+void MacroAssembler::movptr(ArrayAddress dst, Register src) {
+  movq(as_Address(dst), src);
+}
+
+void MacroAssembler::movptr(Register dst, ArrayAddress src) {
+  movq(dst, as_Address(src));
+}
+
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Address dst, intptr_t src) {
+  mov64(rscratch1, src);
+  movq(dst, rscratch1);
+}
+
+// These are mostly for initializing NULL
+void MacroAssembler::movptr(Address dst, int32_t src) {
+  movslq(dst, src);
+}
+
+void MacroAssembler::movptr(Register dst, int32_t src) {
+  mov64(dst, (intptr_t)src);
+}
+
+void MacroAssembler::pushoop(jobject obj) {
+  movoop(rscratch1, obj);
+  push(rscratch1);
+}
+
+void MacroAssembler::pushptr(AddressLiteral src) {
+  lea(rscratch1, src);
+  if (src.is_lval()) {
+    push(rscratch1);
+  } else {
+    pushq(Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::reset_last_Java_frame(bool clear_fp,
+                                           bool clear_pc) {
+  // we must set sp to zero to clear frame
+  movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), (int32_t)NULL_WORD);
+  // must clear fp, so that compiled frames are not confused; it is
+  // possible that we need it only for debugging
+  if (clear_fp) {
+    movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), (int32_t)NULL_WORD);
+  }
+
+  if (clear_pc) {
+    movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), (int32_t)NULL_WORD);
+  }
+}
+
+void MacroAssembler::set_last_Java_frame(Register last_java_sp,
+                                         Register last_java_fp,
+                                         address  last_java_pc) {
+  // determine last_java_sp register
+  if (!last_java_sp->is_valid()) {
+    last_java_sp = rsp;
+  }
+
+  // last_java_fp is optional
+  if (last_java_fp->is_valid()) {
+    movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
+           last_java_fp);
+  }
+
+  // last_java_pc is optional
+  if (last_java_pc != NULL) {
+    Address java_pc(r15_thread,
+                    JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
+    lea(rscratch1, InternalAddress(last_java_pc));
+    movptr(java_pc, rscratch1);
+  }
+
+  movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
+}
+
+static void pass_arg0(MacroAssembler* masm, Register arg) {
+  if (c_rarg0 != arg ) {
+    masm->mov(c_rarg0, arg);
+  }
+}
+
+static void pass_arg1(MacroAssembler* masm, Register arg) {
+  if (c_rarg1 != arg ) {
+    masm->mov(c_rarg1, arg);
+  }
+}
+
+static void pass_arg2(MacroAssembler* masm, Register arg) {
+  if (c_rarg2 != arg ) {
+    masm->mov(c_rarg2, arg);
+  }
+}
+
+static void pass_arg3(MacroAssembler* masm, Register arg) {
+  if (c_rarg3 != arg ) {
+    masm->mov(c_rarg3, arg);
+  }
+}
+
+void MacroAssembler::stop(const char* msg) {
+  address rip = pc();
+  pusha(); // get regs on stack
+  lea(c_rarg0, ExternalAddress((address) msg));
+  lea(c_rarg1, InternalAddress(rip));
+  movq(c_rarg2, rsp); // pass pointer to regs array
+  andq(rsp, -16); // align stack as required by ABI
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
+  hlt();
+}
+
+void MacroAssembler::warn(const char* msg) {
+  push(r12);
+  movq(r12, rsp);
+  andq(rsp, -16);     // align stack as required by push_CPU_state and call
+
+  push_CPU_state();   // keeps alignment at 16 bytes
+  lea(c_rarg0, ExternalAddress((address) msg));
+  call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
+  pop_CPU_state();
+
+  movq(rsp, r12);
+  pop(r12);
+}
+
+#ifndef PRODUCT
+extern "C" void findpc(intptr_t x);
+#endif
+
+void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
+  // In order to get locks to work, we need to fake a in_VM state
+  if (ShowMessageBoxOnError ) {
+    JavaThread* thread = JavaThread::current();
+    JavaThreadState saved_state = thread->thread_state();
+    thread->set_thread_state(_thread_in_vm);
+#ifndef PRODUCT
+    if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
+      ttyLocker ttyl;
+      BytecodeCounter::print();
+    }
+#endif
+    // To see where a verify_oop failed, get $ebx+40/X for this frame.
+    // XXX correct this offset for amd64
+    // This is the value of eip which points to where verify_oop will return.
+    if (os::message_box(msg, "Execution stopped, print registers?")) {
+      ttyLocker ttyl;
+      tty->print_cr("rip = 0x%016lx", pc);
+#ifndef PRODUCT
+      tty->cr();
+      findpc(pc);
+      tty->cr();
+#endif
+      tty->print_cr("rax = 0x%016lx", regs[15]);
+      tty->print_cr("rbx = 0x%016lx", regs[12]);
+      tty->print_cr("rcx = 0x%016lx", regs[14]);
+      tty->print_cr("rdx = 0x%016lx", regs[13]);
+      tty->print_cr("rdi = 0x%016lx", regs[8]);
+      tty->print_cr("rsi = 0x%016lx", regs[9]);
+      tty->print_cr("rbp = 0x%016lx", regs[10]);
+      tty->print_cr("rsp = 0x%016lx", regs[11]);
+      tty->print_cr("r8  = 0x%016lx", regs[7]);
+      tty->print_cr("r9  = 0x%016lx", regs[6]);
+      tty->print_cr("r10 = 0x%016lx", regs[5]);
+      tty->print_cr("r11 = 0x%016lx", regs[4]);
+      tty->print_cr("r12 = 0x%016lx", regs[3]);
+      tty->print_cr("r13 = 0x%016lx", regs[2]);
+      tty->print_cr("r14 = 0x%016lx", regs[1]);
+      tty->print_cr("r15 = 0x%016lx", regs[0]);
+      BREAKPOINT;
+    }
+    ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
+  } else {
+    ttyLocker ttyl;
+    ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
+                    msg);
+  }
+}
+
+#endif // _LP64
+
+// Now versions that are common to 32/64 bit
+
+void MacroAssembler::addptr(Register dst, int32_t imm32) {
+  LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
+}
+
+void MacroAssembler::addptr(Register dst, Register src) {
+  LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
+}
+
+void MacroAssembler::addptr(Address dst, Register src) {
+  LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
+}
+
+void MacroAssembler::align(int modulus) {
+  if (offset() % modulus != 0) {
+    nop(modulus - (offset() % modulus));
+  }
+}
+
+void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
+  andpd(dst, as_Address(src));
+}
+
+void MacroAssembler::andptr(Register dst, int32_t imm32) {
+  LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
+}
+
+void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
+  pushf();
+  if (os::is_MP())
+    lock();
+  incrementl(counter_addr);
+  popf();
+}
+
+// Writes to stack successive pages until offset reached to check for
+// stack overflow + shadow pages.  This clobbers tmp.
+void MacroAssembler::bang_stack_size(Register size, Register tmp) {
+  movptr(tmp, rsp);
+  // Bang stack for total size given plus shadow page size.
+  // Bang one page at a time because large size can bang beyond yellow and
+  // red zones.
+  Label loop;
+  bind(loop);
+  movl(Address(tmp, (-os::vm_page_size())), size );
+  subptr(tmp, os::vm_page_size());
+  subl(size, os::vm_page_size());
+  jcc(Assembler::greater, loop);
+
+  // Bang down shadow pages too.
+  // The -1 because we already subtracted 1 page.
+  for (int i = 0; i< StackShadowPages-1; i++) {
+    // this could be any sized move but this is can be a debugging crumb
+    // so the bigger the better.
+    movptr(Address(tmp, (-i*os::vm_page_size())), size );
+  }
+}
+
+void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
+  assert(UseBiasedLocking, "why call this otherwise?");
+
+  // Check for biased locking unlock case, which is a no-op
+  // Note: we do not have to check the thread ID for two reasons.
+  // First, the interpreter checks for IllegalMonitorStateException at
+  // a higher level. Second, if the bias was revoked while we held the
+  // lock, the object could not be rebiased toward another thread, so
+  // the bias bit would be clear.
+  movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
+  andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
+  cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
+  jcc(Assembler::equal, done);
+}
+
+void MacroAssembler::c2bool(Register x) {
+  // implements x == 0 ? 0 : 1
+  // note: must only look at least-significant byte of x
+  //       since C-style booleans are stored in one byte
+  //       only! (was bug)
+  andl(x, 0xFF);
+  setb(Assembler::notZero, x);
+}
+
+// Wouldn't need if AddressLiteral version had new name
+void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
+  Assembler::call(L, rtype);
+}
+
+void MacroAssembler::call(Register entry) {
+  Assembler::call(entry);
+}
+
+void MacroAssembler::call(AddressLiteral entry) {
+  if (reachable(entry)) {
+    Assembler::call_literal(entry.target(), entry.rspec());
+  } else {
+    lea(rscratch1, entry);
+    Assembler::call(rscratch1);
+  }
+}
+
+// Implementation of call_VM versions
+
+void MacroAssembler::call_VM(Register oop_result,
+                             address entry_point,
+                             bool check_exceptions) {
+  Label C, E;
+  call(C, relocInfo::none);
+  jmp(E);
+
+  bind(C);
+  call_VM_helper(oop_result, entry_point, 0, check_exceptions);
+  ret(0);
+
+  bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             address entry_point,
+                             Register arg_1,
+                             bool check_exceptions) {
+  Label C, E;
+  call(C, relocInfo::none);
+  jmp(E);
+
+  bind(C);
+  pass_arg1(this, arg_1);
+  call_VM_helper(oop_result, entry_point, 1, check_exceptions);
+  ret(0);
+
+  bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             address entry_point,
+                             Register arg_1,
+                             Register arg_2,
+                             bool check_exceptions) {
+  Label C, E;
+  call(C, relocInfo::none);
+  jmp(E);
+
+  bind(C);
+
+  LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+
+  pass_arg2(this, arg_2);
+  pass_arg1(this, arg_1);
+  call_VM_helper(oop_result, entry_point, 2, check_exceptions);
+  ret(0);
+
+  bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             address entry_point,
+                             Register arg_1,
+                             Register arg_2,
+                             Register arg_3,
+                             bool check_exceptions) {
+  Label C, E;
+  call(C, relocInfo::none);
+  jmp(E);
+
+  bind(C);
+
+  LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
+  LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
+  pass_arg3(this, arg_3);
+
+  LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+  pass_arg2(this, arg_2);
+
+  pass_arg1(this, arg_1);
+  call_VM_helper(oop_result, entry_point, 3, check_exceptions);
+  ret(0);
+
+  bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             Register last_java_sp,
+                             address entry_point,
+                             int number_of_arguments,
+                             bool check_exceptions) {
+  Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
+  call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             Register last_java_sp,
+                             address entry_point,
+                             Register arg_1,
+                             bool check_exceptions) {
+  pass_arg1(this, arg_1);
+  call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             Register last_java_sp,
+                             address entry_point,
+                             Register arg_1,
+                             Register arg_2,
+                             bool check_exceptions) {
+
+  LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+  pass_arg2(this, arg_2);
+  pass_arg1(this, arg_1);
+  call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+                             Register last_java_sp,
+                             address entry_point,
+                             Register arg_1,
+                             Register arg_2,
+                             Register arg_3,
+                             bool check_exceptions) {
+  LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
+  LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
+  pass_arg3(this, arg_3);
+  LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+  pass_arg2(this, arg_2);
+  pass_arg1(this, arg_1);
+  call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
+}
+
+void MacroAssembler::call_VM_base(Register oop_result,
+                                  Register java_thread,
+                                  Register last_java_sp,
+                                  address  entry_point,
+                                  int      number_of_arguments,
+                                  bool     check_exceptions) {
+  // determine java_thread register
+  if (!java_thread->is_valid()) {
+#ifdef _LP64
+    java_thread = r15_thread;
+#else
+    java_thread = rdi;
+    get_thread(java_thread);
+#endif // LP64
+  }
+  // determine last_java_sp register
+  if (!last_java_sp->is_valid()) {
+    last_java_sp = rsp;
+  }
+  // debugging support
+  assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
+  LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
+  assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
+  assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
+
+  // push java thread (becomes first argument of C function)
+
+  NOT_LP64(push(java_thread); number_of_arguments++);
+  LP64_ONLY(mov(c_rarg0, r15_thread));
+
+  // set last Java frame before call
+  assert(last_java_sp != rbp, "can't use ebp/rbp");
+
+  // Only interpreter should have to set fp
+  set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
+
+  // do the call, remove parameters
+  MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
+
+  // restore the thread (cannot use the pushed argument since arguments
+  // may be overwritten by C code generated by an optimizing compiler);
+  // however can use the register value directly if it is callee saved.
+  if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
+    // rdi & rsi (also r15) are callee saved -> nothing to do
+#ifdef ASSERT
+    guarantee(java_thread != rax, "change this code");
+    push(rax);
+    { Label L;
+      get_thread(rax);
+      cmpptr(java_thread, rax);
+      jcc(Assembler::equal, L);
+      stop("MacroAssembler::call_VM_base: rdi not callee saved?");
+      bind(L);
+    }
+    pop(rax);
+#endif
+  } else {
+    get_thread(java_thread);
+  }
+  // reset last Java frame
+  // Only interpreter should have to clear fp
+  reset_last_Java_frame(java_thread, true, false);
+
+#ifndef CC_INTERP
+   // C++ interp handles this in the interpreter
+  check_and_handle_popframe(java_thread);
+  check_and_handle_earlyret(java_thread);
+#endif /* CC_INTERP */
+
+  if (check_exceptions) {
+    // check for pending exceptions (java_thread is set upon return)
+    cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
+#ifndef _LP64
+    jump_cc(Assembler::notEqual,
+            RuntimeAddress(StubRoutines::forward_exception_entry()));
+#else
+    // This used to conditionally jump to forward_exception however it is
+    // possible if we relocate that the branch will not reach. So we must jump
+    // around so we can always reach
+
+    Label ok;
+    jcc(Assembler::equal, ok);
+    jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
+    bind(ok);
+#endif // LP64
+  }
+
+  // get oop result if there is one and reset the value in the thread
+  if (oop_result->is_valid()) {
+    movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
+    movptr(Address(java_thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+    verify_oop(oop_result, "broken oop in call_VM_base");
+  }
+}
+
+void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
+
+  // Calculate the value for last_Java_sp
+  // somewhat subtle. call_VM does an intermediate call
+  // which places a return address on the stack just under the
+  // stack pointer as the user finsihed with it. This allows
+  // use to retrieve last_Java_pc from last_Java_sp[-1].
+  // On 32bit we then have to push additional args on the stack to accomplish
+  // the actual requested call. On 64bit call_VM only can use register args
+  // so the only extra space is the return address that call_VM created.
+  // This hopefully explains the calculations here.
+
+#ifdef _LP64
+  // We've pushed one address, correct last_Java_sp
+  lea(rax, Address(rsp, wordSize));
+#else
+  lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
+#endif // LP64
+
+  call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
+
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
+  call_VM_leaf_base(entry_point, number_of_arguments);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
+  pass_arg0(this, arg_0);
+  call_VM_leaf(entry_point, 1);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
+
+  LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
+  pass_arg1(this, arg_1);
+  pass_arg0(this, arg_0);
+  call_VM_leaf(entry_point, 2);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
+  LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
+  LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+  pass_arg2(this, arg_2);
+  LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
+  pass_arg1(this, arg_1);
+  pass_arg0(this, arg_0);
+  call_VM_leaf(entry_point, 3);
+}
+
+void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
+}
+
+void MacroAssembler::check_and_handle_popframe(Register java_thread) {
+}
+
+void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
+  if (reachable(src1)) {
+    cmpl(as_Address(src1), imm);
+  } else {
+    lea(rscratch1, src1);
+    cmpl(Address(rscratch1, 0), imm);
+  }
+}
+
+void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
+  assert(!src2.is_lval(), "use cmpptr");
+  if (reachable(src2)) {
+    cmpl(src1, as_Address(src2));
+  } else {
+    lea(rscratch1, src2);
+    cmpl(src1, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::cmp32(Register src1, int32_t imm) {
+  Assembler::cmpl(src1, imm);
+}
+
+void MacroAssembler::cmp32(Register src1, Address src2) {
+  Assembler::cmpl(src1, src2);
+}
+
+void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
+  ucomisd(opr1, opr2);
+
+  Label L;
+  if (unordered_is_less) {
+    movl(dst, -1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::below , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    increment(dst);
+  } else { // unordered is greater
+    movl(dst, 1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::above , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    decrementl(dst);
+  }
+  bind(L);
+}
+
+void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
+  ucomiss(opr1, opr2);
+
+  Label L;
+  if (unordered_is_less) {
+    movl(dst, -1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::below , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    increment(dst);
+  } else { // unordered is greater
+    movl(dst, 1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::above , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    decrementl(dst);
+  }
+  bind(L);
+}
+
+
+void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
+  if (reachable(src1)) {
+    cmpb(as_Address(src1), imm);
+  } else {
+    lea(rscratch1, src1);
+    cmpb(Address(rscratch1, 0), imm);
+  }
+}
+
+void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
+#ifdef _LP64
+  if (src2.is_lval()) {
+    movptr(rscratch1, src2);
+    Assembler::cmpq(src1, rscratch1);
+  } else if (reachable(src2)) {
+    cmpq(src1, as_Address(src2));
+  } else {
+    lea(rscratch1, src2);
+    Assembler::cmpq(src1, Address(rscratch1, 0));
+  }
+#else
+  if (src2.is_lval()) {
+    cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
+  } else {
+    cmpl(src1, as_Address(src2));
+  }
+#endif // _LP64
+}
+
+void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
+  assert(src2.is_lval(), "not a mem-mem compare");
+#ifdef _LP64
+  // moves src2's literal address
+  movptr(rscratch1, src2);
+  Assembler::cmpq(src1, rscratch1);
+#else
+  cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
+#endif // _LP64
+}
+
+void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
+  if (reachable(adr)) {
+    if (os::is_MP())
+      lock();
+    cmpxchgptr(reg, as_Address(adr));
+  } else {
+    lea(rscratch1, adr);
+    if (os::is_MP())
+      lock();
+    cmpxchgptr(reg, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
+  LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
+}
+
+void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
+  comisd(dst, as_Address(src));
+}
+
+void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
+  comiss(dst, as_Address(src));
+}
+
+
+void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
+  Condition negated_cond = negate_condition(cond);
+  Label L;
+  jcc(negated_cond, L);
+  atomic_incl(counter_addr);
+  bind(L);
+}
+
+int MacroAssembler::corrected_idivl(Register reg) {
+  // Full implementation of Java idiv and irem; checks for
+  // special case as described in JVM spec., p.243 & p.271.
+  // The function returns the (pc) offset of the idivl
+  // instruction - may be needed for implicit exceptions.
+  //
+  //         normal case                           special case
+  //
+  // input : rax,: dividend                         min_int
+  //         reg: divisor   (may not be rax,/rdx)   -1
+  //
+  // output: rax,: quotient  (= rax, idiv reg)       min_int
+  //         rdx: remainder (= rax, irem reg)       0
+  assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
+  const int min_int = 0x80000000;
+  Label normal_case, special_case;
+
+  // check for special case
+  cmpl(rax, min_int);
+  jcc(Assembler::notEqual, normal_case);
+  xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
+  cmpl(reg, -1);
+  jcc(Assembler::equal, special_case);
+
+  // handle normal case
+  bind(normal_case);
+  cdql();
+  int idivl_offset = offset();
+  idivl(reg);
+
+  // normal and special case exit
+  bind(special_case);
+
+  return idivl_offset;
+}
+
+
+
+void MacroAssembler::decrementl(Register reg, int value) {
+  if (value == min_jint) {subl(reg, value) ; return; }
+  if (value <  0) { incrementl(reg, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { decl(reg) ; return; }
+  /* else */      { subl(reg, value)       ; return; }
+}
+
+void MacroAssembler::decrementl(Address dst, int value) {
+  if (value == min_jint) {subl(dst, value) ; return; }
+  if (value <  0) { incrementl(dst, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { decl(dst) ; return; }
+  /* else */      { subl(dst, value)       ; return; }
+}
+
+void MacroAssembler::division_with_shift (Register reg, int shift_value) {
+  assert (shift_value > 0, "illegal shift value");
+  Label _is_positive;
+  testl (reg, reg);
+  jcc (Assembler::positive, _is_positive);
+  int offset = (1 << shift_value) - 1 ;
+
+  if (offset == 1) {
+    incrementl(reg);
+  } else {
+    addl(reg, offset);
+  }
+
+  bind (_is_positive);
+  sarl(reg, shift_value);
+}
+
+// !defined(COMPILER2) is because of stupid core builds
+#if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
+void MacroAssembler::empty_FPU_stack() {
+  if (VM_Version::supports_mmx()) {
+    emms();
+  } else {
+    for (int i = 8; i-- > 0; ) ffree(i);
+  }
+}
+#endif // !LP64 || C1 || !C2
+
+
+// Defines obj, preserves var_size_in_bytes
+void MacroAssembler::eden_allocate(Register obj,
+                                   Register var_size_in_bytes,
+                                   int con_size_in_bytes,
+                                   Register t1,
+                                   Label& slow_case) {
+  assert(obj == rax, "obj must be in rax, for cmpxchg");
+  assert_different_registers(obj, var_size_in_bytes, t1);
+  Register end = t1;
+  Label retry;
+  bind(retry);
+  ExternalAddress heap_top((address) Universe::heap()->top_addr());
+  movptr(obj, heap_top);
+  if (var_size_in_bytes == noreg) {
+    lea(end, Address(obj, con_size_in_bytes));
+  } else {
+    lea(end, Address(obj, var_size_in_bytes, Address::times_1));
+  }
+  // if end < obj then we wrapped around => object too long => slow case
+  cmpptr(end, obj);
+  jcc(Assembler::below, slow_case);
+  cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
+  jcc(Assembler::above, slow_case);
+  // Compare obj with the top addr, and if still equal, store the new top addr in
+  // end at the address of the top addr pointer. Sets ZF if was equal, and clears
+  // it otherwise. Use lock prefix for atomicity on MPs.
+  locked_cmpxchgptr(end, heap_top);
+  jcc(Assembler::notEqual, retry);
+}
+
+void MacroAssembler::enter() {
+  push(rbp);
+  mov(rbp, rsp);
+}
+
+void MacroAssembler::fcmp(Register tmp) {
+  fcmp(tmp, 1, true, true);
+}
+
+void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
+  assert(!pop_right || pop_left, "usage error");
+  if (VM_Version::supports_cmov()) {
+    assert(tmp == noreg, "unneeded temp");
+    if (pop_left) {
+      fucomip(index);
+    } else {
+      fucomi(index);
+    }
+    if (pop_right) {
+      fpop();
+    }
+  } else {
+    assert(tmp != noreg, "need temp");
+    if (pop_left) {
+      if (pop_right) {
+        fcompp();
+      } else {
+        fcomp(index);
+      }
+    } else {
+      fcom(index);
+    }
+    // convert FPU condition into eflags condition via rax,
+    save_rax(tmp);
+    fwait(); fnstsw_ax();
+    sahf();
+    restore_rax(tmp);
+  }
+  // condition codes set as follows:
+  //
+  // CF (corresponds to C0) if x < y
+  // PF (corresponds to C2) if unordered
+  // ZF (corresponds to C3) if x = y
+}
+
+void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
+  fcmp2int(dst, unordered_is_less, 1, true, true);
+}
+
+void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
+  fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
+  Label L;
+  if (unordered_is_less) {
+    movl(dst, -1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::below , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    increment(dst);
+  } else { // unordered is greater
+    movl(dst, 1);
+    jcc(Assembler::parity, L);
+    jcc(Assembler::above , L);
+    movl(dst, 0);
+    jcc(Assembler::equal , L);
+    decrementl(dst);
+  }
+  bind(L);
+}
+
+void MacroAssembler::fld_d(AddressLiteral src) {
+  fld_d(as_Address(src));
+}
+
+void MacroAssembler::fld_s(AddressLiteral src) {
+  fld_s(as_Address(src));
+}
+
+void MacroAssembler::fld_x(AddressLiteral src) {
+  Assembler::fld_x(as_Address(src));
+}
+
+void MacroAssembler::fldcw(AddressLiteral src) {
+  Assembler::fldcw(as_Address(src));
+}
+
+void MacroAssembler::fpop() {
+  ffree();
+  fincstp();
+}
+
+void MacroAssembler::fremr(Register tmp) {
+  save_rax(tmp);
+  { Label L;
+    bind(L);
+    fprem();
+    fwait(); fnstsw_ax();
+#ifdef _LP64
+    testl(rax, 0x400);
+    jcc(Assembler::notEqual, L);
+#else
+    sahf();
+    jcc(Assembler::parity, L);
+#endif // _LP64
+  }
+  restore_rax(tmp);
+  // Result is in ST0.
+  // Note: fxch & fpop to get rid of ST1
+  // (otherwise FPU stack could overflow eventually)
+  fxch(1);
+  fpop();
+}
+
+
+void MacroAssembler::incrementl(AddressLiteral dst) {
+  if (reachable(dst)) {
+    incrementl(as_Address(dst));
+  } else {
+    lea(rscratch1, dst);
+    incrementl(Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::incrementl(ArrayAddress dst) {
+  incrementl(as_Address(dst));
+}
+
+void MacroAssembler::incrementl(Register reg, int value) {
+  if (value == min_jint) {addl(reg, value) ; return; }
+  if (value <  0) { decrementl(reg, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { incl(reg) ; return; }
+  /* else */      { addl(reg, value)       ; return; }
+}
+
+void MacroAssembler::incrementl(Address dst, int value) {
+  if (value == min_jint) {addl(dst, value) ; return; }
+  if (value <  0) { decrementl(dst, -value); return; }
+  if (value == 0) {                        ; return; }
+  if (value == 1 && UseIncDec) { incl(dst) ; return; }
+  /* else */      { addl(dst, value)       ; return; }
+}
+
+void MacroAssembler::jump(AddressLiteral dst) {
+  if (reachable(dst)) {
+    jmp_literal(dst.target(), dst.rspec());
+  } else {
+    lea(rscratch1, dst);
+    jmp(rscratch1);
+  }
+}
+
+void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
+  if (reachable(dst)) {
+    InstructionMark im(this);
+    relocate(dst.reloc());
+    const int short_size = 2;
+    const int long_size = 6;
+    int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
+    if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
+      // 0111 tttn #8-bit disp
+      emit_byte(0x70 | cc);
+      emit_byte((offs - short_size) & 0xFF);
+    } else {
+      // 0000 1111 1000 tttn #32-bit disp
+      emit_byte(0x0F);
+      emit_byte(0x80 | cc);
+      emit_long(offs - long_size);
+    }
+  } else {
+#ifdef ASSERT
+    warning("reversing conditional branch");
+#endif /* ASSERT */
+    Label skip;
+    jccb(reverse[cc], skip);
+    lea(rscratch1, dst);
+    Assembler::jmp(rscratch1);
+    bind(skip);
+  }
+}
+
+void MacroAssembler::ldmxcsr(AddressLiteral src) {
+  if (reachable(src)) {
+    Assembler::ldmxcsr(as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    Assembler::ldmxcsr(Address(rscratch1, 0));
+  }
+}
+
+int MacroAssembler::load_signed_byte(Register dst, Address src) {
+  int off;
+  if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+    off = offset();
+    movsbl(dst, src); // movsxb
+  } else {
+    off = load_unsigned_byte(dst, src);
+    shll(dst, 24);
+    sarl(dst, 24);
+  }
+  return off;
+}
+
+// word => int32 which seems bad for 64bit
+int MacroAssembler::load_signed_word(Register dst, Address src) {
+  int off;
+  if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+    // This is dubious to me since it seems safe to do a signed 16 => 64 bit
+    // version but this is what 64bit has always done. This seems to imply
+    // that users are only using 32bits worth.
+    off = offset();
+    movswl(dst, src); // movsxw
+  } else {
+    off = load_unsigned_word(dst, src);
+    shll(dst, 16);
+    sarl(dst, 16);
+  }
+  return off;
+}
+
+int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
+  // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
+  // and "3.9 Partial Register Penalties", p. 22).
+  int off;
+  if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
+    off = offset();
+    movzbl(dst, src); // movzxb
+  } else {
+    xorl(dst, dst);
+    off = offset();
+    movb(dst, src);
+  }
+  return off;
+}
+
+int MacroAssembler::load_unsigned_word(Register dst, Address src) {
+  // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
+  // and "3.9 Partial Register Penalties", p. 22).
+  int off;
+  if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
+    off = offset();
+    movzwl(dst, src); // movzxw
+  } else {
+    xorl(dst, dst);
+    off = offset();
+    movw(dst, src);
+  }
+  return off;
+}
+
+void MacroAssembler::mov32(AddressLiteral dst, Register src) {
+  if (reachable(dst)) {
+    movl(as_Address(dst), src);
+  } else {
+    lea(rscratch1, dst);
+    movl(Address(rscratch1, 0), src);
+  }
+}
+
+void MacroAssembler::mov32(Register dst, AddressLiteral src) {
+  if (reachable(src)) {
+    movl(dst, as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    movl(dst, Address(rscratch1, 0));
+  }
+}
+
+// C++ bool manipulation
+
+void MacroAssembler::movbool(Register dst, Address src) {
+  if(sizeof(bool) == 1)
+    movb(dst, src);
+  else if(sizeof(bool) == 2)
+    movw(dst, src);
+  else if(sizeof(bool) == 4)
+    movl(dst, src);
+  else
+    // unsupported
+    ShouldNotReachHere();
+}
+
+void MacroAssembler::movbool(Address dst, bool boolconst) {
+  if(sizeof(bool) == 1)
+    movb(dst, (int) boolconst);
+  else if(sizeof(bool) == 2)
+    movw(dst, (int) boolconst);
+  else if(sizeof(bool) == 4)
+    movl(dst, (int) boolconst);
+  else
+    // unsupported
+    ShouldNotReachHere();
+}
+
+void MacroAssembler::movbool(Address dst, Register src) {
+  if(sizeof(bool) == 1)
+    movb(dst, src);
+  else if(sizeof(bool) == 2)
+    movw(dst, src);
+  else if(sizeof(bool) == 4)
+    movl(dst, src);
+  else
+    // unsupported
+    ShouldNotReachHere();
+}
+
+void MacroAssembler::movbyte(ArrayAddress dst, int src) {
+  movb(as_Address(dst), src);
+}
+
+void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
+  if (reachable(src)) {
+    if (UseXmmLoadAndClearUpper) {
+      movsd (dst, as_Address(src));
+    } else {
+      movlpd(dst, as_Address(src));
+    }
+  } else {
+    lea(rscratch1, src);
+    if (UseXmmLoadAndClearUpper) {
+      movsd (dst, Address(rscratch1, 0));
+    } else {
+      movlpd(dst, Address(rscratch1, 0));
+    }
+  }
+}
+
+void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
+  if (reachable(src)) {
+    movss(dst, as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    movss(dst, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::movptr(Register dst, Register src) {
+  LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movptr(Register dst, Address src) {
+  LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Register dst, intptr_t src) {
+  LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movptr(Address dst, Register src) {
+  LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
+  if (reachable(src)) {
+    movss(dst, as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    movss(dst, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::null_check(Register reg, int offset) {
+  if (needs_explicit_null_check(offset)) {
+    // provoke OS NULL exception if reg = NULL by
+    // accessing M[reg] w/o changing any (non-CC) registers
+    // NOTE: cmpl is plenty here to provoke a segv
+    cmpptr(rax, Address(reg, 0));
+    // Note: should probably use testl(rax, Address(reg, 0));
+    //       may be shorter code (however, this version of
+    //       testl needs to be implemented first)
+  } else {
+    // nothing to do, (later) access of M[reg + offset]
+    // will provoke OS NULL exception if reg = NULL
+  }
+}
+
+void MacroAssembler::os_breakpoint() {
+  // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
+  // (e.g., MSVC can't call ps() otherwise)
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+}
+
+void MacroAssembler::pop_CPU_state() {
+  pop_FPU_state();
+  pop_IU_state();
+}
+
+void MacroAssembler::pop_FPU_state() {
+  NOT_LP64(frstor(Address(rsp, 0));)
+  LP64_ONLY(fxrstor(Address(rsp, 0));)
+  addptr(rsp, FPUStateSizeInWords * wordSize);
+}
+
+void MacroAssembler::pop_IU_state() {
+  popa();
+  LP64_ONLY(addq(rsp, 8));
+  popf();
+}
+
+// Save Integer and Float state
+// Warning: Stack must be 16 byte aligned (64bit)
+void MacroAssembler::push_CPU_state() {
+  push_IU_state();
+  push_FPU_state();
+}
+
+void MacroAssembler::push_FPU_state() {
+  subptr(rsp, FPUStateSizeInWords * wordSize);
+#ifndef _LP64
+  fnsave(Address(rsp, 0));
+  fwait();
+#else
+  fxsave(Address(rsp, 0));
+#endif // LP64
+}
+
+void MacroAssembler::push_IU_state() {
+  // Push flags first because pusha kills them
+  pushf();
+  // Make sure rsp stays 16-byte aligned
+  LP64_ONLY(subq(rsp, 8));
+  pusha();
+}
+
+void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
+  // determine java_thread register
+  if (!java_thread->is_valid()) {
+    java_thread = rdi;
+    get_thread(java_thread);
+  }
+  // we must set sp to zero to clear frame
+  movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), (int32_t)NULL_WORD);
+  if (clear_fp) {
+    movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), (int32_t)NULL_WORD);
+  }
+
+  if (clear_pc)
+    movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), (int32_t)NULL_WORD);
+
+}
+
+void MacroAssembler::restore_rax(Register tmp) {
+  if (tmp == noreg) pop(rax);
+  else if (tmp != rax) mov(rax, tmp);
+}
+
+void MacroAssembler::round_to(Register reg, int modulus) {
+  addptr(reg, modulus - 1);
+  andptr(reg, -modulus);
+}
+
+void MacroAssembler::save_rax(Register tmp) {
+  if (tmp == noreg) push(rax);
+  else if (tmp != rax) mov(tmp, rax);
+}
+
+// Write serialization page so VM thread can do a pseudo remote membar.
+// We use the current thread pointer to calculate a thread specific
+// offset to write to within the page. This minimizes bus traffic
+// due to cache line collision.
+void MacroAssembler::serialize_memory(Register thread, Register tmp) {
+  movl(tmp, thread);
+  shrl(tmp, os::get_serialize_page_shift_count());
+  andl(tmp, (os::vm_page_size() - sizeof(int)));
+
+  Address index(noreg, tmp, Address::times_1);
+  ExternalAddress page(os::get_memory_serialize_page());
+
+  movptr(ArrayAddress(page, index), tmp);
+}
+
+// Calls to C land
+//
+// When entering C land, the rbp, & rsp of the last Java frame have to be recorded
+// in the (thread-local) JavaThread object. When leaving C land, the last Java fp
+// has to be reset to 0. This is required to allow proper stack traversal.
+void MacroAssembler::set_last_Java_frame(Register java_thread,
+                                         Register last_java_sp,
+                                         Register last_java_fp,
+                                         address  last_java_pc) {
+  // determine java_thread register
+  if (!java_thread->is_valid()) {
+    java_thread = rdi;
+    get_thread(java_thread);
+  }
+  // determine last_java_sp register
+  if (!last_java_sp->is_valid()) {
+    last_java_sp = rsp;
+  }
+
+  // last_java_fp is optional
+
+  if (last_java_fp->is_valid()) {
+    movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
+  }
+
+  // last_java_pc is optional
+
+  if (last_java_pc != NULL) {
+    lea(Address(java_thread,
+                 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
+        InternalAddress(last_java_pc));
+
+  }
+  movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
+}
+
+void MacroAssembler::shlptr(Register dst, int imm8) {
+  LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
+}
+
+void MacroAssembler::shrptr(Register dst, int imm8) {
+  LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
+}
+
+void MacroAssembler::sign_extend_byte(Register reg) {
+  if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
+    movsbl(reg, reg); // movsxb
+  } else {
+    shll(reg, 24);
+    sarl(reg, 24);
+  }
+}
+
+void MacroAssembler::sign_extend_short(Register reg) {
+  if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+    movswl(reg, reg); // movsxw
+  } else {
+    shll(reg, 16);
+    sarl(reg, 16);
+  }
+}
+
+void MacroAssembler::store_check(Register obj) {
+  // Does a store check for the oop in register obj. The content of
+  // register obj is destroyed afterwards.
+  store_check_part_1(obj);
+  store_check_part_2(obj);
+}
+
+void MacroAssembler::store_check(Register obj, Address dst) {
+  store_check(obj);
+}
+
+
+// split the store check operation so that other instructions can be scheduled inbetween
+void MacroAssembler::store_check_part_1(Register obj) {
+  BarrierSet* bs = Universe::heap()->barrier_set();
+  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
+  shrptr(obj, CardTableModRefBS::card_shift);
+}
+
+void MacroAssembler::store_check_part_2(Register obj) {
+  BarrierSet* bs = Universe::heap()->barrier_set();
+  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
+  CardTableModRefBS* ct = (CardTableModRefBS*)bs;
+  assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
+
+  // The calculation for byte_map_base is as follows:
+  // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
+  // So this essentially converts an address to a displacement and
+  // it will never need to be relocated. On 64bit however the value may be too
+  // large for a 32bit displacement
+
+  intptr_t disp = (intptr_t) ct->byte_map_base;
+  if (is_simm32(disp)) {
+    Address cardtable(noreg, obj, Address::times_1, disp);
+    movb(cardtable, 0);
+  } else {
+    // By doing it as an ExternalAddress disp could be converted to a rip-relative
+    // displacement and done in a single instruction given favorable mapping and
+    // a smarter version of as_Address. Worst case it is two instructions which
+    // is no worse off then loading disp into a register and doing as a simple
+    // Address() as above.
+    // We can't do as ExternalAddress as the only style since if disp == 0 we'll
+    // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
+    // in some cases we'll get a single instruction version.
+
+    ExternalAddress cardtable((address)disp);
+    Address index(noreg, obj, Address::times_1);
+    movb(as_Address(ArrayAddress(cardtable, index)), 0);
+  }
+}
+
+void MacroAssembler::subptr(Register dst, int32_t imm32) {
+  LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
+}
+
+void MacroAssembler::subptr(Register dst, Register src) {
+  LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
+}
+
+void MacroAssembler::test32(Register src1, AddressLiteral src2) {
+  // src2 must be rval
+
+  if (reachable(src2)) {
+    testl(src1, as_Address(src2));
+  } else {
+    lea(rscratch1, src2);
+    testl(src1, Address(rscratch1, 0));
+  }
+}
+
+// C++ bool manipulation
+void MacroAssembler::testbool(Register dst) {
+  if(sizeof(bool) == 1)
+    testb(dst, 0xff);
+  else if(sizeof(bool) == 2) {
+    // testw implementation needed for two byte bools
+    ShouldNotReachHere();
+  } else if(sizeof(bool) == 4)
+    testl(dst, dst);
+  else
+    // unsupported
+    ShouldNotReachHere();
+}
+
+void MacroAssembler::testptr(Register dst, Register src) {
+  LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
+}
+
+// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
+void MacroAssembler::tlab_allocate(Register obj,
+                                   Register var_size_in_bytes,
+                                   int con_size_in_bytes,
+                                   Register t1,
+                                   Register t2,
+                                   Label& slow_case) {
+  assert_different_registers(obj, t1, t2);
+  assert_different_registers(obj, var_size_in_bytes, t1);
+  Register end = t2;
+  Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
+
+  verify_tlab();
+
+  NOT_LP64(get_thread(thread));
+
+  movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
+  if (var_size_in_bytes == noreg) {
+    lea(end, Address(obj, con_size_in_bytes));
+  } else {
+    lea(end, Address(obj, var_size_in_bytes, Address::times_1));
+  }
+  cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
+  jcc(Assembler::above, slow_case);
+
+  // update the tlab top pointer
+  movptr(Address(thread, JavaThread::tlab_top_offset()), end);
+
+  // recover var_size_in_bytes if necessary
+  if (var_size_in_bytes == end) {
+    subptr(var_size_in_bytes, obj);
+  }
+  verify_tlab();
+}
+
+// Preserves rbx, and rdx.
+void MacroAssembler::tlab_refill(Label& retry,
+                                 Label& try_eden,
+                                 Label& slow_case) {
+  Register top = rax;
+  Register t1  = rcx;
+  Register t2  = rsi;
+  Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
+  assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
+  Label do_refill, discard_tlab;
+
+  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
+    // No allocation in the shared eden.
+    jmp(slow_case);
+  }
+
+  NOT_LP64(get_thread(thread_reg));
+
+  movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+  movptr(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
+
+  // calculate amount of free space
+  subptr(t1, top);
+  shrptr(t1, LogHeapWordSize);
+
+  // Retain tlab and allocate object in shared space if
+  // the amount free in the tlab is too large to discard.
+  cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
+  jcc(Assembler::lessEqual, discard_tlab);
+
+  // Retain
+  // %%% yuck as movptr...
+  movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
+  addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
+  if (TLABStats) {
+    // increment number of slow_allocations
+    addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
+  }
+  jmp(try_eden);
+
+  bind(discard_tlab);
+  if (TLABStats) {
+    // increment number of refills
+    addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
+    // accumulate wastage -- t1 is amount free in tlab
+    addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
+  }
+
+  // if tlab is currently allocated (top or end != null) then
+  // fill [top, end + alignment_reserve) with array object
+  testptr (top, top);
+  jcc(Assembler::zero, do_refill);
+
+  // set up the mark word
+  movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
+  // set the length to the remaining space
+  subptr(t1, typeArrayOopDesc::header_size(T_INT));
+  addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
+  shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
+  movptr(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
+  // set klass to intArrayKlass
+  // dubious reloc why not an oop reloc?
+  movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
+  // store klass last.  concurrent gcs assumes klass length is valid if
+  // klass field is not null.
+  store_klass(top, t1);
+
+  // refill the tlab with an eden allocation
+  bind(do_refill);
+  movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
+  shlptr(t1, LogHeapWordSize);
+  // add object_size ??
+  eden_allocate(top, t1, 0, t2, slow_case);
+
+  // Check that t1 was preserved in eden_allocate.
+#ifdef ASSERT
+  if (UseTLAB) {
+    Label ok;
+    Register tsize = rsi;
+    assert_different_registers(tsize, thread_reg, t1);
+    push(tsize);
+    movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
+    shlptr(tsize, LogHeapWordSize);
+    cmpptr(t1, tsize);
+    jcc(Assembler::equal, ok);
+    stop("assert(t1 != tlab size)");
+    should_not_reach_here();
+
+    bind(ok);
+    pop(tsize);
+  }
+#endif
+  movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
+  movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
+  addptr(top, t1);
+  subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
+  movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
+  verify_tlab();
+  jmp(retry);
+}
+
+static const double     pi_4 =  0.7853981633974483;
+
+void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
+  // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
+  // was attempted in this code; unfortunately it appears that the
+  // switch to 80-bit precision and back causes this to be
+  // unprofitable compared with simply performing a runtime call if
+  // the argument is out of the (-pi/4, pi/4) range.
+
+  Register tmp = noreg;
+  if (!VM_Version::supports_cmov()) {
+    // fcmp needs a temporary so preserve rbx,
+    tmp = rbx;
+    push(tmp);
+  }
+
+  Label slow_case, done;
+
+  // x ?<= pi/4
+  fld_d(ExternalAddress((address)&pi_4));
+  fld_s(1);                // Stack:  X  PI/4  X
+  fabs();                  // Stack: |X| PI/4  X
+  fcmp(tmp);
+  jcc(Assembler::above, slow_case);
+
+  // fastest case: -pi/4 <= x <= pi/4
+  switch(trig) {
+  case 's':
+    fsin();
+    break;
+  case 'c':
+    fcos();
+    break;
+  case 't':
+    ftan();
+    break;
+  default:
+    assert(false, "bad intrinsic");
+    break;
+  }
+  jmp(done);
+
+  // slow case: runtime call
+  bind(slow_case);
+  // Preserve registers across runtime call
+  pusha();
+  int incoming_argument_and_return_value_offset = -1;
+  if (num_fpu_regs_in_use > 1) {
+    // Must preserve all other FPU regs (could alternatively convert
+    // SharedRuntime::dsin and dcos into assembly routines known not to trash
+    // FPU state, but can not trust C compiler)
+    NEEDS_CLEANUP;
+    // NOTE that in this case we also push the incoming argument to
+    // the stack and restore it later; we also use this stack slot to
+    // hold the return value from dsin or dcos.
+    for (int i = 0; i < num_fpu_regs_in_use; i++) {
+      subptr(rsp, sizeof(jdouble));
+      fstp_d(Address(rsp, 0));
+    }
+    incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
+    fld_d(Address(rsp, incoming_argument_and_return_value_offset));
+  }
+  subptr(rsp, sizeof(jdouble));
+  fstp_d(Address(rsp, 0));
+#ifdef _LP64
+  movdbl(xmm0, Address(rsp, 0));
+#endif // _LP64
+
+  // NOTE: we must not use call_VM_leaf here because that requires a
+  // complete interpreter frame in debug mode -- same bug as 4387334
+  // MacroAssembler::call_VM_leaf_base is perfectly safe and will
+  // do proper 64bit abi
+
+  NEEDS_CLEANUP;
+  // Need to add stack banging before this runtime call if it needs to
+  // be taken; however, there is no generic stack banging routine at
+  // the MacroAssembler level
+  switch(trig) {
+  case 's':
+    {
+      MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
+    }
+    break;
+  case 'c':
+    {
+      MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
+    }
+    break;
+  case 't':
+    {
+      MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
+    }
+    break;
+  default:
+    assert(false, "bad intrinsic");
+    break;
+  }
+#ifdef _LP64
+    movsd(Address(rsp, 0), xmm0);
+    fld_d(Address(rsp, 0));
+#endif // _LP64
+  addptr(rsp, sizeof(jdouble));
+  if (num_fpu_regs_in_use > 1) {
+    // Must save return value to stack and then restore entire FPU stack
+    fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
+    for (int i = 0; i < num_fpu_regs_in_use; i++) {
+      fld_d(Address(rsp, 0));
+      addptr(rsp, sizeof(jdouble));
+    }
+  }
+  popa();
+
+  // Come here with result in F-TOS
+  bind(done);
+
+  if (tmp != noreg) {
+    pop(tmp);
+  }
+}
+
+
+void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
+  ucomisd(dst, as_Address(src));
+}
+
+void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
+  ucomiss(dst, as_Address(src));
+}
+
+void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
+  if (reachable(src)) {
+    xorpd(dst, as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    xorpd(dst, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
+  if (reachable(src)) {
+    xorps(dst, as_Address(src));
+  } else {
+    lea(rscratch1, src);
+    xorps(dst, Address(rscratch1, 0));
+  }
+}
+
+void MacroAssembler::verify_oop(Register reg, const char* s) {
+  if (!VerifyOops) return;
+
+  // Pass register number to verify_oop_subroutine
+  char* b = new char[strlen(s) + 50];
+  sprintf(b, "verify_oop: %s: %s", reg->name(), s);
+  push(rax);                          // save rax,
+  push(reg);                          // pass register argument
+  ExternalAddress buffer((address) b);
+  // avoid using pushptr, as it modifies scratch registers
+  // and our contract is not to modify anything
+  movptr(rax, buffer.addr());
+  push(rax);
+  // call indirectly to solve generation ordering problem
+  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+  call(rax);
+}
+
+
+void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
+  if (!VerifyOops) return;
+
+  // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
+  // Pass register number to verify_oop_subroutine
+  char* b = new char[strlen(s) + 50];
+  sprintf(b, "verify_oop_addr: %s", s);
+
+  push(rax);                          // save rax,
+  // addr may contain rsp so we will have to adjust it based on the push
+  // we just did
+  // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
+  // stores rax into addr which is backwards of what was intended.
+  if (addr.uses(rsp)) {
+    lea(rax, addr);
+    pushptr(Address(rax, BytesPerWord));
+  } else {
+    pushptr(addr);
+  }
+
+  ExternalAddress buffer((address) b);
+  // pass msg argument
+  // avoid using pushptr, as it modifies scratch registers
+  // and our contract is not to modify anything
+  movptr(rax, buffer.addr());
+  push(rax);
+
+  // call indirectly to solve generation ordering problem
+  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+  call(rax);
+  // Caller pops the arguments and restores rax, from the stack
+}
+
+void MacroAssembler::verify_tlab() {
+#ifdef ASSERT
+  if (UseTLAB && VerifyOops) {
+    Label next, ok;
+    Register t1 = rsi;
+    Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
+
+    push(t1);
+    NOT_LP64(push(thread_reg));
+    NOT_LP64(get_thread(thread_reg));
+
+    movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+    cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
+    jcc(Assembler::aboveEqual, next);
+    stop("assert(top >= start)");
+    should_not_reach_here();
+
+    bind(next);
+    movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
+    cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+    jcc(Assembler::aboveEqual, ok);
+    stop("assert(top <= end)");
+    should_not_reach_here();
+
+    bind(ok);
+    NOT_LP64(pop(thread_reg));
+    pop(t1);
+  }
+#endif
+}
+
+class ControlWord {
+ public:
+  int32_t _value;
+
+  int  rounding_control() const        { return  (_value >> 10) & 3      ; }
+  int  precision_control() const       { return  (_value >>  8) & 3      ; }
+  bool precision() const               { return ((_value >>  5) & 1) != 0; }
+  bool underflow() const               { return ((_value >>  4) & 1) != 0; }
+  bool overflow() const                { return ((_value >>  3) & 1) != 0; }
+  bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
+  bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
+  bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
+
+  void print() const {
+    // rounding control
+    const char* rc;
+    switch (rounding_control()) {
+      case 0: rc = "round near"; break;
+      case 1: rc = "round down"; break;
+      case 2: rc = "round up  "; break;
+      case 3: rc = "chop      "; break;
+    };
+    // precision control
+    const char* pc;
+    switch (precision_control()) {
+      case 0: pc = "24 bits "; break;
+      case 1: pc = "reserved"; break;
+      case 2: pc = "53 bits "; break;
+      case 3: pc = "64 bits "; break;
+    };
+    // flags
+    char f[9];
+    f[0] = ' ';
+    f[1] = ' ';
+    f[2] = (precision   ()) ? 'P' : 'p';
+    f[3] = (underflow   ()) ? 'U' : 'u';
+    f[4] = (overflow    ()) ? 'O' : 'o';
+    f[5] = (zero_divide ()) ? 'Z' : 'z';
+    f[6] = (denormalized()) ? 'D' : 'd';
+    f[7] = (invalid     ()) ? 'I' : 'i';
+    f[8] = '\x0';
+    // output
+    printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
+  }
+
+};
+
+class StatusWord {
+ public:
+  int32_t _value;
+
+  bool busy() const                    { return ((_value >> 15) & 1) != 0; }
+  bool C3() const                      { return ((_value >> 14) & 1) != 0; }
+  bool C2() const                      { return ((_value >> 10) & 1) != 0; }
+  bool C1() const                      { return ((_value >>  9) & 1) != 0; }
+  bool C0() const                      { return ((_value >>  8) & 1) != 0; }
+  int  top() const                     { return  (_value >> 11) & 7      ; }
+  bool error_status() const            { return ((_value >>  7) & 1) != 0; }
+  bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
+  bool precision() const               { return ((_value >>  5) & 1) != 0; }
+  bool underflow() const               { return ((_value >>  4) & 1) != 0; }
+  bool overflow() const                { return ((_value >>  3) & 1) != 0; }
+  bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
+  bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
+  bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
+
+  void print() const {
+    // condition codes
+    char c[5];
+    c[0] = (C3()) ? '3' : '-';
+    c[1] = (C2()) ? '2' : '-';
+    c[2] = (C1()) ? '1' : '-';
+    c[3] = (C0()) ? '0' : '-';
+    c[4] = '\x0';
+    // flags
+    char f[9];
+    f[0] = (error_status()) ? 'E' : '-';
+    f[1] = (stack_fault ()) ? 'S' : '-';
+    f[2] = (precision   ()) ? 'P' : '-';
+    f[3] = (underflow   ()) ? 'U' : '-';
+    f[4] = (overflow    ()) ? 'O' : '-';
+    f[5] = (zero_divide ()) ? 'Z' : '-';
+    f[6] = (denormalized()) ? 'D' : '-';
+    f[7] = (invalid     ()) ? 'I' : '-';
+    f[8] = '\x0';
+    // output
+    printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
+  }
+
+};
+
+class TagWord {
+ public:
+  int32_t _value;
+
+  int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
+
+  void print() const {
+    printf("%04x", _value & 0xFFFF);
+  }
+
+};
+
+class FPU_Register {
+ public:
+  int32_t _m0;
+  int32_t _m1;
+  int16_t _ex;
+
+  bool is_indefinite() const           {
+    return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
+  }
+
+  void print() const {
+    char  sign = (_ex < 0) ? '-' : '+';
+    const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
+    printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
+  };
+
+};
+
+class FPU_State {
+ public:
+  enum {
+    register_size       = 10,
+    number_of_registers =  8,
+    register_mask       =  7
+  };
+
+  ControlWord  _control_word;
+  StatusWord   _status_word;
+  TagWord      _tag_word;
+  int32_t      _error_offset;
+  int32_t      _error_selector;
+  int32_t      _data_offset;
+  int32_t      _data_selector;
+  int8_t       _register[register_size * number_of_registers];
+
+  int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
+  FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
+
+  const char* tag_as_string(int tag) const {
+    switch (tag) {
+      case 0: return "valid";
+      case 1: return "zero";
+      case 2: return "special";
+      case 3: return "empty";
+    }
+    ShouldNotReachHere()
+    return NULL;
+  }
+
+  void print() const {
+    // print computation registers
+    { int t = _status_word.top();
+      for (int i = 0; i < number_of_registers; i++) {
+        int j = (i - t) & register_mask;
+        printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
+        st(j)->print();
+        printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
+      }
+    }
+    printf("\n");
+    // print control registers
+    printf("ctrl = "); _control_word.print(); printf("\n");
+    printf("stat = "); _status_word .print(); printf("\n");
+    printf("tags = "); _tag_word    .print(); printf("\n");
+  }
+
+};
+
+class Flag_Register {
+ public:
+  int32_t _value;
+
+  bool overflow() const                { return ((_value >> 11) & 1) != 0; }
+  bool direction() const               { return ((_value >> 10) & 1) != 0; }
+  bool sign() const                    { return ((_value >>  7) & 1) != 0; }
+  bool zero() const                    { return ((_value >>  6) & 1) != 0; }
+  bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
+  bool parity() const                  { return ((_value >>  2) & 1) != 0; }
+  bool carry() const                   { return ((_value >>  0) & 1) != 0; }
+
+  void print() const {
+    // flags
+    char f[8];
+    f[0] = (overflow       ()) ? 'O' : '-';
+    f[1] = (direction      ()) ? 'D' : '-';
+    f[2] = (sign           ()) ? 'S' : '-';
+    f[3] = (zero           ()) ? 'Z' : '-';
+    f[4] = (auxiliary_carry()) ? 'A' : '-';
+    f[5] = (parity         ()) ? 'P' : '-';
+    f[6] = (carry          ()) ? 'C' : '-';
+    f[7] = '\x0';
+    // output
+    printf("%08x  flags = %s", _value, f);
+  }
+
+};
+
+class IU_Register {
+ public:
+  int32_t _value;
+
+  void print() const {
+    printf("%08x  %11d", _value, _value);
+  }
+
+};
+
+class IU_State {
+ public:
+  Flag_Register _eflags;
+  IU_Register   _rdi;
+  IU_Register   _rsi;
+  IU_Register   _rbp;
+  IU_Register   _rsp;
+  IU_Register   _rbx;
+  IU_Register   _rdx;
+  IU_Register   _rcx;
+  IU_Register   _rax;
+
+  void print() const {
+    // computation registers
+    printf("rax,  = "); _rax.print(); printf("\n");
+    printf("rbx,  = "); _rbx.print(); printf("\n");
+    printf("rcx  = "); _rcx.print(); printf("\n");
+    printf("rdx  = "); _rdx.print(); printf("\n");
+    printf("rdi  = "); _rdi.print(); printf("\n");
+    printf("rsi  = "); _rsi.print(); printf("\n");
+    printf("rbp,  = "); _rbp.print(); printf("\n");
+    printf("rsp  = "); _rsp.print(); printf("\n");
+    printf("\n");
+    // control registers
+    printf("flgs = "); _eflags.print(); printf("\n");
+  }
+};
+
+
+class CPU_State {
+ public:
+  FPU_State _fpu_state;
+  IU_State  _iu_state;
+
+  void print() const {
+    printf("--------------------------------------------------\n");
+    _iu_state .print();
+    printf("\n");
+    _fpu_state.print();
+    printf("--------------------------------------------------\n");
+  }
+
+};
+
+
+static void _print_CPU_state(CPU_State* state) {
+  state->print();
+};
+
+
+void MacroAssembler::print_CPU_state() {
+  push_CPU_state();
+  push(rsp);                // pass CPU state
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
+  addptr(rsp, wordSize);       // discard argument
+  pop_CPU_state();
+}
+
+
+static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
+  static int counter = 0;
+  FPU_State* fs = &state->_fpu_state;
+  counter++;
+  // For leaf calls, only verify that the top few elements remain empty.
+  // We only need 1 empty at the top for C2 code.
+  if( stack_depth < 0 ) {
+    if( fs->tag_for_st(7) != 3 ) {
+      printf("FPR7 not empty\n");
+      state->print();
+      assert(false, "error");
+      return false;
+    }
+    return true;                // All other stack states do not matter
+  }
+
+  assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
+         "bad FPU control word");
+
+  // compute stack depth
+  int i = 0;
+  while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
+  int d = i;
+  while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
+  // verify findings
+  if (i != FPU_State::number_of_registers) {
+    // stack not contiguous
+    printf("%s: stack not contiguous at ST%d\n", s, i);
+    state->print();
+    assert(false, "error");
+    return false;
+  }
+  // check if computed stack depth corresponds to expected stack depth
+  if (stack_depth < 0) {
+    // expected stack depth is -stack_depth or less
+    if (d > -stack_depth) {
+      // too many elements on the stack
+      printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
+      state->print();
+      assert(false, "error");
+      return false;
+    }
+  } else {
+    // expected stack depth is stack_depth
+    if (d != stack_depth) {
+      // wrong stack depth
+      printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
+      state->print();
+      assert(false, "error");
+      return false;
+    }
+  }
+  // everything is cool
+  return true;
+}
+
+
+void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
+  if (!VerifyFPU) return;
+  push_CPU_state();
+  push(rsp);                // pass CPU state
+  ExternalAddress msg((address) s);
+  // pass message string s
+  pushptr(msg.addr());
+  push(stack_depth);        // pass stack depth
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
+  addptr(rsp, 3 * wordSize);   // discard arguments
+  // check for error
+  { Label L;
+    testl(rax, rax);
+    jcc(Assembler::notZero, L);
+    int3();                  // break if error condition
+    bind(L);
+  }
+  pop_CPU_state();
+}
+
+void MacroAssembler::load_klass(Register dst, Register src) {
+#ifdef _LP64
+  if (UseCompressedOops) {
+    movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
+    decode_heap_oop_not_null(dst);
+  } else
+#endif
+    movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
+}
+
+void MacroAssembler::load_prototype_header(Register dst, Register src) {
+#ifdef _LP64
+  if (UseCompressedOops) {
+    movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
+    movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+  } else
+#endif
+    {
+      movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
+      movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+    }
+}
+
+void MacroAssembler::store_klass(Register dst, Register src) {
+#ifdef _LP64
+  if (UseCompressedOops) {
+    encode_heap_oop_not_null(src);
+    movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
+  } else
+#endif
+    movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
+}
+
+#ifdef _LP64
+void MacroAssembler::store_klass_gap(Register dst, Register src) {
+  if (UseCompressedOops) {
+    // Store to klass gap in destination
+    movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
+  }
+}
+
+void MacroAssembler::load_heap_oop(Register dst, Address src) {
+  if (UseCompressedOops) {
+    movl(dst, src);
+    decode_heap_oop(dst);
+  } else {
+    movq(dst, src);
+  }
+}
+
+void MacroAssembler::store_heap_oop(Address dst, Register src) {
+  if (UseCompressedOops) {
+    assert(!dst.uses(src), "not enough registers");
+    encode_heap_oop(src);
+    movl(dst, src);
+  } else {
+    movq(dst, src);
+  }
+}
+
+// Algorithm must match oop.inline.hpp encode_heap_oop.
+void MacroAssembler::encode_heap_oop(Register r) {
+  assert (UseCompressedOops, "should be compressed");
+#ifdef ASSERT
+  if (CheckCompressedOops) {
+    Label ok;
+    push(rscratch1); // cmpptr trashes rscratch1
+    cmpptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
+    jcc(Assembler::equal, ok);
+    stop("MacroAssembler::encode_heap_oop: heap base corrupted?");
+    bind(ok);
+    pop(rscratch1);
+  }
+#endif
+  verify_oop(r, "broken oop in encode_heap_oop");
+  testq(r, r);
+  cmovq(Assembler::equal, r, r12_heapbase);
+  subq(r, r12_heapbase);
+  shrq(r, LogMinObjAlignmentInBytes);
+}
+
+void MacroAssembler::encode_heap_oop_not_null(Register r) {
+  assert (UseCompressedOops, "should be compressed");
+#ifdef ASSERT
+  if (CheckCompressedOops) {
+    Label ok;
+    testq(r, r);
+    jcc(Assembler::notEqual, ok);
+    stop("null oop passed to encode_heap_oop_not_null");
+    bind(ok);
+  }
+#endif
+  verify_oop(r, "broken oop in encode_heap_oop_not_null");
+  subq(r, r12_heapbase);
+  shrq(r, LogMinObjAlignmentInBytes);
+}
+
+void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
+  assert (UseCompressedOops, "should be compressed");
+#ifdef ASSERT
+  if (CheckCompressedOops) {
+    Label ok;
+    testq(src, src);
+    jcc(Assembler::notEqual, ok);
+    stop("null oop passed to encode_heap_oop_not_null2");
+    bind(ok);
+  }
+#endif
+  verify_oop(src, "broken oop in encode_heap_oop_not_null2");
+  if (dst != src) {
+    movq(dst, src);
+  }
+  subq(dst, r12_heapbase);
+  shrq(dst, LogMinObjAlignmentInBytes);
+}
+
+void  MacroAssembler::decode_heap_oop(Register r) {
+  assert (UseCompressedOops, "should be compressed");
+#ifdef ASSERT
+  if (CheckCompressedOops) {
+    Label ok;
+    push(rscratch1);
+    cmpptr(r12_heapbase,
+           ExternalAddress((address)Universe::heap_base_addr()));
+    jcc(Assembler::equal, ok);
+    stop("MacroAssembler::decode_heap_oop: heap base corrupted?");
+    bind(ok);
+    pop(rscratch1);
+  }
+#endif
+
+  Label done;
+  shlq(r, LogMinObjAlignmentInBytes);
+  jccb(Assembler::equal, done);
+  addq(r, r12_heapbase);
+#if 0
+   // alternate decoding probably a wash.
+   testq(r, r);
+   jccb(Assembler::equal, done);
+   leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
+#endif
+  bind(done);
+  verify_oop(r, "broken oop in decode_heap_oop");
+}
+
+void  MacroAssembler::decode_heap_oop_not_null(Register r) {
+  assert (UseCompressedOops, "should only be used for compressed headers");
+  // Cannot assert, unverified entry point counts instructions (see .ad file)
+  // vtableStubs also counts instructions in pd_code_size_limit.
+  // Also do not verify_oop as this is called by verify_oop.
+  assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong");
+  leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
+}
+
+void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
+  assert (UseCompressedOops, "should only be used for compressed headers");
+  // Cannot assert, unverified entry point counts instructions (see .ad file)
+  // vtableStubs also counts instructions in pd_code_size_limit.
+  // Also do not verify_oop as this is called by verify_oop.
+  assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong");
+  leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
+}
+
+void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
+  assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
+  int oop_index = oop_recorder()->find_index(obj);
+  RelocationHolder rspec = oop_Relocation::spec(oop_index);
+  mov_literal32(dst, oop_index, rspec, narrow_oop_operand);
+}
+
+void MacroAssembler::reinit_heapbase() {
+  if (UseCompressedOops) {
+    movptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
+  }
+}
+#endif // _LP64
+
+Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
+  switch (cond) {
+    // Note some conditions are synonyms for others
+    case Assembler::zero:         return Assembler::notZero;
+    case Assembler::notZero:      return Assembler::zero;
+    case Assembler::less:         return Assembler::greaterEqual;
+    case Assembler::lessEqual:    return Assembler::greater;
+    case Assembler::greater:      return Assembler::lessEqual;
+    case Assembler::greaterEqual: return Assembler::less;
+    case Assembler::below:        return Assembler::aboveEqual;
+    case Assembler::belowEqual:   return Assembler::above;
+    case Assembler::above:        return Assembler::belowEqual;
+    case Assembler::aboveEqual:   return Assembler::below;
+    case Assembler::overflow:     return Assembler::noOverflow;
+    case Assembler::noOverflow:   return Assembler::overflow;
+    case Assembler::negative:     return Assembler::positive;
+    case Assembler::positive:     return Assembler::negative;
+    case Assembler::parity:       return Assembler::noParity;
+    case Assembler::noParity:     return Assembler::parity;
+  }
+  ShouldNotReachHere(); return Assembler::overflow;
+}
+
+SkipIfEqual::SkipIfEqual(
+    MacroAssembler* masm, const bool* flag_addr, bool value) {
+  _masm = masm;
+  _masm->cmp8(ExternalAddress((address)flag_addr), value);
+  _masm->jcc(Assembler::equal, _label);
+}
+
+SkipIfEqual::~SkipIfEqual() {
+  _masm->bind(_label);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,2044 @@
+/*
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+class BiasedLockingCounters;
+
+// Contains all the definitions needed for x86 assembly code generation.
+
+// Calling convention
+class Argument VALUE_OBJ_CLASS_SPEC {
+ public:
+  enum {
+#ifdef _LP64
+#ifdef _WIN64
+    n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
+    n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
+#else
+    n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
+    n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
+#endif // _WIN64
+    n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
+    n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
+#else
+    n_register_parameters = 0   // 0 registers used to pass arguments
+#endif // _LP64
+  };
+};
+
+
+#ifdef _LP64
+// Symbolically name the register arguments used by the c calling convention.
+// Windows is different from linux/solaris. So much for standards...
+
+#ifdef _WIN64
+
+REGISTER_DECLARATION(Register, c_rarg0, rcx);
+REGISTER_DECLARATION(Register, c_rarg1, rdx);
+REGISTER_DECLARATION(Register, c_rarg2, r8);
+REGISTER_DECLARATION(Register, c_rarg3, r9);
+
+REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
+
+#else
+
+REGISTER_DECLARATION(Register, c_rarg0, rdi);
+REGISTER_DECLARATION(Register, c_rarg1, rsi);
+REGISTER_DECLARATION(Register, c_rarg2, rdx);
+REGISTER_DECLARATION(Register, c_rarg3, rcx);
+REGISTER_DECLARATION(Register, c_rarg4, r8);
+REGISTER_DECLARATION(Register, c_rarg5, r9);
+
+REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
+REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
+REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
+REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
+REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
+
+#endif // _WIN64
+
+// Symbolically name the register arguments used by the Java calling convention.
+// We have control over the convention for java so we can do what we please.
+// What pleases us is to offset the java calling convention so that when
+// we call a suitable jni method the arguments are lined up and we don't
+// have to do little shuffling. A suitable jni method is non-static and a
+// small number of arguments (two fewer args on windows)
+//
+//        |-------------------------------------------------------|
+//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
+//        |-------------------------------------------------------|
+//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
+//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
+//        |-------------------------------------------------------|
+//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
+//        |-------------------------------------------------------|
+
+REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
+REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
+REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
+// Windows runs out of register args here
+#ifdef _WIN64
+REGISTER_DECLARATION(Register, j_rarg3, rdi);
+REGISTER_DECLARATION(Register, j_rarg4, rsi);
+#else
+REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
+REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
+#endif /* _WIN64 */
+REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
+
+REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
+REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
+REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
+REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
+REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
+
+REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
+REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
+
+REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
+REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
+
+#else
+// rscratch1 will apear in 32bit code that is dead but of course must compile
+// Using noreg ensures if the dead code is incorrectly live and executed it
+// will cause an assertion failure
+#define rscratch1 noreg
+
+#endif // _LP64
+
+// Address is an abstraction used to represent a memory location
+// using any of the amd64 addressing modes with one object.
+//
+// Note: A register location is represented via a Register, not
+//       via an address for efficiency & simplicity reasons.
+
+class ArrayAddress;
+
+class Address VALUE_OBJ_CLASS_SPEC {
+ public:
+  enum ScaleFactor {
+    no_scale = -1,
+    times_1  =  0,
+    times_2  =  1,
+    times_4  =  2,
+    times_8  =  3,
+    times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
+  };
+
+ private:
+  Register         _base;
+  Register         _index;
+  ScaleFactor      _scale;
+  int              _disp;
+  RelocationHolder _rspec;
+
+  // Easily misused constructors make them private
+  // %%% can we make these go away?
+  NOT_LP64(Address(address loc, RelocationHolder spec);)
+  Address(int disp, address loc, relocInfo::relocType rtype);
+  Address(int disp, address loc, RelocationHolder spec);
+
+ public:
+
+ int disp() { return _disp; }
+  // creation
+  Address()
+    : _base(noreg),
+      _index(noreg),
+      _scale(no_scale),
+      _disp(0) {
+  }
+
+  // No default displacement otherwise Register can be implicitly
+  // converted to 0(Register) which is quite a different animal.
+
+  Address(Register base, int disp)
+    : _base(base),
+      _index(noreg),
+      _scale(no_scale),
+      _disp(disp) {
+  }
+
+  Address(Register base, Register index, ScaleFactor scale, int disp = 0)
+    : _base (base),
+      _index(index),
+      _scale(scale),
+      _disp (disp) {
+    assert(!index->is_valid() == (scale == Address::no_scale),
+           "inconsistent address");
+  }
+
+  // The following two overloads are used in connection with the
+  // ByteSize type (see sizes.hpp).  They simplify the use of
+  // ByteSize'd arguments in assembly code. Note that their equivalent
+  // for the optimized build are the member functions with int disp
+  // argument since ByteSize is mapped to an int type in that case.
+  //
+  // Note: DO NOT introduce similar overloaded functions for WordSize
+  // arguments as in the optimized mode, both ByteSize and WordSize
+  // are mapped to the same type and thus the compiler cannot make a
+  // distinction anymore (=> compiler errors).
+
+#ifdef ASSERT
+  Address(Register base, ByteSize disp)
+    : _base(base),
+      _index(noreg),
+      _scale(no_scale),
+      _disp(in_bytes(disp)) {
+  }
+
+  Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
+    : _base(base),
+      _index(index),
+      _scale(scale),
+      _disp(in_bytes(disp)) {
+    assert(!index->is_valid() == (scale == Address::no_scale),
+           "inconsistent address");
+  }
+#endif // ASSERT
+
+  // accessors
+  bool uses(Register reg) const {
+    return _base == reg || _index == reg;
+  }
+
+  // Convert the raw encoding form into the form expected by the constructor for
+  // Address.  An index of 4 (rsp) corresponds to having no index, so convert
+  // that to noreg for the Address constructor.
+  static Address make_raw(int base, int index, int scale, int disp);
+
+  static Address make_array(ArrayAddress);
+
+
+ private:
+  bool base_needs_rex() const {
+    return _base != noreg && _base->encoding() >= 8;
+  }
+
+  bool index_needs_rex() const {
+    return _index != noreg &&_index->encoding() >= 8;
+  }
+
+  relocInfo::relocType reloc() const { return _rspec.type(); }
+
+  friend class Assembler;
+  friend class MacroAssembler;
+  friend class LIR_Assembler; // base/index/scale/disp
+};
+
+//
+// AddressLiteral has been split out from Address because operands of this type
+// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
+// the few instructions that need to deal with address literals are unique and the
+// MacroAssembler does not have to implement every instruction in the Assembler
+// in order to search for address literals that may need special handling depending
+// on the instruction and the platform. As small step on the way to merging i486/amd64
+// directories.
+//
+class AddressLiteral VALUE_OBJ_CLASS_SPEC {
+  friend class ArrayAddress;
+  RelocationHolder _rspec;
+  // Typically we use AddressLiterals we want to use their rval
+  // However in some situations we want the lval (effect address) of the item.
+  // We provide a special factory for making those lvals.
+  bool _is_lval;
+
+  // If the target is far we'll need to load the ea of this to
+  // a register to reach it. Otherwise if near we can do rip
+  // relative addressing.
+
+  address          _target;
+
+ protected:
+  // creation
+  AddressLiteral()
+    : _is_lval(false),
+      _target(NULL)
+  {}
+
+  public:
+
+
+  AddressLiteral(address target, relocInfo::relocType rtype);
+
+  AddressLiteral(address target, RelocationHolder const& rspec)
+    : _rspec(rspec),
+      _is_lval(false),
+      _target(target)
+  {}
+
+  AddressLiteral addr() {
+    AddressLiteral ret = *this;
+    ret._is_lval = true;
+    return ret;
+  }
+
+
+ private:
+
+  address target() { return _target; }
+  bool is_lval() { return _is_lval; }
+
+  relocInfo::relocType reloc() const { return _rspec.type(); }
+  const RelocationHolder& rspec() const { return _rspec; }
+
+  friend class Assembler;
+  friend class MacroAssembler;
+  friend class Address;
+  friend class LIR_Assembler;
+};
+
+// Convience classes
+class RuntimeAddress: public AddressLiteral {
+
+  public:
+
+  RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
+
+};
+
+class OopAddress: public AddressLiteral {
+
+  public:
+
+  OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
+
+};
+
+class ExternalAddress: public AddressLiteral {
+
+  public:
+
+  ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
+
+};
+
+class InternalAddress: public AddressLiteral {
+
+  public:
+
+  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
+
+};
+
+// x86 can do array addressing as a single operation since disp can be an absolute
+// address amd64 can't. We create a class that expresses the concept but does extra
+// magic on amd64 to get the final result
+
+class ArrayAddress VALUE_OBJ_CLASS_SPEC {
+  private:
+
+  AddressLiteral _base;
+  Address        _index;
+
+  public:
+
+  ArrayAddress() {};
+  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
+  AddressLiteral base() { return _base; }
+  Address index() { return _index; }
+
+};
+
+const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
+
+// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
+// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
+// is what you get. The Assembler is generating code into a CodeBuffer.
+
+class Assembler : public AbstractAssembler  {
+  friend class AbstractAssembler; // for the non-virtual hack
+  friend class LIR_Assembler; // as_Address()
+  friend class StubGenerator;
+
+ public:
+  enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
+    zero          = 0x4,
+    notZero       = 0x5,
+    equal         = 0x4,
+    notEqual      = 0x5,
+    less          = 0xc,
+    lessEqual     = 0xe,
+    greater       = 0xf,
+    greaterEqual  = 0xd,
+    below         = 0x2,
+    belowEqual    = 0x6,
+    above         = 0x7,
+    aboveEqual    = 0x3,
+    overflow      = 0x0,
+    noOverflow    = 0x1,
+    carrySet      = 0x2,
+    carryClear    = 0x3,
+    negative      = 0x8,
+    positive      = 0x9,
+    parity        = 0xa,
+    noParity      = 0xb
+  };
+
+  enum Prefix {
+    // segment overrides
+    CS_segment = 0x2e,
+    SS_segment = 0x36,
+    DS_segment = 0x3e,
+    ES_segment = 0x26,
+    FS_segment = 0x64,
+    GS_segment = 0x65,
+
+    REX        = 0x40,
+
+    REX_B      = 0x41,
+    REX_X      = 0x42,
+    REX_XB     = 0x43,
+    REX_R      = 0x44,
+    REX_RB     = 0x45,
+    REX_RX     = 0x46,
+    REX_RXB    = 0x47,
+
+    REX_W      = 0x48,
+
+    REX_WB     = 0x49,
+    REX_WX     = 0x4A,
+    REX_WXB    = 0x4B,
+    REX_WR     = 0x4C,
+    REX_WRB    = 0x4D,
+    REX_WRX    = 0x4E,
+    REX_WRXB   = 0x4F
+  };
+
+  enum WhichOperand {
+    // input to locate_operand, and format code for relocations
+    imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
+    disp32_operand = 1,          // embedded 32-bit displacement or address
+    call32_operand = 2,          // embedded 32-bit self-relative displacement
+#ifndef _LP64
+    _WhichOperand_limit = 3
+#else
+     narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
+    _WhichOperand_limit = 4
+#endif
+  };
+
+
+
+  // NOTE: The general philopsophy of the declarations here is that 64bit versions
+  // of instructions are freely declared without the need for wrapping them an ifdef.
+  // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
+  // In the .cpp file the implementations are wrapped so that they are dropped out
+  // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
+  // to the size it was prior to merging up the 32bit and 64bit assemblers.
+  //
+  // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
+  // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
+
+private:
+
+
+  // 64bit prefixes
+  int prefix_and_encode(int reg_enc, bool byteinst = false);
+  int prefixq_and_encode(int reg_enc);
+
+  int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
+  int prefixq_and_encode(int dst_enc, int src_enc);
+
+  void prefix(Register reg);
+  void prefix(Address adr);
+  void prefixq(Address adr);
+
+  void prefix(Address adr, Register reg,  bool byteinst = false);
+  void prefixq(Address adr, Register reg);
+
+  void prefix(Address adr, XMMRegister reg);
+
+  void prefetch_prefix(Address src);
+
+  // Helper functions for groups of instructions
+  void emit_arith_b(int op1, int op2, Register dst, int imm8);
+
+  void emit_arith(int op1, int op2, Register dst, int32_t imm32);
+  // only 32bit??
+  void emit_arith(int op1, int op2, Register dst, jobject obj);
+  void emit_arith(int op1, int op2, Register dst, Register src);
+
+  void emit_operand(Register reg,
+                    Register base, Register index, Address::ScaleFactor scale,
+                    int disp,
+                    RelocationHolder const& rspec,
+                    int rip_relative_correction = 0);
+
+  void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
+
+  // operands that only take the original 32bit registers
+  void emit_operand32(Register reg, Address adr);
+
+  void emit_operand(XMMRegister reg,
+                    Register base, Register index, Address::ScaleFactor scale,
+                    int disp,
+                    RelocationHolder const& rspec);
+
+  void emit_operand(XMMRegister reg, Address adr);
+
+  void emit_operand(MMXRegister reg, Address adr);
+
+  // workaround gcc (3.2.1-7) bug
+  void emit_operand(Address adr, MMXRegister reg);
+
+
+  // Immediate-to-memory forms
+  void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
+
+  void emit_farith(int b1, int b2, int i);
+
+
+ protected:
+  #ifdef ASSERT
+  void check_relocation(RelocationHolder const& rspec, int format);
+  #endif
+
+  inline void emit_long64(jlong x);
+
+  void emit_data(jint data, relocInfo::relocType    rtype, int format);
+  void emit_data(jint data, RelocationHolder const& rspec, int format);
+  void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
+  void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
+
+
+  bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
+
+  // These are all easily abused and hence protected
+
+  void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
+
+  // 32BIT ONLY SECTION
+#ifndef _LP64
+  // Make these disappear in 64bit mode since they would never be correct
+  void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
+  void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
+
+  void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
+
+  void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
+#else
+  // 64BIT ONLY SECTION
+  void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
+#endif // _LP64
+
+  // These are unique in that we are ensured by the caller that the 32bit
+  // relative in these instructions will always be able to reach the potentially
+  // 64bit address described by entry. Since they can take a 64bit address they
+  // don't have the 32 suffix like the other instructions in this class.
+
+  void call_literal(address entry, RelocationHolder const& rspec);
+  void jmp_literal(address entry, RelocationHolder const& rspec);
+
+  // Avoid using directly section
+  // Instructions in this section are actually usable by anyone without danger
+  // of failure but have performance issues that are addressed my enhanced
+  // instructions which will do the proper thing base on the particular cpu.
+  // We protect them because we don't trust you...
+
+  // Don't use next inc() and dec() methods directly. INC & DEC instructions
+  // could cause a partial flag stall since they don't set CF flag.
+  // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
+  // which call inc() & dec() or add() & sub() in accordance with
+  // the product flag UseIncDec value.
+
+  void decl(Register dst);
+  void decl(Address dst);
+  void decq(Register dst);
+  void decq(Address dst);
+
+  void incl(Register dst);
+  void incl(Address dst);
+  void incq(Register dst);
+  void incq(Address dst);
+
+  // New cpus require use of movsd and movss to avoid partial register stall
+  // when loading from memory. But for old Opteron use movlpd instead of movsd.
+  // The selection is done in MacroAssembler::movdbl() and movflt().
+
+  // Move Scalar Single-Precision Floating-Point Values
+  void movss(XMMRegister dst, Address src);
+  void movss(XMMRegister dst, XMMRegister src);
+  void movss(Address dst, XMMRegister src);
+
+  // Move Scalar Double-Precision Floating-Point Values
+  void movsd(XMMRegister dst, Address src);
+  void movsd(XMMRegister dst, XMMRegister src);
+  void movsd(Address dst, XMMRegister src);
+  void movlpd(XMMRegister dst, Address src);
+
+  // New cpus require use of movaps and movapd to avoid partial register stall
+  // when moving between registers.
+  void movaps(XMMRegister dst, XMMRegister src);
+  void movapd(XMMRegister dst, XMMRegister src);
+
+  // End avoid using directly
+
+
+  // Instruction prefixes
+  void prefix(Prefix p);
+
+  public:
+
+  // Creation
+  Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
+
+  // Decoding
+  static address locate_operand(address inst, WhichOperand which);
+  static address locate_next_instruction(address inst);
+
+  // Utilities
+
+#ifdef _LP64
+ static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) )  <= x   &&   x  <  ( CONST64(1) << (nbits-1) ); }
+ static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
+#else
+ static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) )  <= x   &&   x  <  ( 1 << (nbits-1) ); }
+ static bool is_simm32(int32_t x) { return true; }
+#endif // LP64
+
+  // Generic instructions
+  // Does 32bit or 64bit as needed for the platform. In some sense these
+  // belong in macro assembler but there is no need for both varieties to exist
+
+  void lea(Register dst, Address src);
+
+  void mov(Register dst, Register src);
+
+  void pusha();
+  void popa();
+
+  void pushf();
+  void popf();
+
+  void push(int32_t imm32);
+
+  void push(Register src);
+
+  void pop(Register dst);
+
+  // These are dummies to prevent surprise implicit conversions to Register
+  void push(void* v);
+  void pop(void* v);
+
+
+  // These do register sized moves/scans
+  void rep_mov();
+  void rep_set();
+  void repne_scan();
+#ifdef _LP64
+  void repne_scanl();
+#endif
+
+  // Vanilla instructions in lexical order
+
+  void adcl(Register dst, int32_t imm32);
+  void adcl(Register dst, Address src);
+  void adcl(Register dst, Register src);
+
+  void adcq(Register dst, int32_t imm32);
+  void adcq(Register dst, Address src);
+  void adcq(Register dst, Register src);
+
+
+  void addl(Address dst, int32_t imm32);
+  void addl(Address dst, Register src);
+  void addl(Register dst, int32_t imm32);
+  void addl(Register dst, Address src);
+  void addl(Register dst, Register src);
+
+  void addq(Address dst, int32_t imm32);
+  void addq(Address dst, Register src);
+  void addq(Register dst, int32_t imm32);
+  void addq(Register dst, Address src);
+  void addq(Register dst, Register src);
+
+
+  void addr_nop_4();
+  void addr_nop_5();
+  void addr_nop_7();
+  void addr_nop_8();
+
+  // Add Scalar Double-Precision Floating-Point Values
+  void addsd(XMMRegister dst, Address src);
+  void addsd(XMMRegister dst, XMMRegister src);
+
+  // Add Scalar Single-Precision Floating-Point Values
+  void addss(XMMRegister dst, Address src);
+  void addss(XMMRegister dst, XMMRegister src);
+
+  void andl(Register dst, int32_t imm32);
+  void andl(Register dst, Address src);
+  void andl(Register dst, Register src);
+
+  void andq(Register dst, int32_t imm32);
+  void andq(Register dst, Address src);
+  void andq(Register dst, Register src);
+
+
+  // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
+  void andpd(XMMRegister dst, Address src);
+  void andpd(XMMRegister dst, XMMRegister src);
+
+  void bswapl(Register reg);
+
+  void bswapq(Register reg);
+
+  void call(Label& L, relocInfo::relocType rtype);
+  void call(Register reg);  // push pc; pc <- reg
+  void call(Address adr);   // push pc; pc <- adr
+
+  void cdql();
+
+  void cdqq();
+
+  void cld() { emit_byte(0xfc); }
+
+  void clflush(Address adr);
+
+  void cmovl(Condition cc, Register dst, Register src);
+  void cmovl(Condition cc, Register dst, Address src);
+
+  void cmovq(Condition cc, Register dst, Register src);
+  void cmovq(Condition cc, Register dst, Address src);
+
+
+  void cmpb(Address dst, int imm8);
+
+  void cmpl(Address dst, int32_t imm32);
+
+  void cmpl(Register dst, int32_t imm32);
+  void cmpl(Register dst, Register src);
+  void cmpl(Register dst, Address src);
+
+  void cmpq(Address dst, int32_t imm32);
+  void cmpq(Address dst, Register src);
+
+  void cmpq(Register dst, int32_t imm32);
+  void cmpq(Register dst, Register src);
+  void cmpq(Register dst, Address src);
+
+  // these are dummies used to catch attempting to convert NULL to Register
+  void cmpl(Register dst, void* junk); // dummy
+  void cmpq(Register dst, void* junk); // dummy
+
+  void cmpw(Address dst, int imm16);
+
+  void cmpxchg8 (Address adr);
+
+  void cmpxchgl(Register reg, Address adr);
+
+  void cmpxchgq(Register reg, Address adr);
+
+  // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
+  void comisd(XMMRegister dst, Address src);
+
+  // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
+  void comiss(XMMRegister dst, Address src);
+
+  // Identify processor type and features
+  void cpuid() {
+    emit_byte(0x0F);
+    emit_byte(0xA2);
+  }
+
+  // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
+  void cvtsd2ss(XMMRegister dst, XMMRegister src);
+
+  // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
+  void cvtsi2sdl(XMMRegister dst, Register src);
+  void cvtsi2sdq(XMMRegister dst, Register src);
+
+  // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
+  void cvtsi2ssl(XMMRegister dst, Register src);
+  void cvtsi2ssq(XMMRegister dst, Register src);
+
+  // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
+  void cvtdq2pd(XMMRegister dst, XMMRegister src);
+
+  // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
+  void cvtdq2ps(XMMRegister dst, XMMRegister src);
+
+  // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
+  void cvtss2sd(XMMRegister dst, XMMRegister src);
+
+  // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
+  void cvttsd2sil(Register dst, Address src);
+  void cvttsd2sil(Register dst, XMMRegister src);
+  void cvttsd2siq(Register dst, XMMRegister src);
+
+  // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
+  void cvttss2sil(Register dst, XMMRegister src);
+  void cvttss2siq(Register dst, XMMRegister src);
+
+  // Divide Scalar Double-Precision Floating-Point Values
+  void divsd(XMMRegister dst, Address src);
+  void divsd(XMMRegister dst, XMMRegister src);
+
+  // Divide Scalar Single-Precision Floating-Point Values
+  void divss(XMMRegister dst, Address src);
+  void divss(XMMRegister dst, XMMRegister src);
+
+  void emms();
+
+  void fabs();
+
+  void fadd(int i);
+
+  void fadd_d(Address src);
+  void fadd_s(Address src);
+
+  // "Alternate" versions of x87 instructions place result down in FPU
+  // stack instead of on TOS
+
+  void fadda(int i); // "alternate" fadd
+  void faddp(int i = 1);
+
+  void fchs();
+
+  void fcom(int i);
+
+  void fcomp(int i = 1);
+  void fcomp_d(Address src);
+  void fcomp_s(Address src);
+
+  void fcompp();
+
+  void fcos();
+
+  void fdecstp();
+
+  void fdiv(int i);
+  void fdiv_d(Address src);
+  void fdivr_s(Address src);
+  void fdiva(int i);  // "alternate" fdiv
+  void fdivp(int i = 1);
+
+  void fdivr(int i);
+  void fdivr_d(Address src);
+  void fdiv_s(Address src);
+
+  void fdivra(int i); // "alternate" reversed fdiv
+
+  void fdivrp(int i = 1);
+
+  void ffree(int i = 0);
+
+  void fild_d(Address adr);
+  void fild_s(Address adr);
+
+  void fincstp();
+
+  void finit();
+
+  void fist_s (Address adr);
+  void fistp_d(Address adr);
+  void fistp_s(Address adr);
+
+  void fld1();
+
+  void fld_d(Address adr);
+  void fld_s(Address adr);
+  void fld_s(int index);
+  void fld_x(Address adr);  // extended-precision (80-bit) format
+
+  void fldcw(Address src);
+
+  void fldenv(Address src);
+
+  void fldlg2();
+
+  void fldln2();
+
+  void fldz();
+
+  void flog();
+  void flog10();
+
+  void fmul(int i);
+
+  void fmul_d(Address src);
+  void fmul_s(Address src);
+
+  void fmula(int i);  // "alternate" fmul
+
+  void fmulp(int i = 1);
+
+  void fnsave(Address dst);
+
+  void fnstcw(Address src);
+
+  void fnstsw_ax();
+
+  void fprem();
+  void fprem1();
+
+  void frstor(Address src);
+
+  void fsin();
+
+  void fsqrt();
+
+  void fst_d(Address adr);
+  void fst_s(Address adr);
+
+  void fstp_d(Address adr);
+  void fstp_d(int index);
+  void fstp_s(Address adr);
+  void fstp_x(Address adr); // extended-precision (80-bit) format
+
+  void fsub(int i);
+  void fsub_d(Address src);
+  void fsub_s(Address src);
+
+  void fsuba(int i);  // "alternate" fsub
+
+  void fsubp(int i = 1);
+
+  void fsubr(int i);
+  void fsubr_d(Address src);
+  void fsubr_s(Address src);
+
+  void fsubra(int i); // "alternate" reversed fsub
+
+  void fsubrp(int i = 1);
+
+  void ftan();
+
+  void ftst();
+
+  void fucomi(int i = 1);
+  void fucomip(int i = 1);
+
+  void fwait();
+
+  void fxch(int i = 1);
+
+  void fxrstor(Address src);
+
+  void fxsave(Address dst);
+
+  void fyl2x();
+
+  void hlt();
+
+  void idivl(Register src);
+
+  void idivq(Register src);
+
+  void imull(Register dst, Register src);
+  void imull(Register dst, Register src, int value);
+
+  void imulq(Register dst, Register src);
+  void imulq(Register dst, Register src, int value);
+
+
+  // jcc is the generic conditional branch generator to run-
+  // time routines, jcc is used for branches to labels. jcc
+  // takes a branch opcode (cc) and a label (L) and generates
+  // either a backward branch or a forward branch and links it
+  // to the label fixup chain. Usage:
+  //
+  // Label L;      // unbound label
+  // jcc(cc, L);   // forward branch to unbound label
+  // bind(L);      // bind label to the current pc
+  // jcc(cc, L);   // backward branch to bound label
+  // bind(L);      // illegal: a label may be bound only once
+  //
+  // Note: The same Label can be used for forward and backward branches
+  // but it may be bound only once.
+
+  void jcc(Condition cc, Label& L,
+           relocInfo::relocType rtype = relocInfo::none);
+
+  // Conditional jump to a 8-bit offset to L.
+  // WARNING: be very careful using this for forward jumps.  If the label is
+  // not bound within an 8-bit offset of this instruction, a run-time error
+  // will occur.
+  void jccb(Condition cc, Label& L);
+
+  void jmp(Address entry);    // pc <- entry
+
+  // Label operations & relative jumps (PPUM Appendix D)
+  void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);   // unconditional jump to L
+
+  void jmp(Register entry); // pc <- entry
+
+  // Unconditional 8-bit offset jump to L.
+  // WARNING: be very careful using this for forward jumps.  If the label is
+  // not bound within an 8-bit offset of this instruction, a run-time error
+  // will occur.
+  void jmpb(Label& L);
+
+  void ldmxcsr( Address src );
+
+  void leal(Register dst, Address src);
+
+  void leaq(Register dst, Address src);
+
+  void lfence() {
+    emit_byte(0x0F);
+    emit_byte(0xAE);
+    emit_byte(0xE8);
+  }
+
+  void lock();
+
+  enum Membar_mask_bits {
+    StoreStore = 1 << 3,
+    LoadStore  = 1 << 2,
+    StoreLoad  = 1 << 1,
+    LoadLoad   = 1 << 0
+  };
+
+  // Serializes memory.
+  void membar(Membar_mask_bits order_constraint) {
+    // We only have to handle StoreLoad and LoadLoad
+    if (order_constraint & StoreLoad) {
+      // MFENCE subsumes LFENCE
+      mfence();
+    } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
+         lfence();
+    } */
+  }
+
+  void mfence();
+
+  // Moves
+
+  void mov64(Register dst, int64_t imm64);
+
+  void movb(Address dst, Register src);
+  void movb(Address dst, int imm8);
+  void movb(Register dst, Address src);
+
+  void movdl(XMMRegister dst, Register src);
+  void movdl(Register dst, XMMRegister src);
+
+  // Move Double Quadword
+  void movdq(XMMRegister dst, Register src);
+  void movdq(Register dst, XMMRegister src);
+
+  // Move Aligned Double Quadword
+  void movdqa(Address     dst, XMMRegister src);
+  void movdqa(XMMRegister dst, Address src);
+  void movdqa(XMMRegister dst, XMMRegister src);
+
+  void movl(Register dst, int32_t imm32);
+  void movl(Address dst, int32_t imm32);
+  void movl(Register dst, Register src);
+  void movl(Register dst, Address src);
+  void movl(Address dst, Register src);
+
+  // These dummies prevent using movl from converting a zero (like NULL) into Register
+  // by giving the compiler two choices it can't resolve
+
+  void movl(Address  dst, void* junk);
+  void movl(Register dst, void* junk);
+
+#ifdef _LP64
+  void movq(Register dst, Register src);
+  void movq(Register dst, Address src);
+  void movq(Address dst, Register src);
+#endif
+
+  void movq(Address     dst, MMXRegister src );
+  void movq(MMXRegister dst, Address src );
+
+#ifdef _LP64
+  // These dummies prevent using movq from converting a zero (like NULL) into Register
+  // by giving the compiler two choices it can't resolve
+
+  void movq(Address  dst, void* dummy);
+  void movq(Register dst, void* dummy);
+#endif
+
+  // Move Quadword
+  void movq(Address     dst, XMMRegister src);
+  void movq(XMMRegister dst, Address src);
+
+  void movsbl(Register dst, Address src);
+  void movsbl(Register dst, Register src);
+
+#ifdef _LP64
+  // Move signed 32bit immediate to 64bit extending sign
+  void movslq(Address dst, int32_t imm64);
+  void movslq(Register dst, int32_t imm64);
+
+  void movslq(Register dst, Address src);
+  void movslq(Register dst, Register src);
+  void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
+#endif
+
+  void movswl(Register dst, Address src);
+  void movswl(Register dst, Register src);
+
+  void movw(Address dst, int imm16);
+  void movw(Register dst, Address src);
+  void movw(Address dst, Register src);
+
+  void movzbl(Register dst, Address src);
+  void movzbl(Register dst, Register src);
+
+  void movzwl(Register dst, Address src);
+  void movzwl(Register dst, Register src);
+
+  void mull(Address src);
+  void mull(Register src);
+
+  // Multiply Scalar Double-Precision Floating-Point Values
+  void mulsd(XMMRegister dst, Address src);
+  void mulsd(XMMRegister dst, XMMRegister src);
+
+  // Multiply Scalar Single-Precision Floating-Point Values
+  void mulss(XMMRegister dst, Address src);
+  void mulss(XMMRegister dst, XMMRegister src);
+
+  void negl(Register dst);
+
+#ifdef _LP64
+  void negq(Register dst);
+#endif
+
+  void nop(int i = 1);
+
+  void notl(Register dst);
+
+#ifdef _LP64
+  void notq(Register dst);
+#endif
+
+  void orl(Address dst, int32_t imm32);
+  void orl(Register dst, int32_t imm32);
+  void orl(Register dst, Address src);
+  void orl(Register dst, Register src);
+
+  void orq(Address dst, int32_t imm32);
+  void orq(Register dst, int32_t imm32);
+  void orq(Register dst, Address src);
+  void orq(Register dst, Register src);
+
+  void popl(Address dst);
+
+#ifdef _LP64
+  void popq(Address dst);
+#endif
+
+  // Prefetches (SSE, SSE2, 3DNOW only)
+
+  void prefetchnta(Address src);
+  void prefetchr(Address src);
+  void prefetcht0(Address src);
+  void prefetcht1(Address src);
+  void prefetcht2(Address src);
+  void prefetchw(Address src);
+
+  // Shuffle Packed Doublewords
+  void pshufd(XMMRegister dst, XMMRegister src, int mode);
+  void pshufd(XMMRegister dst, Address src,     int mode);
+
+  // Shuffle Packed Low Words
+  void pshuflw(XMMRegister dst, XMMRegister src, int mode);
+  void pshuflw(XMMRegister dst, Address src,     int mode);
+
+  // Shift Right Logical Quadword Immediate
+  void psrlq(XMMRegister dst, int shift);
+
+  // Interleave Low Bytes
+  void punpcklbw(XMMRegister dst, XMMRegister src);
+
+  void pushl(Address src);
+
+  void pushq(Address src);
+
+  // Xor Packed Byte Integer Values
+  void pxor(XMMRegister dst, Address src);
+  void pxor(XMMRegister dst, XMMRegister src);
+
+  void rcll(Register dst, int imm8);
+
+  void rclq(Register dst, int imm8);
+
+  void ret(int imm16);
+
+  void sahf();
+
+  void sarl(Register dst, int imm8);
+  void sarl(Register dst);
+
+  void sarq(Register dst, int imm8);
+  void sarq(Register dst);
+
+  void sbbl(Address dst, int32_t imm32);
+  void sbbl(Register dst, int32_t imm32);
+  void sbbl(Register dst, Address src);
+  void sbbl(Register dst, Register src);
+
+  void sbbq(Address dst, int32_t imm32);
+  void sbbq(Register dst, int32_t imm32);
+  void sbbq(Register dst, Address src);
+  void sbbq(Register dst, Register src);
+
+  void setb(Condition cc, Register dst);
+
+  void shldl(Register dst, Register src);
+
+  void shll(Register dst, int imm8);
+  void shll(Register dst);
+
+  void shlq(Register dst, int imm8);
+  void shlq(Register dst);
+
+  void shrdl(Register dst, Register src);
+
+  void shrl(Register dst, int imm8);
+  void shrl(Register dst);
+
+  void shrq(Register dst, int imm8);
+  void shrq(Register dst);
+
+  void smovl(); // QQQ generic?
+
+  // Compute Square Root of Scalar Double-Precision Floating-Point Value
+  void sqrtsd(XMMRegister dst, Address src);
+  void sqrtsd(XMMRegister dst, XMMRegister src);
+
+  void std() { emit_byte(0xfd); }
+
+  void stmxcsr( Address dst );
+
+  void subl(Address dst, int32_t imm32);
+  void subl(Address dst, Register src);
+  void subl(Register dst, int32_t imm32);
+  void subl(Register dst, Address src);
+  void subl(Register dst, Register src);
+
+  void subq(Address dst, int32_t imm32);
+  void subq(Address dst, Register src);
+  void subq(Register dst, int32_t imm32);
+  void subq(Register dst, Address src);
+  void subq(Register dst, Register src);
+
+
+  // Subtract Scalar Double-Precision Floating-Point Values
+  void subsd(XMMRegister dst, Address src);
+  void subsd(XMMRegister dst, XMMRegister src);
+
+  // Subtract Scalar Single-Precision Floating-Point Values
+  void subss(XMMRegister dst, Address src);
+  void subss(XMMRegister dst, XMMRegister src);
+
+  void testb(Register dst, int imm8);
+
+  void testl(Register dst, int32_t imm32);
+  void testl(Register dst, Register src);
+  void testl(Register dst, Address src);
+
+  void testq(Register dst, int32_t imm32);
+  void testq(Register dst, Register src);
+
+
+  // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
+  void ucomisd(XMMRegister dst, Address src);
+  void ucomisd(XMMRegister dst, XMMRegister src);
+
+  // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
+  void ucomiss(XMMRegister dst, Address src);
+  void ucomiss(XMMRegister dst, XMMRegister src);
+
+  void xaddl(Address dst, Register src);
+
+  void xaddq(Address dst, Register src);
+
+  void xchgl(Register reg, Address adr);
+  void xchgl(Register dst, Register src);
+
+  void xchgq(Register reg, Address adr);
+  void xchgq(Register dst, Register src);
+
+  void xorl(Register dst, int32_t imm32);
+  void xorl(Register dst, Address src);
+  void xorl(Register dst, Register src);
+
+  void xorq(Register dst, Address src);
+  void xorq(Register dst, Register src);
+
+  // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
+  void xorpd(XMMRegister dst, Address src);
+  void xorpd(XMMRegister dst, XMMRegister src);
+
+  // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
+  void xorps(XMMRegister dst, Address src);
+  void xorps(XMMRegister dst, XMMRegister src);
+
+  void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
+};
+
+
+// MacroAssembler extends Assembler by frequently used macros.
+//
+// Instructions for which a 'better' code sequence exists depending
+// on arguments should also go in here.
+
+class MacroAssembler: public Assembler {
+ friend class LIR_Assembler;
+ protected:
+
+  Address as_Address(AddressLiteral adr);
+  Address as_Address(ArrayAddress adr);
+
+  // Support for VM calls
+  //
+  // This is the base routine called by the different versions of call_VM_leaf. The interpreter
+  // may customize this version by overriding it for its purposes (e.g., to save/restore
+  // additional registers when doing a VM call).
+#ifdef CC_INTERP
+  // c++ interpreter never wants to use interp_masm version of call_VM
+  #define VIRTUAL
+#else
+  #define VIRTUAL virtual
+#endif
+
+  VIRTUAL void call_VM_leaf_base(
+    address entry_point,               // the entry point
+    int     number_of_arguments        // the number of arguments to pop after the call
+  );
+
+  // This is the base routine called by the different versions of call_VM. The interpreter
+  // may customize this version by overriding it for its purposes (e.g., to save/restore
+  // additional registers when doing a VM call).
+  //
+  // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
+  // returns the register which contains the thread upon return. If a thread register has been
+  // specified, the return value will correspond to that register. If no last_java_sp is specified
+  // (noreg) than rsp will be used instead.
+  VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
+    Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
+    Register java_thread,              // the thread if computed before     ; use noreg otherwise
+    Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
+    address  entry_point,              // the entry point
+    int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
+    bool     check_exceptions          // whether to check for pending exceptions after return
+  );
+
+  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
+  // The implementation is only non-empty for the InterpreterMacroAssembler,
+  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
+  virtual void check_and_handle_popframe(Register java_thread);
+  virtual void check_and_handle_earlyret(Register java_thread);
+
+  void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
+
+  // helpers for FPU flag access
+  // tmp is a temporary register, if none is available use noreg
+  void save_rax   (Register tmp);
+  void restore_rax(Register tmp);
+
+ public:
+  MacroAssembler(CodeBuffer* code) : Assembler(code) {}
+
+  // Support for NULL-checks
+  //
+  // Generates code that causes a NULL OS exception if the content of reg is NULL.
+  // If the accessed location is M[reg + offset] and the offset is known, provide the
+  // offset. No explicit code generation is needed if the offset is within a certain
+  // range (0 <= offset <= page_size).
+
+  void null_check(Register reg, int offset = -1);
+  static bool needs_explicit_null_check(intptr_t offset);
+
+  // Required platform-specific helpers for Label::patch_instructions.
+  // They _shadow_ the declarations in AbstractAssembler, which are undefined.
+  void pd_patch_instruction(address branch, address target);
+#ifndef PRODUCT
+  static void pd_print_patched_instruction(address branch);
+#endif
+
+  // The following 4 methods return the offset of the appropriate move instruction
+
+  // Support for fast byte/word loading with zero extension (depending on particular CPU)
+  int load_unsigned_byte(Register dst, Address src);
+  int load_unsigned_word(Register dst, Address src);
+
+  // Support for fast byte/word loading with sign extension (depending on particular CPU)
+  int load_signed_byte(Register dst, Address src);
+  int load_signed_word(Register dst, Address src);
+
+  // Support for sign-extension (hi:lo = extend_sign(lo))
+  void extend_sign(Register hi, Register lo);
+
+  // Support for inc/dec with optimal instruction selection depending on value
+
+  void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
+  void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
+
+  void decrementl(Address dst, int value = 1);
+  void decrementl(Register reg, int value = 1);
+
+  void decrementq(Register reg, int value = 1);
+  void decrementq(Address dst, int value = 1);
+
+  void incrementl(Address dst, int value = 1);
+  void incrementl(Register reg, int value = 1);
+
+  void incrementq(Register reg, int value = 1);
+  void incrementq(Address dst, int value = 1);
+
+
+  // Support optimal SSE move instructions.
+  void movflt(XMMRegister dst, XMMRegister src) {
+    if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
+    else                       { movss (dst, src); return; }
+  }
+  void movflt(XMMRegister dst, Address src) { movss(dst, src); }
+  void movflt(XMMRegister dst, AddressLiteral src);
+  void movflt(Address dst, XMMRegister src) { movss(dst, src); }
+
+  void movdbl(XMMRegister dst, XMMRegister src) {
+    if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
+    else                       { movsd (dst, src); return; }
+  }
+
+  void movdbl(XMMRegister dst, AddressLiteral src);
+
+  void movdbl(XMMRegister dst, Address src) {
+    if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
+    else                         { movlpd(dst, src); return; }
+  }
+  void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
+
+  void incrementl(AddressLiteral dst);
+  void incrementl(ArrayAddress dst);
+
+  // Alignment
+  void align(int modulus);
+
+  // Misc
+  void fat_nop(); // 5 byte nop
+
+  // Stack frame creation/removal
+  void enter();
+  void leave();
+
+  // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
+  // The pointer will be loaded into the thread register.
+  void get_thread(Register thread);
+
+  // Support for VM calls
+  //
+  // It is imperative that all calls into the VM are handled via the call_VM macros.
+  // They make sure that the stack linkage is setup correctly. call_VM's correspond
+  // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
+
+
+  void call_VM(Register oop_result,
+               address entry_point,
+               bool check_exceptions = true);
+  void call_VM(Register oop_result,
+               address entry_point,
+               Register arg_1,
+               bool check_exceptions = true);
+  void call_VM(Register oop_result,
+               address entry_point,
+               Register arg_1, Register arg_2,
+               bool check_exceptions = true);
+  void call_VM(Register oop_result,
+               address entry_point,
+               Register arg_1, Register arg_2, Register arg_3,
+               bool check_exceptions = true);
+
+  // Overloadings with last_Java_sp
+  void call_VM(Register oop_result,
+               Register last_java_sp,
+               address entry_point,
+               int number_of_arguments = 0,
+               bool check_exceptions = true);
+  void call_VM(Register oop_result,
+               Register last_java_sp,
+               address entry_point,
+               Register arg_1, bool
+               check_exceptions = true);
+  void call_VM(Register oop_result,
+               Register last_java_sp,
+               address entry_point,
+               Register arg_1, Register arg_2,
+               bool check_exceptions = true);
+  void call_VM(Register oop_result,
+               Register last_java_sp,
+               address entry_point,
+               Register arg_1, Register arg_2, Register arg_3,
+               bool check_exceptions = true);
+
+  void call_VM_leaf(address entry_point,
+                    int number_of_arguments = 0);
+  void call_VM_leaf(address entry_point,
+                    Register arg_1);
+  void call_VM_leaf(address entry_point,
+                    Register arg_1, Register arg_2);
+  void call_VM_leaf(address entry_point,
+                    Register arg_1, Register arg_2, Register arg_3);
+
+  // last Java Frame (fills frame anchor)
+  void set_last_Java_frame(Register thread,
+                           Register last_java_sp,
+                           Register last_java_fp,
+                           address last_java_pc);
+
+  // thread in the default location (r15_thread on 64bit)
+  void set_last_Java_frame(Register last_java_sp,
+                           Register last_java_fp,
+                           address last_java_pc);
+
+  void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
+
+  // thread in the default location (r15_thread on 64bit)
+  void reset_last_Java_frame(bool clear_fp, bool clear_pc);
+
+  // Stores
+  void store_check(Register obj);                // store check for obj - register is destroyed afterwards
+  void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
+
+  // split store_check(Register obj) to enhance instruction interleaving
+  void store_check_part_1(Register obj);
+  void store_check_part_2(Register obj);
+
+  // C 'boolean' to Java boolean: x == 0 ? 0 : 1
+  void c2bool(Register x);
+
+  // C++ bool manipulation
+
+  void movbool(Register dst, Address src);
+  void movbool(Address dst, bool boolconst);
+  void movbool(Address dst, Register src);
+  void testbool(Register dst);
+
+  // oop manipulations
+  void load_klass(Register dst, Register src);
+  void store_klass(Register dst, Register src);
+
+  void load_prototype_header(Register dst, Register src);
+
+#ifdef _LP64
+  void store_klass_gap(Register dst, Register src);
+
+  void load_heap_oop(Register dst, Address src);
+  void store_heap_oop(Address dst, Register src);
+  void encode_heap_oop(Register r);
+  void decode_heap_oop(Register r);
+  void encode_heap_oop_not_null(Register r);
+  void decode_heap_oop_not_null(Register r);
+  void encode_heap_oop_not_null(Register dst, Register src);
+  void decode_heap_oop_not_null(Register dst, Register src);
+
+  void set_narrow_oop(Register dst, jobject obj);
+
+  // if heap base register is used - reinit it with the correct value
+  void reinit_heapbase();
+#endif // _LP64
+
+  // Int division/remainder for Java
+  // (as idivl, but checks for special case as described in JVM spec.)
+  // returns idivl instruction offset for implicit exception handling
+  int corrected_idivl(Register reg);
+
+  // Long division/remainder for Java
+  // (as idivq, but checks for special case as described in JVM spec.)
+  // returns idivq instruction offset for implicit exception handling
+  int corrected_idivq(Register reg);
+
+  void int3();
+
+  // Long operation macros for a 32bit cpu
+  // Long negation for Java
+  void lneg(Register hi, Register lo);
+
+  // Long multiplication for Java
+  // (destroys contents of eax, ebx, ecx and edx)
+  void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
+
+  // Long shifts for Java
+  // (semantics as described in JVM spec.)
+  void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
+  void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
+
+  // Long compare for Java
+  // (semantics as described in JVM spec.)
+  void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
+
+
+  // misc
+
+  // Sign extension
+  void sign_extend_short(Register reg);
+  void sign_extend_byte(Register reg);
+
+  // Division by power of 2, rounding towards 0
+  void division_with_shift(Register reg, int shift_value);
+
+  // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
+  //
+  // CF (corresponds to C0) if x < y
+  // PF (corresponds to C2) if unordered
+  // ZF (corresponds to C3) if x = y
+  //
+  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
+  // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
+  void fcmp(Register tmp);
+  // Variant of the above which allows y to be further down the stack
+  // and which only pops x and y if specified. If pop_right is
+  // specified then pop_left must also be specified.
+  void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
+
+  // Floating-point comparison for Java
+  // Compares the top-most stack entries on the FPU stack and stores the result in dst.
+  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
+  // (semantics as described in JVM spec.)
+  void fcmp2int(Register dst, bool unordered_is_less);
+  // Variant of the above which allows y to be further down the stack
+  // and which only pops x and y if specified. If pop_right is
+  // specified then pop_left must also be specified.
+  void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
+
+  // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
+  // tmp is a temporary register, if none is available use noreg
+  void fremr(Register tmp);
+
+
+  // same as fcmp2int, but using SSE2
+  void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
+  void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
+
+  // Inlined sin/cos generator for Java; must not use CPU instruction
+  // directly on Intel as it does not have high enough precision
+  // outside of the range [-pi/4, pi/4]. Extra argument indicate the
+  // number of FPU stack slots in use; all but the topmost will
+  // require saving if a slow case is necessary. Assumes argument is
+  // on FP TOS; result is on FP TOS.  No cpu registers are changed by
+  // this code.
+  void trigfunc(char trig, int num_fpu_regs_in_use = 1);
+
+  // branch to L if FPU flag C2 is set/not set
+  // tmp is a temporary register, if none is available use noreg
+  void jC2 (Register tmp, Label& L);
+  void jnC2(Register tmp, Label& L);
+
+  // Pop ST (ffree & fincstp combined)
+  void fpop();
+
+  // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
+  void push_fTOS();
+
+  // pops double TOS element from CPU stack and pushes on FPU stack
+  void pop_fTOS();
+
+  void empty_FPU_stack();
+
+  void push_IU_state();
+  void pop_IU_state();
+
+  void push_FPU_state();
+  void pop_FPU_state();
+
+  void push_CPU_state();
+  void pop_CPU_state();
+
+  // Round up to a power of two
+  void round_to(Register reg, int modulus);
+
+  // Callee saved registers handling
+  void push_callee_saved_registers();
+  void pop_callee_saved_registers();
+
+  // allocation
+  void eden_allocate(
+    Register obj,                      // result: pointer to object after successful allocation
+    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
+    int      con_size_in_bytes,        // object size in bytes if   known at compile time
+    Register t1,                       // temp register
+    Label&   slow_case                 // continuation point if fast allocation fails
+  );
+  void tlab_allocate(
+    Register obj,                      // result: pointer to object after successful allocation
+    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
+    int      con_size_in_bytes,        // object size in bytes if   known at compile time
+    Register t1,                       // temp register
+    Register t2,                       // temp register
+    Label&   slow_case                 // continuation point if fast allocation fails
+  );
+  void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
+
+  //----
+  void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
+
+  // Debugging
+
+  // only if +VerifyOops
+  void verify_oop(Register reg, const char* s = "broken oop");
+  void verify_oop_addr(Address addr, const char * s = "broken oop addr");
+
+  // only if +VerifyFPU
+  void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
+
+  // prints msg, dumps registers and stops execution
+  void stop(const char* msg);
+
+  // prints msg and continues
+  void warn(const char* msg);
+
+  static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
+  static void debug64(char* msg, int64_t pc, int64_t regs[]);
+
+  void os_breakpoint();
+
+  void untested()                                { stop("untested"); }
+
+  void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, sizeof(b), "unimplemented: %s", what);  stop(b); }
+
+  void should_not_reach_here()                   { stop("should not reach here"); }
+
+  void print_CPU_state();
+
+  // Stack overflow checking
+  void bang_stack_with_offset(int offset) {
+    // stack grows down, caller passes positive offset
+    assert(offset > 0, "must bang with negative offset");
+    movl(Address(rsp, (-offset)), rax);
+  }
+
+  // Writes to stack successive pages until offset reached to check for
+  // stack overflow + shadow pages.  Also, clobbers tmp
+  void bang_stack_size(Register size, Register tmp);
+
+  // Support for serializing memory accesses between threads
+  void serialize_memory(Register thread, Register tmp);
+
+  void verify_tlab();
+
+  // Biased locking support
+  // lock_reg and obj_reg must be loaded up with the appropriate values.
+  // swap_reg must be rax, and is killed.
+  // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
+  // be killed; if not supplied, push/pop will be used internally to
+  // allocate a temporary (inefficient, avoid if possible).
+  // Optional slow case is for implementations (interpreter and C1) which branch to
+  // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
+  // Returns offset of first potentially-faulting instruction for null
+  // check info (currently consumed only by C1). If
+  // swap_reg_contains_mark is true then returns -1 as it is assumed
+  // the calling code has already passed any potential faults.
+  int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
+                           bool swap_reg_contains_mark,
+                           Label& done, Label* slow_case = NULL,
+                           BiasedLockingCounters* counters = NULL);
+  void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
+
+
+  Condition negate_condition(Condition cond);
+
+  // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
+  // operands. In general the names are modified to avoid hiding the instruction in Assembler
+  // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
+  // here in MacroAssembler. The major exception to this rule is call
+
+  // Arithmetics
+
+
+  void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
+  void addptr(Address dst, Register src);
+
+  void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
+  void addptr(Register dst, int32_t src);
+  void addptr(Register dst, Register src);
+
+  void andptr(Register dst, int32_t src);
+  void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
+
+  void cmp8(AddressLiteral src1, int imm);
+
+  // renamed to drag out the casting of address to int32_t/intptr_t
+  void cmp32(Register src1, int32_t imm);
+
+  void cmp32(AddressLiteral src1, int32_t imm);
+  // compare reg - mem, or reg - &mem
+  void cmp32(Register src1, AddressLiteral src2);
+
+  void cmp32(Register src1, Address src2);
+
+#ifndef _LP64
+  void cmpoop(Address dst, jobject obj);
+  void cmpoop(Register dst, jobject obj);
+#endif // _LP64
+
+  // NOTE src2 must be the lval. This is NOT an mem-mem compare
+  void cmpptr(Address src1, AddressLiteral src2);
+
+  void cmpptr(Register src1, AddressLiteral src2);
+
+  void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+  void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+  // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+
+  void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+  void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+
+  // cmp64 to avoild hiding cmpq
+  void cmp64(Register src1, AddressLiteral src);
+
+  void cmpxchgptr(Register reg, Address adr);
+
+  void locked_cmpxchgptr(Register reg, AddressLiteral adr);
+
+
+  void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
+
+
+  void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
+
+  void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
+
+  void shlptr(Register dst, int32_t shift);
+  void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
+
+  void shrptr(Register dst, int32_t shift);
+  void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
+
+  void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
+  void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
+
+  void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
+
+  void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
+  void subptr(Register dst, int32_t src);
+  void subptr(Register dst, Register src);
+
+
+  void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
+  void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
+
+  void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
+  void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
+
+  void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
+
+
+
+  // Helper functions for statistics gathering.
+  // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
+  void cond_inc32(Condition cond, AddressLiteral counter_addr);
+  // Unconditional atomic increment.
+  void atomic_incl(AddressLiteral counter_addr);
+
+  void lea(Register dst, AddressLiteral adr);
+  void lea(Address dst, AddressLiteral adr);
+  void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
+
+  void leal32(Register dst, Address src) { leal(dst, src); }
+
+  void test32(Register src1, AddressLiteral src2);
+
+  void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+  void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+  void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+
+  void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
+  void testptr(Register src1, Register src2);
+
+  void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
+  void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
+
+  // Calls
+
+  void call(Label& L, relocInfo::relocType rtype);
+  void call(Register entry);
+
+  // NOTE: this call tranfers to the effective address of entry NOT
+  // the address contained by entry. This is because this is more natural
+  // for jumps/calls.
+  void call(AddressLiteral entry);
+
+  // Jumps
+
+  // NOTE: these jumps tranfer to the effective address of dst NOT
+  // the address contained by dst. This is because this is more natural
+  // for jumps/calls.
+  void jump(AddressLiteral dst);
+  void jump_cc(Condition cc, AddressLiteral dst);
+
+  // 32bit can do a case table jump in one instruction but we no longer allow the base
+  // to be installed in the Address class. This jump will tranfers to the address
+  // contained in the location described by entry (not the address of entry)
+  void jump(ArrayAddress entry);
+
+  // Floating
+
+  void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
+  void andpd(XMMRegister dst, AddressLiteral src);
+
+  void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
+  void comiss(XMMRegister dst, AddressLiteral src);
+
+  void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
+  void comisd(XMMRegister dst, AddressLiteral src);
+
+  void fldcw(Address src) { Assembler::fldcw(src); }
+  void fldcw(AddressLiteral src);
+
+  void fld_s(int index)   { Assembler::fld_s(index); }
+  void fld_s(Address src) { Assembler::fld_s(src); }
+  void fld_s(AddressLiteral src);
+
+  void fld_d(Address src) { Assembler::fld_d(src); }
+  void fld_d(AddressLiteral src);
+
+  void fld_x(Address src) { Assembler::fld_x(src); }
+  void fld_x(AddressLiteral src);
+
+  void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
+  void ldmxcsr(AddressLiteral src);
+
+private:
+  // these are private because users should be doing movflt/movdbl
+
+  void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
+  void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
+  void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
+  void movss(XMMRegister dst, AddressLiteral src);
+
+  void movlpd(XMMRegister dst, Address src)      {Assembler::movlpd(dst, src); }
+  void movlpd(XMMRegister dst, AddressLiteral src);
+
+public:
+
+  void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
+  void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
+  void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
+  void movsd(XMMRegister dst, AddressLiteral src);
+
+  void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
+  void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
+  void ucomiss(XMMRegister dst, AddressLiteral src);
+
+  void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
+  void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
+  void ucomisd(XMMRegister dst, AddressLiteral src);
+
+  // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
+  void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
+  void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
+  void xorpd(XMMRegister dst, AddressLiteral src);
+
+  // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
+  void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
+  void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
+  void xorps(XMMRegister dst, AddressLiteral src);
+
+  // Data
+
+  void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+
+  void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+  void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+
+  void movoop(Register dst, jobject obj);
+  void movoop(Address dst, jobject obj);
+
+  void movptr(ArrayAddress dst, Register src);
+  // can this do an lea?
+  void movptr(Register dst, ArrayAddress src);
+
+  void movptr(Register dst, Address src);
+
+  void movptr(Register dst, AddressLiteral src);
+
+  void movptr(Register dst, intptr_t src);
+  void movptr(Register dst, Register src);
+  void movptr(Address dst, intptr_t src);
+
+  void movptr(Address dst, Register src);
+
+#ifdef _LP64
+  // Generally the next two are only used for moving NULL
+  // Although there are situations in initializing the mark word where
+  // they could be used. They are dangerous.
+
+  // They only exist on LP64 so that int32_t and intptr_t are not the same
+  // and we have ambiguous declarations.
+
+  void movptr(Address dst, int32_t imm32);
+  void movptr(Register dst, int32_t imm32);
+#endif // _LP64
+
+  // to avoid hiding movl
+  void mov32(AddressLiteral dst, Register src);
+  void mov32(Register dst, AddressLiteral src);
+
+  // to avoid hiding movb
+  void movbyte(ArrayAddress dst, int src);
+
+  // Can push value or effective address
+  void pushptr(AddressLiteral src);
+
+  void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
+  void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
+
+  void pushoop(jobject obj);
+
+  // sign extend as need a l to ptr sized element
+  void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
+  void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
+
+
+#undef VIRTUAL
+
+};
+
+/**
+ * class SkipIfEqual:
+ *
+ * Instantiating this class will result in assembly code being output that will
+ * jump around any code emitted between the creation of the instance and it's
+ * automatic destruction at the end of a scope block, depending on the value of
+ * the flag passed to the constructor, which will be checked at run-time.
+ */
+class SkipIfEqual {
+ private:
+  MacroAssembler* _masm;
+  Label _label;
+
+ public:
+   SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
+   ~SkipIfEqual();
+};
+
+#ifdef ASSERT
+inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.inline.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,87 @@
+/*
+ * Copyright 1997-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
+  unsigned char op = branch[0];
+  assert(op == 0xE8 /* call */ ||
+         op == 0xE9 /* jmp */ ||
+         op == 0xEB /* short jmp */ ||
+         (op & 0xF0) == 0x70 /* short jcc */ ||
+         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
+         "Invalid opcode at patch point");
+
+  if (op == 0xEB || (op & 0xF0) == 0x70) {
+    // short offset operators (jmp and jcc)
+    char* disp = (char*) &branch[1];
+    int imm8 = target - (address) &disp[1];
+    guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
+    *disp = imm8;
+  } else {
+    int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
+    int imm32 = target - (address) &disp[1];
+    *disp = imm32;
+  }
+}
+
+#ifndef PRODUCT
+inline void MacroAssembler::pd_print_patched_instruction(address branch) {
+  const char* s;
+  unsigned char op = branch[0];
+  if (op == 0xE8) {
+    s = "call";
+  } else if (op == 0xE9 || op == 0xEB) {
+    s = "jmp";
+  } else if ((op & 0xF0) == 0x70) {
+    s = "jcc";
+  } else if (op == 0x0F) {
+    s = "jcc";
+  } else {
+    s = "????";
+  }
+  tty->print("%s (unresolved)", s);
+}
+#endif // ndef PRODUCT
+
+#ifndef _LP64
+inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
+inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
+
+inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; }
+inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
+
+inline void Assembler::prefix(Register reg) {}
+inline void Assembler::prefix(Address adr) {}
+inline void Assembler::prefixq(Address adr) {}
+
+inline void Assembler::prefix(Address adr, Register reg,  bool byteinst) {}
+inline void Assembler::prefixq(Address adr, Register reg) {}
+
+inline void Assembler::prefix(Address adr, XMMRegister reg) {}
+#else
+inline void Assembler::emit_long64(jlong x) {
+  *(jlong*) _code_pos = x;
+  _code_pos += sizeof(jlong);
+  code_section()->set_end(_code_pos);
+}
+#endif // _LP64
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,5001 +0,0 @@
-/*
- * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_x86_32.cpp.incl"
-
-// Implementation of AddressLiteral
-
-AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
-  _is_lval = false;
-  _target = target;
-  switch (rtype) {
-  case relocInfo::oop_type:
-    // Oops are a special case. Normally they would be their own section
-    // but in cases like icBuffer they are literals in the code stream that
-    // we don't have a section for. We use none so that we get a literal address
-    // which is always patchable.
-    break;
-  case relocInfo::external_word_type:
-    _rspec = external_word_Relocation::spec(target);
-    break;
-  case relocInfo::internal_word_type:
-    _rspec = internal_word_Relocation::spec(target);
-    break;
-  case relocInfo::opt_virtual_call_type:
-    _rspec = opt_virtual_call_Relocation::spec();
-    break;
-  case relocInfo::static_call_type:
-    _rspec = static_call_Relocation::spec();
-    break;
-  case relocInfo::runtime_call_type:
-    _rspec = runtime_call_Relocation::spec();
-    break;
-  case relocInfo::poll_type:
-  case relocInfo::poll_return_type:
-    _rspec = Relocation::spec_simple(rtype);
-    break;
-  case relocInfo::none:
-    break;
-  default:
-    ShouldNotReachHere();
-    break;
-  }
-}
-
-// Implementation of Address
-
-Address Address::make_array(ArrayAddress adr) {
-#ifdef _LP64
-  // Not implementable on 64bit machines
-  // Should have been handled higher up the call chain.
-  ShouldNotReachHere();
-#else
-  AddressLiteral base = adr.base();
-  Address index = adr.index();
-  assert(index._disp == 0, "must not have disp"); // maybe it can?
-  Address array(index._base, index._index, index._scale, (intptr_t) base.target());
-  array._rspec = base._rspec;
-  return array;
-#endif // _LP64
-}
-
-#ifndef _LP64
-
-// exceedingly dangerous constructor
-Address::Address(address loc, RelocationHolder spec) {
-  _base  = noreg;
-  _index = noreg;
-  _scale = no_scale;
-  _disp  = (intptr_t) loc;
-  _rspec = spec;
-}
-#endif // _LP64
-
-// Convert the raw encoding form into the form expected by the constructor for
-// Address.  An index of 4 (rsp) corresponds to having no index, so convert
-// that to noreg for the Address constructor.
-Address Address::make_raw(int base, int index, int scale, int disp) {
-  bool valid_index = index != rsp->encoding();
-  if (valid_index) {
-    Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
-    return madr;
-  } else {
-    Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
-    return madr;
-  }
-}
-
-// Implementation of Assembler
-
-int AbstractAssembler::code_fill_byte() {
-  return (u_char)'\xF4'; // hlt
-}
-
-// make this go away someday
-void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
-  if (rtype == relocInfo::none)
-        emit_long(data);
-  else  emit_data(data, Relocation::spec_simple(rtype), format);
-}
-
-
-void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
-  assert(imm32_operand == 0, "default format must be imm32 in this file");
-  assert(inst_mark() != NULL, "must be inside InstructionMark");
-  if (rspec.type() !=  relocInfo::none) {
-    #ifdef ASSERT
-      check_relocation(rspec, format);
-    #endif
-    // Do not use AbstractAssembler::relocate, which is not intended for
-    // embedded words.  Instead, relocate to the enclosing instruction.
-
-    // hack. call32 is too wide for mask so use disp32
-    if (format == call32_operand)
-      code_section()->relocate(inst_mark(), rspec, disp32_operand);
-    else
-      code_section()->relocate(inst_mark(), rspec, format);
-  }
-  emit_long(data);
-}
-
-
-void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
-  assert(dst->has_byte_register(), "must have byte register");
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  assert(isByte(imm8), "not a byte");
-  assert((op1 & 0x01) == 0, "should be 8bit operation");
-  emit_byte(op1);
-  emit_byte(op2 | dst->encoding());
-  emit_byte(imm8);
-}
-
-
-void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  assert((op1 & 0x01) == 1, "should be 32bit operation");
-  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
-  if (is8bit(imm32)) {
-    emit_byte(op1 | 0x02); // set sign bit
-    emit_byte(op2 | dst->encoding());
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(op1);
-    emit_byte(op2 | dst->encoding());
-    emit_long(imm32);
-  }
-}
-
-// immediate-to-memory forms
-void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {
-  assert((op1 & 0x01) == 1, "should be 32bit operation");
-  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
-  if (is8bit(imm32)) {
-    emit_byte(op1 | 0x02); // set sign bit
-    emit_operand(rm,adr);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(op1);
-    emit_operand(rm,adr);
-    emit_long(imm32);
-  }
-}
-
-void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  assert((op1 & 0x01) == 1, "should be 32bit operation");
-  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
-  InstructionMark im(this);
-  emit_byte(op1);
-  emit_byte(op2 | dst->encoding());
-  emit_data((int)obj, relocInfo::oop_type, 0);
-}
-
-
-void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  emit_byte(op1);
-  emit_byte(op2 | dst->encoding() << 3 | src->encoding());
-}
-
-
-void Assembler::emit_operand(Register reg,
-                             Register base,
-                             Register index,
-                             Address::ScaleFactor scale,
-                             int disp,
-                             RelocationHolder const& rspec) {
-
-  relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
-  if (base->is_valid()) {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      // [base + index*scale + disp]
-      if (disp == 0 && rtype == relocInfo::none && base != rbp) {
-        // [base + index*scale]
-        // [00 reg 100][ss index base]
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x04 | reg->encoding() << 3);
-        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + index*scale + imm8]
-        // [01 reg 100][ss index base] imm8
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x44 | reg->encoding() << 3);
-        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + index*scale + imm32]
-        // [10 reg 100][ss index base] imm32
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x84 | reg->encoding() << 3);
-        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else if (base == rsp) {
-      // [esp + disp]
-      if (disp == 0 && rtype == relocInfo::none) {
-        // [esp]
-        // [00 reg 100][00 100 100]
-        emit_byte(0x04 | reg->encoding() << 3);
-        emit_byte(0x24);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [esp + imm8]
-        // [01 reg 100][00 100 100] imm8
-        emit_byte(0x44 | reg->encoding() << 3);
-        emit_byte(0x24);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [esp + imm32]
-        // [10 reg 100][00 100 100] imm32
-        emit_byte(0x84 | reg->encoding() << 3);
-        emit_byte(0x24);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else {
-      // [base + disp]
-      assert(base != rsp, "illegal addressing mode");
-      if (disp == 0 && rtype == relocInfo::none && base != rbp) {
-        // [base]
-        // [00 reg base]
-        assert(base != rbp, "illegal addressing mode");
-        emit_byte(0x00 | reg->encoding() << 3 | base->encoding());
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + imm8]
-        // [01 reg base] imm8
-        emit_byte(0x40 | reg->encoding() << 3 | base->encoding());
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + imm32]
-        // [10 reg base] imm32
-        emit_byte(0x80 | reg->encoding() << 3 | base->encoding());
-        emit_data(disp, rspec, disp32_operand);
-      }
-    }
-  } else {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      // [index*scale + disp]
-      // [00 reg 100][ss index 101] imm32
-      assert(index != rsp, "illegal addressing mode");
-      emit_byte(0x04 | reg->encoding() << 3);
-      emit_byte(scale << 6 | index->encoding() << 3 | 0x05);
-      emit_data(disp, rspec, disp32_operand);
-    } else {
-      // [disp]
-      // [00 reg 101] imm32
-      emit_byte(0x05 | reg->encoding() << 3);
-      emit_data(disp, rspec, disp32_operand);
-    }
-  }
-}
-
-// Secret local extension to Assembler::WhichOperand:
-#define end_pc_operand (_WhichOperand_limit)
-
-address Assembler::locate_operand(address inst, WhichOperand which) {
-  // Decode the given instruction, and return the address of
-  // an embedded 32-bit operand word.
-
-  // If "which" is disp32_operand, selects the displacement portion
-  // of an effective address specifier.
-  // If "which" is imm32_operand, selects the trailing immediate constant.
-  // If "which" is call32_operand, selects the displacement of a call or jump.
-  // Caller is responsible for ensuring that there is such an operand,
-  // and that it is 32 bits wide.
-
-  // If "which" is end_pc_operand, find the end of the instruction.
-
-  address ip = inst;
-
-  debug_only(bool has_imm32 = false);
-  int tail_size = 0;    // other random bytes (#32, #16, etc.) at end of insn
-
- again_after_prefix:
-  switch (0xFF & *ip++) {
-
-  // These convenience macros generate groups of "case" labels for the switch.
-  #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
-  #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
-             case (x)+4: case (x)+5: case (x)+6: case (x)+7
-  #define REP16(x) REP8((x)+0): \
-              case REP8((x)+8)
-
-  case CS_segment:
-  case SS_segment:
-  case DS_segment:
-  case ES_segment:
-  case FS_segment:
-  case GS_segment:
-    assert(ip == inst+1, "only one prefix allowed");
-    goto again_after_prefix;
-
-  case 0xFF: // pushl a; decl a; incl a; call a; jmp a
-  case 0x88: // movb a, r
-  case 0x89: // movl a, r
-  case 0x8A: // movb r, a
-  case 0x8B: // movl r, a
-  case 0x8F: // popl a
-    break;
-
-  case 0x68: // pushl #32(oop?)
-    if (which == end_pc_operand)  return ip + 4;
-    assert(which == imm32_operand, "pushl has no disp32");
-    return ip;                  // not produced by emit_operand
-
-  case 0x66: // movw ... (size prefix)
-    switch (0xFF & *ip++) {
-    case 0x8B: // movw r, a
-    case 0x89: // movw a, r
-      break;
-    case 0xC7: // movw a, #16
-      tail_size = 2;  // the imm16
-      break;
-    case 0x0F: // several SSE/SSE2 variants
-      ip--;    // reparse the 0x0F
-      goto again_after_prefix;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case REP8(0xB8): // movl r, #32(oop?)
-    if (which == end_pc_operand)  return ip + 4;
-    assert(which == imm32_operand || which == disp32_operand, "");
-    return ip;
-
-  case 0x69: // imul r, a, #32
-  case 0xC7: // movl a, #32(oop?)
-    tail_size = 4;
-    debug_only(has_imm32 = true); // has both kinds of operands!
-    break;
-
-  case 0x0F: // movx..., etc.
-    switch (0xFF & *ip++) {
-    case 0x12: // movlps
-    case 0x28: // movaps
-    case 0x2E: // ucomiss
-    case 0x2F: // comiss
-    case 0x54: // andps
-    case 0x55: // andnps
-    case 0x56: // orps
-    case 0x57: // xorps
-    case 0x6E: // movd
-    case 0x7E: // movd
-    case 0xAE: // ldmxcsr   a
-      // amd side says it these have both operands but that doesn't
-      // appear to be true.
-      // debug_only(has_imm32 = true); // has both kinds of operands!
-      break;
-
-    case 0xAD: // shrd r, a, %cl
-    case 0xAF: // imul r, a
-    case 0xBE: // movsxb r, a
-    case 0xBF: // movsxw r, a
-    case 0xB6: // movzxb r, a
-    case 0xB7: // movzxw r, a
-    case REP16(0x40): // cmovl cc, r, a
-    case 0xB0: // cmpxchgb
-    case 0xB1: // cmpxchg
-    case 0xC1: // xaddl
-    case 0xC7: // cmpxchg8
-    case REP16(0x90): // setcc a
-      // fall out of the switch to decode the address
-      break;
-    case 0xAC: // shrd r, a, #8
-      tail_size = 1;  // the imm8
-      break;
-    case REP16(0x80): // jcc rdisp32
-      if (which == end_pc_operand)  return ip + 4;
-      assert(which == call32_operand, "jcc has no disp32 or imm32");
-      return ip;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case 0x81: // addl a, #32; addl r, #32
-    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
-    // in the case of cmpl, the imm32 might be an oop
-    tail_size = 4;
-    debug_only(has_imm32 = true); // has both kinds of operands!
-    break;
-
-  case 0x85: // test r/m, r
-    break;
-
-  case 0x83: // addl a, #8; addl r, #8
-    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
-    tail_size = 1;
-    break;
-
-  case 0x9B:
-    switch (0xFF & *ip++) {
-    case 0xD9: // fnstcw a
-      break;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
-  case REP4(0x10): // adc...
-  case REP4(0x20): // and...
-  case REP4(0x30): // xor...
-  case REP4(0x08): // or...
-  case REP4(0x18): // sbb...
-  case REP4(0x28): // sub...
-  case REP4(0x38): // cmp...
-  case 0xF7: // mull a
-  case 0x8D: // leal r, a
-  case 0x87: // xchg r, a
-    break;
-
-  case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
-  case 0xC6: // movb a, #8
-  case 0x80: // cmpb a, #8
-  case 0x6B: // imul r, a, #8
-    tail_size = 1; // the imm8
-    break;
-
-  case 0xE8: // call rdisp32
-  case 0xE9: // jmp  rdisp32
-    if (which == end_pc_operand)  return ip + 4;
-    assert(which == call32_operand, "call has no disp32 or imm32");
-    return ip;
-
-  case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
-  case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
-  case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
-  case 0xDD: // fld_d a; fst_d a; fstp_d a
-  case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
-  case 0xDF: // fild_d a; fistp_d a
-  case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
-  case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
-  case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
-    break;
-
-  case 0xF3:                    // For SSE
-  case 0xF2:                    // For SSE2
-    ip++; ip++;
-    break;
-
-  default:
-    ShouldNotReachHere();
-
-  #undef REP8
-  #undef REP16
-  }
-
-  assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
-  assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");
-
-  // parse the output of emit_operand
-  int op2 = 0xFF & *ip++;
-  int base = op2 & 0x07;
-  int op3 = -1;
-  const int b100 = 4;
-  const int b101 = 5;
-  if (base == b100 && (op2 >> 6) != 3) {
-    op3 = 0xFF & *ip++;
-    base = op3 & 0x07;   // refetch the base
-  }
-  // now ip points at the disp (if any)
-
-  switch (op2 >> 6) {
-  case 0:
-    // [00 reg  100][ss index base]
-    // [00 reg  100][00   100  rsp]
-    // [00 reg base]
-    // [00 reg  100][ss index  101][disp32]
-    // [00 reg  101]               [disp32]
-
-    if (base == b101) {
-      if (which == disp32_operand)
-        return ip;              // caller wants the disp32
-      ip += 4;                  // skip the disp32
-    }
-    break;
-
-  case 1:
-    // [01 reg  100][ss index base][disp8]
-    // [01 reg  100][00   100  rsp][disp8]
-    // [01 reg base]               [disp8]
-    ip += 1;                    // skip the disp8
-    break;
-
-  case 2:
-    // [10 reg  100][ss index base][disp32]
-    // [10 reg  100][00   100  rsp][disp32]
-    // [10 reg base]               [disp32]
-    if (which == disp32_operand)
-      return ip;                // caller wants the disp32
-    ip += 4;                    // skip the disp32
-    break;
-
-  case 3:
-    // [11 reg base]  (not a memory addressing mode)
-    break;
-  }
-
-  if (which == end_pc_operand) {
-    return ip + tail_size;
-  }
-
-  assert(which == imm32_operand, "instruction has only an imm32 field");
-  return ip;
-}
-
-address Assembler::locate_next_instruction(address inst) {
-  // Secretly share code with locate_operand:
-  return locate_operand(inst, end_pc_operand);
-}
-
-
-#ifdef ASSERT
-void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
-  address inst = inst_mark();
-  assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
-  address opnd;
-
-  Relocation* r = rspec.reloc();
-  if (r->type() == relocInfo::none) {
-    return;
-  } else if (r->is_call() || format == call32_operand) {
-    // assert(format == imm32_operand, "cannot specify a nonzero format");
-    opnd = locate_operand(inst, call32_operand);
-  } else if (r->is_data()) {
-    assert(format == imm32_operand || format == disp32_operand, "format ok");
-    opnd = locate_operand(inst, (WhichOperand)format);
-  } else {
-    assert(format == imm32_operand, "cannot specify a format");
-    return;
-  }
-  assert(opnd == pc(), "must put operand where relocs can find it");
-}
-#endif
-
-
-
-void Assembler::emit_operand(Register reg, Address adr) {
-  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-
-void Assembler::emit_farith(int b1, int b2, int i) {
-  assert(isByte(b1) && isByte(b2), "wrong opcode");
-  assert(0 <= i &&  i < 8, "illegal stack offset");
-  emit_byte(b1);
-  emit_byte(b2 + i);
-}
-
-
-void Assembler::pushad() {
-  emit_byte(0x60);
-}
-
-void Assembler::popad() {
-  emit_byte(0x61);
-}
-
-void Assembler::pushfd() {
-  emit_byte(0x9C);
-}
-
-void Assembler::popfd() {
-  emit_byte(0x9D);
-}
-
-void Assembler::pushl(int imm32) {
-  emit_byte(0x68);
-  emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0x68);
-  emit_data(imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::pushl(Register src) {
-  emit_byte(0x50 | src->encoding());
-}
-
-
-void Assembler::pushl(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xFF);
-  emit_operand(rsi, src);
-}
-
-void Assembler::popl(Register dst) {
-  emit_byte(0x58 | dst->encoding());
-}
-
-
-void Assembler::popl(Address dst) {
-  InstructionMark im(this);
-  emit_byte(0x8F);
-  emit_operand(rax, dst);
-}
-
-
-void Assembler::prefix(Prefix p) {
-  a_byte(p);
-}
-
-
-void Assembler::movb(Register dst, Address src) {
-  assert(dst->has_byte_register(), "must have byte register");
-  InstructionMark im(this);
-  emit_byte(0x8A);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movb(Address dst, int imm8) {
-  InstructionMark im(this);
-  emit_byte(0xC6);
-  emit_operand(rax, dst);
-  emit_byte(imm8);
-}
-
-
-void Assembler::movb(Address dst, Register src) {
-  assert(src->has_byte_register(), "must have byte register");
-  InstructionMark im(this);
-  emit_byte(0x88);
-  emit_operand(src, dst);
-}
-
-
-void Assembler::movw(Address dst, int imm16) {
-  InstructionMark im(this);
-
-  emit_byte(0x66); // switch to 16-bit mode
-  emit_byte(0xC7);
-  emit_operand(rax, dst);
-  emit_word(imm16);
-}
-
-
-void Assembler::movw(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x8B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movw(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x89);
-  emit_operand(src, dst);
-}
-
-
-void Assembler::movl(Register dst, int imm32) {
-  emit_byte(0xB8 | dst->encoding());
-  emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
-
-  InstructionMark im(this);
-  emit_byte(0xB8 | dst->encoding());
-  emit_data((int)imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::movl(Register dst, Register src) {
-  emit_byte(0x8B);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x8B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movl(Address dst, int imm32) {
-  InstructionMark im(this);
-  emit_byte(0xC7);
-  emit_operand(rax, dst);
-  emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0xC7);
-  emit_operand(rax, dst);
-  emit_data((int)imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::movl(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x89);
-  emit_operand(src, dst);
-}
-
-void Assembler::movsxb(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xBE);
-  emit_operand(dst, src);
-}
-
-void Assembler::movsxb(Register dst, Register src) {
-  assert(src->has_byte_register(), "must have byte register");
-  emit_byte(0x0F);
-  emit_byte(0xBE);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movsxw(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xBF);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movsxw(Register dst, Register src) {
-  emit_byte(0x0F);
-  emit_byte(0xBF);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movzxb(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xB6);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movzxb(Register dst, Register src) {
-  assert(src->has_byte_register(), "must have byte register");
-  emit_byte(0x0F);
-  emit_byte(0xB6);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movzxw(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xB7);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::movzxw(Register dst, Register src) {
-  emit_byte(0x0F);
-  emit_byte(0xB7);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::cmovl(Condition cc, Register dst, Register src) {
-  guarantee(VM_Version::supports_cmov(), "illegal instruction");
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::cmovl(Condition cc, Register dst, Address src) {
-  guarantee(VM_Version::supports_cmov(), "illegal instruction");
-  // The code below seems to be wrong - however the manual is inconclusive
-  // do not use for now (remember to enable all callers when fixing this)
-  Unimplemented();
-  // wrong bytes?
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::prefetcht0(Address src) {
-  assert(VM_Version::supports_sse(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x18);
-  emit_operand(rcx, src); // 1, src
-}
-
-
-void Assembler::prefetcht1(Address src) {
-  assert(VM_Version::supports_sse(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x18);
-  emit_operand(rdx, src); // 2, src
-}
-
-
-void Assembler::prefetcht2(Address src) {
-  assert(VM_Version::supports_sse(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x18);
-  emit_operand(rbx, src); // 3, src
-}
-
-
-void Assembler::prefetchnta(Address src) {
-  assert(VM_Version::supports_sse2(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x18);
-  emit_operand(rax, src); // 0, src
-}
-
-
-void Assembler::prefetchw(Address src) {
-  assert(VM_Version::supports_3dnow(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x0D);
-  emit_operand(rcx, src); // 1, src
-}
-
-
-void Assembler::prefetchr(Address src) {
-  assert(VM_Version::supports_3dnow(), "must support");
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0x0D);
-  emit_operand(rax, src); // 0, src
-}
-
-
-void Assembler::adcl(Register dst, int imm32) {
-  emit_arith(0x81, 0xD0, dst, imm32);
-}
-
-
-void Assembler::adcl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x13);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::adcl(Register dst, Register src) {
-  emit_arith(0x13, 0xC0, dst, src);
-}
-
-
-void Assembler::addl(Address dst, int imm32) {
-  InstructionMark im(this);
-  emit_arith_operand(0x81,rax,dst,imm32);
-}
-
-
-void Assembler::addl(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x01);
-  emit_operand(src, dst);
-}
-
-
-void Assembler::addl(Register dst, int imm32) {
-  emit_arith(0x81, 0xC0, dst, imm32);
-}
-
-
-void Assembler::addl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x03);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::addl(Register dst, Register src) {
-  emit_arith(0x03, 0xC0, dst, src);
-}
-
-
-void Assembler::andl(Register dst, int imm32) {
-  emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-
-void Assembler::andl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x23);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::andl(Register dst, Register src) {
-  emit_arith(0x23, 0xC0, dst, src);
-}
-
-
-void Assembler::cmpb(Address dst, int imm8) {
-  InstructionMark im(this);
-  emit_byte(0x80);
-  emit_operand(rdi, dst);
-  emit_byte(imm8);
-}
-
-void Assembler::cmpw(Address dst, int imm16) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x81);
-  emit_operand(rdi, dst);
-  emit_word(imm16);
-}
-
-void Assembler::cmpl(Address dst, int imm32) {
-  InstructionMark im(this);
-  emit_byte(0x81);
-  emit_operand(rdi, dst);
-  emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0x81);
-  emit_byte(0xF8 | src1->encoding());
-  emit_data(imm32, rspec, 0);
-}
-
-void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0x81);
-  emit_operand(rdi, src1);
-  emit_data(imm32, rspec, 0);
-}
-#endif // _LP64
-
-
-void Assembler::cmpl(Register dst, int imm32) {
-  emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-
-void Assembler::cmpl(Register dst, Register src) {
-  emit_arith(0x3B, 0xC0, dst, src);
-}
-
-
-void Assembler::cmpl(Register dst, Address  src) {
-  InstructionMark im(this);
-  emit_byte(0x3B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::decl(Register dst) {
-  // Don't use it directly. Use MacroAssembler::decrement() instead.
-  emit_byte(0x48 | dst->encoding());
-}
-
-
-void Assembler::decl(Address dst) {
-  // Don't use it directly. Use MacroAssembler::decrement() instead.
-  InstructionMark im(this);
-  emit_byte(0xFF);
-  emit_operand(rcx, dst);
-}
-
-
-void Assembler::idivl(Register src) {
-  emit_byte(0xF7);
-  emit_byte(0xF8 | src->encoding());
-}
-
-
-void Assembler::cdql() {
-  emit_byte(0x99);
-}
-
-
-void Assembler::imull(Register dst, Register src) {
-  emit_byte(0x0F);
-  emit_byte(0xAF);
-  emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-void Assembler::imull(Register dst, Register src, int value) {
-  if (is8bit(value)) {
-    emit_byte(0x6B);
-    emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-    emit_byte(value);
-  } else {
-    emit_byte(0x69);
-    emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-    emit_long(value);
-  }
-}
-
-
-void Assembler::incl(Register dst) {
-  // Don't use it directly. Use MacroAssembler::increment() instead.
-  emit_byte(0x40 | dst->encoding());
-}
-
-
-void Assembler::incl(Address dst) {
-  // Don't use it directly. Use MacroAssembler::increment() instead.
-  InstructionMark im(this);
-  emit_byte(0xFF);
-  emit_operand(rax, dst);
-}
-
-
-void Assembler::leal(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x8D);
-  emit_operand(dst, src);
-}
-
-void Assembler::mull(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF7);
-  emit_operand(rsp, src);
-}
-
-
-void Assembler::mull(Register src) {
-  emit_byte(0xF7);
-  emit_byte(0xE0 | src->encoding());
-}
-
-
-void Assembler::negl(Register dst) {
-  emit_byte(0xF7);
-  emit_byte(0xD8 | dst->encoding());
-}
-
-
-void Assembler::notl(Register dst) {
-  emit_byte(0xF7);
-  emit_byte(0xD0 | dst->encoding());
-}
-
-
-void Assembler::orl(Address dst, int imm32) {
-  InstructionMark im(this);
-  emit_byte(0x81);
-  emit_operand(rcx, dst);
-  emit_long(imm32);
-}
-
-void Assembler::orl(Register dst, int imm32) {
-  emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-
-void Assembler::orl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::orl(Register dst, Register src) {
-  emit_arith(0x0B, 0xC0, dst, src);
-}
-
-
-void Assembler::rcll(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xD0 | dst->encoding());
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xD0 | dst->encoding());
-    emit_byte(imm8);
-  }
-}
-
-
-void Assembler::sarl(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xF8 | dst->encoding());
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xF8 | dst->encoding());
-    emit_byte(imm8);
-  }
-}
-
-
-void Assembler::sarl(Register dst) {
-  emit_byte(0xD3);
-  emit_byte(0xF8 | dst->encoding());
-}
-
-
-void Assembler::sbbl(Address dst, int imm32) {
-  InstructionMark im(this);
-  emit_arith_operand(0x81,rbx,dst,imm32);
-}
-
-
-void Assembler::sbbl(Register dst, int imm32) {
-  emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-
-void Assembler::sbbl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x1B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::sbbl(Register dst, Register src) {
-  emit_arith(0x1B, 0xC0, dst, src);
-}
-
-
-void Assembler::shldl(Register dst, Register src) {
-  emit_byte(0x0F);
-  emit_byte(0xA5);
-  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
-}
-
-
-void Assembler::shll(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  if (imm8 == 1 ) {
-    emit_byte(0xD1);
-    emit_byte(0xE0 | dst->encoding());
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xE0 | dst->encoding());
-    emit_byte(imm8);
-  }
-}
-
-
-void Assembler::shll(Register dst) {
-  emit_byte(0xD3);
-  emit_byte(0xE0 | dst->encoding());
-}
-
-
-void Assembler::shrdl(Register dst, Register src) {
-  emit_byte(0x0F);
-  emit_byte(0xAD);
-  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
-}
-
-
-void Assembler::shrl(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  emit_byte(0xC1);
-  emit_byte(0xE8 | dst->encoding());
-  emit_byte(imm8);
-}
-
-
-void Assembler::shrl(Register dst) {
-  emit_byte(0xD3);
-  emit_byte(0xE8 | dst->encoding());
-}
-
-
-void Assembler::subl(Address dst, int imm32) {
-  if (is8bit(imm32)) {
-    InstructionMark im(this);
-    emit_byte(0x83);
-    emit_operand(rbp, dst);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    InstructionMark im(this);
-    emit_byte(0x81);
-    emit_operand(rbp, dst);
-    emit_long(imm32);
-  }
-}
-
-
-void Assembler::subl(Register dst, int imm32) {
-  emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-
-void Assembler::subl(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x29);
-  emit_operand(src, dst);
-}
-
-
-void Assembler::subl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x2B);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::subl(Register dst, Register src) {
-  emit_arith(0x2B, 0xC0, dst, src);
-}
-
-
-void Assembler::testb(Register dst, int imm8) {
-  assert(dst->has_byte_register(), "must have byte register");
-  emit_arith_b(0xF6, 0xC0, dst, imm8);
-}
-
-
-void Assembler::testl(Register dst, int imm32) {
-  // not using emit_arith because test
-  // doesn't support sign-extension of
-  // 8bit operands
-  if (dst->encoding() == 0) {
-    emit_byte(0xA9);
-  } else {
-    emit_byte(0xF7);
-    emit_byte(0xC0 | dst->encoding());
-  }
-  emit_long(imm32);
-}
-
-
-void Assembler::testl(Register dst, Register src) {
-  emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::testl(Register dst, Address  src) {
-  InstructionMark im(this);
-  emit_byte(0x85);
-  emit_operand(dst, src);
-}
-
-void Assembler::xaddl(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xC1);
-  emit_operand(src, dst);
-}
-
-void Assembler::xorl(Register dst, int imm32) {
-  emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-
-void Assembler::xorl(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x33);
-  emit_operand(dst, src);
-}
-
-
-void Assembler::xorl(Register dst, Register src) {
-  emit_arith(0x33, 0xC0, dst, src);
-}
-
-
-void Assembler::bswap(Register reg) {
-  emit_byte(0x0F);
-  emit_byte(0xC8 | reg->encoding());
-}
-
-
-void Assembler::lock() {
-  if (Atomics & 1) {
-     // Emit either nothing, a NOP, or a NOP: prefix
-     emit_byte(0x90) ;
-  } else {
-     emit_byte(0xF0);
-  }
-}
-
-
-void Assembler::xchg(Register reg, Address adr) {
-  InstructionMark im(this);
-  emit_byte(0x87);
-  emit_operand(reg, adr);
-}
-
-
-void Assembler::xchgl(Register dst, Register src) {
-  emit_byte(0x87);
-  emit_byte(0xc0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-// The 32-bit cmpxchg compares the value at adr with the contents of rax,
-// and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
-// The ZF is set if the compared values were equal, and cleared otherwise.
-void Assembler::cmpxchg(Register reg, Address adr) {
-  if (Atomics & 2) {
-     // caveat: no instructionmark, so this isn't relocatable.
-     // Emit a synthetic, non-atomic, CAS equivalent.
-     // Beware.  The synthetic form sets all ICCs, not just ZF.
-     // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
-     cmpl (rax, adr) ;
-     movl (rax, adr) ;
-     if (reg != rax) {
-        Label L ;
-        jcc (Assembler::notEqual, L) ;
-        movl (adr, reg) ;
-        bind (L) ;
-     }
-  } else {
-     InstructionMark im(this);
-     emit_byte(0x0F);
-     emit_byte(0xB1);
-     emit_operand(reg, adr);
-  }
-}
-
-// The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax,
-// and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
-// into rdx:rax.  The ZF is set if the compared values were equal, and cleared otherwise.
-void Assembler::cmpxchg8(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xc7);
-  emit_operand(rcx, adr);
-}
-
-void Assembler::hlt() {
-  emit_byte(0xF4);
-}
-
-
-void Assembler::addr_nop_4() {
-  // 4 bytes: NOP DWORD PTR [EAX+0]
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
-  emit_byte(0);    // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_5() {
-  // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
-  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
-  emit_byte(0);    // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_7() {
-  // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
-  emit_long(0);    // 32-bits offset (4 bytes)
-}
-
-void Assembler::addr_nop_8() {
-  // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
-  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
-  emit_long(0);    // 32-bits offset (4 bytes)
-}
-
-void Assembler::nop(int i) {
-  assert(i > 0, " ");
-  if (UseAddressNop && VM_Version::is_intel()) {
-    //
-    // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
-    //  1: 0x90
-    //  2: 0x66 0x90
-    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
-    //  4: 0x0F 0x1F 0x40 0x00
-    //  5: 0x0F 0x1F 0x44 0x00 0x00
-    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
-    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
-    // The rest coding is Intel specific - don't use consecutive address nops
-
-    // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-
-    while(i >= 15) {
-      // For Intel don't generate consecutive addess nops (mix with regular nops)
-      i -= 15;
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      addr_nop_8();
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x90);   // nop
-    }
-    switch (i) {
-      case 14:
-        emit_byte(0x66); // size prefix
-      case 13:
-        emit_byte(0x66); // size prefix
-      case 12:
-        addr_nop_8();
-        emit_byte(0x66); // size prefix
-        emit_byte(0x66); // size prefix
-        emit_byte(0x66); // size prefix
-        emit_byte(0x90); // nop
-        break;
-      case 11:
-        emit_byte(0x66); // size prefix
-      case 10:
-        emit_byte(0x66); // size prefix
-      case 9:
-        emit_byte(0x66); // size prefix
-      case 8:
-        addr_nop_8();
-        break;
-      case 7:
-        addr_nop_7();
-        break;
-      case 6:
-        emit_byte(0x66); // size prefix
-      case 5:
-        addr_nop_5();
-        break;
-      case 4:
-        addr_nop_4();
-        break;
-      case 3:
-        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
-        emit_byte(0x66); // size prefix
-      case 2:
-        emit_byte(0x66); // size prefix
-      case 1:
-        emit_byte(0x90); // nop
-        break;
-      default:
-        assert(i == 0, " ");
-    }
-    return;
-  }
-  if (UseAddressNop && VM_Version::is_amd()) {
-    //
-    // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
-    //  1: 0x90
-    //  2: 0x66 0x90
-    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
-    //  4: 0x0F 0x1F 0x40 0x00
-    //  5: 0x0F 0x1F 0x44 0x00 0x00
-    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
-    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
-    // The rest coding is AMD specific - use consecutive address nops
-
-    // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
-    // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
-    // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //     Size prefixes (0x66) are added for larger sizes
-
-    while(i >= 22) {
-      i -= 11;
-      emit_byte(0x66); // size prefix
-      emit_byte(0x66); // size prefix
-      emit_byte(0x66); // size prefix
-      addr_nop_8();
-    }
-    // Generate first nop for size between 21-12
-    switch (i) {
-      case 21:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 20:
-      case 19:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 18:
-      case 17:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 16:
-      case 15:
-        i -= 8;
-        addr_nop_8();
-        break;
-      case 14:
-      case 13:
-        i -= 7;
-        addr_nop_7();
-        break;
-      case 12:
-        i -= 6;
-        emit_byte(0x66); // size prefix
-        addr_nop_5();
-        break;
-      default:
-        assert(i < 12, " ");
-    }
-
-    // Generate second nop for size between 11-1
-    switch (i) {
-      case 11:
-        emit_byte(0x66); // size prefix
-      case 10:
-        emit_byte(0x66); // size prefix
-      case 9:
-        emit_byte(0x66); // size prefix
-      case 8:
-        addr_nop_8();
-        break;
-      case 7:
-        addr_nop_7();
-        break;
-      case 6:
-        emit_byte(0x66); // size prefix
-      case 5:
-        addr_nop_5();
-        break;
-      case 4:
-        addr_nop_4();
-        break;
-      case 3:
-        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
-        emit_byte(0x66); // size prefix
-      case 2:
-        emit_byte(0x66); // size prefix
-      case 1:
-        emit_byte(0x90); // nop
-        break;
-      default:
-        assert(i == 0, " ");
-    }
-    return;
-  }
-
-  // Using nops with size prefixes "0x66 0x90".
-  // From AMD Optimization Guide:
-  //  1: 0x90
-  //  2: 0x66 0x90
-  //  3: 0x66 0x66 0x90
-  //  4: 0x66 0x66 0x66 0x90
-  //  5: 0x66 0x66 0x90 0x66 0x90
-  //  6: 0x66 0x66 0x90 0x66 0x66 0x90
-  //  7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
-  //  8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
-  //  9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
-  // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
-  //
-  while(i > 12) {
-    i -= 4;
-    emit_byte(0x66); // size prefix
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90); // nop
-  }
-  // 1 - 12 nops
-  if(i > 8) {
-    if(i > 9) {
-      i -= 1;
-      emit_byte(0x66);
-    }
-    i -= 3;
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90);
-  }
-  // 1 - 8 nops
-  if(i > 4) {
-    if(i > 6) {
-      i -= 1;
-      emit_byte(0x66);
-    }
-    i -= 3;
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90);
-  }
-  switch (i) {
-    case 4:
-      emit_byte(0x66);
-    case 3:
-      emit_byte(0x66);
-    case 2:
-      emit_byte(0x66);
-    case 1:
-      emit_byte(0x90);
-      break;
-    default:
-      assert(i == 0, " ");
-  }
-}
-
-void Assembler::ret(int imm16) {
-  if (imm16 == 0) {
-    emit_byte(0xC3);
-  } else {
-    emit_byte(0xC2);
-    emit_word(imm16);
-  }
-}
-
-
-void Assembler::set_byte_if_not_zero(Register dst) {
-  emit_byte(0x0F);
-  emit_byte(0x95);
-  emit_byte(0xE0 | dst->encoding());
-}
-
-
-// copies a single word from [esi] to [edi]
-void Assembler::smovl() {
-  emit_byte(0xA5);
-}
-
-// copies data from [esi] to [edi] using rcx double words (m32)
-void Assembler::rep_movl() {
-  emit_byte(0xF3);
-  emit_byte(0xA5);
-}
-
-
-// sets rcx double words (m32) with rax, value at [edi]
-void Assembler::rep_set() {
-  emit_byte(0xF3);
-  emit_byte(0xAB);
-}
-
-// scans rcx double words (m32) at [edi] for occurance of rax,
-void Assembler::repne_scan() {
-  emit_byte(0xF2);
-  emit_byte(0xAF);
-}
-
-
-void Assembler::setb(Condition cc, Register dst) {
-  assert(0 <= cc && cc < 16, "illegal cc");
-  emit_byte(0x0F);
-  emit_byte(0x90 | cc);
-  emit_byte(0xC0 | dst->encoding());
-}
-
-void Assembler::cld() {
-  emit_byte(0xfc);
-}
-
-void Assembler::std() {
-  emit_byte(0xfd);
-}
-
-void Assembler::emit_raw (unsigned char b) {
-  emit_byte (b) ;
-}
-
-// Serializes memory.
-void Assembler::membar() {
-    // Memory barriers are only needed on multiprocessors
-  if (os::is_MP()) {
-    if( VM_Version::supports_sse2() ) {
-      emit_byte( 0x0F );                // MFENCE; faster blows no regs
-      emit_byte( 0xAE );
-      emit_byte( 0xF0 );
-    } else {
-      // All usable chips support "locked" instructions which suffice
-      // as barriers, and are much faster than the alternative of
-      // using cpuid instruction. We use here a locked add [esp],0.
-      // This is conveniently otherwise a no-op except for blowing
-      // flags (which we save and restore.)
-      pushfd();                // Save eflags register
-      lock();
-      addl(Address(rsp, 0), 0);// Assert the lock# signal here
-      popfd();                 // Restore eflags register
-    }
-  }
-}
-
-// Identify processor type and features
-void Assembler::cpuid() {
-  // Note: we can't assert VM_Version::supports_cpuid() here
-  //       because this instruction is used in the processor
-  //       identification code.
-  emit_byte( 0x0F );
-  emit_byte( 0xA2 );
-}
-
-void Assembler::call(Label& L, relocInfo::relocType rtype) {
-  if (L.is_bound()) {
-    const int long_size = 5;
-    int offs = target(L) - pc();
-    assert(offs <= 0, "assembler error");
-    InstructionMark im(this);
-    // 1110 1000 #32-bit disp
-    emit_byte(0xE8);
-    emit_data(offs - long_size, rtype, 0);
-  } else {
-    InstructionMark im(this);
-    // 1110 1000 #32-bit disp
-    L.add_patch_at(code(), locator());
-    emit_byte(0xE8);
-    emit_data(int(0), rtype, 0);
-  }
-}
-
-void Assembler::call(Register dst) {
-  emit_byte(0xFF);
-  emit_byte(0xD0 | dst->encoding());
-}
-
-
-void Assembler::call(Address adr) {
-  InstructionMark im(this);
-  relocInfo::relocType rtype = adr.reloc();
-  if (rtype !=  relocInfo::runtime_call_type) {
-    emit_byte(0xFF);
-    emit_operand(rdx, adr);
-  } else {
-    assert(false, "ack");
-  }
-
-}
-
-void Assembler::call_literal(address dest, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0xE8);
-  intptr_t disp = dest - (_code_pos + sizeof(int32_t));
-  assert(dest != NULL, "must have a target");
-  emit_data(disp, rspec, call32_operand);
-
-}
-
-void Assembler::jmp(Register entry) {
-  emit_byte(0xFF);
-  emit_byte(0xE0 | entry->encoding());
-}
-
-
-void Assembler::jmp(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xFF);
-  emit_operand(rsp, adr);
-}
-
-void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0xE9);
-  assert(dest != NULL, "must have a target");
-  intptr_t disp = dest - (_code_pos + sizeof(int32_t));
-  emit_data(disp, rspec.reloc(), call32_operand);
-}
-
-void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
-  if (L.is_bound()) {
-    address entry = target(L);
-    assert(entry != NULL, "jmp most probably wrong");
-    InstructionMark im(this);
-    const int short_size = 2;
-    const int long_size = 5;
-    intptr_t offs = entry - _code_pos;
-    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
-      emit_byte(0xEB);
-      emit_byte((offs - short_size) & 0xFF);
-    } else {
-      emit_byte(0xE9);
-      emit_long(offs - long_size);
-    }
-  } else {
-    // By default, forward jumps are always 32-bit displacements, since
-    // we can't yet know where the label will be bound.  If you're sure that
-    // the forward jump will not run beyond 256 bytes, use jmpb to
-    // force an 8-bit displacement.
-    InstructionMark im(this);
-    relocate(rtype);
-    L.add_patch_at(code(), locator());
-    emit_byte(0xE9);
-    emit_long(0);
-  }
-}
-
-void Assembler::jmpb(Label& L) {
-  if (L.is_bound()) {
-    const int short_size = 2;
-    address entry = target(L);
-    assert(is8bit((entry - _code_pos) + short_size),
-           "Dispacement too large for a short jmp");
-    assert(entry != NULL, "jmp most probably wrong");
-    intptr_t offs = entry - _code_pos;
-    emit_byte(0xEB);
-    emit_byte((offs - short_size) & 0xFF);
-  } else {
-    InstructionMark im(this);
-    L.add_patch_at(code(), locator());
-    emit_byte(0xEB);
-    emit_byte(0);
-  }
-}
-
-void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
-  InstructionMark im(this);
-  relocate(rtype);
-  assert((0 <= cc) && (cc < 16), "illegal cc");
-  if (L.is_bound()) {
-    address dst = target(L);
-    assert(dst != NULL, "jcc most probably wrong");
-
-    const int short_size = 2;
-    const int long_size = 6;
-    int offs = (int)dst - ((int)_code_pos);
-    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
-      // 0111 tttn #8-bit disp
-      emit_byte(0x70 | cc);
-      emit_byte((offs - short_size) & 0xFF);
-    } else {
-      // 0000 1111 1000 tttn #32-bit disp
-      emit_byte(0x0F);
-      emit_byte(0x80 | cc);
-      emit_long(offs - long_size);
-    }
-  } else {
-    // Note: could eliminate cond. jumps to this jump if condition
-    //       is the same however, seems to be rather unlikely case.
-    // Note: use jccb() if label to be bound is very close to get
-    //       an 8-bit displacement
-    L.add_patch_at(code(), locator());
-    emit_byte(0x0F);
-    emit_byte(0x80 | cc);
-    emit_long(0);
-  }
-}
-
-void Assembler::jccb(Condition cc, Label& L) {
-  if (L.is_bound()) {
-    const int short_size = 2;
-    address entry = target(L);
-    assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
-           "Dispacement too large for a short jmp");
-    intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
-    // 0111 tttn #8-bit disp
-    emit_byte(0x70 | cc);
-    emit_byte((offs - short_size) & 0xFF);
-    jcc(cc, L);
-  } else {
-    InstructionMark im(this);
-    L.add_patch_at(code(), locator());
-    emit_byte(0x70 | cc);
-    emit_byte(0);
-  }
-}
-
-// FPU instructions
-
-void Assembler::fld1() {
-  emit_byte(0xD9);
-  emit_byte(0xE8);
-}
-
-
-void Assembler::fldz() {
-  emit_byte(0xD9);
-  emit_byte(0xEE);
-}
-
-
-void Assembler::fld_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xD9);
-  emit_operand(rax, adr);
-}
-
-
-void Assembler::fld_s (int index) {
-  emit_farith(0xD9, 0xC0, index);
-}
-
-
-void Assembler::fld_d(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDD);
-  emit_operand(rax, adr);
-}
-
-
-void Assembler::fld_x(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDB);
-  emit_operand(rbp, adr);
-}
-
-
-void Assembler::fst_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xD9);
-  emit_operand(rdx, adr);
-}
-
-
-void Assembler::fst_d(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDD);
-  emit_operand(rdx, adr);
-}
-
-
-void Assembler::fstp_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xD9);
-  emit_operand(rbx, adr);
-}
-
-
-void Assembler::fstp_d(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDD);
-  emit_operand(rbx, adr);
-}
-
-
-void Assembler::fstp_x(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDB);
-  emit_operand(rdi, adr);
-}
-
-
-void Assembler::fstp_d(int index) {
-  emit_farith(0xDD, 0xD8, index);
-}
-
-
-void Assembler::fild_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDB);
-  emit_operand(rax, adr);
-}
-
-
-void Assembler::fild_d(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDF);
-  emit_operand(rbp, adr);
-}
-
-
-void Assembler::fistp_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDB);
-  emit_operand(rbx, adr);
-}
-
-
-void Assembler::fistp_d(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDF);
-  emit_operand(rdi, adr);
-}
-
-
-void Assembler::fist_s(Address adr) {
-  InstructionMark im(this);
-  emit_byte(0xDB);
-  emit_operand(rdx, adr);
-}
-
-
-void Assembler::fabs() {
-  emit_byte(0xD9);
-  emit_byte(0xE1);
-}
-
-
-void Assembler::fldln2() {
-  emit_byte(0xD9);
-  emit_byte(0xED);
-}
-
-void Assembler::fyl2x() {
-  emit_byte(0xD9);
-  emit_byte(0xF1);
-}
-
-
-void Assembler::fldlg2() {
-  emit_byte(0xD9);
-  emit_byte(0xEC);
-}
-
-
-void Assembler::flog() {
-  fldln2();
-  fxch();
-  fyl2x();
-}
-
-
-void Assembler::flog10() {
-  fldlg2();
-  fxch();
-  fyl2x();
-}
-
-
-void Assembler::fsin() {
-  emit_byte(0xD9);
-  emit_byte(0xFE);
-}
-
-
-void Assembler::fcos() {
-  emit_byte(0xD9);
-  emit_byte(0xFF);
-}
-
-void Assembler::ftan() {
-  emit_byte(0xD9);
-  emit_byte(0xF2);
-  emit_byte(0xDD);
-  emit_byte(0xD8);
-}
-
-void Assembler::fsqrt() {
-  emit_byte(0xD9);
-  emit_byte(0xFA);
-}
-
-
-void Assembler::fchs() {
-  emit_byte(0xD9);
-  emit_byte(0xE0);
-}
-
-
-void Assembler::fadd_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rax, src);
-}
-
-
-void Assembler::fadd_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rax, src);
-}
-
-
-void Assembler::fadd(int i) {
-  emit_farith(0xD8, 0xC0, i);
-}
-
-
-void Assembler::fadda(int i) {
-  emit_farith(0xDC, 0xC0, i);
-}
-
-
-void Assembler::fsub_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rsp, src);
-}
-
-
-void Assembler::fsub_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rsp, src);
-}
-
-
-void Assembler::fsubr_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rbp, src);
-}
-
-
-void Assembler::fsubr_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rbp, src);
-}
-
-
-void Assembler::fmul_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rcx, src);
-}
-
-
-void Assembler::fmul_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rcx, src);
-}
-
-
-void Assembler::fmul(int i) {
-  emit_farith(0xD8, 0xC8, i);
-}
-
-
-void Assembler::fmula(int i) {
-  emit_farith(0xDC, 0xC8, i);
-}
-
-
-void Assembler::fdiv_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rsi, src);
-}
-
-
-void Assembler::fdiv_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rsi, src);
-}
-
-
-void Assembler::fdivr_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rdi, src);
-}
-
-
-void Assembler::fdivr_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rdi, src);
-}
-
-
-void Assembler::fsub(int i) {
-  emit_farith(0xD8, 0xE0, i);
-}
-
-
-void Assembler::fsuba(int i) {
-  emit_farith(0xDC, 0xE8, i);
-}
-
-
-void Assembler::fsubr(int i) {
-  emit_farith(0xD8, 0xE8, i);
-}
-
-
-void Assembler::fsubra(int i) {
-  emit_farith(0xDC, 0xE0, i);
-}
-
-
-void Assembler::fdiv(int i) {
-  emit_farith(0xD8, 0xF0, i);
-}
-
-
-void Assembler::fdiva(int i) {
-  emit_farith(0xDC, 0xF8, i);
-}
-
-
-void Assembler::fdivr(int i) {
-  emit_farith(0xD8, 0xF8, i);
-}
-
-
-void Assembler::fdivra(int i) {
-  emit_farith(0xDC, 0xF0, i);
-}
-
-
-// Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
-//       is erroneous for some of the floating-point instructions below.
-
-void Assembler::fdivp(int i) {
-  emit_farith(0xDE, 0xF8, i);                    // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fdivrp(int i) {
-  emit_farith(0xDE, 0xF0, i);                    // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fsubp(int i) {
-  emit_farith(0xDE, 0xE8, i);                    // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fsubrp(int i) {
-  emit_farith(0xDE, 0xE0, i);                    // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
-}
-
-
-void Assembler::faddp(int i) {
-  emit_farith(0xDE, 0xC0, i);
-}
-
-
-void Assembler::fmulp(int i) {
-  emit_farith(0xDE, 0xC8, i);
-}
-
-
-void Assembler::fprem() {
-  emit_byte(0xD9);
-  emit_byte(0xF8);
-}
-
-
-void Assembler::fprem1() {
-  emit_byte(0xD9);
-  emit_byte(0xF5);
-}
-
-
-void Assembler::fxch(int i) {
-  emit_farith(0xD9, 0xC8, i);
-}
-
-
-void Assembler::fincstp() {
-  emit_byte(0xD9);
-  emit_byte(0xF7);
-}
-
-
-void Assembler::fdecstp() {
-  emit_byte(0xD9);
-  emit_byte(0xF6);
-}
-
-
-void Assembler::ffree(int i) {
-  emit_farith(0xDD, 0xC0, i);
-}
-
-
-void Assembler::fcomp_s(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD8);
-  emit_operand(rbx, src);
-}
-
-
-void Assembler::fcomp_d(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDC);
-  emit_operand(rbx, src);
-}
-
-
-void Assembler::fcom(int i) {
-  emit_farith(0xD8, 0xD0, i);
-}
-
-
-void Assembler::fcomp(int i) {
-  emit_farith(0xD8, 0xD8, i);
-}
-
-
-void Assembler::fcompp() {
-  emit_byte(0xDE);
-  emit_byte(0xD9);
-}
-
-
-void Assembler::fucomi(int i) {
-  // make sure the instruction is supported (introduced for P6, together with cmov)
-  guarantee(VM_Version::supports_cmov(), "illegal instruction");
-  emit_farith(0xDB, 0xE8, i);
-}
-
-
-void Assembler::fucomip(int i) {
-  // make sure the instruction is supported (introduced for P6, together with cmov)
-  guarantee(VM_Version::supports_cmov(), "illegal instruction");
-  emit_farith(0xDF, 0xE8, i);
-}
-
-
-void Assembler::ftst() {
-  emit_byte(0xD9);
-  emit_byte(0xE4);
-}
-
-
-void Assembler::fnstsw_ax() {
-  emit_byte(0xdF);
-  emit_byte(0xE0);
-}
-
-
-void Assembler::fwait() {
-  emit_byte(0x9B);
-}
-
-
-void Assembler::finit() {
-  emit_byte(0x9B);
-  emit_byte(0xDB);
-  emit_byte(0xE3);
-}
-
-
-void Assembler::fldcw(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xd9);
-  emit_operand(rbp, src);
-}
-
-
-void Assembler::fnstcw(Address src) {
-  InstructionMark im(this);
-  emit_byte(0x9B);
-  emit_byte(0xD9);
-  emit_operand(rdi, src);
-}
-
-void Assembler::fnsave(Address dst) {
-  InstructionMark im(this);
-  emit_byte(0xDD);
-  emit_operand(rsi, dst);
-}
-
-
-void Assembler::frstor(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xDD);
-  emit_operand(rsp, src);
-}
-
-
-void Assembler::fldenv(Address src) {
-  InstructionMark im(this);
-  emit_byte(0xD9);
-  emit_operand(rsp, src);
-}
-
-
-void Assembler::sahf() {
-  emit_byte(0x9E);
-}
-
-// MMX operations
-void Assembler::emit_operand(MMXRegister reg, Address adr) {
-  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-void Assembler::movq( MMXRegister dst, Address src ) {
-  assert( VM_Version::supports_mmx(), "" );
-  emit_byte(0x0F);
-  emit_byte(0x6F);
-  emit_operand(dst,src);
-}
-
-void Assembler::movq( Address dst, MMXRegister src ) {
-  assert( VM_Version::supports_mmx(), "" );
-  emit_byte(0x0F);
-  emit_byte(0x7F);
-  emit_operand(src,dst);
-}
-
-void Assembler::emms() {
-  emit_byte(0x0F);
-  emit_byte(0x77);
-}
-
-
-
-
-// SSE and SSE2 instructions
-inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) {
-  assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid");
-  emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-inline void Assembler::emit_sse_operand(Register reg, Address adr) {
-  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
-  emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
-  emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-// Macro for creation of SSE2 instructions
-// The SSE2 instricution set is highly regular, so this macro saves
-// a lot of cut&paste
-// Each macro expansion creates two methods (same name with different
-// parameter list)
-//
-// Macro parameters:
-//  * name: name of the created methods
-//  * sse_version: either sse or sse2 for the assertion if instruction supported by processor
-//  * prefix: first opcode byte of the instruction (or 0 if no prefix byte)
-//  * opcode: last opcode byte of the instruction
-//  * conversion instruction have parameters of type Register instead of XMMRegister,
-//    so this can also configured with macro parameters
-#define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type)      \
-                                                                         \
-  void Assembler:: name (dst_register_type dst, Address src) {           \
-    assert(VM_Version::supports_##sse_version(), "");                    \
-                                                                         \
-    InstructionMark im(this);                                            \
-    if (prefix != 0) emit_byte(prefix);                                  \
-    emit_byte(0x0F);                                                     \
-    emit_byte(opcode);                                                   \
-    emit_sse_operand(dst, src);                                          \
-  }                                                                      \
-                                                                         \
-  void Assembler:: name (dst_register_type dst, src_register_type src) { \
-    assert(VM_Version::supports_##sse_version(), "");                    \
-                                                                         \
-    if (prefix != 0) emit_byte(prefix);                                  \
-    emit_byte(0x0F);                                                     \
-    emit_byte(opcode);                                                   \
-    emit_sse_operand(dst, src);                                          \
-  }                                                                      \
-
-emit_sse_instruction(addss,  sse,  0xF3, 0x58, XMMRegister, XMMRegister);
-emit_sse_instruction(addsd,  sse2, 0xF2, 0x58, XMMRegister, XMMRegister)
-emit_sse_instruction(subss,  sse,  0xF3, 0x5C, XMMRegister, XMMRegister)
-emit_sse_instruction(subsd,  sse2, 0xF2, 0x5C, XMMRegister, XMMRegister)
-emit_sse_instruction(mulss,  sse,  0xF3, 0x59, XMMRegister, XMMRegister)
-emit_sse_instruction(mulsd,  sse2, 0xF2, 0x59, XMMRegister, XMMRegister)
-emit_sse_instruction(divss,  sse,  0xF3, 0x5E, XMMRegister, XMMRegister)
-emit_sse_instruction(divsd,  sse2, 0xF2, 0x5E, XMMRegister, XMMRegister)
-emit_sse_instruction(sqrtss, sse,  0xF3, 0x51, XMMRegister, XMMRegister)
-emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister)
-
-emit_sse_instruction(pxor,  sse2,  0x66, 0xEF, XMMRegister, XMMRegister)
-
-emit_sse_instruction(comiss,  sse,  0,    0x2F, XMMRegister, XMMRegister)
-emit_sse_instruction(comisd,  sse2, 0x66, 0x2F, XMMRegister, XMMRegister)
-emit_sse_instruction(ucomiss, sse,  0,    0x2E, XMMRegister, XMMRegister)
-emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister)
-
-emit_sse_instruction(cvtss2sd,  sse2, 0xF3, 0x5A, XMMRegister, XMMRegister);
-emit_sse_instruction(cvtsd2ss,  sse2, 0xF2, 0x5A, XMMRegister, XMMRegister)
-emit_sse_instruction(cvtsi2ss,  sse,  0xF3, 0x2A, XMMRegister, Register);
-emit_sse_instruction(cvtsi2sd,  sse2, 0xF2, 0x2A, XMMRegister, Register)
-emit_sse_instruction(cvtss2si,  sse,  0xF3, 0x2D, Register, XMMRegister);
-emit_sse_instruction(cvtsd2si,  sse2, 0xF2, 0x2D, Register, XMMRegister)
-emit_sse_instruction(cvttss2si, sse,  0xF3, 0x2C, Register, XMMRegister);
-emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister)
-
-emit_sse_instruction(movss, sse,  0xF3, 0x10, XMMRegister, XMMRegister)
-emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister)
-
-emit_sse_instruction(movq,  sse2, 0xF3, 0x7E, XMMRegister, XMMRegister);
-emit_sse_instruction(movd,  sse2, 0x66, 0x6E, XMMRegister, Register);
-emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister);
-
-emit_sse_instruction(punpcklbw,  sse2, 0x66, 0x60, XMMRegister, XMMRegister);
-
-
-// Instruction not covered by macro
-void Assembler::movq(Address dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0xD6);
-  emit_sse_operand(src, dst);
-}
-
-void Assembler::movd(Address dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x7E);
-  emit_sse_operand(src, dst);
-}
-
-void Assembler::movd(Register dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x7E);
-  emit_sse_operand(src, dst);
-}
-
-void Assembler::movdqa(Address dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x7F);
-  emit_sse_operand(src, dst);
-}
-
-void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
-  assert(isByte(mode), "invalid value");
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_sse_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
-  assert(isByte(mode), "invalid value");
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_sse_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
-  assert(isByte(mode), "invalid value");
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0xF2);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_sse_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
-  assert(isByte(mode), "invalid value");
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_sse_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::psrlq(XMMRegister dst, int shift) {
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x73);
-  emit_sse_operand(xmm2, dst);
-  emit_byte(shift);
-}
-
-void Assembler::movss( Address dst, XMMRegister src ) {
-  assert(VM_Version::supports_sse(), "");
-
-  InstructionMark im(this);
-  emit_byte(0xF3); // single
-  emit_byte(0x0F);
-  emit_byte(0x11); // store
-  emit_sse_operand(src, dst);
-}
-
-void Assembler::movsd( Address dst, XMMRegister src ) {
-  assert(VM_Version::supports_sse2(), "");
-
-  InstructionMark im(this);
-  emit_byte(0xF2); // double
-  emit_byte(0x0F);
-  emit_byte(0x11); // store
-  emit_sse_operand(src,dst);
-}
-
-// New cpus require to use movaps and movapd to avoid partial register stall
-// when moving between registers.
-void Assembler::movaps(XMMRegister dst, XMMRegister src) {
-  assert(VM_Version::supports_sse(), "");
-
-  emit_byte(0x0F);
-  emit_byte(0x28);
-  emit_sse_operand(dst, src);
-}
-void Assembler::movapd(XMMRegister dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x28);
-  emit_sse_operand(dst, src);
-}
-
-// New cpus require to use movsd and movss to avoid partial register stall
-// when loading from memory. But for old Opteron use movlpd instead of movsd.
-// The selection is done in MacroAssembler::movdbl() and movflt().
-void Assembler::movlpd(XMMRegister dst, Address src) {
-  assert(VM_Version::supports_sse(), "");
-
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x12);
-  emit_sse_operand(dst, src);
-}
-
-void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0xF3);
-  emit_byte(0x0F);
-  emit_byte(0xE6);
-  emit_sse_operand(dst, src);
-}
-
-void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
-  assert(VM_Version::supports_sse2(), "");
-
-  emit_byte(0x0F);
-  emit_byte(0x5B);
-  emit_sse_operand(dst, src);
-}
-
-emit_sse_instruction(andps,  sse,  0,    0x54, XMMRegister, XMMRegister);
-emit_sse_instruction(andpd,  sse2, 0x66, 0x54, XMMRegister, XMMRegister);
-emit_sse_instruction(andnps, sse,  0,    0x55, XMMRegister, XMMRegister);
-emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister);
-emit_sse_instruction(orps,   sse,  0,    0x56, XMMRegister, XMMRegister);
-emit_sse_instruction(orpd,   sse2, 0x66, 0x56, XMMRegister, XMMRegister);
-emit_sse_instruction(xorps,  sse,  0,    0x57, XMMRegister, XMMRegister);
-emit_sse_instruction(xorpd,  sse2, 0x66, 0x57, XMMRegister, XMMRegister);
-
-
-void Assembler::ldmxcsr( Address src) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(rdx /* 2 */, src);
-}
-
-void Assembler::stmxcsr( Address dst) {
-  InstructionMark im(this);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(rbx /* 3 */, dst);
-}
-
-// Implementation of MacroAssembler
-
-Address MacroAssembler::as_Address(AddressLiteral adr) {
-  // amd64 always does this as a pc-rel
-  // we can be absolute or disp based on the instruction type
-  // jmp/call are displacements others are absolute
-  assert(!adr.is_lval(), "must be rval");
-
-  return Address(adr.target(), adr.rspec());
-}
-
-Address MacroAssembler::as_Address(ArrayAddress adr) {
-  return Address::make_array(adr);
-}
-
-void MacroAssembler::fat_nop() {
-  // A 5 byte nop that is safe for patching (see patch_verified_entry)
-  emit_byte(0x26); // es:
-  emit_byte(0x2e); // cs:
-  emit_byte(0x64); // fs:
-  emit_byte(0x65); // gs:
-  emit_byte(0x90);
-}
-
-// 32bit can do a case table jump in one instruction but we no longer allow the base
-// to be installed in the Address class
-void MacroAssembler::jump(ArrayAddress entry) {
-  jmp(as_Address(entry));
-}
-
-void MacroAssembler::jump(AddressLiteral dst) {
-  jmp_literal(dst.target(), dst.rspec());
-}
-
-void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
-  assert((0 <= cc) && (cc < 16), "illegal cc");
-
-  InstructionMark im(this);
-
-  relocInfo::relocType rtype = dst.reloc();
-  relocate(rtype);
-  const int short_size = 2;
-  const int long_size = 6;
-  int offs = (int)dst.target() - ((int)_code_pos);
-  if (rtype == relocInfo::none && is8bit(offs - short_size)) {
-    // 0111 tttn #8-bit disp
-    emit_byte(0x70 | cc);
-    emit_byte((offs - short_size) & 0xFF);
-  } else {
-    // 0000 1111 1000 tttn #32-bit disp
-    emit_byte(0x0F);
-    emit_byte(0x80 | cc);
-    emit_long(offs - long_size);
-  }
-}
-
-// Calls
-void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
-  Assembler::call(L, rtype);
-}
-
-void MacroAssembler::call(Register entry) {
-  Assembler::call(entry);
-}
-
-void MacroAssembler::call(AddressLiteral entry) {
-  Assembler::call_literal(entry.target(), entry.rspec());
-}
-
-
-void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) {
-  Assembler::cmpb(as_Address(src1), imm);
-}
-
-void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
-  Assembler::cmpl(as_Address(src1), imm);
-}
-
-void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
-  if (src2.is_lval()) {
-    cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-  } else {
-    Assembler::cmpl(src1, as_Address(src2));
-  }
-}
-
-void MacroAssembler::cmp32(Register src1, int32_t imm) {
-  Assembler::cmpl(src1, imm);
-}
-
-void MacroAssembler::cmp32(Register src1, Address src2) {
-  Assembler::cmpl(src1, src2);
-}
-
-void MacroAssembler::cmpoop(Address src1, jobject obj) {
-  cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::cmpoop(Register src1, jobject obj) {
-  cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
-  if (src2.is_lval()) {
-    // compare the effect address of src2 to src1
-    cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
-  } else {
-    Assembler::cmpl(src1, as_Address(src2));
-  }
-}
-
-void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
-  assert(src2.is_lval(), "not a mem-mem compare");
-  cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-}
-
-
-void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
-  cmpxchg(reg, as_Address(adr));
-}
-
-void MacroAssembler::increment(AddressLiteral dst) {
-  increment(as_Address(dst));
-}
-
-void MacroAssembler::increment(ArrayAddress dst) {
-  increment(as_Address(dst));
-}
-
-void MacroAssembler::lea(Register dst, AddressLiteral adr) {
-  // leal(dst, as_Address(adr));
-  // see note in movl as to why we musr use a move
-  mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
-}
-
-void MacroAssembler::lea(Address dst, AddressLiteral adr) {
-  // leal(dst, as_Address(adr));
-  // see note in movl as to why we musr use a move
-  mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
-}
-
-void MacroAssembler::mov32(AddressLiteral dst, Register src) {
-  Assembler::movl(as_Address(dst), src);
-}
-
-void MacroAssembler::mov32(Register dst, AddressLiteral src) {
-  Assembler::movl(dst, as_Address(src));
-}
-
-void MacroAssembler::movbyte(ArrayAddress dst, int src) {
-  movb(as_Address(dst), src);
-}
-
-void MacroAssembler::movoop(Address dst, jobject obj) {
-  mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movoop(Register dst, jobject obj) {
-  mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movptr(Register dst, AddressLiteral src) {
-  if (src.is_lval()) {
-    // essentially an lea
-    mov_literal32(dst, (int32_t) src.target(), src.rspec());
-  } else {
-    // mov 32bits from an absolute address
-    movl(dst, as_Address(src));
-  }
-}
-
-void MacroAssembler::movptr(ArrayAddress dst, Register src) {
-  movl(as_Address(dst), src);
-}
-
-void MacroAssembler::movptr(Register dst, ArrayAddress src) {
-  movl(dst, as_Address(src));
-}
-
-void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
-  movss(dst, as_Address(src));
-}
-
-void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
-  if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; }
-  else                         { movlpd(dst, as_Address(src)); return; }
-}
-
-void Assembler::pushoop(jobject obj) {
-  push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-
-void MacroAssembler::pushptr(AddressLiteral src) {
-  if (src.is_lval()) {
-    push_literal32((int32_t)src.target(), src.rspec());
-  } else {
-    pushl(as_Address(src));
-  }
-}
-
-void MacroAssembler::test32(Register src1, AddressLiteral src2) {
-  // src2 must be rval
-  testl(src1, as_Address(src2));
-}
-
-// FPU
-
-void MacroAssembler::fld_x(AddressLiteral src) {
-  Assembler::fld_x(as_Address(src));
-}
-
-void MacroAssembler::fld_d(AddressLiteral src) {
-  fld_d(as_Address(src));
-}
-
-void MacroAssembler::fld_s(AddressLiteral src) {
-  fld_s(as_Address(src));
-}
-
-void MacroAssembler::fldcw(AddressLiteral src) {
-  Assembler::fldcw(as_Address(src));
-}
-
-void MacroAssembler::ldmxcsr(AddressLiteral src) {
-  Assembler::ldmxcsr(as_Address(src));
-}
-
-// SSE
-
-void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
-  andpd(dst, as_Address(src));
-}
-
-void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
-  comisd(dst, as_Address(src));
-}
-
-void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
-  comiss(dst, as_Address(src));
-}
-
-void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
-  movsd(dst, as_Address(src));
-}
-
-void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
-  movss(dst, as_Address(src));
-}
-
-void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
-  xorpd(dst, as_Address(src));
-}
-
-void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
-  xorps(dst, as_Address(src));
-}
-
-void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
-  ucomisd(dst, as_Address(src));
-}
-
-void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
-  ucomiss(dst, as_Address(src));
-}
-
-void MacroAssembler::null_check(Register reg, int offset) {
-  if (needs_explicit_null_check(offset)) {
-    // provoke OS NULL exception if reg = NULL by
-    // accessing M[reg] w/o changing any (non-CC) registers
-    cmpl(rax, Address(reg, 0));
-    // Note: should probably use testl(rax, Address(reg, 0));
-    //       may be shorter code (however, this version of
-    //       testl needs to be implemented first)
-  } else {
-    // nothing to do, (later) access of M[reg + offset]
-    // will provoke OS NULL exception if reg = NULL
-  }
-}
-
-
-int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
-  // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
-  // and "3.9 Partial Register Penalties", p. 22).
-  int off;
-  if (VM_Version::is_P6() || src.uses(dst)) {
-    off = offset();
-    movzxb(dst, src);
-  } else {
-    xorl(dst, dst);
-    off = offset();
-    movb(dst, src);
-  }
-  return off;
-}
-
-
-int MacroAssembler::load_unsigned_word(Register dst, Address src) {
-  // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
-  // and "3.9 Partial Register Penalties", p. 22).
-  int off;
-  if (VM_Version::is_P6() || src.uses(dst)) {
-    off = offset();
-    movzxw(dst, src);
-  } else {
-    xorl(dst, dst);
-    off = offset();
-    movw(dst, src);
-  }
-  return off;
-}
-
-
-int MacroAssembler::load_signed_byte(Register dst, Address src) {
-  int off;
-  if (VM_Version::is_P6()) {
-    off = offset();
-    movsxb(dst, src);
-  } else {
-    off = load_unsigned_byte(dst, src);
-    shll(dst, 24);
-    sarl(dst, 24);
-  }
-  return off;
-}
-
-
-int MacroAssembler::load_signed_word(Register dst, Address src) {
-  int off;
-  if (VM_Version::is_P6()) {
-    off = offset();
-    movsxw(dst, src);
-  } else {
-    off = load_unsigned_word(dst, src);
-    shll(dst, 16);
-    sarl(dst, 16);
-  }
-  return off;
-}
-
-
-void MacroAssembler::extend_sign(Register hi, Register lo) {
-  // According to Intel Doc. AP-526, "Integer Divide", p.18.
-  if (VM_Version::is_P6() && hi == rdx && lo == rax) {
-    cdql();
-  } else {
-    movl(hi, lo);
-    sarl(hi, 31);
-  }
-}
-
-
-void MacroAssembler::increment(Register reg, int value) {
-  if (value == min_jint) {addl(reg, value); return; }
-  if (value <  0) { decrement(reg, -value); return; }
-  if (value == 0) {                       ; return; }
-  if (value == 1 && UseIncDec) { incl(reg); return; }
-  /* else */      { addl(reg, value)      ; return; }
-}
-
-void MacroAssembler::increment(Address dst, int value) {
-  if (value == min_jint) {addl(dst, value); return; }
-  if (value <  0) { decrement(dst, -value); return; }
-  if (value == 0) {                       ; return; }
-  if (value == 1 && UseIncDec) { incl(dst); return; }
-  /* else */      { addl(dst, value)      ; return; }
-}
-
-void MacroAssembler::decrement(Register reg, int value) {
-  if (value == min_jint) {subl(reg, value); return; }
-  if (value <  0) { increment(reg, -value); return; }
-  if (value == 0) {                       ; return; }
-  if (value == 1 && UseIncDec) { decl(reg); return; }
-  /* else */      { subl(reg, value)      ; return; }
-}
-
-void MacroAssembler::decrement(Address dst, int value) {
-  if (value == min_jint) {subl(dst, value); return; }
-  if (value <  0) { increment(dst, -value); return; }
-  if (value == 0) {                       ; return; }
-  if (value == 1 && UseIncDec) { decl(dst); return; }
-  /* else */      { subl(dst, value)      ; return; }
-}
-
-void MacroAssembler::align(int modulus) {
-  if (offset() % modulus != 0) nop(modulus - (offset() % modulus));
-}
-
-
-void MacroAssembler::enter() {
-  pushl(rbp);
-  movl(rbp, rsp);
-}
-
-
-void MacroAssembler::leave() {
-  movl(rsp, rbp);
-  popl(rbp);
-}
-
-void MacroAssembler::set_last_Java_frame(Register java_thread,
-                                         Register last_java_sp,
-                                         Register last_java_fp,
-                                         address  last_java_pc) {
-  // determine java_thread register
-  if (!java_thread->is_valid()) {
-    java_thread = rdi;
-    get_thread(java_thread);
-  }
-  // determine last_java_sp register
-  if (!last_java_sp->is_valid()) {
-    last_java_sp = rsp;
-  }
-
-  // last_java_fp is optional
-
-  if (last_java_fp->is_valid()) {
-    movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
-  }
-
-  // last_java_pc is optional
-
-  if (last_java_pc != NULL) {
-    lea(Address(java_thread,
-                 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
-        InternalAddress(last_java_pc));
-
-  }
-  movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
-}
-
-void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
-  // determine java_thread register
-  if (!java_thread->is_valid()) {
-    java_thread = rdi;
-    get_thread(java_thread);
-  }
-  // we must set sp to zero to clear frame
-  movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0);
-  if (clear_fp) {
-    movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0);
-  }
-
-  if (clear_pc)
-    movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0);
-
-}
-
-
-
-// Implementation of call_VM versions
-
-void MacroAssembler::call_VM_leaf_base(
-  address entry_point,
-  int     number_of_arguments
-) {
-  call(RuntimeAddress(entry_point));
-  increment(rsp, number_of_arguments * wordSize);
-}
-
-
-void MacroAssembler::call_VM_base(
-  Register oop_result,
-  Register java_thread,
-  Register last_java_sp,
-  address  entry_point,
-  int      number_of_arguments,
-  bool     check_exceptions
-) {
-  // determine java_thread register
-  if (!java_thread->is_valid()) {
-    java_thread = rdi;
-    get_thread(java_thread);
-  }
-  // determine last_java_sp register
-  if (!last_java_sp->is_valid()) {
-    last_java_sp = rsp;
-  }
-  // debugging support
-  assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
-  assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
-  assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
-  // push java thread (becomes first argument of C function)
-  pushl(java_thread);
-  // set last Java frame before call
-  assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,");
-  // Only interpreter should have to set fp
-  set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
-  // do the call
-  call(RuntimeAddress(entry_point));
-  // restore the thread (cannot use the pushed argument since arguments
-  // may be overwritten by C code generated by an optimizing compiler);
-  // however can use the register value directly if it is callee saved.
-  if (java_thread == rdi || java_thread == rsi) {
-    // rdi & rsi are callee saved -> nothing to do
-#ifdef ASSERT
-    guarantee(java_thread != rax, "change this code");
-    pushl(rax);
-    { Label L;
-      get_thread(rax);
-      cmpl(java_thread, rax);
-      jcc(Assembler::equal, L);
-      stop("MacroAssembler::call_VM_base: rdi not callee saved?");
-      bind(L);
-    }
-    popl(rax);
-#endif
-  } else {
-    get_thread(java_thread);
-  }
-  // reset last Java frame
-  // Only interpreter should have to clear fp
-  reset_last_Java_frame(java_thread, true, false);
-  // discard thread and arguments
-  addl(rsp, (1 + number_of_arguments)*wordSize);
-
-#ifndef CC_INTERP
-   // C++ interp handles this in the interpreter
-  check_and_handle_popframe(java_thread);
-  check_and_handle_earlyret(java_thread);
-#endif /* CC_INTERP */
-
-  if (check_exceptions) {
-    // check for pending exceptions (java_thread is set upon return)
-    cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
-    jump_cc(Assembler::notEqual,
-            RuntimeAddress(StubRoutines::forward_exception_entry()));
-  }
-
-  // get oop result if there is one and reset the value in the thread
-  if (oop_result->is_valid()) {
-    movl(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
-    movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
-    verify_oop(oop_result);
-  }
-}
-
-
-void MacroAssembler::check_and_handle_popframe(Register java_thread) {
-}
-
-void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
-}
-
-void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
-  leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
-  call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
-  Label C, E;
-  call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  call_VM_helper(oop_result, entry_point, 0, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
-  Label C, E;
-  call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  pushl(arg_1);
-  call_VM_helper(oop_result, entry_point, 1, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
-  Label C, E;
-  call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM_helper(oop_result, entry_point, 2, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
-  Label C, E;
-  call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  pushl(arg_3);
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM_helper(oop_result, entry_point, 3, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
-  call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
-  pushl(arg_1);
-  call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
-  pushl(arg_3);
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
-  call_VM_leaf_base(entry_point, number_of_arguments);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
-  pushl(arg_1);
-  call_VM_leaf(entry_point, 1);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM_leaf(entry_point, 2);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
-  pushl(arg_3);
-  pushl(arg_2);
-  pushl(arg_1);
-  call_VM_leaf(entry_point, 3);
-}
-
-
-// Calls to C land
-//
-// When entering C land, the rbp, & rsp of the last Java frame have to be recorded
-// in the (thread-local) JavaThread object. When leaving C land, the last Java fp
-// has to be reset to 0. This is required to allow proper stack traversal.
-
-void MacroAssembler::store_check(Register obj) {
-  // Does a store check for the oop in register obj. The content of
-  // register obj is destroyed afterwards.
-  store_check_part_1(obj);
-  store_check_part_2(obj);
-}
-
-
-void MacroAssembler::store_check(Register obj, Address dst) {
-  store_check(obj);
-}
-
-
-// split the store check operation so that other instructions can be scheduled inbetween
-void MacroAssembler::store_check_part_1(Register obj) {
-  BarrierSet* bs = Universe::heap()->barrier_set();
-  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
-  shrl(obj, CardTableModRefBS::card_shift);
-}
-
-
-void MacroAssembler::store_check_part_2(Register obj) {
-  BarrierSet* bs = Universe::heap()->barrier_set();
-  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
-  CardTableModRefBS* ct = (CardTableModRefBS*)bs;
-  assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
-
-  // The calculation for byte_map_base is as follows:
-  // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
-  // So this essentially converts an address to a displacement and
-  // it will never need to be relocated. On 64bit however the value may be too
-  // large for a 32bit displacement
-
-  intptr_t disp = (intptr_t) ct->byte_map_base;
-  Address cardtable(noreg, obj, Address::times_1, disp);
-  movb(cardtable, 0);
-}
-
-
-void MacroAssembler::c2bool(Register x) {
-  // implements x == 0 ? 0 : 1
-  // note: must only look at least-significant byte of x
-  //       since C-style booleans are stored in one byte
-  //       only! (was bug)
-  andl(x, 0xFF);
-  setb(Assembler::notZero, x);
-}
-
-
-int MacroAssembler::corrected_idivl(Register reg) {
-  // Full implementation of Java idiv and irem; checks for
-  // special case as described in JVM spec., p.243 & p.271.
-  // The function returns the (pc) offset of the idivl
-  // instruction - may be needed for implicit exceptions.
-  //
-  //         normal case                           special case
-  //
-  // input : rax,: dividend                         min_int
-  //         reg: divisor   (may not be rax,/rdx)   -1
-  //
-  // output: rax,: quotient  (= rax, idiv reg)       min_int
-  //         rdx: remainder (= rax, irem reg)       0
-  assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
-  const int min_int = 0x80000000;
-  Label normal_case, special_case;
-
-  // check for special case
-  cmpl(rax, min_int);
-  jcc(Assembler::notEqual, normal_case);
-  xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
-  cmpl(reg, -1);
-  jcc(Assembler::equal, special_case);
-
-  // handle normal case
-  bind(normal_case);
-  cdql();
-  int idivl_offset = offset();
-  idivl(reg);
-
-  // normal and special case exit
-  bind(special_case);
-
-  return idivl_offset;
-}
-
-
-void MacroAssembler::lneg(Register hi, Register lo) {
-  negl(lo);
-  adcl(hi, 0);
-  negl(hi);
-}
-
-
-void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
-  // Multiplication of two Java long values stored on the stack
-  // as illustrated below. Result is in rdx:rax.
-  //
-  // rsp ---> [  ??  ] \               \
-  //            ....    | y_rsp_offset  |
-  //          [ y_lo ] /  (in bytes)    | x_rsp_offset
-  //          [ y_hi ]                  | (in bytes)
-  //            ....                    |
-  //          [ x_lo ]                 /
-  //          [ x_hi ]
-  //            ....
-  //
-  // Basic idea: lo(result) = lo(x_lo * y_lo)
-  //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
-  Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
-  Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
-  Label quick;
-  // load x_hi, y_hi and check if quick
-  // multiplication is possible
-  movl(rbx, x_hi);
-  movl(rcx, y_hi);
-  movl(rax, rbx);
-  orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
-  jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
-  // do full multiplication
-  // 1st step
-  mull(y_lo);                                    // x_hi * y_lo
-  movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
-  // 2nd step
-  movl(rax, x_lo);
-  mull(rcx);                                     // x_lo * y_hi
-  addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
-  // 3rd step
-  bind(quick);                                   // note: rbx, = 0 if quick multiply!
-  movl(rax, x_lo);
-  mull(y_lo);                                    // x_lo * y_lo
-  addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
-}
-
-
-void MacroAssembler::lshl(Register hi, Register lo) {
-  // Java shift left long support (semantics as described in JVM spec., p.305)
-  // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
-  // shift value is in rcx !
-  assert(hi != rcx, "must not use rcx");
-  assert(lo != rcx, "must not use rcx");
-  const Register s = rcx;                        // shift count
-  const int      n = BitsPerWord;
-  Label L;
-  andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
-  cmpl(s, n);                                    // if (s < n)
-  jcc(Assembler::less, L);                       // else (s >= n)
-  movl(hi, lo);                                  // x := x << n
-  xorl(lo, lo);
-  // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
-  bind(L);                                       // s (mod n) < n
-  shldl(hi, lo);                                 // x := x << s
-  shll(lo);
-}
-
-
-void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
-  // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
-  // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
-  assert(hi != rcx, "must not use rcx");
-  assert(lo != rcx, "must not use rcx");
-  const Register s = rcx;                        // shift count
-  const int      n = BitsPerWord;
-  Label L;
-  andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
-  cmpl(s, n);                                    // if (s < n)
-  jcc(Assembler::less, L);                       // else (s >= n)
-  movl(lo, hi);                                  // x := x >> n
-  if (sign_extension) sarl(hi, 31);
-  else                xorl(hi, hi);
-  // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
-  bind(L);                                       // s (mod n) < n
-  shrdl(lo, hi);                                 // x := x >> s
-  if (sign_extension) sarl(hi);
-  else                shrl(hi);
-}
-
-
-// Note: y_lo will be destroyed
-void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
-  // Long compare for Java (semantics as described in JVM spec.)
-  Label high, low, done;
-
-  cmpl(x_hi, y_hi);
-  jcc(Assembler::less, low);
-  jcc(Assembler::greater, high);
-  // x_hi is the return register
-  xorl(x_hi, x_hi);
-  cmpl(x_lo, y_lo);
-  jcc(Assembler::below, low);
-  jcc(Assembler::equal, done);
-
-  bind(high);
-  xorl(x_hi, x_hi);
-  increment(x_hi);
-  jmp(done);
-
-  bind(low);
-  xorl(x_hi, x_hi);
-  decrement(x_hi);
-
-  bind(done);
-}
-
-
-void MacroAssembler::save_rax(Register tmp) {
-  if (tmp == noreg) pushl(rax);
-  else if (tmp != rax) movl(tmp, rax);
-}
-
-
-void MacroAssembler::restore_rax(Register tmp) {
-  if (tmp == noreg) popl(rax);
-  else if (tmp != rax) movl(rax, tmp);
-}
-
-
-void MacroAssembler::fremr(Register tmp) {
-  save_rax(tmp);
-  { Label L;
-    bind(L);
-    fprem();
-    fwait(); fnstsw_ax();
-    sahf();
-    jcc(Assembler::parity, L);
-  }
-  restore_rax(tmp);
-  // Result is in ST0.
-  // Note: fxch & fpop to get rid of ST1
-  // (otherwise FPU stack could overflow eventually)
-  fxch(1);
-  fpop();
-}
-
-
-static const double     pi_4 =  0.7853981633974483;
-
-void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
-  // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
-  // was attempted in this code; unfortunately it appears that the
-  // switch to 80-bit precision and back causes this to be
-  // unprofitable compared with simply performing a runtime call if
-  // the argument is out of the (-pi/4, pi/4) range.
-
-  Register tmp = noreg;
-  if (!VM_Version::supports_cmov()) {
-    // fcmp needs a temporary so preserve rbx,
-    tmp = rbx;
-    pushl(tmp);
-  }
-
-  Label slow_case, done;
-
-  // x ?<= pi/4
-  fld_d(ExternalAddress((address)&pi_4));
-  fld_s(1);                // Stack:  X  PI/4  X
-  fabs();                  // Stack: |X| PI/4  X
-  fcmp(tmp);
-  jcc(Assembler::above, slow_case);
-
-  // fastest case: -pi/4 <= x <= pi/4
-  switch(trig) {
-  case 's':
-    fsin();
-    break;
-  case 'c':
-    fcos();
-    break;
-  case 't':
-    ftan();
-    break;
-  default:
-    assert(false, "bad intrinsic");
-    break;
-  }
-  jmp(done);
-
-  // slow case: runtime call
-  bind(slow_case);
-  // Preserve registers across runtime call
-  pushad();
-  int incoming_argument_and_return_value_offset = -1;
-  if (num_fpu_regs_in_use > 1) {
-    // Must preserve all other FPU regs (could alternatively convert
-    // SharedRuntime::dsin and dcos into assembly routines known not to trash
-    // FPU state, but can not trust C compiler)
-    NEEDS_CLEANUP;
-    // NOTE that in this case we also push the incoming argument to
-    // the stack and restore it later; we also use this stack slot to
-    // hold the return value from dsin or dcos.
-    for (int i = 0; i < num_fpu_regs_in_use; i++) {
-      subl(rsp, wordSize*2);
-      fstp_d(Address(rsp, 0));
-    }
-    incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1);
-    fld_d(Address(rsp, incoming_argument_and_return_value_offset));
-  }
-  subl(rsp, wordSize*2);
-  fstp_d(Address(rsp, 0));
-  // NOTE: we must not use call_VM_leaf here because that requires a
-  // complete interpreter frame in debug mode -- same bug as 4387334
-  NEEDS_CLEANUP;
-  // Need to add stack banging before this runtime call if it needs to
-  // be taken; however, there is no generic stack banging routine at
-  // the MacroAssembler level
-  switch(trig) {
-  case 's':
-    {
-      call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin)));
-    }
-    break;
-  case 'c':
-    {
-      call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos)));
-    }
-    break;
-  case 't':
-    {
-      call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan)));
-    }
-    break;
-  default:
-    assert(false, "bad intrinsic");
-    break;
-  }
-  addl(rsp, wordSize * 2);
-  if (num_fpu_regs_in_use > 1) {
-    // Must save return value to stack and then restore entire FPU stack
-    fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
-    for (int i = 0; i < num_fpu_regs_in_use; i++) {
-      fld_d(Address(rsp, 0));
-      addl(rsp, wordSize*2);
-    }
-  }
-  popad();
-
-  // Come here with result in F-TOS
-  bind(done);
-
-  if (tmp != noreg) {
-    popl(tmp);
-  }
-}
-
-void MacroAssembler::jC2(Register tmp, Label& L) {
-  // set parity bit if FPU flag C2 is set (via rax)
-  save_rax(tmp);
-  fwait(); fnstsw_ax();
-  sahf();
-  restore_rax(tmp);
-  // branch
-  jcc(Assembler::parity, L);
-}
-
-
-void MacroAssembler::jnC2(Register tmp, Label& L) {
-  // set parity bit if FPU flag C2 is set (via rax)
-  save_rax(tmp);
-  fwait(); fnstsw_ax();
-  sahf();
-  restore_rax(tmp);
-  // branch
-  jcc(Assembler::noParity, L);
-}
-
-
-void MacroAssembler::fcmp(Register tmp) {
-  fcmp(tmp, 1, true, true);
-}
-
-
-void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
-  assert(!pop_right || pop_left, "usage error");
-  if (VM_Version::supports_cmov()) {
-    assert(tmp == noreg, "unneeded temp");
-    if (pop_left) {
-      fucomip(index);
-    } else {
-      fucomi(index);
-    }
-    if (pop_right) {
-      fpop();
-    }
-  } else {
-    assert(tmp != noreg, "need temp");
-    if (pop_left) {
-      if (pop_right) {
-        fcompp();
-      } else {
-        fcomp(index);
-      }
-    } else {
-      fcom(index);
-    }
-    // convert FPU condition into eflags condition via rax,
-    save_rax(tmp);
-    fwait(); fnstsw_ax();
-    sahf();
-    restore_rax(tmp);
-  }
-  // condition codes set as follows:
-  //
-  // CF (corresponds to C0) if x < y
-  // PF (corresponds to C2) if unordered
-  // ZF (corresponds to C3) if x = y
-}
-
-
-void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
-  fcmp2int(dst, unordered_is_less, 1, true, true);
-}
-
-
-void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
-  fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
-  Label L;
-  if (unordered_is_less) {
-    movl(dst, -1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::below , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    increment(dst);
-  } else { // unordered is greater
-    movl(dst, 1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::above , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    decrement(dst);
-  }
-  bind(L);
-}
-
-void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
-  ucomiss(opr1, opr2);
-
-  Label L;
-  if (unordered_is_less) {
-    movl(dst, -1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::below , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    increment(dst);
-  } else { // unordered is greater
-    movl(dst, 1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::above , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    decrement(dst);
-  }
-  bind(L);
-}
-
-void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
-  ucomisd(opr1, opr2);
-
-  Label L;
-  if (unordered_is_less) {
-    movl(dst, -1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::below , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    increment(dst);
-  } else { // unordered is greater
-    movl(dst, 1);
-    jcc(Assembler::parity, L);
-    jcc(Assembler::above , L);
-    movl(dst, 0);
-    jcc(Assembler::equal , L);
-    decrement(dst);
-  }
-  bind(L);
-}
-
-
-
-void MacroAssembler::fpop() {
-  ffree();
-  fincstp();
-}
-
-
-void MacroAssembler::sign_extend_short(Register reg) {
-  if (VM_Version::is_P6()) {
-    movsxw(reg, reg);
-  } else {
-    shll(reg, 16);
-    sarl(reg, 16);
-  }
-}
-
-
-void MacroAssembler::sign_extend_byte(Register reg) {
-  if (VM_Version::is_P6() && reg->has_byte_register()) {
-    movsxb(reg, reg);
-  } else {
-    shll(reg, 24);
-    sarl(reg, 24);
-  }
-}
-
-
-void MacroAssembler::division_with_shift (Register reg, int shift_value) {
-  assert (shift_value > 0, "illegal shift value");
-  Label _is_positive;
-  testl (reg, reg);
-  jcc (Assembler::positive, _is_positive);
-  int offset = (1 << shift_value) - 1 ;
-
-  increment(reg, offset);
-
-  bind (_is_positive);
-  sarl(reg, shift_value);
-}
-
-
-void MacroAssembler::round_to(Register reg, int modulus) {
-  addl(reg, modulus - 1);
-  andl(reg, -modulus);
-}
-
-// C++ bool manipulation
-
-void MacroAssembler::movbool(Register dst, Address src) {
-  if(sizeof(bool) == 1)
-    movb(dst, src);
-  else if(sizeof(bool) == 2)
-    movw(dst, src);
-  else if(sizeof(bool) == 4)
-    movl(dst, src);
-  else
-    // unsupported
-    ShouldNotReachHere();
-}
-
-void MacroAssembler::movbool(Address dst, bool boolconst) {
-  if(sizeof(bool) == 1)
-    movb(dst, (int) boolconst);
-  else if(sizeof(bool) == 2)
-    movw(dst, (int) boolconst);
-  else if(sizeof(bool) == 4)
-    movl(dst, (int) boolconst);
-  else
-    // unsupported
-    ShouldNotReachHere();
-}
-
-void MacroAssembler::movbool(Address dst, Register src) {
-  if(sizeof(bool) == 1)
-    movb(dst, src);
-  else if(sizeof(bool) == 2)
-    movw(dst, src);
-  else if(sizeof(bool) == 4)
-    movl(dst, src);
-  else
-    // unsupported
-    ShouldNotReachHere();
-}
-
-void MacroAssembler::testbool(Register dst) {
-  if(sizeof(bool) == 1)
-    testb(dst, (int) 0xff);
-  else if(sizeof(bool) == 2) {
-    // testw implementation needed for two byte bools
-    ShouldNotReachHere();
-  } else if(sizeof(bool) == 4)
-    testl(dst, dst);
-  else
-    // unsupported
-    ShouldNotReachHere();
-}
-
-void MacroAssembler::verify_oop(Register reg, const char* s) {
-  if (!VerifyOops) return;
-  // Pass register number to verify_oop_subroutine
-  char* b = new char[strlen(s) + 50];
-  sprintf(b, "verify_oop: %s: %s", reg->name(), s);
-  pushl(rax);                          // save rax,
-  pushl(reg);                          // pass register argument
-  ExternalAddress buffer((address) b);
-  pushptr(buffer.addr());
-  // call indirectly to solve generation ordering problem
-  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
-  call(rax);
-}
-
-
-void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
-  if (!VerifyOops) return;
-  // QQQ fix this
-  // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
-  // Pass register number to verify_oop_subroutine
-  char* b = new char[strlen(s) + 50];
-  sprintf(b, "verify_oop_addr: %s", s);
-  pushl(rax);                          // save rax,
-  // addr may contain rsp so we will have to adjust it based on the push
-  // we just did
-  if (addr.uses(rsp)) {
-    leal(rax, addr);
-    pushl(Address(rax, BytesPerWord));
-  } else {
-    pushl(addr);
-  }
-  ExternalAddress buffer((address) b);
-  // pass msg argument
-  pushptr(buffer.addr());
-  // call indirectly to solve generation ordering problem
-  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
-  call(rax);
-  // Caller pops the arguments and restores rax, from the stack
-}
-
-
-void MacroAssembler::stop(const char* msg) {
-  ExternalAddress message((address)msg);
-  // push address of message
-  pushptr(message.addr());
-  { Label L; call(L, relocInfo::none); bind(L); }     // push eip
-  pushad();                                           // push registers
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
-  hlt();
-}
-
-
-void MacroAssembler::warn(const char* msg) {
-  push_CPU_state();
-
-  ExternalAddress message((address) msg);
-  // push address of message
-  pushptr(message.addr());
-
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
-  addl(rsp, wordSize);       // discard argument
-  pop_CPU_state();
-}
-
-
-void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
-  // In order to get locks to work, we need to fake a in_VM state
-  JavaThread* thread = JavaThread::current();
-  JavaThreadState saved_state = thread->thread_state();
-  thread->set_thread_state(_thread_in_vm);
-  if (ShowMessageBoxOnError) {
-    JavaThread* thread = JavaThread::current();
-    JavaThreadState saved_state = thread->thread_state();
-    thread->set_thread_state(_thread_in_vm);
-    ttyLocker ttyl;
-    if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
-      BytecodeCounter::print();
-    }
-    // To see where a verify_oop failed, get $ebx+40/X for this frame.
-    // This is the value of eip which points to where verify_oop will return.
-    if (os::message_box(msg, "Execution stopped, print registers?")) {
-      tty->print_cr("eip = 0x%08x", eip);
-      tty->print_cr("rax, = 0x%08x", rax);
-      tty->print_cr("rbx, = 0x%08x", rbx);
-      tty->print_cr("rcx = 0x%08x", rcx);
-      tty->print_cr("rdx = 0x%08x", rdx);
-      tty->print_cr("rdi = 0x%08x", rdi);
-      tty->print_cr("rsi = 0x%08x", rsi);
-      tty->print_cr("rbp, = 0x%08x", rbp);
-      tty->print_cr("rsp = 0x%08x", rsp);
-      BREAKPOINT;
-    }
-  } else {
-    ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
-    assert(false, "DEBUG MESSAGE");
-  }
-  ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
-}
-
-
-
-void MacroAssembler::os_breakpoint() {
-  // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
-  // (e.g., MSVC can't call ps() otherwise)
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-
-void MacroAssembler::push_fTOS() {
-  subl(rsp, 2 * wordSize);
-  fstp_d(Address(rsp, 0));
-}
-
-
-void MacroAssembler::pop_fTOS() {
-  fld_d(Address(rsp, 0));
-  addl(rsp, 2 * wordSize);
-}
-
-
-void MacroAssembler::empty_FPU_stack() {
-  if (VM_Version::supports_mmx()) {
-    emms();
-  } else {
-    for (int i = 8; i-- > 0; ) ffree(i);
-  }
-}
-
-
-class ControlWord {
- public:
-  int32_t _value;
-
-  int  rounding_control() const        { return  (_value >> 10) & 3      ; }
-  int  precision_control() const       { return  (_value >>  8) & 3      ; }
-  bool precision() const               { return ((_value >>  5) & 1) != 0; }
-  bool underflow() const               { return ((_value >>  4) & 1) != 0; }
-  bool overflow() const                { return ((_value >>  3) & 1) != 0; }
-  bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
-  bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
-  bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
-
-  void print() const {
-    // rounding control
-    const char* rc;
-    switch (rounding_control()) {
-      case 0: rc = "round near"; break;
-      case 1: rc = "round down"; break;
-      case 2: rc = "round up  "; break;
-      case 3: rc = "chop      "; break;
-    };
-    // precision control
-    const char* pc;
-    switch (precision_control()) {
-      case 0: pc = "24 bits "; break;
-      case 1: pc = "reserved"; break;
-      case 2: pc = "53 bits "; break;
-      case 3: pc = "64 bits "; break;
-    };
-    // flags
-    char f[9];
-    f[0] = ' ';
-    f[1] = ' ';
-    f[2] = (precision   ()) ? 'P' : 'p';
-    f[3] = (underflow   ()) ? 'U' : 'u';
-    f[4] = (overflow    ()) ? 'O' : 'o';
-    f[5] = (zero_divide ()) ? 'Z' : 'z';
-    f[6] = (denormalized()) ? 'D' : 'd';
-    f[7] = (invalid     ()) ? 'I' : 'i';
-    f[8] = '\x0';
-    // output
-    printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
-  }
-
-};
-
-
-class StatusWord {
- public:
-  int32_t _value;
-
-  bool busy() const                    { return ((_value >> 15) & 1) != 0; }
-  bool C3() const                      { return ((_value >> 14) & 1) != 0; }
-  bool C2() const                      { return ((_value >> 10) & 1) != 0; }
-  bool C1() const                      { return ((_value >>  9) & 1) != 0; }
-  bool C0() const                      { return ((_value >>  8) & 1) != 0; }
-  int  top() const                     { return  (_value >> 11) & 7      ; }
-  bool error_status() const            { return ((_value >>  7) & 1) != 0; }
-  bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
-  bool precision() const               { return ((_value >>  5) & 1) != 0; }
-  bool underflow() const               { return ((_value >>  4) & 1) != 0; }
-  bool overflow() const                { return ((_value >>  3) & 1) != 0; }
-  bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
-  bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
-  bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
-
-  void print() const {
-    // condition codes
-    char c[5];
-    c[0] = (C3()) ? '3' : '-';
-    c[1] = (C2()) ? '2' : '-';
-    c[2] = (C1()) ? '1' : '-';
-    c[3] = (C0()) ? '0' : '-';
-    c[4] = '\x0';
-    // flags
-    char f[9];
-    f[0] = (error_status()) ? 'E' : '-';
-    f[1] = (stack_fault ()) ? 'S' : '-';
-    f[2] = (precision   ()) ? 'P' : '-';
-    f[3] = (underflow   ()) ? 'U' : '-';
-    f[4] = (overflow    ()) ? 'O' : '-';
-    f[5] = (zero_divide ()) ? 'Z' : '-';
-    f[6] = (denormalized()) ? 'D' : '-';
-    f[7] = (invalid     ()) ? 'I' : '-';
-    f[8] = '\x0';
-    // output
-    printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
-  }
-
-};
-
-
-class TagWord {
- public:
-  int32_t _value;
-
-  int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
-
-  void print() const {
-    printf("%04x", _value & 0xFFFF);
-  }
-
-};
-
-
-class FPU_Register {
- public:
-  int32_t _m0;
-  int32_t _m1;
-  int16_t _ex;
-
-  bool is_indefinite() const           {
-    return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
-  }
-
-  void print() const {
-    char  sign = (_ex < 0) ? '-' : '+';
-    const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
-    printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
-  };
-
-};
-
-
-class FPU_State {
- public:
-  enum {
-    register_size       = 10,
-    number_of_registers =  8,
-    register_mask       =  7
-  };
-
-  ControlWord  _control_word;
-  StatusWord   _status_word;
-  TagWord      _tag_word;
-  int32_t      _error_offset;
-  int32_t      _error_selector;
-  int32_t      _data_offset;
-  int32_t      _data_selector;
-  int8_t       _register[register_size * number_of_registers];
-
-  int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
-  FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
-
-  const char* tag_as_string(int tag) const {
-    switch (tag) {
-      case 0: return "valid";
-      case 1: return "zero";
-      case 2: return "special";
-      case 3: return "empty";
-    }
-    ShouldNotReachHere()
-    return NULL;
-  }
-
-  void print() const {
-    // print computation registers
-    { int t = _status_word.top();
-      for (int i = 0; i < number_of_registers; i++) {
-        int j = (i - t) & register_mask;
-        printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
-        st(j)->print();
-        printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
-      }
-    }
-    printf("\n");
-    // print control registers
-    printf("ctrl = "); _control_word.print(); printf("\n");
-    printf("stat = "); _status_word .print(); printf("\n");
-    printf("tags = "); _tag_word    .print(); printf("\n");
-  }
-
-};
-
-
-class Flag_Register {
- public:
-  int32_t _value;
-
-  bool overflow() const                { return ((_value >> 11) & 1) != 0; }
-  bool direction() const               { return ((_value >> 10) & 1) != 0; }
-  bool sign() const                    { return ((_value >>  7) & 1) != 0; }
-  bool zero() const                    { return ((_value >>  6) & 1) != 0; }
-  bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
-  bool parity() const                  { return ((_value >>  2) & 1) != 0; }
-  bool carry() const                   { return ((_value >>  0) & 1) != 0; }
-
-  void print() const {
-    // flags
-    char f[8];
-    f[0] = (overflow       ()) ? 'O' : '-';
-    f[1] = (direction      ()) ? 'D' : '-';
-    f[2] = (sign           ()) ? 'S' : '-';
-    f[3] = (zero           ()) ? 'Z' : '-';
-    f[4] = (auxiliary_carry()) ? 'A' : '-';
-    f[5] = (parity         ()) ? 'P' : '-';
-    f[6] = (carry          ()) ? 'C' : '-';
-    f[7] = '\x0';
-    // output
-    printf("%08x  flags = %s", _value, f);
-  }
-
-};
-
-
-class IU_Register {
- public:
-  int32_t _value;
-
-  void print() const {
-    printf("%08x  %11d", _value, _value);
-  }
-
-};
-
-
-class IU_State {
- public:
-  Flag_Register _eflags;
-  IU_Register   _rdi;
-  IU_Register   _rsi;
-  IU_Register   _rbp;
-  IU_Register   _rsp;
-  IU_Register   _rbx;
-  IU_Register   _rdx;
-  IU_Register   _rcx;
-  IU_Register   _rax;
-
-  void print() const {
-    // computation registers
-    printf("rax,  = "); _rax.print(); printf("\n");
-    printf("rbx,  = "); _rbx.print(); printf("\n");
-    printf("rcx  = "); _rcx.print(); printf("\n");
-    printf("rdx  = "); _rdx.print(); printf("\n");
-    printf("rdi  = "); _rdi.print(); printf("\n");
-    printf("rsi  = "); _rsi.print(); printf("\n");
-    printf("rbp,  = "); _rbp.print(); printf("\n");
-    printf("rsp  = "); _rsp.print(); printf("\n");
-    printf("\n");
-    // control registers
-    printf("flgs = "); _eflags.print(); printf("\n");
-  }
-};
-
-
-class CPU_State {
- public:
-  FPU_State _fpu_state;
-  IU_State  _iu_state;
-
-  void print() const {
-    printf("--------------------------------------------------\n");
-    _iu_state .print();
-    printf("\n");
-    _fpu_state.print();
-    printf("--------------------------------------------------\n");
-  }
-
-};
-
-
-static void _print_CPU_state(CPU_State* state) {
-  state->print();
-};
-
-
-void MacroAssembler::print_CPU_state() {
-  push_CPU_state();
-  pushl(rsp);                // pass CPU state
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
-  addl(rsp, wordSize);       // discard argument
-  pop_CPU_state();
-}
-
-
-static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
-  static int counter = 0;
-  FPU_State* fs = &state->_fpu_state;
-  counter++;
-  // For leaf calls, only verify that the top few elements remain empty.
-  // We only need 1 empty at the top for C2 code.
-  if( stack_depth < 0 ) {
-    if( fs->tag_for_st(7) != 3 ) {
-      printf("FPR7 not empty\n");
-      state->print();
-      assert(false, "error");
-      return false;
-    }
-    return true;                // All other stack states do not matter
-  }
-
-  assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
-         "bad FPU control word");
-
-  // compute stack depth
-  int i = 0;
-  while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
-  int d = i;
-  while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
-  // verify findings
-  if (i != FPU_State::number_of_registers) {
-    // stack not contiguous
-    printf("%s: stack not contiguous at ST%d\n", s, i);
-    state->print();
-    assert(false, "error");
-    return false;
-  }
-  // check if computed stack depth corresponds to expected stack depth
-  if (stack_depth < 0) {
-    // expected stack depth is -stack_depth or less
-    if (d > -stack_depth) {
-      // too many elements on the stack
-      printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
-      state->print();
-      assert(false, "error");
-      return false;
-    }
-  } else {
-    // expected stack depth is stack_depth
-    if (d != stack_depth) {
-      // wrong stack depth
-      printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
-      state->print();
-      assert(false, "error");
-      return false;
-    }
-  }
-  // everything is cool
-  return true;
-}
-
-
-void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
-  if (!VerifyFPU) return;
-  push_CPU_state();
-  pushl(rsp);                // pass CPU state
-  ExternalAddress msg((address) s);
-  // pass message string s
-  pushptr(msg.addr());
-  pushl(stack_depth);        // pass stack depth
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
-  addl(rsp, 3 * wordSize);   // discard arguments
-  // check for error
-  { Label L;
-    testl(rax, rax);
-    jcc(Assembler::notZero, L);
-    int3();                  // break if error condition
-    bind(L);
-  }
-  pop_CPU_state();
-}
-
-
-void MacroAssembler::push_IU_state() {
-  pushad();
-  pushfd();
-}
-
-
-void MacroAssembler::pop_IU_state() {
-  popfd();
-  popad();
-}
-
-
-void MacroAssembler::push_FPU_state() {
-  subl(rsp, FPUStateSizeInWords * wordSize);
-  fnsave(Address(rsp, 0));
-  fwait();
-}
-
-
-void MacroAssembler::pop_FPU_state() {
-  frstor(Address(rsp, 0));
-  addl(rsp, FPUStateSizeInWords * wordSize);
-}
-
-
-void MacroAssembler::push_CPU_state() {
-  push_IU_state();
-  push_FPU_state();
-}
-
-
-void MacroAssembler::pop_CPU_state() {
-  pop_FPU_state();
-  pop_IU_state();
-}
-
-
-void MacroAssembler::push_callee_saved_registers() {
-  pushl(rsi);
-  pushl(rdi);
-  pushl(rdx);
-  pushl(rcx);
-}
-
-
-void MacroAssembler::pop_callee_saved_registers() {
-  popl(rcx);
-  popl(rdx);
-  popl(rdi);
-  popl(rsi);
-}
-
-
-void MacroAssembler::set_word_if_not_zero(Register dst) {
-  xorl(dst, dst);
-  set_byte_if_not_zero(dst);
-}
-
-// Write serialization page so VM thread can do a pseudo remote membar.
-// We use the current thread pointer to calculate a thread specific
-// offset to write to within the page. This minimizes bus traffic
-// due to cache line collision.
-void MacroAssembler::serialize_memory(Register thread, Register tmp) {
-  movl(tmp, thread);
-  shrl(tmp, os::get_serialize_page_shift_count());
-  andl(tmp, (os::vm_page_size() - sizeof(int)));
-
-  Address index(noreg, tmp, Address::times_1);
-  ExternalAddress page(os::get_memory_serialize_page());
-
-  movptr(ArrayAddress(page, index), tmp);
-}
-
-
-void MacroAssembler::verify_tlab() {
-#ifdef ASSERT
-  if (UseTLAB && VerifyOops) {
-    Label next, ok;
-    Register t1 = rsi;
-    Register thread_reg = rbx;
-
-    pushl(t1);
-    pushl(thread_reg);
-    get_thread(thread_reg);
-
-    movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
-    cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
-    jcc(Assembler::aboveEqual, next);
-    stop("assert(top >= start)");
-    should_not_reach_here();
-
-    bind(next);
-    movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
-    cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
-    jcc(Assembler::aboveEqual, ok);
-    stop("assert(top <= end)");
-    should_not_reach_here();
-
-    bind(ok);
-    popl(thread_reg);
-    popl(t1);
-  }
-#endif
-}
-
-
-// Defines obj, preserves var_size_in_bytes
-void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
-                                   Register t1, Label& slow_case) {
-  assert(obj == rax, "obj must be in rax, for cmpxchg");
-  assert_different_registers(obj, var_size_in_bytes, t1);
-  Register end = t1;
-  Label retry;
-  bind(retry);
-  ExternalAddress heap_top((address) Universe::heap()->top_addr());
-  movptr(obj, heap_top);
-  if (var_size_in_bytes == noreg) {
-    leal(end, Address(obj, con_size_in_bytes));
-  } else {
-    leal(end, Address(obj, var_size_in_bytes, Address::times_1));
-  }
-  // if end < obj then we wrapped around => object too long => slow case
-  cmpl(end, obj);
-  jcc(Assembler::below, slow_case);
-  cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
-  jcc(Assembler::above, slow_case);
-  // Compare obj with the top addr, and if still equal, store the new top addr in
-  // end at the address of the top addr pointer. Sets ZF if was equal, and clears
-  // it otherwise. Use lock prefix for atomicity on MPs.
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchgptr(end, heap_top);
-  jcc(Assembler::notEqual, retry);
-}
-
-
-// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
-void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
-                                   Register t1, Register t2, Label& slow_case) {
-  assert_different_registers(obj, t1, t2);
-  assert_different_registers(obj, var_size_in_bytes, t1);
-  Register end = t2;
-  Register thread = t1;
-
-  verify_tlab();
-
-  get_thread(thread);
-
-  movl(obj, Address(thread, JavaThread::tlab_top_offset()));
-  if (var_size_in_bytes == noreg) {
-    leal(end, Address(obj, con_size_in_bytes));
-  } else {
-    leal(end, Address(obj, var_size_in_bytes, Address::times_1));
-  }
-  cmpl(end, Address(thread, JavaThread::tlab_end_offset()));
-  jcc(Assembler::above, slow_case);
-
-  // update the tlab top pointer
-  movl(Address(thread, JavaThread::tlab_top_offset()), end);
-
-  // recover var_size_in_bytes if necessary
-  if (var_size_in_bytes == end) {
-    subl(var_size_in_bytes, obj);
-  }
-  verify_tlab();
-}
-
-// Preserves rbx, and rdx.
-void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
-  Register top = rax;
-  Register t1  = rcx;
-  Register t2  = rsi;
-  Register thread_reg = rdi;
-  assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
-  Label do_refill, discard_tlab;
-
-  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
-    // No allocation in the shared eden.
-    jmp(slow_case);
-  }
-
-  get_thread(thread_reg);
-
-  movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
-  movl(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
-
-  // calculate amount of free space
-  subl(t1, top);
-  shrl(t1, LogHeapWordSize);
-
-  // Retain tlab and allocate object in shared space if
-  // the amount free in the tlab is too large to discard.
-  cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
-  jcc(Assembler::lessEqual, discard_tlab);
-
-  // Retain
-  movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
-  addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
-  if (TLABStats) {
-    // increment number of slow_allocations
-    addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
-  }
-  jmp(try_eden);
-
-  bind(discard_tlab);
-  if (TLABStats) {
-    // increment number of refills
-    addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
-    // accumulate wastage -- t1 is amount free in tlab
-    addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
-  }
-
-  // if tlab is currently allocated (top or end != null) then
-  // fill [top, end + alignment_reserve) with array object
-  testl (top, top);
-  jcc(Assembler::zero, do_refill);
-
-  // set up the mark word
-  movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2));
-  // set the length to the remaining space
-  subl(t1, typeArrayOopDesc::header_size(T_INT));
-  addl(t1, ThreadLocalAllocBuffer::alignment_reserve());
-  shll(t1, log2_intptr(HeapWordSize/sizeof(jint)));
-  movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
-  // set klass to intArrayKlass
-  // dubious reloc why not an oop reloc?
-  movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
-  movl(Address(top, oopDesc::klass_offset_in_bytes()), t1);
-
-  // refill the tlab with an eden allocation
-  bind(do_refill);
-  movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
-  shll(t1, LogHeapWordSize);
-  // add object_size ??
-  eden_allocate(top, t1, 0, t2, slow_case);
-
-  // Check that t1 was preserved in eden_allocate.
-#ifdef ASSERT
-  if (UseTLAB) {
-    Label ok;
-    Register tsize = rsi;
-    assert_different_registers(tsize, thread_reg, t1);
-    pushl(tsize);
-    movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
-    shll(tsize, LogHeapWordSize);
-    cmpl(t1, tsize);
-    jcc(Assembler::equal, ok);
-    stop("assert(t1 != tlab size)");
-    should_not_reach_here();
-
-    bind(ok);
-    popl(tsize);
-  }
-#endif
-  movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
-  movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
-  addl(top, t1);
-  subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
-  movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
-  verify_tlab();
-  jmp(retry);
-}
-
-
-int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
-                                         bool swap_reg_contains_mark,
-                                         Label& done, Label* slow_case,
-                                         BiasedLockingCounters* counters) {
-  assert(UseBiasedLocking, "why call this otherwise?");
-  assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
-  assert_different_registers(lock_reg, obj_reg, swap_reg);
-
-  if (PrintBiasedLockingStatistics && counters == NULL)
-    counters = BiasedLocking::counters();
-
-  bool need_tmp_reg = false;
-  if (tmp_reg == noreg) {
-    need_tmp_reg = true;
-    tmp_reg = lock_reg;
-  } else {
-    assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
-  }
-  assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
-  Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
-  Address klass_addr     (obj_reg, oopDesc::klass_offset_in_bytes());
-  Address saved_mark_addr(lock_reg, 0);
-
-  // Biased locking
-  // See whether the lock is currently biased toward our thread and
-  // whether the epoch is still valid
-  // Note that the runtime guarantees sufficient alignment of JavaThread
-  // pointers to allow age to be placed into low bits
-  // First check to see whether biasing is even enabled for this object
-  Label cas_label;
-  int null_check_offset = -1;
-  if (!swap_reg_contains_mark) {
-    null_check_offset = offset();
-    movl(swap_reg, mark_addr);
-  }
-  if (need_tmp_reg) {
-    pushl(tmp_reg);
-  }
-  movl(tmp_reg, swap_reg);
-  andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
-  cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
-  if (need_tmp_reg) {
-    popl(tmp_reg);
-  }
-  jcc(Assembler::notEqual, cas_label);
-  // The bias pattern is present in the object's header. Need to check
-  // whether the bias owner and the epoch are both still current.
-  // Note that because there is no current thread register on x86 we
-  // need to store off the mark word we read out of the object to
-  // avoid reloading it and needing to recheck invariants below. This
-  // store is unfortunate but it makes the overall code shorter and
-  // simpler.
-  movl(saved_mark_addr, swap_reg);
-  if (need_tmp_reg) {
-    pushl(tmp_reg);
-  }
-  get_thread(tmp_reg);
-  xorl(swap_reg, tmp_reg);
-  if (swap_reg_contains_mark) {
-    null_check_offset = offset();
-  }
-  movl(tmp_reg, klass_addr);
-  xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-  andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
-  if (need_tmp_reg) {
-    popl(tmp_reg);
-  }
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address)counters->biased_lock_entry_count_addr()));
-  }
-  jcc(Assembler::equal, done);
-
-  Label try_revoke_bias;
-  Label try_rebias;
-
-  // At this point we know that the header has the bias pattern and
-  // that we are not the bias owner in the current epoch. We need to
-  // figure out more details about the state of the header in order to
-  // know what operations can be legally performed on the object's
-  // header.
-
-  // If the low three bits in the xor result aren't clear, that means
-  // the prototype header is no longer biased and we have to revoke
-  // the bias on this object.
-  testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
-  jcc(Assembler::notZero, try_revoke_bias);
-
-  // Biasing is still enabled for this data type. See whether the
-  // epoch of the current bias is still valid, meaning that the epoch
-  // bits of the mark word are equal to the epoch bits of the
-  // prototype header. (Note that the prototype header's epoch bits
-  // only change at a safepoint.) If not, attempt to rebias the object
-  // toward the current thread. Note that we must be absolutely sure
-  // that the current epoch is invalid in order to do this because
-  // otherwise the manipulations it performs on the mark word are
-  // illegal.
-  testl(swap_reg, markOopDesc::epoch_mask_in_place);
-  jcc(Assembler::notZero, try_rebias);
-
-  // The epoch of the current bias is still valid but we know nothing
-  // about the owner; it might be set or it might be clear. Try to
-  // acquire the bias of the object using an atomic operation. If this
-  // fails we will go in to the runtime to revoke the object's bias.
-  // Note that we first construct the presumed unbiased header so we
-  // don't accidentally blow away another thread's valid bias.
-  movl(swap_reg, saved_mark_addr);
-  andl(swap_reg,
-       markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
-  if (need_tmp_reg) {
-    pushl(tmp_reg);
-  }
-  get_thread(tmp_reg);
-  orl(tmp_reg, swap_reg);
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchg(tmp_reg, Address(obj_reg, 0));
-  if (need_tmp_reg) {
-    popl(tmp_reg);
-  }
-  // If the biasing toward our thread failed, this means that
-  // another thread succeeded in biasing it toward itself and we
-  // need to revoke that bias. The revocation will occur in the
-  // interpreter runtime in the slow case.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
-  }
-  if (slow_case != NULL) {
-    jcc(Assembler::notZero, *slow_case);
-  }
-  jmp(done);
-
-  bind(try_rebias);
-  // At this point we know the epoch has expired, meaning that the
-  // current "bias owner", if any, is actually invalid. Under these
-  // circumstances _only_, we are allowed to use the current header's
-  // value as the comparison value when doing the cas to acquire the
-  // bias in the current epoch. In other words, we allow transfer of
-  // the bias from one thread to another directly in this situation.
-  //
-  // FIXME: due to a lack of registers we currently blow away the age
-  // bits in this situation. Should attempt to preserve them.
-  if (need_tmp_reg) {
-    pushl(tmp_reg);
-  }
-  get_thread(tmp_reg);
-  movl(swap_reg, klass_addr);
-  orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-  movl(swap_reg, saved_mark_addr);
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchg(tmp_reg, Address(obj_reg, 0));
-  if (need_tmp_reg) {
-    popl(tmp_reg);
-  }
-  // If the biasing toward our thread failed, then another thread
-  // succeeded in biasing it toward itself and we need to revoke that
-  // bias. The revocation will occur in the runtime in the slow case.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
-  }
-  if (slow_case != NULL) {
-    jcc(Assembler::notZero, *slow_case);
-  }
-  jmp(done);
-
-  bind(try_revoke_bias);
-  // The prototype mark in the klass doesn't have the bias bit set any
-  // more, indicating that objects of this data type are not supposed
-  // to be biased any more. We are going to try to reset the mark of
-  // this object to the prototype value and fall through to the
-  // CAS-based locking scheme. Note that if our CAS fails, it means
-  // that another thread raced us for the privilege of revoking the
-  // bias of this particular object, so it's okay to continue in the
-  // normal locking code.
-  //
-  // FIXME: due to a lack of registers we currently blow away the age
-  // bits in this situation. Should attempt to preserve them.
-  movl(swap_reg, saved_mark_addr);
-  if (need_tmp_reg) {
-    pushl(tmp_reg);
-  }
-  movl(tmp_reg, klass_addr);
-  movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchg(tmp_reg, Address(obj_reg, 0));
-  if (need_tmp_reg) {
-    popl(tmp_reg);
-  }
-  // Fall through to the normal CAS-based lock, because no matter what
-  // the result of the above CAS, some thread must have succeeded in
-  // removing the bias bit from the object's header.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
-  }
-
-  bind(cas_label);
-
-  return null_check_offset;
-}
-
-
-void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
-  assert(UseBiasedLocking, "why call this otherwise?");
-
-  // Check for biased locking unlock case, which is a no-op
-  // Note: we do not have to check the thread ID for two reasons.
-  // First, the interpreter checks for IllegalMonitorStateException at
-  // a higher level. Second, if the bias was revoked while we held the
-  // lock, the object could not be rebiased toward another thread, so
-  // the bias bit would be clear.
-  movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
-  andl(temp_reg, markOopDesc::biased_lock_mask_in_place);
-  cmpl(temp_reg, markOopDesc::biased_lock_pattern);
-  jcc(Assembler::equal, done);
-}
-
-
-Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
-  switch (cond) {
-    // Note some conditions are synonyms for others
-    case Assembler::zero:         return Assembler::notZero;
-    case Assembler::notZero:      return Assembler::zero;
-    case Assembler::less:         return Assembler::greaterEqual;
-    case Assembler::lessEqual:    return Assembler::greater;
-    case Assembler::greater:      return Assembler::lessEqual;
-    case Assembler::greaterEqual: return Assembler::less;
-    case Assembler::below:        return Assembler::aboveEqual;
-    case Assembler::belowEqual:   return Assembler::above;
-    case Assembler::above:        return Assembler::belowEqual;
-    case Assembler::aboveEqual:   return Assembler::below;
-    case Assembler::overflow:     return Assembler::noOverflow;
-    case Assembler::noOverflow:   return Assembler::overflow;
-    case Assembler::negative:     return Assembler::positive;
-    case Assembler::positive:     return Assembler::negative;
-    case Assembler::parity:       return Assembler::noParity;
-    case Assembler::noParity:     return Assembler::parity;
-  }
-  ShouldNotReachHere(); return Assembler::overflow;
-}
-
-
-void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
-  Condition negated_cond = negate_condition(cond);
-  Label L;
-  jcc(negated_cond, L);
-  atomic_incl(counter_addr);
-  bind(L);
-}
-
-void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
-  pushfd();
-  if (os::is_MP())
-    lock();
-  increment(counter_addr);
-  popfd();
-}
-
-SkipIfEqual::SkipIfEqual(
-    MacroAssembler* masm, const bool* flag_addr, bool value) {
-  _masm = masm;
-  _masm->cmp8(ExternalAddress((address)flag_addr), value);
-  _masm->jcc(Assembler::equal, _label);
-}
-
-SkipIfEqual::~SkipIfEqual() {
-  _masm->bind(_label);
-}
-
-
-// Writes to stack successive pages until offset reached to check for
-// stack overflow + shadow pages.  This clobbers tmp.
-void MacroAssembler::bang_stack_size(Register size, Register tmp) {
-  movl(tmp, rsp);
-  // Bang stack for total size given plus shadow page size.
-  // Bang one page at a time because large size can bang beyond yellow and
-  // red zones.
-  Label loop;
-  bind(loop);
-  movl(Address(tmp, (-os::vm_page_size())), size );
-  subl(tmp, os::vm_page_size());
-  subl(size, os::vm_page_size());
-  jcc(Assembler::greater, loop);
-
-  // Bang down shadow pages too.
-  // The -1 because we already subtracted 1 page.
-  for (int i = 0; i< StackShadowPages-1; i++) {
-    movl(Address(tmp, (-i*os::vm_page_size())), size );
-  }
-}
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1506 +0,0 @@
-/*
- * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-class BiasedLockingCounters;
-
-// Contains all the definitions needed for x86 assembly code generation.
-
-// Calling convention
-class Argument VALUE_OBJ_CLASS_SPEC {
- public:
-  enum {
-#ifdef _LP64
-#ifdef _WIN64
-    n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
-    n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
-#else
-    n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
-    n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
-#endif // _WIN64
-    n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
-    n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
-#else
-    n_register_parameters = 0   // 0 registers used to pass arguments
-#endif // _LP64
-  };
-};
-
-
-#ifdef _LP64
-// Symbolically name the register arguments used by the c calling convention.
-// Windows is different from linux/solaris. So much for standards...
-
-#ifdef _WIN64
-
-REGISTER_DECLARATION(Register, c_rarg0, rcx);
-REGISTER_DECLARATION(Register, c_rarg1, rdx);
-REGISTER_DECLARATION(Register, c_rarg2, r8);
-REGISTER_DECLARATION(Register, c_rarg3, r9);
-
-REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
-
-#else
-
-REGISTER_DECLARATION(Register, c_rarg0, rdi);
-REGISTER_DECLARATION(Register, c_rarg1, rsi);
-REGISTER_DECLARATION(Register, c_rarg2, rdx);
-REGISTER_DECLARATION(Register, c_rarg3, rcx);
-REGISTER_DECLARATION(Register, c_rarg4, r8);
-REGISTER_DECLARATION(Register, c_rarg5, r9);
-
-REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
-REGISTER_DECLARATION(FloatRegister, c_farg4, xmm4);
-REGISTER_DECLARATION(FloatRegister, c_farg5, xmm5);
-REGISTER_DECLARATION(FloatRegister, c_farg6, xmm6);
-REGISTER_DECLARATION(FloatRegister, c_farg7, xmm7);
-
-#endif // _WIN64
-
-// Symbolically name the register arguments used by the Java calling convention.
-// We have control over the convention for java so we can do what we please.
-// What pleases us is to offset the java calling convention so that when
-// we call a suitable jni method the arguments are lined up and we don't
-// have to do little shuffling. A suitable jni method is non-static and a
-// small number of arguments (two fewer args on windows)
-//
-//        |-------------------------------------------------------|
-//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
-//        |-------------------------------------------------------|
-//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
-//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
-//        |-------------------------------------------------------|
-//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
-//        |-------------------------------------------------------|
-
-REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
-REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
-REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
-// Windows runs out of register args here
-#ifdef _WIN64
-REGISTER_DECLARATION(Register, j_rarg3, rdi);
-REGISTER_DECLARATION(Register, j_rarg4, rsi);
-#else
-REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
-REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
-#endif /* _WIN64 */
-REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
-
-REGISTER_DECLARATION(FloatRegister, j_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, j_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, j_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, j_farg3, xmm3);
-REGISTER_DECLARATION(FloatRegister, j_farg4, xmm4);
-REGISTER_DECLARATION(FloatRegister, j_farg5, xmm5);
-REGISTER_DECLARATION(FloatRegister, j_farg6, xmm6);
-REGISTER_DECLARATION(FloatRegister, j_farg7, xmm7);
-
-REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
-REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
-
-REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
-
-#endif // _LP64
-
-// Address is an abstraction used to represent a memory location
-// using any of the amd64 addressing modes with one object.
-//
-// Note: A register location is represented via a Register, not
-//       via an address for efficiency & simplicity reasons.
-
-class ArrayAddress;
-
-class Address VALUE_OBJ_CLASS_SPEC {
- public:
-  enum ScaleFactor {
-    no_scale = -1,
-    times_1  =  0,
-    times_2  =  1,
-    times_4  =  2,
-    times_8  =  3
-  };
-
- private:
-  Register         _base;
-  Register         _index;
-  ScaleFactor      _scale;
-  int              _disp;
-  RelocationHolder _rspec;
-
-  // Easily misused constructor make them private
-#ifndef _LP64
-  Address(address loc, RelocationHolder spec);
-#endif // _LP64
-
- public:
-  // creation
-  Address()
-    : _base(noreg),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(0) {
-  }
-
-  // No default displacement otherwise Register can be implicitly
-  // converted to 0(Register) which is quite a different animal.
-
-  Address(Register base, int disp)
-    : _base(base),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(disp) {
-  }
-
-  Address(Register base, Register index, ScaleFactor scale, int disp = 0)
-    : _base (base),
-      _index(index),
-      _scale(scale),
-      _disp (disp) {
-    assert(!index->is_valid() == (scale == Address::no_scale),
-           "inconsistent address");
-  }
-
-  // The following two overloads are used in connection with the
-  // ByteSize type (see sizes.hpp).  They simplify the use of
-  // ByteSize'd arguments in assembly code. Note that their equivalent
-  // for the optimized build are the member functions with int disp
-  // argument since ByteSize is mapped to an int type in that case.
-  //
-  // Note: DO NOT introduce similar overloaded functions for WordSize
-  // arguments as in the optimized mode, both ByteSize and WordSize
-  // are mapped to the same type and thus the compiler cannot make a
-  // distinction anymore (=> compiler errors).
-
-#ifdef ASSERT
-  Address(Register base, ByteSize disp)
-    : _base(base),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(in_bytes(disp)) {
-  }
-
-  Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
-    : _base(base),
-      _index(index),
-      _scale(scale),
-      _disp(in_bytes(disp)) {
-    assert(!index->is_valid() == (scale == Address::no_scale),
-           "inconsistent address");
-  }
-#endif // ASSERT
-
-  // accessors
-  bool uses(Register reg) const {
-    return _base == reg || _index == reg;
-  }
-
-  // Convert the raw encoding form into the form expected by the constructor for
-  // Address.  An index of 4 (rsp) corresponds to having no index, so convert
-  // that to noreg for the Address constructor.
-  static Address make_raw(int base, int index, int scale, int disp);
-
-  static Address make_array(ArrayAddress);
-
-
- private:
-  bool base_needs_rex() const {
-    return _base != noreg && _base->encoding() >= 8;
-  }
-
-  bool index_needs_rex() const {
-    return _index != noreg &&_index->encoding() >= 8;
-  }
-
-  relocInfo::relocType reloc() const { return _rspec.type(); }
-
-  friend class Assembler;
-  friend class MacroAssembler;
-  friend class LIR_Assembler; // base/index/scale/disp
-};
-
-//
-// AddressLiteral has been split out from Address because operands of this type
-// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
-// the few instructions that need to deal with address literals are unique and the
-// MacroAssembler does not have to implement every instruction in the Assembler
-// in order to search for address literals that may need special handling depending
-// on the instruction and the platform. As small step on the way to merging i486/amd64
-// directories.
-//
-class AddressLiteral VALUE_OBJ_CLASS_SPEC {
-  friend class ArrayAddress;
-  RelocationHolder _rspec;
-  // Typically we use AddressLiterals we want to use their rval
-  // However in some situations we want the lval (effect address) of the item.
-  // We provide a special factory for making those lvals.
-  bool _is_lval;
-
-  // If the target is far we'll need to load the ea of this to
-  // a register to reach it. Otherwise if near we can do rip
-  // relative addressing.
-
-  address          _target;
-
- protected:
-  // creation
-  AddressLiteral()
-    : _is_lval(false),
-      _target(NULL)
-  {}
-
-  public:
-
-
-  AddressLiteral(address target, relocInfo::relocType rtype);
-
-  AddressLiteral(address target, RelocationHolder const& rspec)
-    : _rspec(rspec),
-      _is_lval(false),
-      _target(target)
-  {}
-
-  AddressLiteral addr() {
-    AddressLiteral ret = *this;
-    ret._is_lval = true;
-    return ret;
-  }
-
-
- private:
-
-  address target() { return _target; }
-  bool is_lval() { return _is_lval; }
-
-  relocInfo::relocType reloc() const { return _rspec.type(); }
-  const RelocationHolder& rspec() const { return _rspec; }
-
-  friend class Assembler;
-  friend class MacroAssembler;
-  friend class Address;
-  friend class LIR_Assembler;
-};
-
-// Convience classes
-class RuntimeAddress: public AddressLiteral {
-
-  public:
-
-  RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
-
-};
-
-class OopAddress: public AddressLiteral {
-
-  public:
-
-  OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
-
-};
-
-class ExternalAddress: public AddressLiteral {
-
-  public:
-
-  ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
-
-};
-
-class InternalAddress: public AddressLiteral {
-
-  public:
-
-  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
-
-};
-
-// x86 can do array addressing as a single operation since disp can be an absolute
-// address amd64 can't. We create a class that expresses the concept but does extra
-// magic on amd64 to get the final result
-
-class ArrayAddress VALUE_OBJ_CLASS_SPEC {
-  private:
-
-  AddressLiteral _base;
-  Address        _index;
-
-  public:
-
-  ArrayAddress() {};
-  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
-  AddressLiteral base() { return _base; }
-  Address index() { return _index; }
-
-};
-
-#ifndef _LP64
-const int FPUStateSizeInWords = 27;
-#else
-const int FPUStateSizeInWords = 512 / wordSize;
-#endif // _LP64
-
-// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
-// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
-// is what you get. The Assembler is generating code into a CodeBuffer.
-
-class Assembler : public AbstractAssembler  {
-  friend class AbstractAssembler; // for the non-virtual hack
-  friend class LIR_Assembler; // as_Address()
-
- protected:
-  #ifdef ASSERT
-  void check_relocation(RelocationHolder const& rspec, int format);
-  #endif
-
-  inline void emit_long64(jlong x);
-
-  void emit_data(jint data, relocInfo::relocType    rtype, int format /* = 0 */);
-  void emit_data(jint data, RelocationHolder const& rspec, int format /* = 0 */);
-  void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
-  void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
-
-  // Helper functions for groups of instructions
-  void emit_arith_b(int op1, int op2, Register dst, int imm8);
-
-  void emit_arith(int op1, int op2, Register dst, int imm32);
-  // only x86??
-  void emit_arith(int op1, int op2, Register dst, jobject obj);
-  void emit_arith(int op1, int op2, Register dst, Register src);
-
-  void emit_operand(Register reg,
-                    Register base, Register index, Address::ScaleFactor scale,
-                    int disp,
-                    RelocationHolder const& rspec);
-  void emit_operand(Register reg, Address adr);
-
-  // Immediate-to-memory forms
-  void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
-
-  void emit_farith(int b1, int b2, int i);
-
-  // macroassembler?? QQQ
-  bool reachable(AddressLiteral adr) { return true; }
-
-  // These are all easily abused and hence protected
-
-  // Make these disappear in 64bit mode since they would never be correct
-#ifndef _LP64
-  void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
-  void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
-
-  void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
-  void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
-
-  void push_literal32(int32_t imm32, RelocationHolder const& rspec);
-#endif // _LP64
-
-  // These are unique in that we are ensured by the caller that the 32bit
-  // relative in these instructions will always be able to reach the potentially
-  // 64bit address described by entry. Since they can take a 64bit address they
-  // don't have the 32 suffix like the other instructions in this class.
-
-  void call_literal(address entry, RelocationHolder const& rspec);
-  void jmp_literal(address entry, RelocationHolder const& rspec);
-
-
- public:
-  enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
-    zero          = 0x4,
-    notZero       = 0x5,
-    equal         = 0x4,
-    notEqual      = 0x5,
-    less          = 0xc,
-    lessEqual     = 0xe,
-    greater       = 0xf,
-    greaterEqual  = 0xd,
-    below         = 0x2,
-    belowEqual    = 0x6,
-    above         = 0x7,
-    aboveEqual    = 0x3,
-    overflow      = 0x0,
-    noOverflow    = 0x1,
-    carrySet      = 0x2,
-    carryClear    = 0x3,
-    negative      = 0x8,
-    positive      = 0x9,
-    parity        = 0xa,
-    noParity      = 0xb
-  };
-
-  enum Prefix {
-    // segment overrides
-    CS_segment = 0x2e,
-    SS_segment = 0x36,
-    DS_segment = 0x3e,
-    ES_segment = 0x26,
-    FS_segment = 0x64,
-    GS_segment = 0x65,
-
-    REX        = 0x40,
-
-    REX_B      = 0x41,
-    REX_X      = 0x42,
-    REX_XB     = 0x43,
-    REX_R      = 0x44,
-    REX_RB     = 0x45,
-    REX_RX     = 0x46,
-    REX_RXB    = 0x47,
-
-    REX_W      = 0x48,
-
-    REX_WB     = 0x49,
-    REX_WX     = 0x4A,
-    REX_WXB    = 0x4B,
-    REX_WR     = 0x4C,
-    REX_WRB    = 0x4D,
-    REX_WRX    = 0x4E,
-    REX_WRXB   = 0x4F
-  };
-
-  enum WhichOperand {
-    // input to locate_operand, and format code for relocations
-    imm32_operand  = 0,          // embedded 32-bit immediate operand
-    disp32_operand = 1,          // embedded 32-bit displacement or address
-    call32_operand = 2,          // embedded 32-bit self-relative displacement
-    _WhichOperand_limit = 3
-  };
-
-  public:
-
-  // Creation
-  Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
-
-  // Decoding
-  static address locate_operand(address inst, WhichOperand which);
-  static address locate_next_instruction(address inst);
-
-  // Stack
-  void pushad();
-  void popad();
-
-  void pushfd();
-  void popfd();
-
-  void pushl(int imm32);
-  void pushoop(jobject obj);
-
-  void pushl(Register src);
-  void pushl(Address src);
-  // void pushl(Label& L, relocInfo::relocType rtype); ? needed?
-
-  // dummy to prevent NULL being converted to Register
-  void pushl(void* dummy);
-
-  void popl(Register dst);
-  void popl(Address dst);
-
-  // Instruction prefixes
-  void prefix(Prefix p);
-
-  // Moves
-  void movb(Register dst, Address src);
-  void movb(Address dst, int imm8);
-  void movb(Address dst, Register src);
-
-  void movw(Address dst, int imm16);
-  void movw(Register dst, Address src);
-  void movw(Address dst, Register src);
-
-  // these are dummies used to catch attempting to convert NULL to Register
-  void movl(Register dst, void* junk);
-  void movl(Address dst, void* junk);
-
-  void movl(Register dst, int imm32);
-  void movl(Address dst, int imm32);
-  void movl(Register dst, Register src);
-  void movl(Register dst, Address src);
-  void movl(Address dst, Register src);
-
-  void movsxb(Register dst, Address src);
-  void movsxb(Register dst, Register src);
-
-  void movsxw(Register dst, Address src);
-  void movsxw(Register dst, Register src);
-
-  void movzxb(Register dst, Address src);
-  void movzxb(Register dst, Register src);
-
-  void movzxw(Register dst, Address src);
-  void movzxw(Register dst, Register src);
-
-  // Conditional moves (P6 only)
-  void cmovl(Condition cc, Register dst, Register src);
-  void cmovl(Condition cc, Register dst, Address src);
-
-  // Prefetches (SSE, SSE2, 3DNOW only)
-  void prefetcht0(Address src);
-  void prefetcht1(Address src);
-  void prefetcht2(Address src);
-  void prefetchnta(Address src);
-  void prefetchw(Address src);
-  void prefetchr(Address src);
-
-  // Arithmetics
-  void adcl(Register dst, int imm32);
-  void adcl(Register dst, Address src);
-  void adcl(Register dst, Register src);
-
-  void addl(Address dst, int imm32);
-  void addl(Address dst, Register src);
-  void addl(Register dst, int imm32);
-  void addl(Register dst, Address src);
-  void addl(Register dst, Register src);
-
-  void andl(Register dst, int imm32);
-  void andl(Register dst, Address src);
-  void andl(Register dst, Register src);
-
-  void cmpb(Address dst, int imm8);
-  void cmpw(Address dst, int imm16);
-  void cmpl(Address dst, int imm32);
-  void cmpl(Register dst, int imm32);
-  void cmpl(Register dst, Register src);
-  void cmpl(Register dst, Address src);
-
-  // this is a dummy used to catch attempting to convert NULL to Register
-  void cmpl(Register dst, void* junk);
-
- protected:
-  // Don't use next inc() and dec() methods directly. INC & DEC instructions
-  // could cause a partial flag stall since they don't set CF flag.
-  // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
-  // which call inc() & dec() or add() & sub() in accordance with
-  // the product flag UseIncDec value.
-
-  void decl(Register dst);
-  void decl(Address dst);
-
-  void incl(Register dst);
-  void incl(Address dst);
-
- public:
-  void idivl(Register src);
-  void cdql();
-
-  void imull(Register dst, Register src);
-  void imull(Register dst, Register src, int value);
-
-  void leal(Register dst, Address src);
-
-  void mull(Address src);
-  void mull(Register src);
-
-  void negl(Register dst);
-
-  void notl(Register dst);
-
-  void orl(Address dst, int imm32);
-  void orl(Register dst, int imm32);
-  void orl(Register dst, Address src);
-  void orl(Register dst, Register src);
-
-  void rcll(Register dst, int imm8);
-
-  void sarl(Register dst, int imm8);
-  void sarl(Register dst);
-
-  void sbbl(Address dst, int imm32);
-  void sbbl(Register dst, int imm32);
-  void sbbl(Register dst, Address src);
-  void sbbl(Register dst, Register src);
-
-  void shldl(Register dst, Register src);
-
-  void shll(Register dst, int imm8);
-  void shll(Register dst);
-
-  void shrdl(Register dst, Register src);
-
-  void shrl(Register dst, int imm8);
-  void shrl(Register dst);
-
-  void subl(Address dst, int imm32);
-  void subl(Address dst, Register src);
-  void subl(Register dst, int imm32);
-  void subl(Register dst, Address src);
-  void subl(Register dst, Register src);
-
-  void testb(Register dst, int imm8);
-  void testl(Register dst, int imm32);
-  void testl(Register dst, Address src);
-  void testl(Register dst, Register src);
-
-  void xaddl(Address dst, Register src);
-
-  void xorl(Register dst, int imm32);
-  void xorl(Register dst, Address src);
-  void xorl(Register dst, Register src);
-
-  // Miscellaneous
-  void bswap(Register reg);
-  void lock();
-
-  void xchg (Register reg, Address adr);
-  void xchgl(Register dst, Register src);
-
-  void cmpxchg (Register reg, Address adr);
-  void cmpxchg8 (Address adr);
-
-  void nop(int i = 1);
-  void addr_nop_4();
-  void addr_nop_5();
-  void addr_nop_7();
-  void addr_nop_8();
-
-  void hlt();
-  void ret(int imm16);
-  void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
-  void smovl();
-  void rep_movl();
-  void rep_set();
-  void repne_scan();
-  void setb(Condition cc, Register dst);
-  void membar();                // Serializing memory-fence
-  void cpuid();
-  void cld();
-  void std();
-
-  void emit_raw (unsigned char);
-
-  // Calls
-  void call(Label& L, relocInfo::relocType rtype);
-  void call(Register reg);  // push pc; pc <- reg
-  void call(Address adr);   // push pc; pc <- adr
-
-  // Jumps
-  void jmp(Address entry);    // pc <- entry
-  void jmp(Register entry); // pc <- entry
-
-  // Label operations & relative jumps (PPUM Appendix D)
-  void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);   // unconditional jump to L
-
-  // Force an 8-bit jump offset
-  // void jmpb(address entry);
-
-  // Unconditional 8-bit offset jump to L.
-  // WARNING: be very careful using this for forward jumps.  If the label is
-  // not bound within an 8-bit offset of this instruction, a run-time error
-  // will occur.
-  void jmpb(Label& L);
-
-  // jcc is the generic conditional branch generator to run-
-  // time routines, jcc is used for branches to labels. jcc
-  // takes a branch opcode (cc) and a label (L) and generates
-  // either a backward branch or a forward branch and links it
-  // to the label fixup chain. Usage:
-  //
-  // Label L;      // unbound label
-  // jcc(cc, L);   // forward branch to unbound label
-  // bind(L);      // bind label to the current pc
-  // jcc(cc, L);   // backward branch to bound label
-  // bind(L);      // illegal: a label may be bound only once
-  //
-  // Note: The same Label can be used for forward and backward branches
-  // but it may be bound only once.
-
-  void jcc(Condition cc, Label& L,
-           relocInfo::relocType rtype = relocInfo::none);
-
-  // Conditional jump to a 8-bit offset to L.
-  // WARNING: be very careful using this for forward jumps.  If the label is
-  // not bound within an 8-bit offset of this instruction, a run-time error
-  // will occur.
-  void jccb(Condition cc, Label& L);
-
-  // Floating-point operations
-  void fld1();
-  void fldz();
-
-  void fld_s(Address adr);
-  void fld_s(int index);
-  void fld_d(Address adr);
-  void fld_x(Address adr);  // extended-precision (80-bit) format
-
-  void fst_s(Address adr);
-  void fst_d(Address adr);
-
-  void fstp_s(Address adr);
-  void fstp_d(Address adr);
-  void fstp_d(int index);
-  void fstp_x(Address adr); // extended-precision (80-bit) format
-
-  void fild_s(Address adr);
-  void fild_d(Address adr);
-
-  void fist_s (Address adr);
-  void fistp_s(Address adr);
-  void fistp_d(Address adr);
-
-  void fabs();
-  void fchs();
-
-  void flog();
-  void flog10();
-
-  void fldln2();
-  void fyl2x();
-  void fldlg2();
-
-  void fcos();
-  void fsin();
-  void ftan();
-  void fsqrt();
-
-  // "Alternate" versions of instructions place result down in FPU
-  // stack instead of on TOS
-  void fadd_s(Address src);
-  void fadd_d(Address src);
-  void fadd(int i);
-  void fadda(int i); // "alternate" fadd
-
-  void fsub_s(Address src);
-  void fsub_d(Address src);
-  void fsubr_s(Address src);
-  void fsubr_d(Address src);
-
-  void fmul_s(Address src);
-  void fmul_d(Address src);
-  void fmul(int i);
-  void fmula(int i);  // "alternate" fmul
-
-  void fdiv_s(Address src);
-  void fdiv_d(Address src);
-  void fdivr_s(Address src);
-  void fdivr_d(Address src);
-
-  void fsub(int i);
-  void fsuba(int i);  // "alternate" fsub
-  void fsubr(int i);
-  void fsubra(int i); // "alternate" reversed fsub
-  void fdiv(int i);
-  void fdiva(int i);  // "alternate" fdiv
-  void fdivr(int i);
-  void fdivra(int i); // "alternate" reversed fdiv
-
-  void faddp(int i = 1);
-  void fsubp(int i = 1);
-  void fsubrp(int i = 1);
-  void fmulp(int i = 1);
-  void fdivp(int i = 1);
-  void fdivrp(int i = 1);
-  void fprem();
-  void fprem1();
-
-  void fxch(int i = 1);
-  void fincstp();
-  void fdecstp();
-  void ffree(int i = 0);
-
-  void fcomp_s(Address src);
-  void fcomp_d(Address src);
-  void fcom(int i);
-  void fcomp(int i = 1);
-  void fcompp();
-
-  void fucomi(int i = 1);
-  void fucomip(int i = 1);
-
-  void ftst();
-  void fnstsw_ax();
-  void fwait();
-  void finit();
-  void fldcw(Address src);
-  void fnstcw(Address src);
-
-  void fnsave(Address dst);
-  void frstor(Address src);
-  void fldenv(Address src);
-
-  void sahf();
-
- protected:
-  void emit_sse_operand(XMMRegister reg, Address adr);
-  void emit_sse_operand(Register reg, Address adr);
-  void emit_sse_operand(XMMRegister dst, XMMRegister src);
-  void emit_sse_operand(XMMRegister dst, Register src);
-  void emit_sse_operand(Register dst, XMMRegister src);
-
-  void emit_operand(MMXRegister reg, Address adr);
-
- public:
-  // mmx operations
-  void movq( MMXRegister dst, Address src );
-  void movq( Address dst, MMXRegister src );
-  void emms();
-
-  // xmm operations
-  void addss(XMMRegister dst, Address src);      // Add Scalar Single-Precision Floating-Point Values
-  void addss(XMMRegister dst, XMMRegister src);
-  void addsd(XMMRegister dst, Address src);      // Add Scalar Double-Precision Floating-Point Values
-  void addsd(XMMRegister dst, XMMRegister src);
-
-  void subss(XMMRegister dst, Address src);      // Subtract Scalar Single-Precision Floating-Point Values
-  void subss(XMMRegister dst, XMMRegister src);
-  void subsd(XMMRegister dst, Address src);      // Subtract Scalar Double-Precision Floating-Point Values
-  void subsd(XMMRegister dst, XMMRegister src);
-
-  void mulss(XMMRegister dst, Address src);      // Multiply Scalar Single-Precision Floating-Point Values
-  void mulss(XMMRegister dst, XMMRegister src);
-  void mulsd(XMMRegister dst, Address src);      // Multiply Scalar Double-Precision Floating-Point Values
-  void mulsd(XMMRegister dst, XMMRegister src);
-
-  void divss(XMMRegister dst, Address src);      // Divide Scalar Single-Precision Floating-Point Values
-  void divss(XMMRegister dst, XMMRegister src);
-  void divsd(XMMRegister dst, Address src);      // Divide Scalar Double-Precision Floating-Point Values
-  void divsd(XMMRegister dst, XMMRegister src);
-
-  void sqrtss(XMMRegister dst, Address src);     // Compute Square Root of Scalar Single-Precision Floating-Point Value
-  void sqrtss(XMMRegister dst, XMMRegister src);
-  void sqrtsd(XMMRegister dst, Address src);     // Compute Square Root of Scalar Double-Precision Floating-Point Value
-  void sqrtsd(XMMRegister dst, XMMRegister src);
-
-  void pxor(XMMRegister dst, Address src);       // Xor Packed Byte Integer Values
-  void pxor(XMMRegister dst, XMMRegister src);   // Xor Packed Byte Integer Values
-
-  void comiss(XMMRegister dst, Address src);     // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
-  void comiss(XMMRegister dst, XMMRegister src);
-  void comisd(XMMRegister dst, Address src);     // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
-  void comisd(XMMRegister dst, XMMRegister src);
-
-  void ucomiss(XMMRegister dst, Address src);    // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
-  void ucomiss(XMMRegister dst, XMMRegister src);
-  void ucomisd(XMMRegister dst, Address src);    // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
-  void ucomisd(XMMRegister dst, XMMRegister src);
-
-  void cvtss2sd(XMMRegister dst, Address src);   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
-  void cvtss2sd(XMMRegister dst, XMMRegister src);
-  void cvtsd2ss(XMMRegister dst, Address src);   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
-  void cvtsd2ss(XMMRegister dst, XMMRegister src);
-  void cvtdq2pd(XMMRegister dst, XMMRegister src);
-  void cvtdq2ps(XMMRegister dst, XMMRegister src);
-
-  void cvtsi2ss(XMMRegister dst, Address src);   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
-  void cvtsi2ss(XMMRegister dst, Register src);
-  void cvtsi2sd(XMMRegister dst, Address src);   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
-  void cvtsi2sd(XMMRegister dst, Register src);
-
-  void cvtss2si(Register dst, Address src);      // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
-  void cvtss2si(Register dst, XMMRegister src);
-  void cvtsd2si(Register dst, Address src);      // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
-  void cvtsd2si(Register dst, XMMRegister src);
-
-  void cvttss2si(Register dst, Address src);     // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
-  void cvttss2si(Register dst, XMMRegister src);
-  void cvttsd2si(Register dst, Address src);     // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
-  void cvttsd2si(Register dst, XMMRegister src);
-
- protected: // Avoid using the next instructions directly.
-  // New cpus require use of movsd and movss to avoid partial register stall
-  // when loading from memory. But for old Opteron use movlpd instead of movsd.
-  // The selection is done in MacroAssembler::movdbl() and movflt().
-  void movss(XMMRegister dst, Address src);      // Move Scalar Single-Precision Floating-Point Values
-  void movss(XMMRegister dst, XMMRegister src);
-  void movss(Address dst, XMMRegister src);
-  void movsd(XMMRegister dst, Address src);      // Move Scalar Double-Precision Floating-Point Values
-  void movsd(XMMRegister dst, XMMRegister src);
-  void movsd(Address dst, XMMRegister src);
-  void movlpd(XMMRegister dst, Address src);
-  // New cpus require use of movaps and movapd to avoid partial register stall
-  // when moving between registers.
-  void movaps(XMMRegister dst, XMMRegister src);
-  void movapd(XMMRegister dst, XMMRegister src);
- public:
-
-  void andps(XMMRegister dst, Address src);      // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
-  void andps(XMMRegister dst, XMMRegister src);
-  void andpd(XMMRegister dst, Address src);      // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
-  void andpd(XMMRegister dst, XMMRegister src);
-
-  void andnps(XMMRegister dst, Address src);     // Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
-  void andnps(XMMRegister dst, XMMRegister src);
-  void andnpd(XMMRegister dst, Address src);     // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
-  void andnpd(XMMRegister dst, XMMRegister src);
-
-  void orps(XMMRegister dst, Address src);       // Bitwise Logical OR of Packed Single-Precision Floating-Point Values
-  void orps(XMMRegister dst, XMMRegister src);
-  void orpd(XMMRegister dst, Address src);       // Bitwise Logical OR of Packed Double-Precision Floating-Point Values
-  void orpd(XMMRegister dst, XMMRegister src);
-
-  void xorps(XMMRegister dst, Address src);      // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
-  void xorps(XMMRegister dst, XMMRegister src);
-  void xorpd(XMMRegister dst, Address src);      // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
-  void xorpd(XMMRegister dst, XMMRegister src);
-
-  void movq(XMMRegister dst, Address src);       // Move Quadword
-  void movq(XMMRegister dst, XMMRegister src);
-  void movq(Address dst, XMMRegister src);
-
-  void movd(XMMRegister dst, Address src);       // Move Doubleword
-  void movd(XMMRegister dst, Register src);
-  void movd(Register dst, XMMRegister src);
-  void movd(Address dst, XMMRegister src);
-
-  void movdqa(XMMRegister dst, Address src);     // Move Aligned Double Quadword
-  void movdqa(XMMRegister dst, XMMRegister src);
-  void movdqa(Address     dst, XMMRegister src);
-
-  void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
-  void pshufd(XMMRegister dst, Address src,     int mode);
-  void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
-  void pshuflw(XMMRegister dst, Address src,     int mode);
-
-  void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
-
-  void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
-  void punpcklbw(XMMRegister dst, Address src);
-
-  void ldmxcsr( Address src );
-  void stmxcsr( Address dst );
-};
-
-
-// MacroAssembler extends Assembler by frequently used macros.
-//
-// Instructions for which a 'better' code sequence exists depending
-// on arguments should also go in here.
-
-class MacroAssembler: public Assembler {
- friend class LIR_Assembler;
- protected:
-
-  Address as_Address(AddressLiteral adr);
-  Address as_Address(ArrayAddress adr);
-
-  // Support for VM calls
-  //
-  // This is the base routine called by the different versions of call_VM_leaf. The interpreter
-  // may customize this version by overriding it for its purposes (e.g., to save/restore
-  // additional registers when doing a VM call).
-#ifdef CC_INTERP
-  // c++ interpreter never wants to use interp_masm version of call_VM
-  #define VIRTUAL
-#else
-  #define VIRTUAL virtual
-#endif
-
-  VIRTUAL void call_VM_leaf_base(
-    address entry_point,               // the entry point
-    int     number_of_arguments        // the number of arguments to pop after the call
-  );
-
-  // This is the base routine called by the different versions of call_VM. The interpreter
-  // may customize this version by overriding it for its purposes (e.g., to save/restore
-  // additional registers when doing a VM call).
-  //
-  // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
-  // returns the register which contains the thread upon return. If a thread register has been
-  // specified, the return value will correspond to that register. If no last_java_sp is specified
-  // (noreg) than rsp will be used instead.
-  VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
-    Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
-    Register java_thread,              // the thread if computed before     ; use noreg otherwise
-    Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
-    address  entry_point,              // the entry point
-    int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
-    bool     check_exceptions          // whether to check for pending exceptions after return
-  );
-
-  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
-  // The implementation is only non-empty for the InterpreterMacroAssembler,
-  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
-  virtual void check_and_handle_popframe(Register java_thread);
-  virtual void check_and_handle_earlyret(Register java_thread);
-
-  void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
-
-  // helpers for FPU flag access
-  // tmp is a temporary register, if none is available use noreg
-  void save_rax   (Register tmp);
-  void restore_rax(Register tmp);
-
- public:
-  MacroAssembler(CodeBuffer* code) : Assembler(code) {}
-
-  // Support for NULL-checks
-  //
-  // Generates code that causes a NULL OS exception if the content of reg is NULL.
-  // If the accessed location is M[reg + offset] and the offset is known, provide the
-  // offset. No explicit code generation is needed if the offset is within a certain
-  // range (0 <= offset <= page_size).
-
-  void null_check(Register reg, int offset = -1);
-  static bool needs_explicit_null_check(intptr_t offset);
-
-  // Required platform-specific helpers for Label::patch_instructions.
-  // They _shadow_ the declarations in AbstractAssembler, which are undefined.
-  void pd_patch_instruction(address branch, address target);
-#ifndef PRODUCT
-  static void pd_print_patched_instruction(address branch);
-#endif
-
-  // The following 4 methods return the offset of the appropriate move instruction
-
-  // Support for fast byte/word loading with zero extension (depending on particular CPU)
-  int load_unsigned_byte(Register dst, Address src);
-  int load_unsigned_word(Register dst, Address src);
-
-  // Support for fast byte/word loading with sign extension (depending on particular CPU)
-  int load_signed_byte(Register dst, Address src);
-  int load_signed_word(Register dst, Address src);
-
-  // Support for sign-extension (hi:lo = extend_sign(lo))
-  void extend_sign(Register hi, Register lo);
-
-  // Support for inc/dec with optimal instruction selection depending on value
-  void increment(Register reg, int value = 1);
-  void decrement(Register reg, int value = 1);
-  void increment(Address  dst, int value = 1);
-  void decrement(Address  dst, int value = 1);
-
-  // Support optimal SSE move instructions.
-  void movflt(XMMRegister dst, XMMRegister src) {
-    if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
-    else                       { movss (dst, src); return; }
-  }
-  void movflt(XMMRegister dst, Address src) { movss(dst, src); }
-  void movflt(XMMRegister dst, AddressLiteral src);
-  void movflt(Address dst, XMMRegister src) { movss(dst, src); }
-
-  void movdbl(XMMRegister dst, XMMRegister src) {
-    if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
-    else                       { movsd (dst, src); return; }
-  }
-
-  void movdbl(XMMRegister dst, AddressLiteral src);
-
-  void movdbl(XMMRegister dst, Address src) {
-    if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
-    else                         { movlpd(dst, src); return; }
-  }
-  void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
-
-  void increment(AddressLiteral dst);
-  void increment(ArrayAddress dst);
-
-
-  // Alignment
-  void align(int modulus);
-
-  // Misc
-  void fat_nop(); // 5 byte nop
-
-  // Stack frame creation/removal
-  void enter();
-  void leave();
-
-  // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
-  // The pointer will be loaded into the thread register.
-  void get_thread(Register thread);
-
-  // Support for VM calls
-  //
-  // It is imperative that all calls into the VM are handled via the call_VM macros.
-  // They make sure that the stack linkage is setup correctly. call_VM's correspond
-  // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
-
-  void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
-  void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
-  void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
-  void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
-
-  void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
-  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
-  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
-  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
-
-  void call_VM_leaf(address entry_point, int number_of_arguments = 0);
-  void call_VM_leaf(address entry_point, Register arg_1);
-  void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
-  void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
-
-  // last Java Frame (fills frame anchor)
-  void set_last_Java_frame(Register thread, Register last_java_sp, Register last_java_fp, address last_java_pc);
-  void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
-
-  // Stores
-  void store_check(Register obj);                // store check for obj - register is destroyed afterwards
-  void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
-
-  // split store_check(Register obj) to enhance instruction interleaving
-  void store_check_part_1(Register obj);
-  void store_check_part_2(Register obj);
-
-  // C 'boolean' to Java boolean: x == 0 ? 0 : 1
-  void c2bool(Register x);
-
-  // C++ bool manipulation
-
-  void movbool(Register dst, Address src);
-  void movbool(Address dst, bool boolconst);
-  void movbool(Address dst, Register src);
-  void testbool(Register dst);
-
-  // Int division/reminder for Java
-  // (as idivl, but checks for special case as described in JVM spec.)
-  // returns idivl instruction offset for implicit exception handling
-  int corrected_idivl(Register reg);
-
-  void int3();
-
-  // Long negation for Java
-  void lneg(Register hi, Register lo);
-
-  // Long multiplication for Java
-  // (destroys contents of rax, rbx, rcx and rdx)
-  void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
-
-  // Long shifts for Java
-  // (semantics as described in JVM spec.)
-  void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
-  void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
-
-  // Long compare for Java
-  // (semantics as described in JVM spec.)
-  void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
-
-  // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
-  //
-  // CF (corresponds to C0) if x < y
-  // PF (corresponds to C2) if unordered
-  // ZF (corresponds to C3) if x = y
-  //
-  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
-  // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
-  void fcmp(Register tmp);
-  // Variant of the above which allows y to be further down the stack
-  // and which only pops x and y if specified. If pop_right is
-  // specified then pop_left must also be specified.
-  void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
-
-  // Floating-point comparison for Java
-  // Compares the top-most stack entries on the FPU stack and stores the result in dst.
-  // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
-  // (semantics as described in JVM spec.)
-  void fcmp2int(Register dst, bool unordered_is_less);
-  // Variant of the above which allows y to be further down the stack
-  // and which only pops x and y if specified. If pop_right is
-  // specified then pop_left must also be specified.
-  void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
-
-  // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
-  // tmp is a temporary register, if none is available use noreg
-  void fremr(Register tmp);
-
-
-  // same as fcmp2int, but using SSE2
-  void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
-  void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
-
-  // Inlined sin/cos generator for Java; must not use CPU instruction
-  // directly on Intel as it does not have high enough precision
-  // outside of the range [-pi/4, pi/4]. Extra argument indicate the
-  // number of FPU stack slots in use; all but the topmost will
-  // require saving if a slow case is necessary. Assumes argument is
-  // on FP TOS; result is on FP TOS.  No cpu registers are changed by
-  // this code.
-  void trigfunc(char trig, int num_fpu_regs_in_use = 1);
-
-  // branch to L if FPU flag C2 is set/not set
-  // tmp is a temporary register, if none is available use noreg
-  void jC2 (Register tmp, Label& L);
-  void jnC2(Register tmp, Label& L);
-
-  // Pop ST (ffree & fincstp combined)
-  void fpop();
-
-  // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
-  void push_fTOS();
-
-  // pops double TOS element from CPU stack and pushes on FPU stack
-  void pop_fTOS();
-
-  void empty_FPU_stack();
-
-  void push_IU_state();
-  void pop_IU_state();
-
-  void push_FPU_state();
-  void pop_FPU_state();
-
-  void push_CPU_state();
-  void pop_CPU_state();
-
-  // Sign extension
-  void sign_extend_short(Register reg);
-  void sign_extend_byte(Register reg);
-
-  // Division by power of 2, rounding towards 0
-  void division_with_shift(Register reg, int shift_value);
-
-  // Round up to a power of two
-  void round_to(Register reg, int modulus);
-
-  // Callee saved registers handling
-  void push_callee_saved_registers();
-  void pop_callee_saved_registers();
-
-  // allocation
-  void eden_allocate(
-    Register obj,                      // result: pointer to object after successful allocation
-    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
-    int      con_size_in_bytes,        // object size in bytes if   known at compile time
-    Register t1,                       // temp register
-    Label&   slow_case                 // continuation point if fast allocation fails
-  );
-  void tlab_allocate(
-    Register obj,                      // result: pointer to object after successful allocation
-    Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
-    int      con_size_in_bytes,        // object size in bytes if   known at compile time
-    Register t1,                       // temp register
-    Register t2,                       // temp register
-    Label&   slow_case                 // continuation point if fast allocation fails
-  );
-  void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
-
-  //----
-  void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
-
-  // Debugging
-  void verify_oop(Register reg, const char* s = "broken oop");             // only if +VerifyOops
-  void verify_oop_addr(Address addr, const char * s = "broken oop addr");
-
-  void verify_FPU(int stack_depth, const char* s = "illegal FPU state");   // only if +VerifyFPU
-  void stop(const char* msg);                    // prints msg, dumps registers and stops execution
-  void warn(const char* msg);                    // prints msg and continues
-  static void debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
-  void os_breakpoint();
-  void untested()                                { stop("untested"); }
-  void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, sizeof(b), "unimplemented: %s", what);  stop(b); }
-  void should_not_reach_here()                   { stop("should not reach here"); }
-  void print_CPU_state();
-
-  // Stack overflow checking
-  void bang_stack_with_offset(int offset) {
-    // stack grows down, caller passes positive offset
-    assert(offset > 0, "must bang with negative offset");
-    movl(Address(rsp, (-offset)), rax);
-  }
-
-  // Writes to stack successive pages until offset reached to check for
-  // stack overflow + shadow pages.  Also, clobbers tmp
-  void bang_stack_size(Register size, Register tmp);
-
-  // Support for serializing memory accesses between threads
-  void serialize_memory(Register thread, Register tmp);
-
-  void verify_tlab();
-
-  // Biased locking support
-  // lock_reg and obj_reg must be loaded up with the appropriate values.
-  // swap_reg must be rax, and is killed.
-  // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
-  // be killed; if not supplied, push/pop will be used internally to
-  // allocate a temporary (inefficient, avoid if possible).
-  // Optional slow case is for implementations (interpreter and C1) which branch to
-  // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
-  // Returns offset of first potentially-faulting instruction for null
-  // check info (currently consumed only by C1). If
-  // swap_reg_contains_mark is true then returns -1 as it is assumed
-  // the calling code has already passed any potential faults.
-  int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
-                           bool swap_reg_contains_mark,
-                           Label& done, Label* slow_case = NULL,
-                           BiasedLockingCounters* counters = NULL);
-  void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
-
-
-  Condition negate_condition(Condition cond);
-
-  // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
-  // operands. In general the names are modified to avoid hiding the instruction in Assembler
-  // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
-  // here in MacroAssembler. The major exception to this rule is call
-
-  // Arithmetics
-
-  void cmp8(AddressLiteral src1, int8_t imm);
-
-  // QQQ renamed to drag out the casting of address to int32_t/intptr_t
-  void cmp32(Register src1, int32_t imm);
-
-  void cmp32(AddressLiteral src1, int32_t imm);
-  // compare reg - mem, or reg - &mem
-  void cmp32(Register src1, AddressLiteral src2);
-
-  void cmp32(Register src1, Address src2);
-
-  // NOTE src2 must be the lval. This is NOT an mem-mem compare
-  void cmpptr(Address src1, AddressLiteral src2);
-
-  void cmpptr(Register src1, AddressLiteral src2);
-
-  void cmpoop(Address dst, jobject obj);
-  void cmpoop(Register dst, jobject obj);
-
-
-  void cmpxchgptr(Register reg, AddressLiteral adr);
-
-  // Helper functions for statistics gathering.
-  // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
-  void cond_inc32(Condition cond, AddressLiteral counter_addr);
-  // Unconditional atomic increment.
-  void atomic_incl(AddressLiteral counter_addr);
-
-  void lea(Register dst, AddressLiteral adr);
-  void lea(Address dst, AddressLiteral adr);
-
-  void test32(Register dst, AddressLiteral src);
-
-  // Calls
-
-  void call(Label& L, relocInfo::relocType rtype);
-  void call(Register entry);
-
-  // NOTE: this call tranfers to the effective address of entry NOT
-  // the address contained by entry. This is because this is more natural
-  // for jumps/calls.
-  void call(AddressLiteral entry);
-
-  // Jumps
-
-  // NOTE: these jumps tranfer to the effective address of dst NOT
-  // the address contained by dst. This is because this is more natural
-  // for jumps/calls.
-  void jump(AddressLiteral dst);
-  void jump_cc(Condition cc, AddressLiteral dst);
-
-  // 32bit can do a case table jump in one instruction but we no longer allow the base
-  // to be installed in the Address class. This jump will tranfers to the address
-  // contained in the location described by entry (not the address of entry)
-  void jump(ArrayAddress entry);
-
-  // Floating
-
-  void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
-  void andpd(XMMRegister dst, AddressLiteral src);
-
-  void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
-  void comiss(XMMRegister dst, AddressLiteral src);
-
-  void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
-  void comisd(XMMRegister dst, AddressLiteral src);
-
-  void fldcw(Address src) { Assembler::fldcw(src); }
-  void fldcw(AddressLiteral src);
-
-  void fld_s(int index)   { Assembler::fld_s(index); }
-  void fld_s(Address src) { Assembler::fld_s(src); }
-  void fld_s(AddressLiteral src);
-
-  void fld_d(Address src) { Assembler::fld_d(src); }
-  void fld_d(AddressLiteral src);
-
-  void fld_x(Address src) { Assembler::fld_x(src); }
-  void fld_x(AddressLiteral src);
-
-  void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
-  void ldmxcsr(AddressLiteral src);
-
-  void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
-  void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
-  void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
-  void movss(XMMRegister dst, AddressLiteral src);
-
-  void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
-  void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
-  void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
-  void movsd(XMMRegister dst, AddressLiteral src);
-
-  void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
-  void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
-  void ucomiss(XMMRegister dst, AddressLiteral src);
-
-  void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
-  void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
-  void ucomisd(XMMRegister dst, AddressLiteral src);
-
-  // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
-  void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
-  void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
-  void xorpd(XMMRegister dst, AddressLiteral src);
-
-  // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
-  void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
-  void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
-  void xorps(XMMRegister dst, AddressLiteral src);
-
-  // Data
-
-  void movoop(Register dst, jobject obj);
-  void movoop(Address dst, jobject obj);
-
-  void movptr(ArrayAddress dst, Register src);
-  // can this do an lea?
-  void movptr(Register dst, ArrayAddress src);
-
-  void movptr(Register dst, AddressLiteral src);
-
-  // to avoid hiding movl
-  void mov32(AddressLiteral dst, Register src);
-  void mov32(Register dst, AddressLiteral src);
-  // to avoid hiding movb
-  void movbyte(ArrayAddress dst, int src);
-
-  // Can push value or effective address
-  void pushptr(AddressLiteral src);
-
-#undef VIRTUAL
-
-};
-
-/**
- * class SkipIfEqual:
- *
- * Instantiating this class will result in assembly code being output that will
- * jump around any code emitted between the creation of the instance and it's
- * automatic destruction at the end of a scope block, depending on the value of
- * the flag passed to the constructor, which will be checked at run-time.
- */
-class SkipIfEqual {
- private:
-  MacroAssembler* _masm;
-  Label _label;
-
- public:
-   SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
-   ~SkipIfEqual();
-};
-
-#ifdef ASSERT
-inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
-#endif
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.inline.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/*
- * Copyright 1997-2005 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
-  unsigned char op = branch[0];
-  assert(op == 0xE8 /* call */ ||
-         op == 0xE9 /* jmp */ ||
-         op == 0xEB /* short jmp */ ||
-         (op & 0xF0) == 0x70 /* short jcc */ ||
-         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
-         "Invalid opcode at patch point");
-
-  if (op == 0xEB || (op & 0xF0) == 0x70) {
-    // short offset operators (jmp and jcc)
-    char* disp = (char*) &branch[1];
-    int imm8 = target - (address) &disp[1];
-    guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
-    *disp = imm8;
-  } else {
-    int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
-    int imm32 = target - (address) &disp[1];
-    *disp = imm32;
-  }
-}
-
-#ifndef PRODUCT
-inline void MacroAssembler::pd_print_patched_instruction(address branch) {
-  const char* s;
-  unsigned char op = branch[0];
-  if (op == 0xE8) {
-    s = "call";
-  } else if (op == 0xE9 || op == 0xEB) {
-    s = "jmp";
-  } else if ((op & 0xF0) == 0x70) {
-    s = "jcc";
-  } else if (op == 0x0F) {
-    s = "jcc";
-  } else {
-    s = "????";
-  }
-  tty->print("%s (unresolved)", s);
-}
-#endif // ndef PRODUCT
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,5393 +0,0 @@
-/*
- * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_x86_64.cpp.incl"
-
-// Implementation of AddressLiteral
-
-AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
-  _is_lval = false;
-  _target = target;
-  switch (rtype) {
-  case relocInfo::oop_type:
-    // Oops are a special case. Normally they would be their own section
-    // but in cases like icBuffer they are literals in the code stream that
-    // we don't have a section for. We use none so that we get a literal address
-    // which is always patchable.
-    break;
-  case relocInfo::external_word_type:
-    _rspec = external_word_Relocation::spec(target);
-    break;
-  case relocInfo::internal_word_type:
-    _rspec = internal_word_Relocation::spec(target);
-    break;
-  case relocInfo::opt_virtual_call_type:
-    _rspec = opt_virtual_call_Relocation::spec();
-    break;
-  case relocInfo::static_call_type:
-    _rspec = static_call_Relocation::spec();
-    break;
-  case relocInfo::runtime_call_type:
-    _rspec = runtime_call_Relocation::spec();
-    break;
-  case relocInfo::none:
-    break;
-  default:
-    ShouldNotReachHere();
-    break;
-  }
-}
-
-// Implementation of Address
-
-Address Address::make_array(ArrayAddress adr) {
-#ifdef _LP64
-  // Not implementable on 64bit machines
-  // Should have been handled higher up the call chain.
-  ShouldNotReachHere();
-  return Address();
-#else
-  AddressLiteral base = adr.base();
-  Address index = adr.index();
-  assert(index._disp == 0, "must not have disp"); // maybe it can?
-  Address array(index._base, index._index, index._scale, (intptr_t) base.target());
-  array._rspec = base._rspec;
-  return array;
-#endif // _LP64
-}
-
-// exceedingly dangerous constructor
-Address::Address(int disp, address loc, relocInfo::relocType rtype) {
-  _base  = noreg;
-  _index = noreg;
-  _scale = no_scale;
-  _disp  = disp;
-  switch (rtype) {
-    case relocInfo::external_word_type:
-      _rspec = external_word_Relocation::spec(loc);
-      break;
-    case relocInfo::internal_word_type:
-      _rspec = internal_word_Relocation::spec(loc);
-      break;
-    case relocInfo::runtime_call_type:
-      // HMM
-      _rspec = runtime_call_Relocation::spec();
-      break;
-    case relocInfo::none:
-      break;
-    default:
-      ShouldNotReachHere();
-  }
-}
-
-// Convert the raw encoding form into the form expected by the constructor for
-// Address.  An index of 4 (rsp) corresponds to having no index, so convert
-// that to noreg for the Address constructor.
-Address Address::make_raw(int base, int index, int scale, int disp) {
-  bool valid_index = index != rsp->encoding();
-  if (valid_index) {
-    Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
-    return madr;
-  } else {
-    Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
-    return madr;
-  }
-}
-
-
-// Implementation of Assembler
-int AbstractAssembler::code_fill_byte() {
-  return (u_char)'\xF4'; // hlt
-}
-
-// This should only be used by 64bit instructions that can use rip-relative
-// it cannot be used by instructions that want an immediate value.
-
-bool Assembler::reachable(AddressLiteral adr) {
-  int64_t disp;
-
-  // None will force a 64bit literal to the code stream. Likely a placeholder
-  // for something that will be patched later and we need to certain it will
-  // always be reachable.
-  if (adr.reloc() == relocInfo::none) {
-    return false;
-  }
-  if (adr.reloc() == relocInfo::internal_word_type) {
-    // This should be rip relative and easily reachable.
-    return true;
-  }
-  if (adr.reloc() != relocInfo::external_word_type &&
-      adr.reloc() != relocInfo::runtime_call_type ) {
-    return false;
-  }
-
-  // Stress the correction code
-  if (ForceUnreachable) {
-    // Must be runtimecall reloc, see if it is in the codecache
-    // Flipping stuff in the codecache to be unreachable causes issues
-    // with things like inline caches where the additional instructions
-    // are not handled.
-    if (CodeCache::find_blob(adr._target) == NULL) {
-      return false;
-    }
-  }
-  // For external_word_type/runtime_call_type if it is reachable from where we
-  // are now (possibly a temp buffer) and where we might end up
-  // anywhere in the codeCache then we are always reachable.
-  // This would have to change if we ever save/restore shared code
-  // to be more pessimistic.
-
-  disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
-  if (!is_simm32(disp)) return false;
-  disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
-  if (!is_simm32(disp)) return false;
-
-  disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
-
-  // Because rip relative is a disp + address_of_next_instruction and we
-  // don't know the value of address_of_next_instruction we apply a fudge factor
-  // to make sure we will be ok no matter the size of the instruction we get placed into.
-  // We don't have to fudge the checks above here because they are already worst case.
-
-  // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
-  // + 4 because better safe than sorry.
-  const int fudge = 12 + 4;
-  if (disp < 0) {
-    disp -= fudge;
-  } else {
-    disp += fudge;
-  }
-  return is_simm32(disp);
-}
-
-
-// make this go away eventually
-void Assembler::emit_data(jint data,
-                          relocInfo::relocType rtype,
-                          int format) {
-  if (rtype == relocInfo::none) {
-    emit_long(data);
-  } else {
-    emit_data(data, Relocation::spec_simple(rtype), format);
-  }
-}
-
-void Assembler::emit_data(jint data,
-                          RelocationHolder const& rspec,
-                          int format) {
-  assert(imm64_operand == 0, "default format must be imm64 in this file");
-  assert(imm64_operand != format, "must not be imm64");
-  assert(inst_mark() != NULL, "must be inside InstructionMark");
-  if (rspec.type() !=  relocInfo::none) {
-    #ifdef ASSERT
-      check_relocation(rspec, format);
-    #endif
-    // Do not use AbstractAssembler::relocate, which is not intended for
-    // embedded words.  Instead, relocate to the enclosing instruction.
-
-    // hack. call32 is too wide for mask so use disp32
-    if (format == call32_operand)
-      code_section()->relocate(inst_mark(), rspec, disp32_operand);
-    else
-      code_section()->relocate(inst_mark(), rspec, format);
-  }
-  emit_long(data);
-}
-
-void Assembler::emit_data64(jlong data,
-                            relocInfo::relocType rtype,
-                            int format) {
-  if (rtype == relocInfo::none) {
-    emit_long64(data);
-  } else {
-    emit_data64(data, Relocation::spec_simple(rtype), format);
-  }
-}
-
-void Assembler::emit_data64(jlong data,
-                            RelocationHolder const& rspec,
-                            int format) {
-  assert(imm64_operand == 0, "default format must be imm64 in this file");
-  assert(imm64_operand == format, "must be imm64");
-  assert(inst_mark() != NULL, "must be inside InstructionMark");
-  // Do not use AbstractAssembler::relocate, which is not intended for
-  // embedded words.  Instead, relocate to the enclosing instruction.
-  code_section()->relocate(inst_mark(), rspec, format);
-#ifdef ASSERT
-  check_relocation(rspec, format);
-#endif
-  emit_long64(data);
-}
-
-void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  assert(isByte(imm8), "not a byte");
-  assert((op1 & 0x01) == 0, "should be 8bit operation");
-  int dstenc = dst->encoding();
-  if (dstenc >= 8) {
-    dstenc -= 8;
-  }
-  emit_byte(op1);
-  emit_byte(op2 | dstenc);
-  emit_byte(imm8);
-}
-
-void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  assert((op1 & 0x01) == 1, "should be 32bit operation");
-  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
-  int dstenc = dst->encoding();
-  if (dstenc >= 8) {
-    dstenc -= 8;
-  }
-  if (is8bit(imm32)) {
-    emit_byte(op1 | 0x02); // set sign bit
-    emit_byte(op2 | dstenc);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(op1);
-    emit_byte(op2 | dstenc);
-    emit_long(imm32);
-  }
-}
-
-// immediate-to-memory forms
-void Assembler::emit_arith_operand(int op1,
-                                   Register rm, Address adr,
-                                   int imm32) {
-  assert((op1 & 0x01) == 1, "should be 32bit operation");
-  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
-  if (is8bit(imm32)) {
-    emit_byte(op1 | 0x02); // set sign bit
-    emit_operand(rm, adr, 1);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(op1);
-    emit_operand(rm, adr, 4);
-    emit_long(imm32);
-  }
-}
-
-
-void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
-  assert(isByte(op1) && isByte(op2), "wrong opcode");
-  int dstenc = dst->encoding();
-  int srcenc = src->encoding();
-  if (dstenc >= 8) {
-    dstenc -= 8;
-  }
-  if (srcenc >= 8) {
-    srcenc -= 8;
-  }
-  emit_byte(op1);
-  emit_byte(op2 | dstenc << 3 | srcenc);
-}
-
-void Assembler::emit_operand(Register reg, Register base, Register index,
-                             Address::ScaleFactor scale, int disp,
-                             RelocationHolder const& rspec,
-                             int rip_relative_correction) {
-  relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
-  int regenc = reg->encoding();
-  if (regenc >= 8) {
-    regenc -= 8;
-  }
-  if (base->is_valid()) {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      int indexenc = index->encoding();
-      if (indexenc >= 8) {
-        indexenc -= 8;
-      }
-      int baseenc = base->encoding();
-      if (baseenc >= 8) {
-        baseenc -= 8;
-      }
-      // [base + index*scale + disp]
-      if (disp == 0 && rtype == relocInfo::none  &&
-          base != rbp && base != r13) {
-        // [base + index*scale]
-        // [00 reg 100][ss index base]
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x04 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + index*scale + imm8]
-        // [01 reg 100][ss index base] imm8
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x44 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + index*scale + disp32]
-        // [10 reg 100][ss index base] disp32
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x84 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else if (base == rsp || base == r12) {
-      // [rsp + disp]
-      if (disp == 0 && rtype == relocInfo::none) {
-        // [rsp]
-        // [00 reg 100][00 100 100]
-        emit_byte(0x04 | regenc << 3);
-        emit_byte(0x24);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [rsp + imm8]
-        // [01 reg 100][00 100 100] disp8
-        emit_byte(0x44 | regenc << 3);
-        emit_byte(0x24);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [rsp + imm32]
-        // [10 reg 100][00 100 100] disp32
-        emit_byte(0x84 | regenc << 3);
-        emit_byte(0x24);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else {
-      // [base + disp]
-      assert(base != rsp && base != r12, "illegal addressing mode");
-      int baseenc = base->encoding();
-      if (baseenc >= 8) {
-        baseenc -= 8;
-      }
-      if (disp == 0 && rtype == relocInfo::none &&
-          base != rbp && base != r13) {
-        // [base]
-        // [00 reg base]
-        emit_byte(0x00 | regenc << 3 | baseenc);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + disp8]
-        // [01 reg base] disp8
-        emit_byte(0x40 | regenc << 3 | baseenc);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + disp32]
-        // [10 reg base] disp32
-        emit_byte(0x80 | regenc << 3 | baseenc);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    }
-  } else {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      int indexenc = index->encoding();
-      if (indexenc >= 8) {
-        indexenc -= 8;
-      }
-      // [index*scale + disp]
-      // [00 reg 100][ss index 101] disp32
-      assert(index != rsp, "illegal addressing mode");
-      emit_byte(0x04 | regenc << 3);
-      emit_byte(scale << 6 | indexenc << 3 | 0x05);
-      emit_data(disp, rspec, disp32_operand);
-#ifdef _LP64
-    } else if (rtype != relocInfo::none ) {
-      // [disp] RIP-RELATIVE
-      // [00 000 101] disp32
-
-      emit_byte(0x05 | regenc << 3);
-      // Note that the RIP-rel. correction applies to the generated
-      // disp field, but _not_ to the target address in the rspec.
-
-      // disp was created by converting the target address minus the pc
-      // at the start of the instruction. That needs more correction here.
-      // intptr_t disp = target - next_ip;
-      assert(inst_mark() != NULL, "must be inside InstructionMark");
-      address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
-      int64_t adjusted = (int64_t) disp -  (next_ip - inst_mark());
-      assert(is_simm32(adjusted),
-             "must be 32bit offset (RIP relative address)");
-      emit_data((int) adjusted, rspec, disp32_operand);
-
-#endif // _LP64
-    } else {
-      // [disp] ABSOLUTE
-      // [00 reg 100][00 100 101] disp32
-      emit_byte(0x04 | regenc << 3);
-      emit_byte(0x25);
-      emit_data(disp, rspec, disp32_operand);
-    }
-  }
-}
-
-void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
-                             Address::ScaleFactor scale, int disp,
-                             RelocationHolder const& rspec,
-                             int rip_relative_correction) {
-  relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
-  int regenc = reg->encoding();
-  if (regenc >= 8) {
-    regenc -= 8;
-  }
-  if (base->is_valid()) {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      int indexenc = index->encoding();
-      if (indexenc >= 8) {
-        indexenc -= 8;
-      }
-      int baseenc = base->encoding();
-      if (baseenc >= 8) {
-        baseenc -= 8;
-      }
-      // [base + index*scale + disp]
-      if (disp == 0 && rtype == relocInfo::none  &&
-          base != rbp && base != r13) {
-        // [base + index*scale]
-        // [00 reg 100][ss index base]
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x04 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + index*scale + disp8]
-        // [01 reg 100][ss index base] disp8
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x44 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + index*scale + disp32]
-        // [10 reg 100][ss index base] disp32
-        assert(index != rsp, "illegal addressing mode");
-        emit_byte(0x84 | regenc << 3);
-        emit_byte(scale << 6 | indexenc << 3 | baseenc);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else if (base == rsp || base == r12) {
-      // [rsp + disp]
-      if (disp == 0 && rtype == relocInfo::none) {
-        // [rsp]
-        // [00 reg 100][00 100 100]
-        emit_byte(0x04 | regenc << 3);
-        emit_byte(0x24);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [rsp + imm8]
-        // [01 reg 100][00 100 100] disp8
-        emit_byte(0x44 | regenc << 3);
-        emit_byte(0x24);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [rsp + imm32]
-        // [10 reg 100][00 100 100] disp32
-        emit_byte(0x84 | regenc << 3);
-        emit_byte(0x24);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    } else {
-      // [base + disp]
-      assert(base != rsp && base != r12, "illegal addressing mode");
-      int baseenc = base->encoding();
-      if (baseenc >= 8) {
-        baseenc -= 8;
-      }
-      if (disp == 0 && rtype == relocInfo::none &&
-          base != rbp && base != r13) {
-        // [base]
-        // [00 reg base]
-        emit_byte(0x00 | regenc << 3 | baseenc);
-      } else if (is8bit(disp) && rtype == relocInfo::none) {
-        // [base + imm8]
-        // [01 reg base] disp8
-        emit_byte(0x40 | regenc << 3 | baseenc);
-        emit_byte(disp & 0xFF);
-      } else {
-        // [base + imm32]
-        // [10 reg base] disp32
-        emit_byte(0x80 | regenc << 3 | baseenc);
-        emit_data(disp, rspec, disp32_operand);
-      }
-    }
-  } else {
-    if (index->is_valid()) {
-      assert(scale != Address::no_scale, "inconsistent address");
-      int indexenc = index->encoding();
-      if (indexenc >= 8) {
-        indexenc -= 8;
-      }
-      // [index*scale + disp]
-      // [00 reg 100][ss index 101] disp32
-      assert(index != rsp, "illegal addressing mode");
-      emit_byte(0x04 | regenc << 3);
-      emit_byte(scale << 6 | indexenc << 3 | 0x05);
-      emit_data(disp, rspec, disp32_operand);
-#ifdef _LP64
-    } else if ( rtype != relocInfo::none ) {
-      // [disp] RIP-RELATIVE
-      // [00 reg 101] disp32
-      emit_byte(0x05 | regenc << 3);
-      // Note that the RIP-rel. correction applies to the generated
-      // disp field, but _not_ to the target address in the rspec.
-
-      // disp was created by converting the target address minus the pc
-      // at the start of the instruction. That needs more correction here.
-      // intptr_t disp = target - next_ip;
-
-      assert(inst_mark() != NULL, "must be inside InstructionMark");
-      address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
-
-      int64_t adjusted = (int64_t) disp -  (next_ip - inst_mark());
-      assert(is_simm32(adjusted),
-             "must be 32bit offset (RIP relative address)");
-      emit_data((int) adjusted, rspec, disp32_operand);
-#endif // _LP64
-    } else {
-      // [disp] ABSOLUTE
-      // [00 reg 100][00 100 101] disp32
-      emit_byte(0x04 | regenc << 3);
-      emit_byte(0x25);
-      emit_data(disp, rspec, disp32_operand);
-    }
-  }
-}
-
-// Secret local extension to Assembler::WhichOperand:
-#define end_pc_operand (_WhichOperand_limit)
-
-address Assembler::locate_operand(address inst, WhichOperand which) {
-  // Decode the given instruction, and return the address of
-  // an embedded 32-bit operand word.
-
-  // If "which" is disp32_operand, selects the displacement portion
-  // of an effective address specifier.
-  // If "which" is imm64_operand, selects the trailing immediate constant.
-  // If "which" is call32_operand, selects the displacement of a call or jump.
-  // Caller is responsible for ensuring that there is such an operand,
-  // and that it is 32/64 bits wide.
-
-  // If "which" is end_pc_operand, find the end of the instruction.
-
-  address ip = inst;
-  bool is_64bit = false;
-
-  debug_only(bool has_disp32 = false);
-  int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
-
-  again_after_prefix:
-  switch (0xFF & *ip++) {
-
-  // These convenience macros generate groups of "case" labels for the switch.
-#define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
-#define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
-             case (x)+4: case (x)+5: case (x)+6: case (x)+7
-#define REP16(x) REP8((x)+0): \
-              case REP8((x)+8)
-
-  case CS_segment:
-  case SS_segment:
-  case DS_segment:
-  case ES_segment:
-  case FS_segment:
-  case GS_segment:
-    assert(0, "shouldn't have that prefix");
-    assert(ip == inst + 1 || ip == inst + 2, "only two prefixes allowed");
-    goto again_after_prefix;
-
-  case 0x67:
-  case REX:
-  case REX_B:
-  case REX_X:
-  case REX_XB:
-  case REX_R:
-  case REX_RB:
-  case REX_RX:
-  case REX_RXB:
-//     assert(ip == inst + 1, "only one prefix allowed");
-    goto again_after_prefix;
-
-  case REX_W:
-  case REX_WB:
-  case REX_WX:
-  case REX_WXB:
-  case REX_WR:
-  case REX_WRB:
-  case REX_WRX:
-  case REX_WRXB:
-    is_64bit = true;
-//     assert(ip == inst + 1, "only one prefix allowed");
-    goto again_after_prefix;
-
-  case 0xFF: // pushq a; decl a; incl a; call a; jmp a
-  case 0x88: // movb a, r
-  case 0x89: // movl a, r
-  case 0x8A: // movb r, a
-  case 0x8B: // movl r, a
-  case 0x8F: // popl a
-    debug_only(has_disp32 = true;)
-    break;
-
-  case 0x68: // pushq #32
-    if (which == end_pc_operand) {
-      return ip + 4;
-    }
-    assert(0, "pushq has no disp32 or imm64");
-    ShouldNotReachHere();
-
-  case 0x66: // movw ... (size prefix)
-    again_after_size_prefix2:
-    switch (0xFF & *ip++) {
-    case REX:
-    case REX_B:
-    case REX_X:
-    case REX_XB:
-    case REX_R:
-    case REX_RB:
-    case REX_RX:
-    case REX_RXB:
-    case REX_W:
-    case REX_WB:
-    case REX_WX:
-    case REX_WXB:
-    case REX_WR:
-    case REX_WRB:
-    case REX_WRX:
-    case REX_WRXB:
-      goto again_after_size_prefix2;
-    case 0x8B: // movw r, a
-    case 0x89: // movw a, r
-      break;
-    case 0xC7: // movw a, #16
-      tail_size = 2;  // the imm16
-      break;
-    case 0x0F: // several SSE/SSE2 variants
-      ip--;    // reparse the 0x0F
-      goto again_after_prefix;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case REP8(0xB8): // movl/q r, #32/#64(oop?)
-    if (which == end_pc_operand)  return ip + (is_64bit ? 8 : 4);
-    assert((which == call32_operand || which == imm64_operand) && is_64bit ||
-           which == narrow_oop_operand && !is_64bit, "");
-    return ip;
-
-  case 0x69: // imul r, a, #32
-  case 0xC7: // movl a, #32(oop?)
-    tail_size = 4;
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    break;
-
-  case 0x0F: // movx..., etc.
-    switch (0xFF & *ip++) {
-    case 0x12: // movlps
-    case 0x28: // movaps
-    case 0x2E: // ucomiss
-    case 0x2F: // comiss
-    case 0x54: // andps
-    case 0x57: // xorps
-    case 0x6E: // movd
-    case 0x7E: // movd
-    case 0xAE: // ldmxcsr   a
-      debug_only(has_disp32 = true); // has both kinds of operands!
-      break;
-    case 0xAD: // shrd r, a, %cl
-    case 0xAF: // imul r, a
-    case 0xBE: // movsbl r, a
-    case 0xBF: // movswl r, a
-    case 0xB6: // movzbl r, a
-    case 0xB7: // movzwl r, a
-    case REP16(0x40): // cmovl cc, r, a
-    case 0xB0: // cmpxchgb
-    case 0xB1: // cmpxchg
-    case 0xC1: // xaddl
-    case 0xC7: // cmpxchg8
-    case REP16(0x90): // setcc a
-      debug_only(has_disp32 = true);
-      // fall out of the switch to decode the address
-      break;
-    case 0xAC: // shrd r, a, #8
-      debug_only(has_disp32 = true);
-      tail_size = 1;  // the imm8
-      break;
-    case REP16(0x80): // jcc rdisp32
-      if (which == end_pc_operand)  return ip + 4;
-      assert(which == call32_operand, "jcc has no disp32 or imm64");
-      return ip;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case 0x81: // addl a, #32; addl r, #32
-    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
-    tail_size = 4;
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    break;
-
-  case 0x83: // addl a, #8; addl r, #8
-    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    tail_size = 1;
-    break;
-
-  case 0x9B:
-    switch (0xFF & *ip++) {
-    case 0xD9: // fnstcw a
-      debug_only(has_disp32 = true);
-      break;
-    default:
-      ShouldNotReachHere();
-    }
-    break;
-
-  case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
-  case REP4(0x10): // adc...
-  case REP4(0x20): // and...
-  case REP4(0x30): // xor...
-  case REP4(0x08): // or...
-  case REP4(0x18): // sbb...
-  case REP4(0x28): // sub...
-  case 0xF7: // mull a
-  case 0x87: // xchg r, a
-    debug_only(has_disp32 = true);
-    break;
-  case REP4(0x38): // cmp...
-  case 0x8D: // lea r, a
-  case 0x85: // test r, a
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    break;
-
-  case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
-  case 0xC6: // movb a, #8
-  case 0x80: // cmpb a, #8
-  case 0x6B: // imul r, a, #8
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    tail_size = 1; // the imm8
-    break;
-
-  case 0xE8: // call rdisp32
-  case 0xE9: // jmp  rdisp32
-    if (which == end_pc_operand)  return ip + 4;
-    assert(which == call32_operand, "call has no disp32 or imm32");
-    return ip;
-
-  case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
-  case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
-  case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
-  case 0xDD: // fld_d a; fst_d a; fstp_d a
-  case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
-  case 0xDF: // fild_d a; fistp_d a
-  case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
-  case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
-  case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
-    debug_only(has_disp32 = true);
-    break;
-
-  case 0xF3:                    // For SSE
-  case 0xF2:                    // For SSE2
-    switch (0xFF & *ip++) {
-    case REX:
-    case REX_B:
-    case REX_X:
-    case REX_XB:
-    case REX_R:
-    case REX_RB:
-    case REX_RX:
-    case REX_RXB:
-    case REX_W:
-    case REX_WB:
-    case REX_WX:
-    case REX_WXB:
-    case REX_WR:
-    case REX_WRB:
-    case REX_WRX:
-    case REX_WRXB:
-      ip++;
-    default:
-      ip++;
-    }
-    debug_only(has_disp32 = true); // has both kinds of operands!
-    break;
-
-  default:
-    ShouldNotReachHere();
-
-#undef REP8
-#undef REP16
-  }
-
-  assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
-  assert(which != imm64_operand, "instruction is not a movq reg, imm64");
-  assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
-
-  // parse the output of emit_operand
-  int op2 = 0xFF & *ip++;
-  int base = op2 & 0x07;
-  int op3 = -1;
-  const int b100 = 4;
-  const int b101 = 5;
-  if (base == b100 && (op2 >> 6) != 3) {
-    op3 = 0xFF & *ip++;
-    base = op3 & 0x07;   // refetch the base
-  }
-  // now ip points at the disp (if any)
-
-  switch (op2 >> 6) {
-  case 0:
-    // [00 reg  100][ss index base]
-    // [00 reg  100][00   100  esp]
-    // [00 reg base]
-    // [00 reg  100][ss index  101][disp32]
-    // [00 reg  101]               [disp32]
-
-    if (base == b101) {
-      if (which == disp32_operand)
-        return ip;              // caller wants the disp32
-      ip += 4;                  // skip the disp32
-    }
-    break;
-
-  case 1:
-    // [01 reg  100][ss index base][disp8]
-    // [01 reg  100][00   100  esp][disp8]
-    // [01 reg base]               [disp8]
-    ip += 1;                    // skip the disp8
-    break;
-
-  case 2:
-    // [10 reg  100][ss index base][disp32]
-    // [10 reg  100][00   100  esp][disp32]
-    // [10 reg base]               [disp32]
-    if (which == disp32_operand)
-      return ip;                // caller wants the disp32
-    ip += 4;                    // skip the disp32
-    break;
-
-  case 3:
-    // [11 reg base]  (not a memory addressing mode)
-    break;
-  }
-
-  if (which == end_pc_operand) {
-    return ip + tail_size;
-  }
-
-  assert(0, "fix locate_operand");
-  return ip;
-}
-
-address Assembler::locate_next_instruction(address inst) {
-  // Secretly share code with locate_operand:
-  return locate_operand(inst, end_pc_operand);
-}
-
-#ifdef ASSERT
-void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
-  address inst = inst_mark();
-  assert(inst != NULL && inst < pc(),
-         "must point to beginning of instruction");
-  address opnd;
-
-  Relocation* r = rspec.reloc();
-  if (r->type() == relocInfo::none) {
-    return;
-  } else if (r->is_call() || format == call32_operand) {
-    opnd = locate_operand(inst, call32_operand);
-  } else if (r->is_data()) {
-    assert(format == imm64_operand || format == disp32_operand ||
-           format == narrow_oop_operand, "format ok");
-    opnd = locate_operand(inst, (WhichOperand) format);
-  } else {
-    assert(format == 0, "cannot specify a format");
-    return;
-  }
-  assert(opnd == pc(), "must put operand where relocs can find it");
-}
-#endif
-
-int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
-  if (reg_enc >= 8) {
-    prefix(REX_B);
-    reg_enc -= 8;
-  } else if (byteinst && reg_enc >= 4) {
-    prefix(REX);
-  }
-  return reg_enc;
-}
-
-int Assembler::prefixq_and_encode(int reg_enc) {
-  if (reg_enc < 8) {
-    prefix(REX_W);
-  } else {
-    prefix(REX_WB);
-    reg_enc -= 8;
-  }
-  return reg_enc;
-}
-
-int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
-  if (dst_enc < 8) {
-    if (src_enc >= 8) {
-      prefix(REX_B);
-      src_enc -= 8;
-    } else if (byteinst && src_enc >= 4) {
-      prefix(REX);
-    }
-  } else {
-    if (src_enc < 8) {
-      prefix(REX_R);
-    } else {
-      prefix(REX_RB);
-      src_enc -= 8;
-    }
-    dst_enc -= 8;
-  }
-  return dst_enc << 3 | src_enc;
-}
-
-int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
-  if (dst_enc < 8) {
-    if (src_enc < 8) {
-      prefix(REX_W);
-    } else {
-      prefix(REX_WB);
-      src_enc -= 8;
-    }
-  } else {
-    if (src_enc < 8) {
-      prefix(REX_WR);
-    } else {
-      prefix(REX_WRB);
-      src_enc -= 8;
-    }
-    dst_enc -= 8;
-  }
-  return dst_enc << 3 | src_enc;
-}
-
-void Assembler::prefix(Register reg) {
-  if (reg->encoding() >= 8) {
-    prefix(REX_B);
-  }
-}
-
-void Assembler::prefix(Address adr) {
-  if (adr.base_needs_rex()) {
-    if (adr.index_needs_rex()) {
-      prefix(REX_XB);
-    } else {
-      prefix(REX_B);
-    }
-  } else {
-    if (adr.index_needs_rex()) {
-      prefix(REX_X);
-    }
-  }
-}
-
-void Assembler::prefixq(Address adr) {
-  if (adr.base_needs_rex()) {
-    if (adr.index_needs_rex()) {
-      prefix(REX_WXB);
-    } else {
-      prefix(REX_WB);
-    }
-  } else {
-    if (adr.index_needs_rex()) {
-      prefix(REX_WX);
-    } else {
-      prefix(REX_W);
-    }
-  }
-}
-
-
-void Assembler::prefix(Address adr, Register reg, bool byteinst) {
-  if (reg->encoding() < 8) {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_XB);
-      } else {
-        prefix(REX_B);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_X);
-      } else if (reg->encoding() >= 4 ) {
-        prefix(REX);
-      }
-    }
-  } else {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_RXB);
-      } else {
-        prefix(REX_RB);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_RX);
-      } else {
-        prefix(REX_R);
-      }
-    }
-  }
-}
-
-void Assembler::prefixq(Address adr, Register src) {
-  if (src->encoding() < 8) {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_WXB);
-      } else {
-        prefix(REX_WB);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_WX);
-      } else {
-        prefix(REX_W);
-      }
-    }
-  } else {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_WRXB);
-      } else {
-        prefix(REX_WRB);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_WRX);
-      } else {
-        prefix(REX_WR);
-      }
-    }
-  }
-}
-
-void Assembler::prefix(Address adr, XMMRegister reg) {
-  if (reg->encoding() < 8) {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_XB);
-      } else {
-        prefix(REX_B);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_X);
-      }
-    }
-  } else {
-    if (adr.base_needs_rex()) {
-      if (adr.index_needs_rex()) {
-        prefix(REX_RXB);
-      } else {
-        prefix(REX_RB);
-      }
-    } else {
-      if (adr.index_needs_rex()) {
-        prefix(REX_RX);
-      } else {
-        prefix(REX_R);
-      }
-    }
-  }
-}
-
-void Assembler::emit_operand(Register reg, Address adr,
-                             int rip_relative_correction) {
-  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
-               adr._rspec,
-               rip_relative_correction);
-}
-
-void Assembler::emit_operand(XMMRegister reg, Address adr,
-                             int rip_relative_correction) {
-  emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
-               adr._rspec,
-               rip_relative_correction);
-}
-
-void Assembler::emit_farith(int b1, int b2, int i) {
-  assert(isByte(b1) && isByte(b2), "wrong opcode");
-  assert(0 <= i &&  i < 8, "illegal stack offset");
-  emit_byte(b1);
-  emit_byte(b2 + i);
-}
-
-// pushad is invalid, use this instead.
-// NOTE: Kills flags!!
-void Assembler::pushaq() {
-  // we have to store original rsp.  ABI says that 128 bytes
-  // below rsp are local scratch.
-  movq(Address(rsp, -5 * wordSize), rsp);
-
-  subq(rsp, 16 * wordSize);
-
-  movq(Address(rsp, 15 * wordSize), rax);
-  movq(Address(rsp, 14 * wordSize), rcx);
-  movq(Address(rsp, 13 * wordSize), rdx);
-  movq(Address(rsp, 12 * wordSize), rbx);
-  // skip rsp
-  movq(Address(rsp, 10 * wordSize), rbp);
-  movq(Address(rsp, 9 * wordSize), rsi);
-  movq(Address(rsp, 8 * wordSize), rdi);
-  movq(Address(rsp, 7 * wordSize), r8);
-  movq(Address(rsp, 6 * wordSize), r9);
-  movq(Address(rsp, 5 * wordSize), r10);
-  movq(Address(rsp, 4 * wordSize), r11);
-  movq(Address(rsp, 3 * wordSize), r12);
-  movq(Address(rsp, 2 * wordSize), r13);
-  movq(Address(rsp, wordSize), r14);
-  movq(Address(rsp, 0), r15);
-}
-
-// popad is invalid, use this instead
-// NOTE: Kills flags!!
-void Assembler::popaq() {
-  movq(r15, Address(rsp, 0));
-  movq(r14, Address(rsp, wordSize));
-  movq(r13, Address(rsp, 2 * wordSize));
-  movq(r12, Address(rsp, 3 * wordSize));
-  movq(r11, Address(rsp, 4 * wordSize));
-  movq(r10, Address(rsp, 5 * wordSize));
-  movq(r9,  Address(rsp, 6 * wordSize));
-  movq(r8,  Address(rsp, 7 * wordSize));
-  movq(rdi, Address(rsp, 8 * wordSize));
-  movq(rsi, Address(rsp, 9 * wordSize));
-  movq(rbp, Address(rsp, 10 * wordSize));
-  // skip rsp
-  movq(rbx, Address(rsp, 12 * wordSize));
-  movq(rdx, Address(rsp, 13 * wordSize));
-  movq(rcx, Address(rsp, 14 * wordSize));
-  movq(rax, Address(rsp, 15 * wordSize));
-
-  addq(rsp, 16 * wordSize);
-}
-
-void Assembler::pushfq() {
-  emit_byte(0x9C);
-}
-
-void Assembler::popfq() {
-  emit_byte(0x9D);
-}
-
-void Assembler::pushq(int imm32) {
-  emit_byte(0x68);
-  emit_long(imm32);
-}
-
-void Assembler::pushq(Register src) {
-  int encode = prefix_and_encode(src->encoding());
-
-  emit_byte(0x50 | encode);
-}
-
-void Assembler::pushq(Address src) {
-  InstructionMark im(this);
-  prefix(src);
-  emit_byte(0xFF);
-  emit_operand(rsi, src);
-}
-
-void Assembler::popq(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0x58 | encode);
-}
-
-void Assembler::popq(Address dst) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0x8F);
-  emit_operand(rax, dst);
-}
-
-void Assembler::prefix(Prefix p) {
-  a_byte(p);
-}
-
-void Assembler::movb(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst, true);
-  emit_byte(0x8A);
-  emit_operand(dst, src);
-}
-
-void Assembler::movb(Address dst, int imm8) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0xC6);
-  emit_operand(rax, dst, 1);
-  emit_byte(imm8);
-}
-
-void Assembler::movb(Address dst, Register src) {
-  InstructionMark im(this);
-  prefix(dst, src, true);
-  emit_byte(0x88);
-  emit_operand(src, dst);
-}
-
-void Assembler::movw(Address dst, int imm16) {
-  InstructionMark im(this);
-  emit_byte(0x66); // switch to 16-bit mode
-  prefix(dst);
-  emit_byte(0xC7);
-  emit_operand(rax, dst, 2);
-  emit_word(imm16);
-}
-
-void Assembler::movw(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(src, dst);
-  emit_byte(0x8B);
-  emit_operand(dst, src);
-}
-
-void Assembler::movw(Address dst, Register src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(dst, src);
-  emit_byte(0x89);
-  emit_operand(src, dst);
-}
-
-// Uses zero extension.
-void Assembler::movl(Register dst, int imm32) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xB8 | encode);
-  emit_long(imm32);
-}
-
-void Assembler::movl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x8B);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x8B);
-  emit_operand(dst, src);
-}
-
-void Assembler::movl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0xC7);
-  emit_operand(rax, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::movl(Address dst, Register src) {
-  InstructionMark im(this);
-  prefix(dst, src);
-  emit_byte(0x89);
-  emit_operand(src, dst);
-}
-
-void Assembler::mov64(Register dst, intptr_t imm64) {
-  InstructionMark im(this);
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xB8 | encode);
-  emit_long64(imm64);
-}
-
-void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xB8 | encode);
-  emit_data64(imm64, rspec);
-}
-
-void Assembler::movq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x8B);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x8B);
-  emit_operand(dst, src);
-}
-
-void Assembler::mov64(Address dst, intptr_t imm32) {
-  assert(is_simm32(imm32), "lost bits");
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_byte(0xC7);
-  emit_operand(rax, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::movq(Address dst, Register src) {
-  InstructionMark im(this);
-  prefixq(dst, src);
-  emit_byte(0x89);
-  emit_operand(src, dst);
-}
-
-void Assembler::movsbl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0xBE);
-  emit_operand(dst, src);
-}
-
-void Assembler::movsbl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
-  emit_byte(0x0F);
-  emit_byte(0xBE);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movswl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0xBF);
-  emit_operand(dst, src);
-}
-
-void Assembler::movswl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xBF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movslq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x63);
-  emit_operand(dst, src);
-}
-
-void Assembler::movslq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x63);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movzbl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0xB6);
-  emit_operand(dst, src);
-}
-
-void Assembler::movzbl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
-  emit_byte(0x0F);
-  emit_byte(0xB6);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movzwl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0xB7);
-  emit_operand(dst, src);
-}
-
-void Assembler::movzwl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xB7);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x10);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movss(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x10);
-  emit_operand(dst, src);
-}
-
-void Assembler::movss(Address dst, XMMRegister src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0x11);
-  emit_operand(src, dst);
-}
-
-void Assembler::movsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x10);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x10);
-  emit_operand(dst, src);
-}
-
-void Assembler::movsd(Address dst, XMMRegister src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0x11);
-  emit_operand(src, dst);
-}
-
-// New cpus require to use movsd and movss to avoid partial register stall
-// when loading from memory. But for old Opteron use movlpd instead of movsd.
-// The selection is done in MacroAssembler::movdbl() and movflt().
-void Assembler::movlpd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x12);
-  emit_operand(dst, src);
-}
-
-void Assembler::movapd(XMMRegister dst, XMMRegister src) {
-  int dstenc = dst->encoding();
-  int srcenc = src->encoding();
-  emit_byte(0x66);
-  if (dstenc < 8) {
-    if (srcenc >= 8) {
-      prefix(REX_B);
-      srcenc -= 8;
-    }
-  } else {
-    if (srcenc < 8) {
-      prefix(REX_R);
-    } else {
-      prefix(REX_RB);
-      srcenc -= 8;
-    }
-    dstenc -= 8;
-  }
-  emit_byte(0x0F);
-  emit_byte(0x28);
-  emit_byte(0xC0 | dstenc << 3 | srcenc);
-}
-
-void Assembler::movaps(XMMRegister dst, XMMRegister src) {
-  int dstenc = dst->encoding();
-  int srcenc = src->encoding();
-  if (dstenc < 8) {
-    if (srcenc >= 8) {
-      prefix(REX_B);
-      srcenc -= 8;
-    }
-  } else {
-    if (srcenc < 8) {
-      prefix(REX_R);
-    } else {
-      prefix(REX_RB);
-      srcenc -= 8;
-    }
-    dstenc -= 8;
-  }
-  emit_byte(0x0F);
-  emit_byte(0x28);
-  emit_byte(0xC0 | dstenc << 3 | srcenc);
-}
-
-void Assembler::movdl(XMMRegister dst, Register src) {
-  emit_byte(0x66);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x6E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdl(Register dst, XMMRegister src) {
-  emit_byte(0x66);
-  // swap src/dst to get correct prefix
-  int encode = prefix_and_encode(src->encoding(), dst->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x7E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdq(XMMRegister dst, Register src) {
-  emit_byte(0x66);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x6E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdq(Register dst, XMMRegister src) {
-  emit_byte(0x66);
-  // swap src/dst to get correct prefix
-  int encode = prefixq_and_encode(src->encoding(), dst->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x7E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::pxor(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0xEF);
-  emit_operand(dst, src);
-}
-
-void Assembler::pxor(XMMRegister dst, XMMRegister src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xEF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdqa(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x6F);
-  emit_operand(dst, src);
-}
-
-void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
-  emit_byte(0x66);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x6F);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdqa(Address dst, XMMRegister src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0x7F);
-  emit_operand(src, dst);
-}
-
-void Assembler::movq(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x7E);
-  emit_operand(dst, src);
-}
-
-void Assembler::movq(Address dst, XMMRegister src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0xD6);
-  emit_operand(src, dst);
-}
-
-void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
-  assert(isByte(mode), "invalid value");
-  emit_byte(0x66);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_byte(0xC0 | encode);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
-  assert(isByte(mode), "invalid value");
-  InstructionMark im(this);
-  emit_byte(0x66);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
-  assert(isByte(mode), "invalid value");
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_byte(0xC0 | encode);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
-  assert(isByte(mode), "invalid value");
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  emit_byte(0x0F);
-  emit_byte(0x70);
-  emit_operand(dst, src);
-  emit_byte(mode & 0xFF);
-}
-
-void Assembler::cmovl(Condition cc, Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cmovl(Condition cc, Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_operand(dst, src);
-}
-
-void Assembler::cmovq(Condition cc, Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cmovq(Condition cc, Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x40 | cc);
-  emit_operand(dst, src);
-}
-
-void Assembler::prefetch_prefix(Address src) {
-  prefix(src);
-  emit_byte(0x0F);
-}
-
-void Assembler::prefetcht0(Address src) {
-  InstructionMark im(this);
-  prefetch_prefix(src);
-  emit_byte(0x18);
-  emit_operand(rcx, src); // 1, src
-}
-
-void Assembler::prefetcht1(Address src) {
-  InstructionMark im(this);
-  prefetch_prefix(src);
-  emit_byte(0x18);
-  emit_operand(rdx, src); // 2, src
-}
-
-void Assembler::prefetcht2(Address src) {
-  InstructionMark im(this);
-  prefetch_prefix(src);
-  emit_byte(0x18);
-  emit_operand(rbx, src); // 3, src
-}
-
-void Assembler::prefetchnta(Address src) {
-  InstructionMark im(this);
-  prefetch_prefix(src);
-  emit_byte(0x18);
-  emit_operand(rax, src); // 0, src
-}
-
-void Assembler::prefetchw(Address src) {
-  InstructionMark im(this);
-  prefetch_prefix(src);
-  emit_byte(0x0D);
-  emit_operand(rcx, src); // 1, src
-}
-
-void Assembler::adcl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xD0, dst, imm32);
-}
-
-void Assembler::adcl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x13);
-  emit_operand(dst, src);
-}
-
-void Assembler::adcl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x13, 0xC0, dst, src);
-}
-
-void Assembler::adcq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xD0, dst, imm32);
-}
-
-void Assembler::adcq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x13);
-  emit_operand(dst, src);
-}
-
-void Assembler::adcq(Register dst, Register src) {
-  (int) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x13, 0xC0, dst, src);
-}
-
-void Assembler::addl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_arith_operand(0x81, rax, dst,imm32);
-}
-
-void Assembler::addl(Address dst, Register src) {
-  InstructionMark im(this);
-  prefix(dst, src);
-  emit_byte(0x01);
-  emit_operand(src, dst);
-}
-
-void Assembler::addl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xC0, dst, imm32);
-}
-
-void Assembler::addl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x03);
-  emit_operand(dst, src);
-}
-
-void Assembler::addl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x03, 0xC0, dst, src);
-}
-
-void Assembler::addq(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_arith_operand(0x81, rax, dst,imm32);
-}
-
-void Assembler::addq(Address dst, Register src) {
-  InstructionMark im(this);
-  prefixq(dst, src);
-  emit_byte(0x01);
-  emit_operand(src, dst);
-}
-
-void Assembler::addq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xC0, dst, imm32);
-}
-
-void Assembler::addq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x03);
-  emit_operand(dst, src);
-}
-
-void Assembler::addq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x03, 0xC0, dst, src);
-}
-
-void Assembler::andl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-void Assembler::andl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x23);
-  emit_operand(dst, src);
-}
-
-void Assembler::andl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x23, 0xC0, dst, src);
-}
-
-void Assembler::andq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-void Assembler::andq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x23);
-  emit_operand(dst, src);
-}
-
-void Assembler::andq(Register dst, Register src) {
-  (int) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x23, 0xC0, dst, src);
-}
-
-void Assembler::cmpb(Address dst, int imm8) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0x80);
-  emit_operand(rdi, dst, 1);
-  emit_byte(imm8);
-}
-
-void Assembler::cmpl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0x81);
-  emit_operand(rdi, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::cmpl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-void Assembler::cmpl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x3B, 0xC0, dst, src);
-}
-
-void Assembler::cmpl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x3B);
-  emit_operand(dst, src);
-}
-
-void Assembler::cmpq(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_byte(0x81);
-  emit_operand(rdi, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::cmpq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-void Assembler::cmpq(Address dst, Register src) {
-  prefixq(dst, src);
-  emit_byte(0x3B);
-  emit_operand(src, dst);
-}
-
-void Assembler::cmpq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x3B, 0xC0, dst, src);
-}
-
-void Assembler::cmpq(Register dst, Address  src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x3B);
-  emit_operand(dst, src);
-}
-
-void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0x66);
-  ucomiss(dst, src);
-}
-
-void Assembler::decl(Register dst) {
-  // Don't use it directly. Use MacroAssembler::decrementl() instead.
-  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xC8 | encode);
-}
-
-void Assembler::decl(Address dst) {
-  // Don't use it directly. Use MacroAssembler::decrementl() instead.
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0xFF);
-  emit_operand(rcx, dst);
-}
-
-void Assembler::decq(Register dst) {
-  // Don't use it directly. Use MacroAssembler::decrementq() instead.
-  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xC8 | encode);
-}
-
-void Assembler::decq(Address dst) {
-  // Don't use it directly. Use MacroAssembler::decrementq() instead.
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_byte(0xFF);
-  emit_operand(rcx, dst);
-}
-
-void Assembler::idivl(Register src) {
-  int encode = prefix_and_encode(src->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xF8 | encode);
-}
-
-void Assembler::idivq(Register src) {
-  int encode = prefixq_and_encode(src->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xF8 | encode);
-}
-
-void Assembler::cdql() {
-  emit_byte(0x99);
-}
-
-void Assembler::cdqq() {
-  prefix(REX_W);
-  emit_byte(0x99);
-}
-
-void Assembler::imull(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xAF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::imull(Register dst, Register src, int value) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  if (is8bit(value)) {
-    emit_byte(0x6B);
-    emit_byte(0xC0 | encode);
-    emit_byte(value);
-  } else {
-    emit_byte(0x69);
-    emit_byte(0xC0 | encode);
-    emit_long(value);
-  }
-}
-
-void Assembler::imulq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xAF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::imulq(Register dst, Register src, int value) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  if (is8bit(value)) {
-    emit_byte(0x6B);
-    emit_byte(0xC0 | encode);
-    emit_byte(value);
-  } else {
-    emit_byte(0x69);
-    emit_byte(0xC0 | encode);
-    emit_long(value);
-  }
-}
-
-void Assembler::incl(Register dst) {
-  // Don't use it directly. Use MacroAssembler::incrementl() instead.
-  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::incl(Address dst) {
-  // Don't use it directly. Use MacroAssembler::incrementl() instead.
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0xFF);
-  emit_operand(rax, dst);
-}
-
-void Assembler::incq(Register dst) {
-  // Don't use it directly. Use MacroAssembler::incrementq() instead.
-  // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::incq(Address dst) {
-  // Don't use it directly. Use MacroAssembler::incrementq() instead.
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_byte(0xFF);
-  emit_operand(rax, dst);
-}
-
-void Assembler::leal(Register dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x67); // addr32
-  prefix(src, dst);
-  emit_byte(0x8D);
-  emit_operand(dst, src);
-}
-
-void Assembler::leaq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x8D);
-  emit_operand(dst, src);
-}
-
-void Assembler::mull(Address src) {
-  InstructionMark im(this);
-  // was missing
-  prefix(src);
-  emit_byte(0xF7);
-  emit_operand(rsp, src);
-}
-
-void Assembler::mull(Register src) {
-  // was missing
-  int encode = prefix_and_encode(src->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xE0 | encode);
-}
-
-void Assembler::negl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xD8 | encode);
-}
-
-void Assembler::negq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xD8 | encode);
-}
-
-void Assembler::notl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xD0 | encode);
-}
-
-void Assembler::notq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xF7);
-  emit_byte(0xD0 | encode);
-}
-
-void Assembler::orl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0x81);
-  emit_operand(rcx, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::orl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-void Assembler::orl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0B);
-  emit_operand(dst, src);
-}
-
-void Assembler::orl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x0B, 0xC0, dst, src);
-}
-
-void Assembler::orq(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_byte(0x81);
-  emit_operand(rcx, dst, 4);
-  emit_long(imm32);
-}
-
-void Assembler::orq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-void Assembler::orq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x0B);
-  emit_operand(dst, src);
-}
-
-void Assembler::orq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x0B, 0xC0, dst, src);
-}
-
-void Assembler::rcll(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xD0 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xD0 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::rclq(Register dst, int imm8) {
-  assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xD0 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xD0 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::sarl(Register dst, int imm8) {
-  int encode = prefix_and_encode(dst->encoding());
-  assert(isShiftCount(imm8), "illegal shift count");
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xF8 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xF8 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::sarl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xF8 | encode);
-}
-
-void Assembler::sarq(Register dst, int imm8) {
-  assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xF8 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xF8 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::sarq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xF8 | encode);
-}
-
-void Assembler::sbbl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_arith_operand(0x81, rbx, dst, imm32);
-}
-
-void Assembler::sbbl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-void Assembler::sbbl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x1B);
-  emit_operand(dst, src);
-}
-
-void Assembler::sbbl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x1B, 0xC0, dst, src);
-}
-
-void Assembler::sbbq(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefixq(dst);
-  emit_arith_operand(0x81, rbx, dst, imm32);
-}
-
-void Assembler::sbbq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-void Assembler::sbbq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x1B);
-  emit_operand(dst, src);
-}
-
-void Assembler::sbbq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x1B, 0xC0, dst, src);
-}
-
-void Assembler::shll(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
-  if (imm8 == 1 ) {
-    emit_byte(0xD1);
-    emit_byte(0xE0 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xE0 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::shll(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xE0 | encode);
-}
-
-void Assembler::shlq(Register dst, int imm8) {
-  assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
-  if (imm8 == 1) {
-    emit_byte(0xD1);
-    emit_byte(0xE0 | encode);
-  } else {
-    emit_byte(0xC1);
-    emit_byte(0xE0 | encode);
-    emit_byte(imm8);
-  }
-}
-
-void Assembler::shlq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xE0 | encode);
-}
-
-void Assembler::shrl(Register dst, int imm8) {
-  assert(isShiftCount(imm8), "illegal shift count");
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xC1);
-  emit_byte(0xE8 | encode);
-  emit_byte(imm8);
-}
-
-void Assembler::shrl(Register dst) {
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xE8 | encode);
-}
-
-void Assembler::shrq(Register dst, int imm8) {
-  assert(isShiftCount(imm8 >> 1), "illegal shift count");
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xC1);
-  emit_byte(0xE8 | encode);
-  emit_byte(imm8);
-}
-
-void Assembler::shrq(Register dst) {
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xD3);
-  emit_byte(0xE8 | encode);
-}
-
-void Assembler::subl(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefix(dst);
-  if (is8bit(imm32)) {
-    emit_byte(0x83);
-    emit_operand(rbp, dst, 1);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(0x81);
-    emit_operand(rbp, dst, 4);
-    emit_long(imm32);
-  }
-}
-
-void Assembler::subl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-void Assembler::subl(Address dst, Register src) {
-  InstructionMark im(this);
-  prefix(dst, src);
-  emit_byte(0x29);
-  emit_operand(src, dst);
-}
-
-void Assembler::subl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x2B);
-  emit_operand(dst, src);
-}
-
-void Assembler::subl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x2B, 0xC0, dst, src);
-}
-
-void Assembler::subq(Address dst, int imm32) {
-  InstructionMark im(this);
-  prefixq(dst);
-  if (is8bit(imm32)) {
-    emit_byte(0x83);
-    emit_operand(rbp, dst, 1);
-    emit_byte(imm32 & 0xFF);
-  } else {
-    emit_byte(0x81);
-    emit_operand(rbp, dst, 4);
-    emit_long(imm32);
-  }
-}
-
-void Assembler::subq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-void Assembler::subq(Address dst, Register src) {
-  InstructionMark im(this);
-  prefixq(dst, src);
-  emit_byte(0x29);
-  emit_operand(src, dst);
-}
-
-void Assembler::subq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x2B);
-  emit_operand(dst, src);
-}
-
-void Assembler::subq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x2B, 0xC0, dst, src);
-}
-
-void Assembler::testb(Register dst, int imm8) {
-  (void) prefix_and_encode(dst->encoding(), true);
-  emit_arith_b(0xF6, 0xC0, dst, imm8);
-}
-
-void Assembler::testl(Register dst, int imm32) {
-  // not using emit_arith because test
-  // doesn't support sign-extension of
-  // 8bit operands
-  int encode = dst->encoding();
-  if (encode == 0) {
-    emit_byte(0xA9);
-  } else {
-    encode = prefix_and_encode(encode);
-    emit_byte(0xF7);
-    emit_byte(0xC0 | encode);
-  }
-  emit_long(imm32);
-}
-
-void Assembler::testl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::testq(Register dst, int imm32) {
-  // not using emit_arith because test
-  // doesn't support sign-extension of
-  // 8bit operands
-  int encode = dst->encoding();
-  if (encode == 0) {
-    prefix(REX_W);
-    emit_byte(0xA9);
-  } else {
-    encode = prefixq_and_encode(encode);
-    emit_byte(0xF7);
-    emit_byte(0xC0 | encode);
-  }
-  emit_long(imm32);
-}
-
-void Assembler::testq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::xaddl(Address dst, Register src) {
-  InstructionMark im(this);
-  prefix(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0xC1);
-  emit_operand(src, dst);
-}
-
-void Assembler::xaddq(Address dst, Register src) {
-  InstructionMark im(this);
-  prefixq(dst, src);
-  emit_byte(0x0F);
-  emit_byte(0xC1);
-  emit_operand(src, dst);
-}
-
-void Assembler::xorl(Register dst, int imm32) {
-  prefix(dst);
-  emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-void Assembler::xorl(Register dst, Register src) {
-  (void) prefix_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x33, 0xC0, dst, src);
-}
-
-void Assembler::xorl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x33);
-  emit_operand(dst, src);
-}
-
-void Assembler::xorq(Register dst, int imm32) {
-  (void) prefixq_and_encode(dst->encoding());
-  emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-void Assembler::xorq(Register dst, Register src) {
-  (void) prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_arith(0x33, 0xC0, dst, src);
-}
-
-void Assembler::xorq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x33);
-  emit_operand(dst, src);
-}
-
-void Assembler::bswapl(Register reg) {
-  int encode = prefix_and_encode(reg->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xC8 | encode);
-}
-
-void Assembler::bswapq(Register reg) {
-  int encode = prefixq_and_encode(reg->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xC8 | encode);
-}
-
-void Assembler::lock() {
-  emit_byte(0xF0);
-}
-
-void Assembler::xchgl(Register dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x87);
-  emit_operand(dst, src);
-}
-
-void Assembler::xchgl(Register dst, Register src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x87);
-  emit_byte(0xc0 | encode);
-}
-
-void Assembler::xchgq(Register dst, Address src) {
-  InstructionMark im(this);
-  prefixq(src, dst);
-  emit_byte(0x87);
-  emit_operand(dst, src);
-}
-
-void Assembler::xchgq(Register dst, Register src) {
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x87);
-  emit_byte(0xc0 | encode);
-}
-
-void Assembler::cmpxchgl(Register reg, Address adr) {
-  InstructionMark im(this);
-  prefix(adr, reg);
-  emit_byte(0x0F);
-  emit_byte(0xB1);
-  emit_operand(reg, adr);
-}
-
-void Assembler::cmpxchgq(Register reg, Address adr) {
-  InstructionMark im(this);
-  prefixq(adr, reg);
-  emit_byte(0x0F);
-  emit_byte(0xB1);
-  emit_operand(reg, adr);
-}
-
-void Assembler::hlt() {
-  emit_byte(0xF4);
-}
-
-
-void Assembler::addr_nop_4() {
-  // 4 bytes: NOP DWORD PTR [EAX+0]
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
-  emit_byte(0);    // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_5() {
-  // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
-  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
-  emit_byte(0);    // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_7() {
-  // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
-  emit_long(0);    // 32-bits offset (4 bytes)
-}
-
-void Assembler::addr_nop_8() {
-  // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
-  emit_byte(0x0F);
-  emit_byte(0x1F);
-  emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
-  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
-  emit_long(0);    // 32-bits offset (4 bytes)
-}
-
-void Assembler::nop(int i) {
-  assert(i > 0, " ");
-  if (UseAddressNop && VM_Version::is_intel()) {
-    //
-    // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
-    //  1: 0x90
-    //  2: 0x66 0x90
-    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
-    //  4: 0x0F 0x1F 0x40 0x00
-    //  5: 0x0F 0x1F 0x44 0x00 0x00
-    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
-    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
-    // The rest coding is Intel specific - don't use consecutive address nops
-
-    // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-    // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-
-    while(i >= 15) {
-      // For Intel don't generate consecutive addess nops (mix with regular nops)
-      i -= 15;
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      addr_nop_8();
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x66);   // size prefix
-      emit_byte(0x90);   // nop
-    }
-    switch (i) {
-      case 14:
-        emit_byte(0x66); // size prefix
-      case 13:
-        emit_byte(0x66); // size prefix
-      case 12:
-        addr_nop_8();
-        emit_byte(0x66); // size prefix
-        emit_byte(0x66); // size prefix
-        emit_byte(0x66); // size prefix
-        emit_byte(0x90); // nop
-        break;
-      case 11:
-        emit_byte(0x66); // size prefix
-      case 10:
-        emit_byte(0x66); // size prefix
-      case 9:
-        emit_byte(0x66); // size prefix
-      case 8:
-        addr_nop_8();
-        break;
-      case 7:
-        addr_nop_7();
-        break;
-      case 6:
-        emit_byte(0x66); // size prefix
-      case 5:
-        addr_nop_5();
-        break;
-      case 4:
-        addr_nop_4();
-        break;
-      case 3:
-        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
-        emit_byte(0x66); // size prefix
-      case 2:
-        emit_byte(0x66); // size prefix
-      case 1:
-        emit_byte(0x90); // nop
-        break;
-      default:
-        assert(i == 0, " ");
-    }
-    return;
-  }
-  if (UseAddressNop && VM_Version::is_amd()) {
-    //
-    // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
-    //  1: 0x90
-    //  2: 0x66 0x90
-    //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
-    //  4: 0x0F 0x1F 0x40 0x00
-    //  5: 0x0F 0x1F 0x44 0x00 0x00
-    //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
-    //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
-    // The rest coding is AMD specific - use consecutive address nops
-
-    // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
-    // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
-    // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
-    // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-    //     Size prefixes (0x66) are added for larger sizes
-
-    while(i >= 22) {
-      i -= 11;
-      emit_byte(0x66); // size prefix
-      emit_byte(0x66); // size prefix
-      emit_byte(0x66); // size prefix
-      addr_nop_8();
-    }
-    // Generate first nop for size between 21-12
-    switch (i) {
-      case 21:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 20:
-      case 19:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 18:
-      case 17:
-        i -= 1;
-        emit_byte(0x66); // size prefix
-      case 16:
-      case 15:
-        i -= 8;
-        addr_nop_8();
-        break;
-      case 14:
-      case 13:
-        i -= 7;
-        addr_nop_7();
-        break;
-      case 12:
-        i -= 6;
-        emit_byte(0x66); // size prefix
-        addr_nop_5();
-        break;
-      default:
-        assert(i < 12, " ");
-    }
-
-    // Generate second nop for size between 11-1
-    switch (i) {
-      case 11:
-        emit_byte(0x66); // size prefix
-      case 10:
-        emit_byte(0x66); // size prefix
-      case 9:
-        emit_byte(0x66); // size prefix
-      case 8:
-        addr_nop_8();
-        break;
-      case 7:
-        addr_nop_7();
-        break;
-      case 6:
-        emit_byte(0x66); // size prefix
-      case 5:
-        addr_nop_5();
-        break;
-      case 4:
-        addr_nop_4();
-        break;
-      case 3:
-        // Don't use "0x0F 0x1F 0x00" - need patching safe padding
-        emit_byte(0x66); // size prefix
-      case 2:
-        emit_byte(0x66); // size prefix
-      case 1:
-        emit_byte(0x90); // nop
-        break;
-      default:
-        assert(i == 0, " ");
-    }
-    return;
-  }
-
-  // Using nops with size prefixes "0x66 0x90".
-  // From AMD Optimization Guide:
-  //  1: 0x90
-  //  2: 0x66 0x90
-  //  3: 0x66 0x66 0x90
-  //  4: 0x66 0x66 0x66 0x90
-  //  5: 0x66 0x66 0x90 0x66 0x90
-  //  6: 0x66 0x66 0x90 0x66 0x66 0x90
-  //  7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
-  //  8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
-  //  9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
-  // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
-  //
-  while(i > 12) {
-    i -= 4;
-    emit_byte(0x66); // size prefix
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90); // nop
-  }
-  // 1 - 12 nops
-  if(i > 8) {
-    if(i > 9) {
-      i -= 1;
-      emit_byte(0x66);
-    }
-    i -= 3;
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90);
-  }
-  // 1 - 8 nops
-  if(i > 4) {
-    if(i > 6) {
-      i -= 1;
-      emit_byte(0x66);
-    }
-    i -= 3;
-    emit_byte(0x66);
-    emit_byte(0x66);
-    emit_byte(0x90);
-  }
-  switch (i) {
-    case 4:
-      emit_byte(0x66);
-    case 3:
-      emit_byte(0x66);
-    case 2:
-      emit_byte(0x66);
-    case 1:
-      emit_byte(0x90);
-      break;
-    default:
-      assert(i == 0, " ");
-  }
-}
-
-void Assembler::ret(int imm16) {
-  if (imm16 == 0) {
-    emit_byte(0xC3);
-  } else {
-    emit_byte(0xC2);
-    emit_word(imm16);
-  }
-}
-
-// copies a single word from [esi] to [edi]
-void Assembler::smovl() {
-  emit_byte(0xA5);
-}
-
-// copies data from [rsi] to [rdi] using rcx words (m32)
-void Assembler::rep_movl() {
-  // REP
-  emit_byte(0xF3);
-  // MOVSL
-  emit_byte(0xA5);
-}
-
-// copies data from [rsi] to [rdi] using rcx double words (m64)
-void Assembler::rep_movq() {
-  // REP
-  emit_byte(0xF3);
-  // MOVSQ
-  prefix(REX_W);
-  emit_byte(0xA5);
-}
-
-// sets rcx double words (m64) with rax value at [rdi]
-void Assembler::rep_set() {
-  // REP
-  emit_byte(0xF3);
-  // STOSQ
-  prefix(REX_W);
-  emit_byte(0xAB);
-}
-
-// scans rcx double words (m64) at [rdi] for occurance of rax
-void Assembler::repne_scanq() {
-  // REPNE/REPNZ
-  emit_byte(0xF2);
-  // SCASQ
-  prefix(REX_W);
-  emit_byte(0xAF);
-}
-
-void Assembler::repne_scanl() {
-  // REPNE/REPNZ
-  emit_byte(0xF2);
-  // SCASL
-  emit_byte(0xAF);
-}
-
-
-void Assembler::setb(Condition cc, Register dst) {
-  assert(0 <= cc && cc < 16, "illegal cc");
-  int encode = prefix_and_encode(dst->encoding(), true);
-  emit_byte(0x0F);
-  emit_byte(0x90 | cc);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::clflush(Address adr) {
-  prefix(adr);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(rdi, adr);
-}
-
-void Assembler::call(Label& L, relocInfo::relocType rtype) {
-  if (L.is_bound()) {
-    const int long_size = 5;
-    int offs = (int)( target(L) - pc() );
-    assert(offs <= 0, "assembler error");
-    InstructionMark im(this);
-    // 1110 1000 #32-bit disp
-    emit_byte(0xE8);
-    emit_data(offs - long_size, rtype, disp32_operand);
-  } else {
-    InstructionMark im(this);
-    // 1110 1000 #32-bit disp
-    L.add_patch_at(code(), locator());
-
-    emit_byte(0xE8);
-    emit_data(int(0), rtype, disp32_operand);
-  }
-}
-
-void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
-  assert(entry != NULL, "call most probably wrong");
-  InstructionMark im(this);
-  emit_byte(0xE8);
-  intptr_t disp = entry - (_code_pos + sizeof(int32_t));
-  assert(is_simm32(disp), "must be 32bit offset (call2)");
-  // Technically, should use call32_operand, but this format is
-  // implied by the fact that we're emitting a call instruction.
-  emit_data((int) disp, rspec, disp32_operand);
-}
-
-
-void Assembler::call(Register dst) {
-  // This was originally using a 32bit register encoding
-  // and surely we want 64bit!
-  // this is a 32bit encoding but in 64bit mode the default
-  // operand size is 64bit so there is no need for the
-  // wide prefix. So prefix only happens if we use the
-  // new registers. Much like push/pop.
-  int encode = prefixq_and_encode(dst->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xD0 | encode);
-}
-
-void Assembler::call(Address adr) {
-  InstructionMark im(this);
-  prefix(adr);
-  emit_byte(0xFF);
-  emit_operand(rdx, adr);
-}
-
-void Assembler::jmp(Register reg) {
-  int encode = prefix_and_encode(reg->encoding());
-  emit_byte(0xFF);
-  emit_byte(0xE0 | encode);
-}
-
-void Assembler::jmp(Address adr) {
-  InstructionMark im(this);
-  prefix(adr);
-  emit_byte(0xFF);
-  emit_operand(rsp, adr);
-}
-
-void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
-  InstructionMark im(this);
-  emit_byte(0xE9);
-  assert(dest != NULL, "must have a target");
-  intptr_t disp = dest - (_code_pos + sizeof(int32_t));
-  assert(is_simm32(disp), "must be 32bit offset (jmp)");
-  emit_data(disp, rspec.reloc(), call32_operand);
-}
-
-void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
-  if (L.is_bound()) {
-    address entry = target(L);
-    assert(entry != NULL, "jmp most probably wrong");
-    InstructionMark im(this);
-    const int short_size = 2;
-    const int long_size = 5;
-    intptr_t offs = entry - _code_pos;
-    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
-      emit_byte(0xEB);
-      emit_byte((offs - short_size) & 0xFF);
-    } else {
-      emit_byte(0xE9);
-      emit_long(offs - long_size);
-    }
-  } else {
-    // By default, forward jumps are always 32-bit displacements, since
-    // we can't yet know where the label will be bound.  If you're sure that
-    // the forward jump will not run beyond 256 bytes, use jmpb to
-    // force an 8-bit displacement.
-    InstructionMark im(this);
-    relocate(rtype);
-    L.add_patch_at(code(), locator());
-    emit_byte(0xE9);
-    emit_long(0);
-  }
-}
-
-void Assembler::jmpb(Label& L) {
-  if (L.is_bound()) {
-    const int short_size = 2;
-    address entry = target(L);
-    assert(is8bit((entry - _code_pos) + short_size),
-           "Dispacement too large for a short jmp");
-    assert(entry != NULL, "jmp most probably wrong");
-    intptr_t offs = entry - _code_pos;
-    emit_byte(0xEB);
-    emit_byte((offs - short_size) & 0xFF);
-  } else {
-    InstructionMark im(this);
-    L.add_patch_at(code(), locator());
-    emit_byte(0xEB);
-    emit_byte(0);
-  }
-}
-
-void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
-  InstructionMark im(this);
-  relocate(rtype);
-  assert((0 <= cc) && (cc < 16), "illegal cc");
-  if (L.is_bound()) {
-    address dst = target(L);
-    assert(dst != NULL, "jcc most probably wrong");
-
-    const int short_size = 2;
-    const int long_size = 6;
-    intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
-    if (rtype == relocInfo::none && is8bit(offs - short_size)) {
-      // 0111 tttn #8-bit disp
-      emit_byte(0x70 | cc);
-      emit_byte((offs - short_size) & 0xFF);
-    } else {
-      // 0000 1111 1000 tttn #32-bit disp
-      assert(is_simm32(offs - long_size),
-             "must be 32bit offset (call4)");
-      emit_byte(0x0F);
-      emit_byte(0x80 | cc);
-      emit_long(offs - long_size);
-    }
-  } else {
-    // Note: could eliminate cond. jumps to this jump if condition
-    //       is the same however, seems to be rather unlikely case.
-    // Note: use jccb() if label to be bound is very close to get
-    //       an 8-bit displacement
-    L.add_patch_at(code(), locator());
-    emit_byte(0x0F);
-    emit_byte(0x80 | cc);
-    emit_long(0);
-  }
-}
-
-void Assembler::jccb(Condition cc, Label& L) {
-  if (L.is_bound()) {
-    const int short_size = 2;
-    const int long_size = 6;
-    address entry = target(L);
-    assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
-           "Dispacement too large for a short jmp");
-    intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
-    // 0111 tttn #8-bit disp
-    emit_byte(0x70 | cc);
-    emit_byte((offs - short_size) & 0xFF);
-  } else {
-    InstructionMark im(this);
-    L.add_patch_at(code(), locator());
-    emit_byte(0x70 | cc);
-    emit_byte(0);
-  }
-}
-
-// FP instructions
-
-void Assembler::fxsave(Address dst) {
-  prefixq(dst);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(as_Register(0), dst);
-}
-
-void Assembler::fxrstor(Address src) {
-  prefixq(src);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(as_Register(1), src);
-}
-
-void Assembler::ldmxcsr(Address src) {
-  InstructionMark im(this);
-  prefix(src);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(as_Register(2), src);
-}
-
-void Assembler::stmxcsr(Address dst) {
-  InstructionMark im(this);
-  prefix(dst);
-  emit_byte(0x0F);
-  emit_byte(0xAE);
-  emit_operand(as_Register(3), dst);
-}
-
-void Assembler::addss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x58);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::addss(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x58);
-  emit_operand(dst, src);
-}
-
-void Assembler::subss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::subss(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x5C);
-  emit_operand(dst, src);
-}
-
-void Assembler::mulss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x59);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::mulss(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x59);
-  emit_operand(dst, src);
-}
-
-void Assembler::divss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::divss(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF3);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x5E);
-  emit_operand(dst, src);
-}
-
-void Assembler::addsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x58);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::addsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x58);
-  emit_operand(dst, src);
-}
-
-void Assembler::subsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::subsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x5C);
-  emit_operand(dst, src);
-}
-
-void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x59);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::mulsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x59);
-  emit_operand(dst, src);
-}
-
-void Assembler::divsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5E);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::divsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x5E);
-  emit_operand(dst, src);
-}
-
-void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x51);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::sqrtsd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0xF2);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x51);
-  emit_operand(dst, src);
-}
-
-void Assembler::xorps(XMMRegister dst, XMMRegister src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x57);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::xorps(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x57);
-  emit_operand(dst, src);
-}
-
-void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0x66);
-  xorps(dst, src);
-}
-
-void Assembler::xorpd(XMMRegister dst, Address src) {
-  InstructionMark im(this);
-  emit_byte(0x66);
-  prefix(src, dst);
-  emit_byte(0x0F);
-  emit_byte(0x57);
-  emit_operand(dst, src);
-}
-
-void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
-  emit_byte(0xF3);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
-  emit_byte(0xF2);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttss2sil(Register dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttss2siq(Register dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefixq_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x2C);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF3);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0xE6);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5B);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
-  emit_byte(0xF2);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x5A);
-  emit_byte(0xC0 | encode);
-}
-
-void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
-  emit_byte(0x66);
-  int encode = prefix_and_encode(dst->encoding(), src->encoding());
-  emit_byte(0x0F);
-  emit_byte(0x60);
-  emit_byte(0xC0 | encode);
-}
-
-// Implementation of MacroAssembler
-
-// On 32 bit it returns a vanilla displacement on 64 bit is a rip relative displacement
-Address MacroAssembler::as_Address(AddressLiteral adr) {
-  assert(!adr.is_lval(), "must be rval");
-  assert(reachable(adr), "must be");
-  return Address((int)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
-}
-
-Address MacroAssembler::as_Address(ArrayAddress adr) {
-#ifdef _LP64
-  AddressLiteral base = adr.base();
-  lea(rscratch1, base);
-  Address index = adr.index();
-  assert(index._disp == 0, "must not have disp"); // maybe it can?
-  Address array(rscratch1, index._index, index._scale, index._disp);
-  return array;
-#else
-  return Address::make_array(adr);
-#endif // _LP64
-
-}
-
-void MacroAssembler::fat_nop() {
-  // A 5 byte nop that is safe for patching (see patch_verified_entry)
-  // Recommened sequence from 'Software Optimization Guide for the AMD
-  // Hammer Processor'
-  emit_byte(0x66);
-  emit_byte(0x66);
-  emit_byte(0x90);
-  emit_byte(0x66);
-  emit_byte(0x90);
-}
-
-static Assembler::Condition reverse[] = {
-    Assembler::noOverflow     /* overflow      = 0x0 */ ,
-    Assembler::overflow       /* noOverflow    = 0x1 */ ,
-    Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
-    Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
-    Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
-    Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
-    Assembler::above          /* belowEqual    = 0x6 */ ,
-    Assembler::belowEqual     /* above         = 0x7 */ ,
-    Assembler::positive       /* negative      = 0x8 */ ,
-    Assembler::negative       /* positive      = 0x9 */ ,
-    Assembler::noParity       /* parity        = 0xa */ ,
-    Assembler::parity         /* noParity      = 0xb */ ,
-    Assembler::greaterEqual   /* less          = 0xc */ ,
-    Assembler::less           /* greaterEqual  = 0xd */ ,
-    Assembler::greater        /* lessEqual     = 0xe */ ,
-    Assembler::lessEqual      /* greater       = 0xf, */
-
-};
-
-// 32bit can do a case table jump in one instruction but we no longer allow the base
-// to be installed in the Address class
-void MacroAssembler::jump(ArrayAddress entry) {
-#ifdef _LP64
-  lea(rscratch1, entry.base());
-  Address dispatch = entry.index();
-  assert(dispatch._base == noreg, "must be");
-  dispatch._base = rscratch1;
-  jmp(dispatch);
-#else
-  jmp(as_Address(entry));
-#endif // _LP64
-}
-
-void MacroAssembler::jump(AddressLiteral dst) {
-  if (reachable(dst)) {
-    jmp_literal(dst.target(), dst.rspec());
-  } else {
-    lea(rscratch1, dst);
-    jmp(rscratch1);
-  }
-}
-
-void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
-  if (reachable(dst)) {
-    InstructionMark im(this);
-    relocate(dst.reloc());
-    const int short_size = 2;
-    const int long_size = 6;
-    int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
-    if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
-      // 0111 tttn #8-bit disp
-      emit_byte(0x70 | cc);
-      emit_byte((offs - short_size) & 0xFF);
-    } else {
-      // 0000 1111 1000 tttn #32-bit disp
-      emit_byte(0x0F);
-      emit_byte(0x80 | cc);
-      emit_long(offs - long_size);
-    }
-  } else {
-#ifdef ASSERT
-    warning("reversing conditional branch");
-#endif /* ASSERT */
-    Label skip;
-    jccb(reverse[cc], skip);
-    lea(rscratch1, dst);
-    Assembler::jmp(rscratch1);
-    bind(skip);
-  }
-}
-
-// Wouldn't need if AddressLiteral version had new name
-void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
-  Assembler::call(L, rtype);
-}
-
-// Wouldn't need if AddressLiteral version had new name
-void MacroAssembler::call(Register entry) {
-  Assembler::call(entry);
-}
-
-void MacroAssembler::call(AddressLiteral entry) {
-  if (reachable(entry)) {
-    Assembler::call_literal(entry.target(), entry.rspec());
-  } else {
-    lea(rscratch1, entry);
-    Assembler::call(rscratch1);
-  }
-}
-
-void MacroAssembler::cmp8(AddressLiteral src1, int8_t src2) {
-  if (reachable(src1)) {
-    cmpb(as_Address(src1), src2);
-  } else {
-    lea(rscratch1, src1);
-    cmpb(Address(rscratch1, 0), src2);
-  }
-}
-
-void MacroAssembler::cmp32(AddressLiteral src1, int32_t src2) {
-  if (reachable(src1)) {
-    cmpl(as_Address(src1), src2);
-  } else {
-    lea(rscratch1, src1);
-    cmpl(Address(rscratch1, 0), src2);
-  }
-}
-
-void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
-  if (reachable(src2)) {
-    cmpl(src1, as_Address(src2));
-  } else {
-    lea(rscratch1, src2);
-    cmpl(src1, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
-#ifdef _LP64
-  if (src2.is_lval()) {
-    movptr(rscratch1, src2);
-    Assembler::cmpq(src1, rscratch1);
-  } else if (reachable(src2)) {
-    cmpq(src1, as_Address(src2));
-  } else {
-    lea(rscratch1, src2);
-    Assembler::cmpq(src1, Address(rscratch1, 0));
-  }
-#else
-  if (src2.is_lval()) {
-    cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-  } else {
-    cmpl(src1, as_Address(src2));
-  }
-#endif // _LP64
-}
-
-void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
-  assert(src2.is_lval(), "not a mem-mem compare");
-#ifdef _LP64
-  // moves src2's literal address
-  movptr(rscratch1, src2);
-  Assembler::cmpq(src1, rscratch1);
-#else
-  cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-#endif // _LP64
-}
-
-void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
-  assert(!src2.is_lval(), "should use cmpptr");
-
-  if (reachable(src2)) {
-#ifdef _LP64
-    cmpq(src1, as_Address(src2));
-#else
-    ShouldNotReachHere();
-#endif // _LP64
-  } else {
-    lea(rscratch1, src2);
-    Assembler::cmpq(src1, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
-  if (reachable(adr)) {
-#ifdef _LP64
-    cmpxchgq(reg, as_Address(adr));
-#else
-    cmpxchgl(reg, as_Address(adr));
-#endif // _LP64
-  } else {
-    lea(rscratch1, adr);
-    cmpxchgq(reg, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::incrementl(AddressLiteral dst) {
-  if (reachable(dst)) {
-    incrementl(as_Address(dst));
-  } else {
-    lea(rscratch1, dst);
-    incrementl(Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::incrementl(ArrayAddress dst) {
-  incrementl(as_Address(dst));
-}
-
-void MacroAssembler::lea(Register dst, Address src) {
-#ifdef _LP64
-  leaq(dst, src);
-#else
-  leal(dst, src);
-#endif // _LP64
-}
-
-void MacroAssembler::lea(Register dst, AddressLiteral src) {
-#ifdef _LP64
-    mov_literal64(dst, (intptr_t)src.target(), src.rspec());
-#else
-    mov_literal32(dst, (intptr_t)src.target(), src.rspec());
-#endif // _LP64
-}
-
-void MacroAssembler::mov32(AddressLiteral dst, Register src) {
-  if (reachable(dst)) {
-    movl(as_Address(dst), src);
-  } else {
-    lea(rscratch1, dst);
-    movl(Address(rscratch1, 0), src);
-  }
-}
-
-void MacroAssembler::mov32(Register dst, AddressLiteral src) {
-  if (reachable(src)) {
-    movl(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    movl(dst, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    if (UseXmmLoadAndClearUpper) {
-      movsd (dst, as_Address(src));
-    } else {
-      movlpd(dst, as_Address(src));
-    }
-  } else {
-    lea(rscratch1, src);
-    if (UseXmmLoadAndClearUpper) {
-      movsd (dst, Address(rscratch1, 0));
-    } else {
-      movlpd(dst, Address(rscratch1, 0));
-    }
-  }
-}
-
-void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    movss(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    movss(dst, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::movoop(Register dst, jobject obj) {
-  mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movoop(Address dst, jobject obj) {
-  mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
-  movq(dst, rscratch1);
-}
-
-void MacroAssembler::movptr(Register dst, AddressLiteral src) {
-#ifdef _LP64
-  if (src.is_lval()) {
-    mov_literal64(dst, (intptr_t)src.target(), src.rspec());
-  } else {
-    if (reachable(src)) {
-      movq(dst, as_Address(src));
-    } else {
-      lea(rscratch1, src);
-      movq(dst, Address(rscratch1,0));
-    }
-  }
-#else
-  if (src.is_lval()) {
-    mov_literal32(dst, (intptr_t)src.target(), src.rspec());
-  } else {
-    movl(dst, as_Address(src));
-  }
-#endif // LP64
-}
-
-void MacroAssembler::movptr(ArrayAddress dst, Register src) {
-#ifdef _LP64
-  movq(as_Address(dst), src);
-#else
-  movl(as_Address(dst), src);
-#endif // _LP64
-}
-
-void MacroAssembler::pushoop(jobject obj) {
-#ifdef _LP64
-  movoop(rscratch1, obj);
-  pushq(rscratch1);
-#else
-  push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
-#endif // _LP64
-}
-
-void MacroAssembler::pushptr(AddressLiteral src) {
-#ifdef _LP64
-  lea(rscratch1, src);
-  if (src.is_lval()) {
-    pushq(rscratch1);
-  } else {
-    pushq(Address(rscratch1, 0));
-  }
-#else
-  if (src.is_lval()) {
-    push_literal((int32_t)src.target(), src.rspec());
-  else {
-    pushl(as_Address(src));
-  }
-#endif // _LP64
-}
-
-void MacroAssembler::ldmxcsr(AddressLiteral src) {
-  if (reachable(src)) {
-    Assembler::ldmxcsr(as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    Assembler::ldmxcsr(Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::movlpd(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    movlpd(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    movlpd(dst, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    movss(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    movss(dst, Address(rscratch1, 0));
-  }
-}
-void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    xorpd(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    xorpd(dst, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
-  if (reachable(src)) {
-    xorps(dst, as_Address(src));
-  } else {
-    lea(rscratch1, src);
-    xorps(dst, Address(rscratch1, 0));
-  }
-}
-
-void MacroAssembler::null_check(Register reg, int offset) {
-  if (needs_explicit_null_check(offset)) {
-    // provoke OS NULL exception if reg = NULL by
-    // accessing M[reg] w/o changing any (non-CC) registers
-    cmpq(rax, Address(reg, 0));
-    // Note: should probably use testl(rax, Address(reg, 0));
-    //       may be shorter code (however, this version of
-    //       testl needs to be implemented first)
-  } else {
-    // nothing to do, (later) access of M[reg + offset]
-    // will provoke OS NULL exception if reg = NULL
-  }
-}
-
-int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
-  int off = offset();
-  movzbl(dst, src);
-  return off;
-}
-
-int MacroAssembler::load_unsigned_word(Register dst, Address src) {
-  int off = offset();
-  movzwl(dst, src);
-  return off;
-}
-
-int MacroAssembler::load_signed_byte(Register dst, Address src) {
-  int off = offset();
-  movsbl(dst, src);
-  return off;
-}
-
-int MacroAssembler::load_signed_word(Register dst, Address src) {
-  int off = offset();
-  movswl(dst, src);
-  return off;
-}
-
-void MacroAssembler::incrementl(Register reg, int value) {
-  if (value == min_jint) { addl(reg, value); return; }
-  if (value <  0) { decrementl(reg, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { incl(reg) ; return; }
-  /* else */      { addl(reg, value)       ; return; }
-}
-
-void MacroAssembler::decrementl(Register reg, int value) {
-  if (value == min_jint) { subl(reg, value); return; }
-  if (value <  0) { incrementl(reg, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { decl(reg) ; return; }
-  /* else */      { subl(reg, value)       ; return; }
-}
-
-void MacroAssembler::incrementq(Register reg, int value) {
-  if (value == min_jint) { addq(reg, value); return; }
-  if (value <  0) { decrementq(reg, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { incq(reg) ; return; }
-  /* else */      { addq(reg, value)       ; return; }
-}
-
-void MacroAssembler::decrementq(Register reg, int value) {
-  if (value == min_jint) { subq(reg, value); return; }
-  if (value <  0) { incrementq(reg, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { decq(reg) ; return; }
-  /* else */      { subq(reg, value)       ; return; }
-}
-
-void MacroAssembler::incrementl(Address dst, int value) {
-  if (value == min_jint) { addl(dst, value); return; }
-  if (value <  0) { decrementl(dst, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { incl(dst) ; return; }
-  /* else */      { addl(dst, value)       ; return; }
-}
-
-void MacroAssembler::decrementl(Address dst, int value) {
-  if (value == min_jint) { subl(dst, value); return; }
-  if (value <  0) { incrementl(dst, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { decl(dst) ; return; }
-  /* else */      { subl(dst, value)       ; return; }
-}
-
-void MacroAssembler::incrementq(Address dst, int value) {
-  if (value == min_jint) { addq(dst, value); return; }
-  if (value <  0) { decrementq(dst, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { incq(dst) ; return; }
-  /* else */      { addq(dst, value)       ; return; }
-}
-
-void MacroAssembler::decrementq(Address dst, int value) {
-  if (value == min_jint) { subq(dst, value); return; }
-  if (value <  0) { incrementq(dst, -value); return; }
-  if (value == 0) {                        ; return; }
-  if (value == 1 && UseIncDec) { decq(dst) ; return; }
-  /* else */      { subq(dst, value)       ; return; }
-}
-
-void MacroAssembler::align(int modulus) {
-  if (offset() % modulus != 0) {
-    nop(modulus - (offset() % modulus));
-  }
-}
-
-void MacroAssembler::enter() {
-  pushq(rbp);
-  movq(rbp, rsp);
-}
-
-void MacroAssembler::leave() {
-  emit_byte(0xC9); // LEAVE
-}
-
-// C++ bool manipulation
-
-void MacroAssembler::movbool(Register dst, Address src) {
-  if(sizeof(bool) == 1)
-    movb(dst, src);
-  else if(sizeof(bool) == 2)
-    movw(dst, src);
-  else if(sizeof(bool) == 4)
-    movl(dst, src);
-  else {
-    // unsupported
-    ShouldNotReachHere();
-  }
-}
-
-void MacroAssembler::movbool(Address dst, bool boolconst) {
-  if(sizeof(bool) == 1)
-    movb(dst, (int) boolconst);
-  else if(sizeof(bool) == 2)
-    movw(dst, (int) boolconst);
-  else if(sizeof(bool) == 4)
-    movl(dst, (int) boolconst);
-  else {
-    // unsupported
-    ShouldNotReachHere();
-  }
-}
-
-void MacroAssembler::movbool(Address dst, Register src) {
-  if(sizeof(bool) == 1)
-    movb(dst, src);
-  else if(sizeof(bool) == 2)
-    movw(dst, src);
-  else if(sizeof(bool) == 4)
-    movl(dst, src);
-  else {
-    // unsupported
-    ShouldNotReachHere();
-  }
-}
-
-void MacroAssembler::testbool(Register dst) {
-  if(sizeof(bool) == 1)
-    testb(dst, (int) 0xff);
-  else if(sizeof(bool) == 2) {
-    // need testw impl
-    ShouldNotReachHere();
-  } else if(sizeof(bool) == 4)
-    testl(dst, dst);
-  else {
-    // unsupported
-    ShouldNotReachHere();
-  }
-}
-
-void MacroAssembler::set_last_Java_frame(Register last_java_sp,
-                                         Register last_java_fp,
-                                         address  last_java_pc) {
-  // determine last_java_sp register
-  if (!last_java_sp->is_valid()) {
-    last_java_sp = rsp;
-  }
-
-  // last_java_fp is optional
-  if (last_java_fp->is_valid()) {
-    movq(Address(r15_thread, JavaThread::last_Java_fp_offset()),
-         last_java_fp);
-  }
-
-  // last_java_pc is optional
-  if (last_java_pc != NULL) {
-    Address java_pc(r15_thread,
-                    JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
-    lea(rscratch1, InternalAddress(last_java_pc));
-    movq(java_pc, rscratch1);
-  }
-
-  movq(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
-}
-
-void MacroAssembler::reset_last_Java_frame(bool clear_fp,
-                                           bool clear_pc) {
-  // we must set sp to zero to clear frame
-  movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
-  // must clear fp, so that compiled frames are not confused; it is
-  // possible that we need it only for debugging
-  if (clear_fp) {
-    movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
-  }
-
-  if (clear_pc) {
-    movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
-  }
-}
-
-
-// Implementation of call_VM versions
-
-void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
-  Label L, E;
-
-#ifdef _WIN64
-  // Windows always allocates space for it's register args
-  assert(num_args <= 4, "only register arguments supported");
-  subq(rsp,  frame::arg_reg_save_area_bytes);
-#endif
-
-  // Align stack if necessary
-  testl(rsp, 15);
-  jcc(Assembler::zero, L);
-
-  subq(rsp, 8);
-  {
-    call(RuntimeAddress(entry_point));
-  }
-  addq(rsp, 8);
-  jmp(E);
-
-  bind(L);
-  {
-    call(RuntimeAddress(entry_point));
-  }
-
-  bind(E);
-
-#ifdef _WIN64
-  // restore stack pointer
-  addq(rsp, frame::arg_reg_save_area_bytes);
-#endif
-
-}
-
-
-void MacroAssembler::call_VM_base(Register oop_result,
-                                  Register java_thread,
-                                  Register last_java_sp,
-                                  address entry_point,
-                                  int num_args,
-                                  bool check_exceptions) {
-  // determine last_java_sp register
-  if (!last_java_sp->is_valid()) {
-    last_java_sp = rsp;
-  }
-
-  // debugging support
-  assert(num_args >= 0, "cannot have negative number of arguments");
-  assert(r15_thread != oop_result,
-         "cannot use the same register for java_thread & oop_result");
-  assert(r15_thread != last_java_sp,
-         "cannot use the same register for java_thread & last_java_sp");
-
-  // set last Java frame before call
-
-  // This sets last_Java_fp which is only needed from interpreted frames
-  // and should really be done only from the interp_masm version before
-  // calling the underlying call_VM. That doesn't happen yet so we set
-  // last_Java_fp here even though some callers don't need it and
-  // also clear it below.
-  set_last_Java_frame(last_java_sp, rbp, NULL);
-
-  {
-    Label L, E;
-
-    // Align stack if necessary
-#ifdef _WIN64
-    assert(num_args <= 4, "only register arguments supported");
-    // Windows always allocates space for it's register args
-    subq(rsp, frame::arg_reg_save_area_bytes);
-#endif
-    testl(rsp, 15);
-    jcc(Assembler::zero, L);
-
-    subq(rsp, 8);
-    {
-      call(RuntimeAddress(entry_point));
-    }
-    addq(rsp, 8);
-    jmp(E);
-
-
-    bind(L);
-    {
-      call(RuntimeAddress(entry_point));
-    }
-
-    bind(E);
-
-#ifdef _WIN64
-    // restore stack pointer
-    addq(rsp, frame::arg_reg_save_area_bytes);
-#endif
-  }
-
-#ifdef ASSERT
-  pushq(rax);
-  {
-    Label L;
-    get_thread(rax);
-    cmpq(r15_thread, rax);
-    jcc(Assembler::equal, L);
-    stop("MacroAssembler::call_VM_base: register not callee saved?");
-    bind(L);
-  }
-  popq(rax);
-#endif
-
-  // reset last Java frame
-  // This really shouldn't have to clear fp set note above at the
-  // call to set_last_Java_frame
-  reset_last_Java_frame(true, false);
-
-  check_and_handle_popframe(noreg);
-  check_and_handle_earlyret(noreg);
-
-  if (check_exceptions) {
-    cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int) NULL);
-    // This used to conditionally jump to forward_exception however it is
-    // possible if we relocate that the branch will not reach. So we must jump
-    // around so we can always reach
-    Label ok;
-    jcc(Assembler::equal, ok);
-    jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
-    bind(ok);
-  }
-
-  // get oop result if there is one and reset the value in the thread
-  if (oop_result->is_valid()) {
-    movq(oop_result, Address(r15_thread, JavaThread::vm_result_offset()));
-    movptr(Address(r15_thread, JavaThread::vm_result_offset()), NULL_WORD);
-    verify_oop(oop_result, "broken oop in call_VM_base");
-  }
-}
-
-void MacroAssembler::check_and_handle_popframe(Register java_thread) {}
-void MacroAssembler::check_and_handle_earlyret(Register java_thread) {}
-
-void MacroAssembler::call_VM_helper(Register oop_result,
-                                    address entry_point,
-                                    int num_args,
-                                    bool check_exceptions) {
-  // Java thread becomes first argument of C function
-  movq(c_rarg0, r15_thread);
-
-  // We've pushed one address, correct last_Java_sp
-  leaq(rax, Address(rsp, wordSize));
-
-  call_VM_base(oop_result, noreg, rax, entry_point, num_args,
-               check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
-                             address entry_point,
-                             bool check_exceptions) {
-  Label C, E;
-  Assembler::call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  call_VM_helper(oop_result, entry_point, 0, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
-                             address entry_point,
-                             Register arg_1,
-                             bool check_exceptions) {
-  assert(rax != arg_1, "smashed argument");
-  assert(c_rarg0 != arg_1, "smashed argument");
-
-  Label C, E;
-  Assembler::call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  call_VM_helper(oop_result, entry_point, 1, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
-                             address entry_point,
-                             Register arg_1,
-                             Register arg_2,
-                             bool check_exceptions) {
-  assert(rax != arg_1, "smashed argument");
-  assert(rax != arg_2, "smashed argument");
-  assert(c_rarg0 != arg_1, "smashed argument");
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg1 != arg_2, "smashed argument");
-  assert(c_rarg2 != arg_1, "smashed argument");
-
-  Label C, E;
-  Assembler::call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  if (c_rarg2 != arg_2) {
-    movq(c_rarg2, arg_2);
-  }
-  call_VM_helper(oop_result, entry_point, 2, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
-                             address entry_point,
-                             Register arg_1,
-                             Register arg_2,
-                             Register arg_3,
-                             bool check_exceptions) {
-  assert(rax != arg_1, "smashed argument");
-  assert(rax != arg_2, "smashed argument");
-  assert(rax != arg_3, "smashed argument");
-  assert(c_rarg0 != arg_1, "smashed argument");
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg0 != arg_3, "smashed argument");
-  assert(c_rarg1 != arg_2, "smashed argument");
-  assert(c_rarg1 != arg_3, "smashed argument");
-  assert(c_rarg2 != arg_1, "smashed argument");
-  assert(c_rarg2 != arg_3, "smashed argument");
-  assert(c_rarg3 != arg_1, "smashed argument");
-  assert(c_rarg3 != arg_2, "smashed argument");
-
-  Label C, E;
-  Assembler::call(C, relocInfo::none);
-  jmp(E);
-
-  bind(C);
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  if (c_rarg2 != arg_2) {
-    movq(c_rarg2, arg_2);
-  }
-  if (c_rarg3 != arg_3) {
-    movq(c_rarg3, arg_3);
-  }
-  call_VM_helper(oop_result, entry_point, 3, check_exceptions);
-  ret(0);
-
-  bind(E);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
-                             Register last_java_sp,
-                             address entry_point,
-                             int num_args,
-                             bool check_exceptions) {
-  call_VM_base(oop_result, noreg, last_java_sp, entry_point, num_args,
-               check_exceptions);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
-                             Register last_java_sp,
-                             address entry_point,
-                             Register arg_1,
-                             bool check_exceptions) {
-  assert(c_rarg0 != arg_1, "smashed argument");
-  assert(c_rarg1 != last_java_sp, "smashed argument");
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
-                             Register last_java_sp,
-                             address entry_point,
-                             Register arg_1,
-                             Register arg_2,
-                             bool check_exceptions) {
-  assert(c_rarg0 != arg_1, "smashed argument");
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg1 != arg_2, "smashed argument");
-  assert(c_rarg1 != last_java_sp, "smashed argument");
-  assert(c_rarg2 != arg_1, "smashed argument");
-  assert(c_rarg2 != last_java_sp, "smashed argument");
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  if (c_rarg2 != arg_2) {
-    movq(c_rarg2, arg_2);
-  }
-  call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
-                             Register last_java_sp,
-                             address entry_point,
-                             Register arg_1,
-                             Register arg_2,
-                             Register arg_3,
-                             bool check_exceptions) {
-  assert(c_rarg0 != arg_1, "smashed argument");
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg0 != arg_3, "smashed argument");
-  assert(c_rarg1 != arg_2, "smashed argument");
-  assert(c_rarg1 != arg_3, "smashed argument");
-  assert(c_rarg1 != last_java_sp, "smashed argument");
-  assert(c_rarg2 != arg_1, "smashed argument");
-  assert(c_rarg2 != arg_3, "smashed argument");
-  assert(c_rarg2 != last_java_sp, "smashed argument");
-  assert(c_rarg3 != arg_1, "smashed argument");
-  assert(c_rarg3 != arg_2, "smashed argument");
-  assert(c_rarg3 != last_java_sp, "smashed argument");
-  // c_rarg0 is reserved for thread
-  if (c_rarg1 != arg_1) {
-    movq(c_rarg1, arg_1);
-  }
-  if (c_rarg2 != arg_2) {
-    movq(c_rarg2, arg_2);
-  }
-  if (c_rarg3 != arg_3) {
-    movq(c_rarg2, arg_3);
-  }
-  call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point, int num_args) {
-  call_VM_leaf_base(entry_point, num_args);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
-  if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
-  }
-  call_VM_leaf(entry_point, 1);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point,
-                                  Register arg_1,
-                                  Register arg_2) {
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg1 != arg_1, "smashed argument");
-  if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
-  }
-  if (c_rarg1 != arg_2) {
-    movq(c_rarg1, arg_2);
-  }
-  call_VM_leaf(entry_point, 2);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point,
-                                  Register arg_1,
-                                  Register arg_2,
-                                  Register arg_3) {
-  assert(c_rarg0 != arg_2, "smashed argument");
-  assert(c_rarg0 != arg_3, "smashed argument");
-  assert(c_rarg1 != arg_1, "smashed argument");
-  assert(c_rarg1 != arg_3, "smashed argument");
-  assert(c_rarg2 != arg_1, "smashed argument");
-  assert(c_rarg2 != arg_2, "smashed argument");
-  if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
-  }
-  if (c_rarg1 != arg_2) {
-    movq(c_rarg1, arg_2);
-  }
-  if (c_rarg2 != arg_3) {
-    movq(c_rarg2, arg_3);
-  }
-  call_VM_leaf(entry_point, 3);
-}
-
-
-// Calls to C land
-//
-// When entering C land, the rbp & rsp of the last Java frame have to
-// be recorded in the (thread-local) JavaThread object. When leaving C
-// land, the last Java fp has to be reset to 0. This is required to
-// allow proper stack traversal.
-void MacroAssembler::store_check(Register obj) {
-  // Does a store check for the oop in register obj. The content of
-  // register obj is destroyed afterwards.
-  store_check_part_1(obj);
-  store_check_part_2(obj);
-}
-
-void MacroAssembler::store_check(Register obj, Address dst) {
-  store_check(obj);
-}
-
-// split the store check operation so that other instructions can be
-// scheduled inbetween
-void MacroAssembler::store_check_part_1(Register obj) {
-  BarrierSet* bs = Universe::heap()->barrier_set();
-  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
-  shrq(obj, CardTableModRefBS::card_shift);
-}
-
-void MacroAssembler::store_check_part_2(Register obj) {
-  BarrierSet* bs = Universe::heap()->barrier_set();
-  assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
-  CardTableModRefBS* ct = (CardTableModRefBS*)bs;
-  assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
-
-  // The calculation for byte_map_base is as follows:
-  // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
-  // So this essentially converts an address to a displacement and
-  // it will never need to be relocated. On 64bit however the value may be too
-  // large for a 32bit displacement
-
-  intptr_t disp = (intptr_t) ct->byte_map_base;
-  if (is_simm32(disp)) {
-    Address cardtable(noreg, obj, Address::times_1, disp);
-    movb(cardtable, 0);
-  } else {
-    // By doing it as an ExternalAddress disp could be converted to a rip-relative
-    // displacement and done in a single instruction given favorable mapping and
-    // a smarter version of as_Address. Worst case it is two instructions which
-    // is no worse off then loading disp into a register and doing as a simple
-    // Address() as above.
-    // We can't do as ExternalAddress as the only style since if disp == 0 we'll
-    // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
-    // in some cases we'll get a single instruction version.
-
-    ExternalAddress cardtable((address)disp);
-    Address index(noreg, obj, Address::times_1);
-    movb(as_Address(ArrayAddress(cardtable, index)), 0);
-  }
-
-}
-
-void MacroAssembler::c2bool(Register x) {
-  // implements x == 0 ? 0 : 1
-  // note: must only look at least-significant byte of x
-  //       since C-style booleans are stored in one byte
-  //       only! (was bug)
-  andl(x, 0xFF);
-  setb(Assembler::notZero, x);
-}
-
-int MacroAssembler::corrected_idivl(Register reg) {
-  // Full implementation of Java idiv and irem; checks for special
-  // case as described in JVM spec., p.243 & p.271.  The function
-  // returns the (pc) offset of the idivl instruction - may be needed
-  // for implicit exceptions.
-  //
-  //         normal case                           special case
-  //
-  // input : eax: dividend                         min_int
-  //         reg: divisor   (may not be eax/edx)   -1
-  //
-  // output: eax: quotient  (= eax idiv reg)       min_int
-  //         edx: remainder (= eax irem reg)       0
-  assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
-  const int min_int = 0x80000000;
-  Label normal_case, special_case;
-
-  // check for special case
-  cmpl(rax, min_int);
-  jcc(Assembler::notEqual, normal_case);
-  xorl(rdx, rdx); // prepare edx for possible special case (where
-                  // remainder = 0)
-  cmpl(reg, -1);
-  jcc(Assembler::equal, special_case);
-
-  // handle normal case
-  bind(normal_case);
-  cdql();
-  int idivl_offset = offset();
-  idivl(reg);
-
-  // normal and special case exit
-  bind(special_case);
-
-  return idivl_offset;
-}
-
-int MacroAssembler::corrected_idivq(Register reg) {
-  // Full implementation of Java ldiv and lrem; checks for special
-  // case as described in JVM spec., p.243 & p.271.  The function
-  // returns the (pc) offset of the idivl instruction - may be needed
-  // for implicit exceptions.
-  //
-  //         normal case                           special case
-  //
-  // input : rax: dividend                         min_long
-  //         reg: divisor   (may not be eax/edx)   -1
-  //
-  // output: rax: quotient  (= rax idiv reg)       min_long
-  //         rdx: remainder (= rax irem reg)       0
-  assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
-  static const int64_t min_long = 0x8000000000000000;
-  Label normal_case, special_case;
-
-  // check for special case
-  cmp64(rax, ExternalAddress((address) &min_long));
-  jcc(Assembler::notEqual, normal_case);
-  xorl(rdx, rdx); // prepare rdx for possible special case (where
-                  // remainder = 0)
-  cmpq(reg, -1);
-  jcc(Assembler::equal, special_case);
-
-  // handle normal case
-  bind(normal_case);
-  cdqq();
-  int idivq_offset = offset();
-  idivq(reg);
-
-  // normal and special case exit
-  bind(special_case);
-
-  return idivq_offset;
-}
-
-void MacroAssembler::push_IU_state() {
-  pushfq();     // Push flags first because pushaq kills them
-  subq(rsp, 8); // Make sure rsp stays 16-byte aligned
-  pushaq();
-}
-
-void MacroAssembler::pop_IU_state() {
-  popaq();
-  addq(rsp, 8);
-  popfq();
-}
-
-void MacroAssembler::push_FPU_state() {
-  subq(rsp, FPUStateSizeInWords * wordSize);
-  fxsave(Address(rsp, 0));
-}
-
-void MacroAssembler::pop_FPU_state() {
-  fxrstor(Address(rsp, 0));
-  addq(rsp, FPUStateSizeInWords * wordSize);
-}
-
-// Save Integer and Float state
-// Warning: Stack must be 16 byte aligned
-void MacroAssembler::push_CPU_state() {
-  push_IU_state();
-  push_FPU_state();
-}
-
-void MacroAssembler::pop_CPU_state() {
-  pop_FPU_state();
-  pop_IU_state();
-}
-
-void MacroAssembler::sign_extend_short(Register reg) {
-  movswl(reg, reg);
-}
-
-void MacroAssembler::sign_extend_byte(Register reg) {
-  movsbl(reg, reg);
-}
-
-void MacroAssembler::division_with_shift(Register reg, int shift_value) {
-  assert (shift_value > 0, "illegal shift value");
-  Label _is_positive;
-  testl (reg, reg);
-  jcc (Assembler::positive, _is_positive);
-  int offset = (1 << shift_value) - 1 ;
-
-  if (offset == 1) {
-    incrementl(reg);
-  } else {
-    addl(reg, offset);
-  }
-
-  bind (_is_positive);
-  sarl(reg, shift_value);
-}
-
-void MacroAssembler::round_to_l(Register reg, int modulus) {
-  addl(reg, modulus - 1);
-  andl(reg, -modulus);
-}
-
-void MacroAssembler::round_to_q(Register reg, int modulus) {
-  addq(reg, modulus - 1);
-  andq(reg, -modulus);
-}
-
-void MacroAssembler::verify_oop(Register reg, const char* s) {
-  if (!VerifyOops) {
-    return;
-  }
-
-  // Pass register number to verify_oop_subroutine
-  char* b = new char[strlen(s) + 50];
-  sprintf(b, "verify_oop: %s: %s", reg->name(), s);
-
-  pushq(rax); // save rax, restored by receiver
-
-  // pass args on stack, only touch rax
-  pushq(reg);
-  // avoid using pushptr, as it modifies scratch registers
-  // and our contract is not to modify anything
-  ExternalAddress buffer((address)b);
-  movptr(rax, buffer.addr());
-  pushq(rax);
-
-  // call indirectly to solve generation ordering problem
-  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
-  call(rax); // no alignment requirement
-  // everything popped by receiver
-}
-
-void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
-  if (!VerifyOops) return;
-  // Pass register number to verify_oop_subroutine
-  char* b = new char[strlen(s) + 50];
-  sprintf(b, "verify_oop_addr: %s", s);
-  pushq(rax);                          // save rax
-  movq(addr, rax);
-  pushq(rax);                          // pass register argument
-
-
-  // avoid using pushptr, as it modifies scratch registers
-  // and our contract is not to modify anything
-  ExternalAddress buffer((address)b);
-  movptr(rax, buffer.addr());
-  pushq(rax);
-
-  // call indirectly to solve generation ordering problem
-  movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
-  call(rax); // no alignment requirement
-  // everything popped by receiver
-}
-
-
-void MacroAssembler::stop(const char* msg) {
-  address rip = pc();
-  pushaq(); // get regs on stack
-  lea(c_rarg0, ExternalAddress((address) msg));
-  lea(c_rarg1, InternalAddress(rip));
-  movq(c_rarg2, rsp); // pass pointer to regs array
-  andq(rsp, -16); // align stack as required by ABI
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
-  hlt();
-}
-
-void MacroAssembler::warn(const char* msg) {
-  pushq(r12);
-  movq(r12, rsp);
-  andq(rsp, -16);     // align stack as required by push_CPU_state and call
-
-  push_CPU_state();   // keeps alignment at 16 bytes
-  lea(c_rarg0, ExternalAddress((address) msg));
-  call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
-  pop_CPU_state();
-
-  movq(rsp, r12);
-  popq(r12);
-}
-
-#ifndef PRODUCT
-extern "C" void findpc(intptr_t x);
-#endif
-
-void MacroAssembler::debug(char* msg, int64_t pc, int64_t regs[]) {
-  // In order to get locks to work, we need to fake a in_VM state
-  if (ShowMessageBoxOnError ) {
-    JavaThread* thread = JavaThread::current();
-    JavaThreadState saved_state = thread->thread_state();
-    thread->set_thread_state(_thread_in_vm);
-#ifndef PRODUCT
-    if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
-      ttyLocker ttyl;
-      BytecodeCounter::print();
-    }
-#endif
-    // To see where a verify_oop failed, get $ebx+40/X for this frame.
-    // XXX correct this offset for amd64
-    // This is the value of eip which points to where verify_oop will return.
-    if (os::message_box(msg, "Execution stopped, print registers?")) {
-      ttyLocker ttyl;
-      tty->print_cr("rip = 0x%016lx", pc);
-#ifndef PRODUCT
-      tty->cr();
-      findpc(pc);
-      tty->cr();
-#endif
-      tty->print_cr("rax = 0x%016lx", regs[15]);
-      tty->print_cr("rbx = 0x%016lx", regs[12]);
-      tty->print_cr("rcx = 0x%016lx", regs[14]);
-      tty->print_cr("rdx = 0x%016lx", regs[13]);
-      tty->print_cr("rdi = 0x%016lx", regs[8]);
-      tty->print_cr("rsi = 0x%016lx", regs[9]);
-      tty->print_cr("rbp = 0x%016lx", regs[10]);
-      tty->print_cr("rsp = 0x%016lx", regs[11]);
-      tty->print_cr("r8  = 0x%016lx", regs[7]);
-      tty->print_cr("r9  = 0x%016lx", regs[6]);
-      tty->print_cr("r10 = 0x%016lx", regs[5]);
-      tty->print_cr("r11 = 0x%016lx", regs[4]);
-      tty->print_cr("r12 = 0x%016lx", regs[3]);
-      tty->print_cr("r13 = 0x%016lx", regs[2]);
-      tty->print_cr("r14 = 0x%016lx", regs[1]);
-      tty->print_cr("r15 = 0x%016lx", regs[0]);
-      BREAKPOINT;
-    }
-    ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
-  } else {
-    ttyLocker ttyl;
-    ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
-                    msg);
-  }
-}
-
-void MacroAssembler::os_breakpoint() {
-  // instead of directly emitting a breakpoint, call os:breakpoint for
-  // better debugability
-  // This shouldn't need alignment, it's an empty function
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-// Write serialization page so VM thread can do a pseudo remote membar.
-// We use the current thread pointer to calculate a thread specific
-// offset to write to within the page. This minimizes bus traffic
-// due to cache line collision.
-void MacroAssembler::serialize_memory(Register thread,
-                                      Register tmp) {
-
-  movl(tmp, thread);
-  shrl(tmp, os::get_serialize_page_shift_count());
-  andl(tmp, (os::vm_page_size() - sizeof(int)));
-
-  Address index(noreg, tmp, Address::times_1);
-  ExternalAddress page(os::get_memory_serialize_page());
-
-  movptr(ArrayAddress(page, index), tmp);
-}
-
-void MacroAssembler::verify_tlab() {
-#ifdef ASSERT
-  if (UseTLAB) {
-    Label next, ok;
-    Register t1 = rsi;
-
-    pushq(t1);
-
-    movq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
-    cmpq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
-    jcc(Assembler::aboveEqual, next);
-    stop("assert(top >= start)");
-    should_not_reach_here();
-
-    bind(next);
-    movq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
-    cmpq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
-    jcc(Assembler::aboveEqual, ok);
-    stop("assert(top <= end)");
-    should_not_reach_here();
-
-    bind(ok);
-
-    popq(t1);
-  }
-#endif
-}
-
-// Defines obj, preserves var_size_in_bytes
-void MacroAssembler::eden_allocate(Register obj,
-                                   Register var_size_in_bytes,
-                                   int con_size_in_bytes,
-                                   Register t1,
-                                   Label& slow_case) {
-  assert(obj == rax, "obj must be in rax for cmpxchg");
-  assert_different_registers(obj, var_size_in_bytes, t1);
-  Register end = t1;
-  Label retry;
-  bind(retry);
-  ExternalAddress heap_top((address) Universe::heap()->top_addr());
-  movptr(obj, heap_top);
-  if (var_size_in_bytes == noreg) {
-    leaq(end, Address(obj, con_size_in_bytes));
-  } else {
-    leaq(end, Address(obj, var_size_in_bytes, Address::times_1));
-  }
-  // if end < obj then we wrapped around => object too long => slow case
-  cmpq(end, obj);
-  jcc(Assembler::below, slow_case);
-  cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
-
-  jcc(Assembler::above, slow_case);
-  // Compare obj with the top addr, and if still equal, store the new
-  // top addr in end at the address of the top addr pointer. Sets ZF
-  // if was equal, and clears it otherwise. Use lock prefix for
-  // atomicity on MPs.
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchgptr(end, heap_top);
-  // if someone beat us on the allocation, try again, otherwise continue
-  jcc(Assembler::notEqual, retry);
-}
-
-// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
-void MacroAssembler::tlab_allocate(Register obj,
-                                   Register var_size_in_bytes,
-                                   int con_size_in_bytes,
-                                   Register t1,
-                                   Register t2,
-                                   Label& slow_case) {
-  assert_different_registers(obj, t1, t2);
-  assert_different_registers(obj, var_size_in_bytes, t1);
-  Register end = t2;
-
-  verify_tlab();
-
-  movq(obj, Address(r15_thread, JavaThread::tlab_top_offset()));
-  if (var_size_in_bytes == noreg) {
-    leaq(end, Address(obj, con_size_in_bytes));
-  } else {
-    leaq(end, Address(obj, var_size_in_bytes, Address::times_1));
-  }
-  cmpq(end, Address(r15_thread, JavaThread::tlab_end_offset()));
-  jcc(Assembler::above, slow_case);
-
-  // update the tlab top pointer
-  movq(Address(r15_thread, JavaThread::tlab_top_offset()), end);
-
-  // recover var_size_in_bytes if necessary
-  if (var_size_in_bytes == end) {
-    subq(var_size_in_bytes, obj);
-  }
-  verify_tlab();
-}
-
-// Preserves rbx and rdx.
-void MacroAssembler::tlab_refill(Label& retry,
-                                 Label& try_eden,
-                                 Label& slow_case) {
-  Register top = rax;
-  Register t1 = rcx;
-  Register t2 = rsi;
-  Register t3 = r10;
-  Register thread_reg = r15_thread;
-  assert_different_registers(top, thread_reg, t1, t2, t3,
-                             /* preserve: */ rbx, rdx);
-  Label do_refill, discard_tlab;
-
-  if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
-    // No allocation in the shared eden.
-    jmp(slow_case);
-  }
-
-  movq(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
-  movq(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
-
-  // calculate amount of free space
-  subq(t1, top);
-  shrq(t1, LogHeapWordSize);
-
-  // Retain tlab and allocate object in shared space if
-  // the amount free in the tlab is too large to discard.
-  cmpq(t1, Address(thread_reg, // size_t
-                   in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
-  jcc(Assembler::lessEqual, discard_tlab);
-
-  // Retain
-  mov64(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
-  addq(Address(thread_reg,  // size_t
-               in_bytes(JavaThread::tlab_refill_waste_limit_offset())),
-       t2);
-  if (TLABStats) {
-    // increment number of slow_allocations
-    addl(Address(thread_reg, // unsigned int
-                 in_bytes(JavaThread::tlab_slow_allocations_offset())),
-         1);
-  }
-  jmp(try_eden);
-
-  bind(discard_tlab);
-  if (TLABStats) {
-    // increment number of refills
-    addl(Address(thread_reg, // unsigned int
-                 in_bytes(JavaThread::tlab_number_of_refills_offset())),
-         1);
-    // accumulate wastage -- t1 is amount free in tlab
-    addl(Address(thread_reg, // unsigned int
-                 in_bytes(JavaThread::tlab_fast_refill_waste_offset())),
-         t1);
-  }
-
-  // if tlab is currently allocated (top or end != null) then
-  // fill [top, end + alignment_reserve) with array object
-  testq(top, top);
-  jcc(Assembler::zero, do_refill);
-
-  // set up the mark word
-  mov64(t3, (int64_t) markOopDesc::prototype()->copy_set_hash(0x2));
-  movq(Address(top, oopDesc::mark_offset_in_bytes()), t3);
-  // set the length to the remaining space
-  subq(t1, typeArrayOopDesc::header_size(T_INT));
-  addq(t1, (int)ThreadLocalAllocBuffer::alignment_reserve());
-  shlq(t1, log2_intptr(HeapWordSize / sizeof(jint)));
-  movq(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
-  // set klass to intArrayKlass
-  movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
-  // store klass last.  concurrent gcs assumes klass length is valid if
-  // klass field is not null.
-  store_klass(top, t1);
-
-  // refill the tlab with an eden allocation
-  bind(do_refill);
-  movq(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
-  shlq(t1, LogHeapWordSize);
-  // add object_size ??
-  eden_allocate(top, t1, 0, t2, slow_case);
-
-  // Check that t1 was preserved in eden_allocate.
-#ifdef ASSERT
-  if (UseTLAB) {
-    Label ok;
-    Register tsize = rsi;
-    assert_different_registers(tsize, thread_reg, t1);
-    pushq(tsize);
-    movq(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
-    shlq(tsize, LogHeapWordSize);
-    cmpq(t1, tsize);
-    jcc(Assembler::equal, ok);
-    stop("assert(t1 != tlab size)");
-    should_not_reach_here();
-
-    bind(ok);
-    popq(tsize);
-  }
-#endif
-  movq(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
-  movq(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
-  addq(top, t1);
-  subq(top, (int)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
-  movq(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
-  verify_tlab();
-  jmp(retry);
-}
-
-
-int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
-                                         bool swap_reg_contains_mark,
-                                         Label& done, Label* slow_case,
-                                         BiasedLockingCounters* counters) {
-  assert(UseBiasedLocking, "why call this otherwise?");
-  assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
-  assert(tmp_reg != noreg, "tmp_reg must be supplied");
-  assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
-  assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
-  Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
-  Address saved_mark_addr(lock_reg, 0);
-
-  if (PrintBiasedLockingStatistics && counters == NULL)
-    counters = BiasedLocking::counters();
-
-  // Biased locking
-  // See whether the lock is currently biased toward our thread and
-  // whether the epoch is still valid
-  // Note that the runtime guarantees sufficient alignment of JavaThread
-  // pointers to allow age to be placed into low bits
-  // First check to see whether biasing is even enabled for this object
-  Label cas_label;
-  int null_check_offset = -1;
-  if (!swap_reg_contains_mark) {
-    null_check_offset = offset();
-    movq(swap_reg, mark_addr);
-  }
-  movq(tmp_reg, swap_reg);
-  andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
-  cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
-  jcc(Assembler::notEqual, cas_label);
-  // The bias pattern is present in the object's header. Need to check
-  // whether the bias owner and the epoch are both still current.
-  load_prototype_header(tmp_reg, obj_reg);
-  orq(tmp_reg, r15_thread);
-  xorq(tmp_reg, swap_reg);
-  andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
-  }
-  jcc(Assembler::equal, done);
-
-  Label try_revoke_bias;
-  Label try_rebias;
-
-  // At this point we know that the header has the bias pattern and
-  // that we are not the bias owner in the current epoch. We need to
-  // figure out more details about the state of the header in order to
-  // know what operations can be legally performed on the object's
-  // header.
-
-  // If the low three bits in the xor result aren't clear, that means
-  // the prototype header is no longer biased and we have to revoke
-  // the bias on this object.
-  testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
-  jcc(Assembler::notZero, try_revoke_bias);
-
-  // Biasing is still enabled for this data type. See whether the
-  // epoch of the current bias is still valid, meaning that the epoch
-  // bits of the mark word are equal to the epoch bits of the
-  // prototype header. (Note that the prototype header's epoch bits
-  // only change at a safepoint.) If not, attempt to rebias the object
-  // toward the current thread. Note that we must be absolutely sure
-  // that the current epoch is invalid in order to do this because
-  // otherwise the manipulations it performs on the mark word are
-  // illegal.
-  testq(tmp_reg, markOopDesc::epoch_mask_in_place);
-  jcc(Assembler::notZero, try_rebias);
-
-  // The epoch of the current bias is still valid but we know nothing
-  // about the owner; it might be set or it might be clear. Try to
-  // acquire the bias of the object using an atomic operation. If this
-  // fails we will go in to the runtime to revoke the object's bias.
-  // Note that we first construct the presumed unbiased header so we
-  // don't accidentally blow away another thread's valid bias.
-  andq(swap_reg,
-       markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
-  movq(tmp_reg, swap_reg);
-  orq(tmp_reg, r15_thread);
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchgq(tmp_reg, Address(obj_reg, 0));
-  // If the biasing toward our thread failed, this means that
-  // another thread succeeded in biasing it toward itself and we
-  // need to revoke that bias. The revocation will occur in the
-  // interpreter runtime in the slow case.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
-  }
-  if (slow_case != NULL) {
-    jcc(Assembler::notZero, *slow_case);
-  }
-  jmp(done);
-
-  bind(try_rebias);
-  // At this point we know the epoch has expired, meaning that the
-  // current "bias owner", if any, is actually invalid. Under these
-  // circumstances _only_, we are allowed to use the current header's
-  // value as the comparison value when doing the cas to acquire the
-  // bias in the current epoch. In other words, we allow transfer of
-  // the bias from one thread to another directly in this situation.
-  //
-  // FIXME: due to a lack of registers we currently blow away the age
-  // bits in this situation. Should attempt to preserve them.
-  load_prototype_header(tmp_reg, obj_reg);
-  orq(tmp_reg, r15_thread);
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchgq(tmp_reg, Address(obj_reg, 0));
-  // If the biasing toward our thread failed, then another thread
-  // succeeded in biasing it toward itself and we need to revoke that
-  // bias. The revocation will occur in the runtime in the slow case.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
-  }
-  if (slow_case != NULL) {
-    jcc(Assembler::notZero, *slow_case);
-  }
-  jmp(done);
-
-  bind(try_revoke_bias);
-  // The prototype mark in the klass doesn't have the bias bit set any
-  // more, indicating that objects of this data type are not supposed
-  // to be biased any more. We are going to try to reset the mark of
-  // this object to the prototype value and fall through to the
-  // CAS-based locking scheme. Note that if our CAS fails, it means
-  // that another thread raced us for the privilege of revoking the
-  // bias of this particular object, so it's okay to continue in the
-  // normal locking code.
-  //
-  // FIXME: due to a lack of registers we currently blow away the age
-  // bits in this situation. Should attempt to preserve them.
-  load_prototype_header(tmp_reg, obj_reg);
-  if (os::is_MP()) {
-    lock();
-  }
-  cmpxchgq(tmp_reg, Address(obj_reg, 0));
-  // Fall through to the normal CAS-based lock, because no matter what
-  // the result of the above CAS, some thread must have succeeded in
-  // removing the bias bit from the object's header.
-  if (counters != NULL) {
-    cond_inc32(Assembler::zero,
-               ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
-  }
-
-  bind(cas_label);
-
-  return null_check_offset;
-}
-
-
-void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
-  assert(UseBiasedLocking, "why call this otherwise?");
-
-  // Check for biased locking unlock case, which is a no-op
-  // Note: we do not have to check the thread ID for two reasons.
-  // First, the interpreter checks for IllegalMonitorStateException at
-  // a higher level. Second, if the bias was revoked while we held the
-  // lock, the object could not be rebiased toward another thread, so
-  // the bias bit would be clear.
-  movq(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
-  andq(temp_reg, markOopDesc::biased_lock_mask_in_place);
-  cmpq(temp_reg, markOopDesc::biased_lock_pattern);
-  jcc(Assembler::equal, done);
-}
-
-
-void MacroAssembler::load_klass(Register dst, Register src) {
-  if (UseCompressedOops) {
-    movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
-    decode_heap_oop_not_null(dst);
-  } else {
-    movq(dst, Address(src, oopDesc::klass_offset_in_bytes()));
-  }
-}
-
-void MacroAssembler::load_prototype_header(Register dst, Register src) {
-  if (UseCompressedOops) {
-    movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
-    movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-  } else {
-    movq(dst, Address(src, oopDesc::klass_offset_in_bytes()));
-    movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-  }
-}
-
-void MacroAssembler::store_klass(Register dst, Register src) {
-  if (UseCompressedOops) {
-    encode_heap_oop_not_null(src);
-    movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
-  } else {
-    movq(Address(dst, oopDesc::klass_offset_in_bytes()), src);
-  }
-}
-
-void MacroAssembler::store_klass_gap(Register dst, Register src) {
-  if (UseCompressedOops) {
-    // Store to klass gap in destination
-    movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
-  }
-}
-
-void MacroAssembler::load_heap_oop(Register dst, Address src) {
-  if (UseCompressedOops) {
-    movl(dst, src);
-    decode_heap_oop(dst);
-  } else {
-    movq(dst, src);
-  }
-}
-
-void MacroAssembler::store_heap_oop(Address dst, Register src) {
-  if (UseCompressedOops) {
-    assert(!dst.uses(src), "not enough registers");
-    encode_heap_oop(src);
-    movl(dst, src);
-  } else {
-    movq(dst, src);
-  }
-}
-
-// Algorithm must match oop.inline.hpp encode_heap_oop.
-void MacroAssembler::encode_heap_oop(Register r) {
-  assert (UseCompressedOops, "should be compressed");
-#ifdef ASSERT
-  if (CheckCompressedOops) {
-    Label ok;
-    pushq(rscratch1); // cmpptr trashes rscratch1
-    cmpptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
-    jcc(Assembler::equal, ok);
-    stop("MacroAssembler::encode_heap_oop: heap base corrupted?");
-    bind(ok);
-    popq(rscratch1);
-  }
-#endif
-  verify_oop(r, "broken oop in encode_heap_oop");
-  testq(r, r);
-  cmovq(Assembler::equal, r, r12_heapbase);
-  subq(r, r12_heapbase);
-  shrq(r, LogMinObjAlignmentInBytes);
-}
-
-void MacroAssembler::encode_heap_oop_not_null(Register r) {
-  assert (UseCompressedOops, "should be compressed");
-#ifdef ASSERT
-  if (CheckCompressedOops) {
-    Label ok;
-    testq(r, r);
-    jcc(Assembler::notEqual, ok);
-    stop("null oop passed to encode_heap_oop_not_null");
-    bind(ok);
-  }
-#endif
-  verify_oop(r, "broken oop in encode_heap_oop_not_null");
-  subq(r, r12_heapbase);
-  shrq(r, LogMinObjAlignmentInBytes);
-}
-
-void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
-  assert (UseCompressedOops, "should be compressed");
-#ifdef ASSERT
-  if (CheckCompressedOops) {
-    Label ok;
-    testq(src, src);
-    jcc(Assembler::notEqual, ok);
-    stop("null oop passed to encode_heap_oop_not_null2");
-    bind(ok);
-  }
-#endif
-  verify_oop(src, "broken oop in encode_heap_oop_not_null2");
-  if (dst != src) {
-    movq(dst, src);
-  }
-  subq(dst, r12_heapbase);
-  shrq(dst, LogMinObjAlignmentInBytes);
-}
-
-void  MacroAssembler::decode_heap_oop(Register r) {
-  assert (UseCompressedOops, "should be compressed");
-#ifdef ASSERT
-  if (CheckCompressedOops) {
-    Label ok;
-    pushq(rscratch1);
-    cmpptr(r12_heapbase,
-           ExternalAddress((address)Universe::heap_base_addr()));
-    jcc(Assembler::equal, ok);
-    stop("MacroAssembler::decode_heap_oop: heap base corrupted?");
-    bind(ok);
-    popq(rscratch1);
-  }
-#endif
-
-  Label done;
-  shlq(r, LogMinObjAlignmentInBytes);
-  jccb(Assembler::equal, done);
-  addq(r, r12_heapbase);
-#if 0
-   // alternate decoding probably a wash.
-   testq(r, r);
-   jccb(Assembler::equal, done);
-   leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
-#endif
-  bind(done);
-  verify_oop(r, "broken oop in decode_heap_oop");
-}
-
-void  MacroAssembler::decode_heap_oop_not_null(Register r) {
-  assert (UseCompressedOops, "should only be used for compressed headers");
-  // Cannot assert, unverified entry point counts instructions (see .ad file)
-  // vtableStubs also counts instructions in pd_code_size_limit.
-  // Also do not verify_oop as this is called by verify_oop.
-  assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong");
-  leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
-}
-
-void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
-  assert (UseCompressedOops, "should only be used for compressed headers");
-  // Cannot assert, unverified entry point counts instructions (see .ad file)
-  // vtableStubs also counts instructions in pd_code_size_limit.
-  // Also do not verify_oop as this is called by verify_oop.
-  assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong");
-  leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
-}
-
-void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
-  assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
-  int oop_index = oop_recorder()->find_index(obj);
-  RelocationHolder rspec = oop_Relocation::spec(oop_index);
-
-  // movl dst,obj
-  InstructionMark im(this);
-  int encode = prefix_and_encode(dst->encoding());
-  emit_byte(0xB8 | encode);
-  emit_data(oop_index, rspec, narrow_oop_operand);
-}
-
-
-Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
-  switch (cond) {
-    // Note some conditions are synonyms for others
-    case Assembler::zero:         return Assembler::notZero;
-    case Assembler::notZero:      return Assembler::zero;
-    case Assembler::less:         return Assembler::greaterEqual;
-    case Assembler::lessEqual:    return Assembler::greater;
-    case Assembler::greater:      return Assembler::lessEqual;
-    case Assembler::greaterEqual: return Assembler::less;
-    case Assembler::below:        return Assembler::aboveEqual;
-    case Assembler::belowEqual:   return Assembler::above;
-    case Assembler::above:        return Assembler::belowEqual;
-    case Assembler::aboveEqual:   return Assembler::below;
-    case Assembler::overflow:     return Assembler::noOverflow;
-    case Assembler::noOverflow:   return Assembler::overflow;
-    case Assembler::negative:     return Assembler::positive;
-    case Assembler::positive:     return Assembler::negative;
-    case Assembler::parity:       return Assembler::noParity;
-    case Assembler::noParity:     return Assembler::parity;
-  }
-  ShouldNotReachHere(); return Assembler::overflow;
-}
-
-
-void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
-  Condition negated_cond = negate_condition(cond);
-  Label L;
-  jcc(negated_cond, L);
-  atomic_incl(counter_addr);
-  bind(L);
-}
-
-void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
-  pushfq();
-  if (os::is_MP())
-    lock();
-  incrementl(counter_addr);
-  popfq();
-}
-
-SkipIfEqual::SkipIfEqual(
-    MacroAssembler* masm, const bool* flag_addr, bool value) {
-  _masm = masm;
-  _masm->cmp8(ExternalAddress((address)flag_addr), value);
-  _masm->jcc(Assembler::equal, _label);
-}
-
-SkipIfEqual::~SkipIfEqual() {
-  _masm->bind(_label);
-}
-
-void MacroAssembler::bang_stack_size(Register size, Register tmp) {
-  movq(tmp, rsp);
-  // Bang stack for total size given plus shadow page size.
-  // Bang one page at a time because large size can bang beyond yellow and
-  // red zones.
-  Label loop;
-  bind(loop);
-  movl(Address(tmp, (-os::vm_page_size())), size );
-  subq(tmp, os::vm_page_size());
-  subl(size, os::vm_page_size());
-  jcc(Assembler::greater, loop);
-
-  // Bang down shadow pages too.
-  // The -1 because we already subtracted 1 page.
-  for (int i = 0; i< StackShadowPages-1; i++) {
-    movq(Address(tmp, (-i*os::vm_page_size())), size );
-  }
-}
-
-void MacroAssembler::reinit_heapbase() {
-  if (UseCompressedOops) {
-    movptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
-  }
-}
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1477 +0,0 @@
-/*
- * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-class BiasedLockingCounters;
-
-// Contains all the definitions needed for amd64 assembly code generation.
-
-#ifdef _LP64
-// Calling convention
-class Argument VALUE_OBJ_CLASS_SPEC {
- public:
-  enum {
-#ifdef _WIN64
-    n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
-    n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
-#else
-    n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
-    n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
-#endif  // _WIN64
-    n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
-    n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
-  };
-};
-
-
-// Symbolically name the register arguments used by the c calling convention.
-// Windows is different from linux/solaris. So much for standards...
-
-#ifdef _WIN64
-
-REGISTER_DECLARATION(Register, c_rarg0, rcx);
-REGISTER_DECLARATION(Register, c_rarg1, rdx);
-REGISTER_DECLARATION(Register, c_rarg2, r8);
-REGISTER_DECLARATION(Register, c_rarg3, r9);
-
-REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
-
-#else
-
-REGISTER_DECLARATION(Register, c_rarg0, rdi);
-REGISTER_DECLARATION(Register, c_rarg1, rsi);
-REGISTER_DECLARATION(Register, c_rarg2, rdx);
-REGISTER_DECLARATION(Register, c_rarg3, rcx);
-REGISTER_DECLARATION(Register, c_rarg4, r8);
-REGISTER_DECLARATION(Register, c_rarg5, r9);
-
-REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
-REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
-REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
-REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
-REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
-
-#endif  // _WIN64
-
-// Symbolically name the register arguments used by the Java calling convention.
-// We have control over the convention for java so we can do what we please.
-// What pleases us is to offset the java calling convention so that when
-// we call a suitable jni method the arguments are lined up and we don't
-// have to do little shuffling. A suitable jni method is non-static and a
-// small number of arguments (two fewer args on windows)
-//
-//        |-------------------------------------------------------|
-//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
-//        |-------------------------------------------------------|
-//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
-//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
-//        |-------------------------------------------------------|
-//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
-//        |-------------------------------------------------------|
-
-REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
-REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
-REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
-// Windows runs out of register args here
-#ifdef _WIN64
-REGISTER_DECLARATION(Register, j_rarg3, rdi);
-REGISTER_DECLARATION(Register, j_rarg4, rsi);
-#else
-REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
-REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
-#endif // _WIN64
-REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
-
-REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
-REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
-REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
-REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
-REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
-
-REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
-REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
-
-REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
-REGISTER_DECLARATION(Register, r15_thread, r15);   // callee-saved
-
-#endif // _LP64
-
-// Address is an abstraction used to represent a memory location
-// using any of the amd64 addressing modes with one object.
-//
-// Note: A register location is represented via a Register, not
-//       via an address for efficiency & simplicity reasons.
-
-class ArrayAddress;
-
-class Address VALUE_OBJ_CLASS_SPEC {
- public:
-  enum ScaleFactor {
-    no_scale = -1,
-    times_1  =  0,
-    times_2  =  1,
-    times_4  =  2,
-    times_8  =  3
-  };
-
- private:
-  Register         _base;
-  Register         _index;
-  ScaleFactor      _scale;
-  int              _disp;
-  RelocationHolder _rspec;
-
-  // Easily misused constructors make them private
-  Address(int disp, address loc, relocInfo::relocType rtype);
-  Address(int disp, address loc, RelocationHolder spec);
-
- public:
-  // creation
-  Address()
-    : _base(noreg),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(0) {
-  }
-
-  // No default displacement otherwise Register can be implicitly
-  // converted to 0(Register) which is quite a different animal.
-
-  Address(Register base, int disp)
-    : _base(base),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(disp) {
-  }
-
-  Address(Register base, Register index, ScaleFactor scale, int disp = 0)
-    : _base (base),
-      _index(index),
-      _scale(scale),
-      _disp (disp) {
-    assert(!index->is_valid() == (scale == Address::no_scale),
-           "inconsistent address");
-  }
-
-  // The following two overloads are used in connection with the
-  // ByteSize type (see sizes.hpp).  They simplify the use of
-  // ByteSize'd arguments in assembly code. Note that their equivalent
-  // for the optimized build are the member functions with int disp
-  // argument since ByteSize is mapped to an int type in that case.
-  //
-  // Note: DO NOT introduce similar overloaded functions for WordSize
-  // arguments as in the optimized mode, both ByteSize and WordSize
-  // are mapped to the same type and thus the compiler cannot make a
-  // distinction anymore (=> compiler errors).
-
-#ifdef ASSERT
-  Address(Register base, ByteSize disp)
-    : _base(base),
-      _index(noreg),
-      _scale(no_scale),
-      _disp(in_bytes(disp)) {
-  }
-
-  Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
-    : _base(base),
-      _index(index),
-      _scale(scale),
-      _disp(in_bytes(disp)) {
-    assert(!index->is_valid() == (scale == Address::no_scale),
-           "inconsistent address");
-  }
-#endif // ASSERT
-
-  // accessors
-  bool uses(Register reg) const {
-    return _base == reg || _index == reg;
-  }
-
-  // Convert the raw encoding form into the form expected by the constructor for
-  // Address.  An index of 4 (rsp) corresponds to having no index, so convert
-  // that to noreg for the Address constructor.
-  static Address make_raw(int base, int index, int scale, int disp);
-
-  static Address make_array(ArrayAddress);
-
- private:
-  bool base_needs_rex() const {
-    return _base != noreg && _base->encoding() >= 8;
-  }
-
-  bool index_needs_rex() const {
-    return _index != noreg &&_index->encoding() >= 8;
-  }
-
-  relocInfo::relocType reloc() const { return _rspec.type(); }
-
-  friend class Assembler;
-  friend class MacroAssembler;
-  friend class LIR_Assembler; // base/index/scale/disp
-};
-
-//
-// AddressLiteral has been split out from Address because operands of this type
-// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
-// the few instructions that need to deal with address literals are unique and the
-// MacroAssembler does not have to implement every instruction in the Assembler
-// in order to search for address literals that may need special handling depending
-// on the instruction and the platform. As small step on the way to merging i486/amd64
-// directories.
-//
-class AddressLiteral VALUE_OBJ_CLASS_SPEC {
-  friend class ArrayAddress;
-  RelocationHolder _rspec;
-  // Typically we use AddressLiterals we want to use their rval
-  // However in some situations we want the lval (effect address) of the item.
-  // We provide a special factory for making those lvals.
-  bool _is_lval;
-
-  // If the target is far we'll need to load the ea of this to
-  // a register to reach it. Otherwise if near we can do rip
-  // relative addressing.
-
-  address          _target;
-
- protected:
-  // creation
-  AddressLiteral()
-    : _is_lval(false),
-      _target(NULL)
-  {}
-
-  public:
-
-
-  AddressLiteral(address target, relocInfo::relocType rtype);
-
-  AddressLiteral(address target, RelocationHolder const& rspec)
-    : _rspec(rspec),
-      _is_lval(false),
-      _target(target)
-  {}
-
-  AddressLiteral addr() {
-    AddressLiteral ret = *this;
-    ret._is_lval = true;
-    return ret;
-  }
-
-
- private:
-
-  address target() { return _target; }
-  bool is_lval() { return _is_lval; }
-
-  relocInfo::relocType reloc() const { return _rspec.type(); }
-  const RelocationHolder& rspec() const { return _rspec; }
-
-  friend class Assembler;
-  friend class MacroAssembler;
-  friend class Address;
-  friend class LIR_Assembler;
-};
-
-// Convience classes
-class RuntimeAddress: public AddressLiteral {
-
-  public:
-
-  RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
-
-};
-
-class OopAddress: public AddressLiteral {
-
-  public:
-
-  OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
-
-};
-
-class ExternalAddress: public AddressLiteral {
-
-  public:
-
-  ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
-
-};
-
-class InternalAddress: public AddressLiteral {
-
-  public:
-
-  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
-
-};
-
-// x86 can do array addressing as a single operation since disp can be an absolute
-// address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class
-// that expresses the concept but does extra magic on amd64 to get the final result
-
-class ArrayAddress VALUE_OBJ_CLASS_SPEC {
-  private:
-
-  AddressLiteral _base;
-  Address        _index;
-
-  public:
-
-  ArrayAddress() {};
-  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
-  AddressLiteral base() { return _base; }
-  Address index() { return _index; }
-
-};
-
-// The amd64 Assembler: Pure assembler doing NO optimizations on
-// the instruction level (e.g. mov rax, 0 is not translated into xor
-// rax, rax!); i.e., what you write is what you get. The Assembler is
-// generating code into a CodeBuffer.
-
-const int FPUStateSizeInWords = 512 / wordSize;
-
-class Assembler : public AbstractAssembler  {
-  friend class AbstractAssembler; // for the non-virtual hack
-  friend class StubGenerator;
-
-
- protected:
-#ifdef ASSERT
-  void check_relocation(RelocationHolder const& rspec, int format);
-#endif
-
-  inline void emit_long64(jlong x);
-
-  void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);
-  void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);
-  void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
-  void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
-
-  // Helper functions for groups of instructions
-  void emit_arith_b(int op1, int op2, Register dst, int imm8);
-
-  void emit_arith(int op1, int op2, Register dst, int imm32);
-  // only x86??
-  void emit_arith(int op1, int op2, Register dst, jobject obj);
-  void emit_arith(int op1, int op2, Register dst, Register src);
-
-  void emit_operand(Register reg,
-                    Register base, Register index, Address::ScaleFactor scale,
-                    int disp,
-                    RelocationHolder const& rspec,
-                    int rip_relative_correction = 0);
-  void emit_operand(Register reg, Address adr,
-                    int rip_relative_correction = 0);
-  void emit_operand(XMMRegister reg,
-                    Register base, Register index, Address::ScaleFactor scale,
-                    int disp,
-                    RelocationHolder const& rspec,
-                    int rip_relative_correction = 0);
-  void emit_operand(XMMRegister reg, Address adr,
-                    int rip_relative_correction = 0);
-
-  // Immediate-to-memory forms
-  void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
-
-  void emit_farith(int b1, int b2, int i);
-
-  bool reachable(AddressLiteral adr);
-
-  // These are all easily abused and hence protected
-
-  // Make these disappear in 64bit mode since they would never be correct
-#ifndef _LP64
-  void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
-  void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
-
-  void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
-  void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
-
-  void push_literal32(int32_t imm32, RelocationHolder const& rspec);
-#endif // _LP64
-
-
-  void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);
-
-  // These are unique in that we are ensured by the caller that the 32bit
-  // relative in these instructions will always be able to reach the potentially
-  // 64bit address described by entry. Since they can take a 64bit address they
-  // don't have the 32 suffix like the other instructions in this class.
-  void jmp_literal(address entry, RelocationHolder const& rspec);
-  void call_literal(address entry, RelocationHolder const& rspec);
-
- public:
-  enum Condition { // The amd64 condition codes used for conditional jumps/moves.
-    zero          = 0x4,
-    notZero       = 0x5,
-    equal         = 0x4,
-    notEqual      = 0x5,
-    less          = 0xc,
-    lessEqual     = 0xe,
-    greater       = 0xf,
-    greaterEqual  = 0xd,
-    below         = 0x2,
-    belowEqual    = 0x6,
-    above         = 0x7,
-    aboveEqual    = 0x3,
-    overflow      = 0x0,
-    noOverflow    = 0x1,
-    carrySet      = 0x2,
-    carryClear    = 0x3,
-    negative      = 0x8,
-    positive      = 0x9,
-    parity        = 0xa,
-    noParity      = 0xb
-  };
-
-  enum Prefix {
-    // segment overrides
-    // XXX remove segment prefixes
-    CS_segment = 0x2e,
-    SS_segment = 0x36,
-    DS_segment = 0x3e,
-    ES_segment = 0x26,
-    FS_segment = 0x64,
-    GS_segment = 0x65,
-
-    REX        = 0x40,
-
-    REX_B      = 0x41,
-    REX_X      = 0x42,
-    REX_XB     = 0x43,
-    REX_R      = 0x44,
-    REX_RB     = 0x45,
-    REX_RX     = 0x46,
-    REX_RXB    = 0x47,
-
-    REX_W      = 0x48,
-
-    REX_WB     = 0x49,
-    REX_WX     = 0x4A,
-    REX_WXB    = 0x4B,
-    REX_WR     = 0x4C,
-    REX_WRB    = 0x4D,
-    REX_WRX    = 0x4E,
-    REX_WRXB   = 0x4F
-  };
-
-  enum WhichOperand {
-    // input to locate_operand, and format code for relocations
-    imm64_operand  = 0,          // embedded 64-bit immediate operand
-    disp32_operand = 1,          // embedded 32-bit displacement
-    call32_operand = 2,          // embedded 32-bit self-relative displacement
-#ifndef AMD64
-    _WhichOperand_limit = 3
-#else
-     narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
-    _WhichOperand_limit = 4
-#endif
-  };
-
-  public:
-
-  // Creation
-  Assembler(CodeBuffer* code)
-    : AbstractAssembler(code) {
-  }
-
-  // Decoding
-  static address locate_operand(address inst, WhichOperand which);
-  static address locate_next_instruction(address inst);
-
-  // Utilities
-
- static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) )  <= x   &&   x  <  ( CONST64(1) << (nbits-1) ); }
- static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }
-
-
-  // Stack
-  void pushaq();
-  void popaq();
-
-  void pushfq();
-  void popfq();
-
-  void pushq(int imm32);
-
-  void pushq(Register src);
-  void pushq(Address src);
-
-  void popq(Register dst);
-  void popq(Address dst);
-
-  // Instruction prefixes
-  void prefix(Prefix p);
-
-  int prefix_and_encode(int reg_enc, bool byteinst = false);
-  int prefixq_and_encode(int reg_enc);
-
-  int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
-  int prefixq_and_encode(int dst_enc, int src_enc);
-
-  void prefix(Register reg);
-  void prefix(Address adr);
-  void prefixq(Address adr);
-
-  void prefix(Address adr, Register reg,  bool byteinst = false);
-  void prefixq(Address adr, Register reg);
-
-  void prefix(Address adr, XMMRegister reg);
-
-  // Moves
-  void movb(Register dst, Address src);
-  void movb(Address dst, int imm8);
-  void movb(Address dst, Register src);
-
-  void movw(Address dst, int imm16);
-  void movw(Register dst, Address src);
-  void movw(Address dst, Register src);
-
-  void movl(Register dst, int imm32);
-  void movl(Register dst, Register src);
-  void movl(Register dst, Address src);
-  void movl(Address dst, int imm32);
-  void movl(Address dst, Register src);
-
-  void movq(Register dst, Register src);
-  void movq(Register dst, Address src);
-  void movq(Address dst, Register src);
-  // These prevent using movq from converting a zero (like NULL) into Register
-  // by giving the compiler two choices it can't resolve
-  void movq(Address dst, void* dummy);
-  void movq(Register dst, void* dummy);
-
-  void mov64(Register dst, intptr_t imm64);
-  void mov64(Address dst, intptr_t imm64);
-
-  void movsbl(Register dst, Address src);
-  void movsbl(Register dst, Register src);
-  void movswl(Register dst, Address src);
-  void movswl(Register dst, Register src);
-  void movslq(Register dst, Address src);
-  void movslq(Register dst, Register src);
-
-  void movzbl(Register dst, Address src);
-  void movzbl(Register dst, Register src);
-  void movzwl(Register dst, Address src);
-  void movzwl(Register dst, Register src);
-
- protected: // Avoid using the next instructions directly.
-  // New cpus require use of movsd and movss to avoid partial register stall
-  // when loading from memory. But for old Opteron use movlpd instead of movsd.
-  // The selection is done in MacroAssembler::movdbl() and movflt().
-  void movss(XMMRegister dst, XMMRegister src);
-  void movss(XMMRegister dst, Address src);
-  void movss(Address dst, XMMRegister src);
-  void movsd(XMMRegister dst, XMMRegister src);
-  void movsd(Address dst, XMMRegister src);
-  void movsd(XMMRegister dst, Address src);
-  void movlpd(XMMRegister dst, Address src);
-  // New cpus require use of movaps and movapd to avoid partial register stall
-  // when moving between registers.
-  void movapd(XMMRegister dst, XMMRegister src);
-  void movaps(XMMRegister dst, XMMRegister src);
- public:
-
-  void movdl(XMMRegister dst, Register src);
-  void movdl(Register dst, XMMRegister src);
-  void movdq(XMMRegister dst, Register src);
-  void movdq(Register dst, XMMRegister src);
-
-  void cmovl(Condition cc, Register dst, Register src);
-  void cmovl(Condition cc, Register dst, Address src);
-  void cmovq(Condition cc, Register dst, Register src);
-  void cmovq(Condition cc, Register dst, Address src);
-
-  // Prefetches
- private:
-  void prefetch_prefix(Address src);
- public:
-  void prefetcht0(Address src);
-  void prefetcht1(Address src);
-  void prefetcht2(Address src);
-  void prefetchnta(Address src);
-  void prefetchw(Address src);
-
-  // Arithmetics
-  void adcl(Register dst, int imm32);
-  void adcl(Register dst, Address src);
-  void adcl(Register dst, Register src);
-  void adcq(Register dst, int imm32);
-  void adcq(Register dst, Address src);
-  void adcq(Register dst, Register src);
-
-  void addl(Address dst, int imm32);
-  void addl(Address dst, Register src);
-  void addl(Register dst, int imm32);
-  void addl(Register dst, Address src);
-  void addl(Register dst, Register src);
-  void addq(Address dst, int imm32);
-  void addq(Address dst, Register src);
-  void addq(Register dst, int imm32);
-  void addq(Register dst, Address src);
-  void addq(Register dst, Register src);
-
-  void andl(Register dst, int imm32);
-  void andl(Register dst, Address src);
-  void andl(Register dst, Register src);
-  void andq(Register dst, int imm32);
-  void andq(Register dst, Address src);
-  void andq(Register dst, Register src);
-
-  void cmpb(Address dst, int imm8);
-  void cmpl(Address dst, int imm32);
-  void cmpl(Register dst, int imm32);
-  void cmpl(Register dst, Register src);
-  void cmpl(Register dst, Address src);
-  void cmpq(Address dst, int imm32);
-  void cmpq(Address dst, Register src);
-  void cmpq(Register dst, int imm32);
-  void cmpq(Register dst, Register src);
-  void cmpq(Register dst, Address src);
-
-  void ucomiss(XMMRegister dst, XMMRegister src);
-  void ucomisd(XMMRegister dst, XMMRegister src);
-
- protected:
-  // Don't use next inc() and dec() methods directly. INC & DEC instructions
-  // could cause a partial flag stall since they don't set CF flag.
-  // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
-  // which call inc() & dec() or add() & sub() in accordance with
-  // the product flag UseIncDec value.
-
-  void decl(Register dst);
-  void decl(Address dst);
-  void decq(Register dst);
-  void decq(Address dst);
-
-  void incl(Register dst);
-  void incl(Address dst);
-  void incq(Register dst);
-  void incq(Address dst);
-
- public:
-  void idivl(Register src);
-  void idivq(Register src);
-  void cdql();
-  void cdqq();
-
-  void imull(Register dst, Register src);
-  void imull(Register dst, Register src, int value);
-  void imulq(Register dst, Register src);
-  void imulq(Register dst, Register src, int value);
-
-  void leal(Register dst, Address src);
-  void leaq(Register dst, Address src);
-
-  void mull(Address src);
-  void mull(Register src);
-
-  void negl(Register dst);
-  void negq(Register dst);
-
-  void notl(Register dst);
-  void notq(Register dst);
-
-  void orl(Address dst, int imm32);
-  void orl(Register dst, int imm32);
-  void orl(Register dst, Address src);
-  void orl(Register dst, Register src);
-  void orq(Address dst, int imm32);
-  void orq(Register dst, int imm32);
-  void orq(Register dst, Address src);
-  void orq(Register dst, Register src);
-
-  void rcll(Register dst, int imm8);
-  void rclq(Register dst, int imm8);
-
-  void sarl(Register dst, int imm8);
-  void sarl(Register dst);
-  void sarq(Register dst, int imm8);
-  void sarq(Register dst);
-
-  void sbbl(Address dst, int imm32);
-  void sbbl(Register dst, int imm32);
-  void sbbl(Register dst, Address src);
-  void sbbl(Register dst, Register src);
-  void sbbq(Address dst, int imm32);
-  void sbbq(Register dst, int imm32);
-  void sbbq(Register dst, Address src);
-  void sbbq(Register dst, Register src);
-
-  void shll(Register dst, int imm8);
-  void shll(Register dst);
-  void shlq(Register dst, int imm8);
-  void shlq(Register dst);
-
-  void shrl(Register dst, int imm8);
-  void shrl(Register dst);
-  void shrq(Register dst, int imm8);
-  void shrq(Register dst);
-
-  void subl(Address dst, int imm32);
-  void subl(Address dst, Register src);
-  void subl(Register dst, int imm32);
-  void subl(Register dst, Address src);
-  void subl(Register dst, Register src);
-  void subq(Address dst, int imm32);
-  void subq(Address dst, Register src);
-  void subq(Register dst, int imm32);
-  void subq(Register dst, Address src);
-  void subq(Register dst, Register src);
-
-  void testb(Register dst, int imm8);
-  void testl(Register dst, int imm32);
-  void testl(Register dst, Register src);
-  void testq(Register dst, int imm32);
-  void testq(Register dst, Register src);
-
-  void xaddl(Address dst, Register src);
-  void xaddq(Address dst, Register src);
-
-  void xorl(Register dst, int imm32);
-  void xorl(Register dst, Address src);
-  void xorl(Register dst, Register src);
-  void xorq(Register dst, int imm32);
-  void xorq(Register dst, Address src);
-  void xorq(Register dst, Register src);
-
-  // Miscellaneous
-  void bswapl(Register reg);
-  void bswapq(Register reg);
-  void lock();
-
-  void xchgl(Register reg, Address adr);
-  void xchgl(Register dst, Register src);
-  void xchgq(Register reg, Address adr);
-  void xchgq(Register dst, Register src);
-
-  void cmpxchgl(Register reg, Address adr);
-  void cmpxchgq(Register reg, Address adr);
-
-  void nop(int i = 1);
-  void addr_nop_4();
-  void addr_nop_5();
-  void addr_nop_7();
-  void addr_nop_8();
-
-  void hlt();
-  void ret(int imm16);
-  void smovl();
-  void rep_movl();
-  void rep_movq();
-  void rep_set();
-  void repne_scanl();
-  void repne_scanq();
-  void setb(Condition cc, Register dst);
-
-  void clflush(Address adr);
-
-  enum Membar_mask_bits {
-    StoreStore = 1 << 3,
-    LoadStore  = 1 << 2,
-    StoreLoad  = 1 << 1,
-    LoadLoad   = 1 << 0
-  };
-
-  // Serializes memory.
-  void membar(Membar_mask_bits order_constraint) {
-    // We only have to handle StoreLoad and LoadLoad
-    if (order_constraint & StoreLoad) {
-      // MFENCE subsumes LFENCE
-      mfence();
-    } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
-         lfence();
-    } */
-  }
-
-  void lfence() {
-    emit_byte(0x0F);
-    emit_byte(0xAE);
-    emit_byte(0xE8);
-  }
-
-  void mfence() {
-    emit_byte(0x0F);
-    emit_byte(0xAE);
-    emit_byte(0xF0);
-  }
-
-  // Identify processor type and features
-  void cpuid() {
-    emit_byte(0x0F);
-    emit_byte(0xA2);
-  }
-
-  void cld() { emit_byte(0xfc);
-  }
-
-  void std() { emit_byte(0xfd);
-  }
-
-
-  // Calls
-
-  void call(Label& L, relocInfo::relocType rtype);
-  void call(Register reg);
-  void call(Address adr);
-
-  // Jumps
-
-  void jmp(Register reg);
-  void jmp(Address adr);
-
-  // Label operations & relative jumps (PPUM Appendix D)
-  // unconditional jump to L
-  void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);
-
-
-  // Unconditional 8-bit offset jump to L.
-  // WARNING: be very careful using this for forward jumps.  If the label is
-  // not bound within an 8-bit offset of this instruction, a run-time error
-  // will occur.
-  void jmpb(Label& L);
-
-  // jcc is the generic conditional branch generator to run- time
-  // routines, jcc is used for branches to labels. jcc takes a branch
-  // opcode (cc) and a label (L) and generates either a backward
-  // branch or a forward branch and links it to the label fixup
-  // chain. Usage:
-  //
-  // Label L;      // unbound label
-  // jcc(cc, L);   // forward branch to unbound label
-  // bind(L);      // bind label to the current pc
-  // jcc(cc, L);   // backward branch to bound label
-  // bind(L);      // illegal: a label may be bound only once
-  //
-  // Note: The same Label can be used for forward and backward branches
-  // but it may be bound only once.
-
-  void jcc(Condition cc, Label& L,
-           relocInfo::relocType rtype = relocInfo::none);
-
-  // Conditional jump to a 8-bit offset to L.
-  // WARNING: be very careful using this for forward jumps.  If the label is
-  // not bound within an 8-bit offset of this instruction, a run-time error
-  // will occur.
-  void jccb(Condition cc, Label& L);
-
-  // Floating-point operations
-
-  void fxsave(Address dst);
-  void fxrstor(Address src);
-  void ldmxcsr(Address src);
-  void stmxcsr(Address dst);
-
-  void addss(XMMRegister dst, XMMRegister src);
-  void addss(XMMRegister dst, Address src);
-  void subss(XMMRegister dst, XMMRegister src);
-  void subss(XMMRegister dst, Address src);
-  void mulss(XMMRegister dst, XMMRegister src);
-  void mulss(XMMRegister dst, Address src);
-  void divss(XMMRegister dst, XMMRegister src);
-  void divss(XMMRegister dst, Address src);
-  void addsd(XMMRegister dst, XMMRegister src);
-  void addsd(XMMRegister dst, Address src);
-  void subsd(XMMRegister dst, XMMRegister src);
-  void subsd(XMMRegister dst, Address src);
-  void mulsd(XMMRegister dst, XMMRegister src);
-  void mulsd(XMMRegister dst, Address src);
-  void divsd(XMMRegister dst, XMMRegister src);
-  void divsd(XMMRegister dst, Address src);
-
-  // We only need the double form
-  void sqrtsd(XMMRegister dst, XMMRegister src);
-  void sqrtsd(XMMRegister dst, Address src);
-
-  void xorps(XMMRegister dst, XMMRegister src);
-  void xorps(XMMRegister dst, Address src);
-  void xorpd(XMMRegister dst, XMMRegister src);
-  void xorpd(XMMRegister dst, Address src);
-
-  void cvtsi2ssl(XMMRegister dst, Register src);
-  void cvtsi2ssq(XMMRegister dst, Register src);
-  void cvtsi2sdl(XMMRegister dst, Register src);
-  void cvtsi2sdq(XMMRegister dst, Register src);
-  void cvttss2sil(Register dst, XMMRegister src); // truncates
-  void cvttss2siq(Register dst, XMMRegister src); // truncates
-  void cvttsd2sil(Register dst, XMMRegister src); // truncates
-  void cvttsd2siq(Register dst, XMMRegister src); // truncates
-  void cvtss2sd(XMMRegister dst, XMMRegister src);
-  void cvtsd2ss(XMMRegister dst, XMMRegister src);
-  void cvtdq2pd(XMMRegister dst, XMMRegister src);
-  void cvtdq2ps(XMMRegister dst, XMMRegister src);
-
-  void pxor(XMMRegister dst, Address src);       // Xor Packed Byte Integer Values
-  void pxor(XMMRegister dst, XMMRegister src);   // Xor Packed Byte Integer Values
-
-  void movdqa(XMMRegister dst, Address src);     // Move Aligned Double Quadword
-  void movdqa(XMMRegister dst, XMMRegister src);
-  void movdqa(Address     dst, XMMRegister src);
-
-  void movq(XMMRegister dst, Address src);
-  void movq(Address dst, XMMRegister src);
-
-  void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
-  void pshufd(XMMRegister dst, Address src,     int mode);
-  void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
-  void pshuflw(XMMRegister dst, Address src,     int mode);
-
-  void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
-
-  void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
-  void punpcklbw(XMMRegister dst, Address src);
-};
-
-
-// MacroAssembler extends Assembler by frequently used macros.
-//
-// Instructions for which a 'better' code sequence exists depending
-// on arguments should also go in here.
-
-class MacroAssembler : public Assembler {
- friend class LIR_Assembler;
- protected:
-
-  Address as_Address(AddressLiteral adr);
-  Address as_Address(ArrayAddress adr);
-
-  // Support for VM calls
-  //
-  // This is the base routine called by the different versions of
-  // call_VM_leaf. The interpreter may customize this version by
-  // overriding it for its purposes (e.g., to save/restore additional
-  // registers when doing a VM call).
-
-  virtual void call_VM_leaf_base(
-    address entry_point,               // the entry point
-    int     number_of_arguments        // the number of arguments to
-                                       // pop after the call
-  );
-
-  // This is the base routine called by the different versions of
-  // call_VM. The interpreter may customize this version by overriding
-  // it for its purposes (e.g., to save/restore additional registers
-  // when doing a VM call).
-  //
-  // If no java_thread register is specified (noreg) than rdi will be
-  // used instead. call_VM_base returns the register which contains
-  // the thread upon return. If a thread register has been specified,
-  // the return value will correspond to that register. If no
-  // last_java_sp is specified (noreg) than rsp will be used instead.
-  virtual void call_VM_base(           // returns the register
-                                       // containing the thread upon
-                                       // return
-    Register oop_result,               // where an oop-result ends up
-                                       // if any; use noreg otherwise
-    Register java_thread,              // the thread if computed
-                                       // before ; use noreg otherwise
-    Register last_java_sp,             // to set up last_Java_frame in
-                                       // stubs; use noreg otherwise
-    address  entry_point,              // the entry point
-    int      number_of_arguments,      // the number of arguments (w/o
-                                       // thread) to pop after the
-                                       // call
-    bool     check_exceptions          // whether to check for pending
-                                       // exceptions after return
-  );
-
-  // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code.
-  // The implementation is only non-empty for the InterpreterMacroAssembler,
-  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
-  virtual void check_and_handle_popframe(Register java_thread);
-  virtual void check_and_handle_earlyret(Register java_thread);
-
-  void call_VM_helper(Register oop_result,
-                      address entry_point,
-                      int number_of_arguments,
-                      bool check_exceptions = true);
-
- public:
-  MacroAssembler(CodeBuffer* code) : Assembler(code) {}
-
-  // Support for NULL-checks
-  //
-  // Generates code that causes a NULL OS exception if the content of
-  // reg is NULL.  If the accessed location is M[reg + offset] and the
-  // offset is known, provide the offset. No explicit code generation
-  // is needed if the offset is within a certain range (0 <= offset <=
-  // page_size).
-  void null_check(Register reg, int offset = -1);
-  static bool needs_explicit_null_check(intptr_t offset);
-
-  // Required platform-specific helpers for Label::patch_instructions.
-  // They _shadow_ the declarations in AbstractAssembler, which are undefined.
-  void pd_patch_instruction(address branch, address target);
-#ifndef PRODUCT
-  static void pd_print_patched_instruction(address branch);
-#endif
-
-
-  // The following 4 methods return the offset of the appropriate move
-  // instruction.  Note: these are 32 bit instructions
-
-  // Support for fast byte/word loading with zero extension (depending
-  // on particular CPU)
-  int load_unsigned_byte(Register dst, Address src);
-  int load_unsigned_word(Register dst, Address src);
-
-  // Support for fast byte/word loading with sign extension (depending
-  // on particular CPU)
-  int load_signed_byte(Register dst, Address src);
-  int load_signed_word(Register dst, Address src);
-
-  // Support for inc/dec with optimal instruction selection depending
-  // on value
-  void incrementl(Register reg, int value = 1);
-  void decrementl(Register reg, int value = 1);
-  void incrementq(Register reg, int value = 1);
-  void decrementq(Register reg, int value = 1);
-
-  void incrementl(Address dst, int value = 1);
-  void decrementl(Address dst, int value = 1);
-  void incrementq(Address dst, int value = 1);
-  void decrementq(Address dst, int value = 1);
-
-  // Support optimal SSE move instructions.
-  void movflt(XMMRegister dst, XMMRegister src) {
-    if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
-    else                       { movss (dst, src); return; }
-  }
-
-  void movflt(XMMRegister dst, Address src) { movss(dst, src); }
-
-  void movflt(XMMRegister dst, AddressLiteral src);
-
-  void movflt(Address dst, XMMRegister src) { movss(dst, src); }
-
-  void movdbl(XMMRegister dst, XMMRegister src) {
-    if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
-    else                       { movsd (dst, src); return; }
-  }
-
-  void movdbl(XMMRegister dst, AddressLiteral src);
-
-  void movdbl(XMMRegister dst, Address src) {
-    if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
-    else                         { movlpd(dst, src); return; }
-  }
-
-  void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
-
-  void incrementl(AddressLiteral dst);
-  void incrementl(ArrayAddress dst);
-
-  // Alignment
-  void align(int modulus);
-
-  // Misc
-  void fat_nop(); // 5 byte nop
-
-
-  // C++ bool manipulation
-
-  void movbool(Register dst, Address src);
-  void movbool(Address dst, bool boolconst);
-  void movbool(Address dst, Register src);
-  void testbool(Register dst);
-
-  // oop manipulations
-  void load_klass(Register dst, Register src);
-  void store_klass(Register dst, Register src);
-  void store_klass_gap(Register dst, Register src);
-
-  void load_prototype_header(Register dst, Register src);
-
-  void load_heap_oop(Register dst, Address src);
-  void store_heap_oop(Address dst, Register src);
-  void encode_heap_oop(Register r);
-  void decode_heap_oop(Register r);
-  void encode_heap_oop_not_null(Register r);
-  void decode_heap_oop_not_null(Register r);
-  void encode_heap_oop_not_null(Register dst, Register src);
-  void decode_heap_oop_not_null(Register dst, Register src);
-
-  void set_narrow_oop(Register dst, jobject obj);
-
-  // Stack frame creation/removal
-  void enter();
-  void leave();
-
-  // Support for getting the JavaThread pointer (i.e.; a reference to
-  // thread-local information) The pointer will be loaded into the
-  // thread register.
-  void get_thread(Register thread);
-
-  void int3();
-
-  // Support for VM calls
-  //
-  // It is imperative that all calls into the VM are handled via the
-  // call_VM macros.  They make sure that the stack linkage is setup
-  // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
-  // while call_VM_leaf's correspond to LEAF entry points.
-  void call_VM(Register oop_result,
-               address entry_point,
-               bool check_exceptions = true);
-  void call_VM(Register oop_result,
-               address entry_point,
-               Register arg_1,
-               bool check_exceptions = true);
-  void call_VM(Register oop_result,
-               address entry_point,
-               Register arg_1, Register arg_2,
-               bool check_exceptions = true);
-  void call_VM(Register oop_result,
-               address entry_point,
-               Register arg_1, Register arg_2, Register arg_3,
-               bool check_exceptions = true);
-
-  // Overloadings with last_Java_sp
-  void call_VM(Register oop_result,
-               Register last_java_sp,
-               address entry_point,
-               int number_of_arguments = 0,
-               bool check_exceptions = true);
-  void call_VM(Register oop_result,
-               Register last_java_sp,
-               address entry_point,
-               Register arg_1, bool
-               check_exceptions = true);
-  void call_VM(Register oop_result,
-               Register last_java_sp,
-               address entry_point,
-               Register arg_1, Register arg_2,
-               bool check_exceptions = true);
-  void call_VM(Register oop_result,
-               Register last_java_sp,
-               address entry_point,
-               Register arg_1, Register arg_2, Register arg_3,
-               bool check_exceptions = true);
-
-  void call_VM_leaf(address entry_point,
-                    int number_of_arguments = 0);
-  void call_VM_leaf(address entry_point,
-                    Register arg_1);
-  void call_VM_leaf(address entry_point,
-                    Register arg_1, Register arg_2);
-  void call_VM_leaf(address entry_point,
-                    Register arg_1, Register arg_2, Register arg_3);
-
-  // last Java Frame (fills frame anchor)
-  void set_last_Java_frame(Register last_java_sp,
-                           Register last_java_fp,
-                           address last_java_pc);
-  void reset_last_Java_frame(bool clear_fp, bool clear_pc);
-
-  // Stores
-  void store_check(Register obj);                // store check for
-                                                 // obj - register is
-                                                 // destroyed
-                                                 // afterwards
-  void store_check(Register obj, Address dst);   // same as above, dst
-                                                 // is exact store
-                                                 // location (reg. is
-                                                 // destroyed)
-
-  // split store_check(Register obj) to enhance instruction interleaving
-  void store_check_part_1(Register obj);
-  void store_check_part_2(Register obj);
-
-  // C 'boolean' to Java boolean: x == 0 ? 0 : 1
-  void c2bool(Register x);
-
-  // Int division/reminder for Java
-  // (as idivl, but checks for special case as described in JVM spec.)
-  // returns idivl instruction offset for implicit exception handling
-  int corrected_idivl(Register reg);
-  // Long division/reminder for Java
-  // (as idivq, but checks for special case as described in JVM spec.)
-  // returns idivq instruction offset for implicit exception handling
-  int corrected_idivq(Register reg);
-
-  // Push and pop integer/fpu/cpu state
-  void push_IU_state();
-  void pop_IU_state();
-
-  void push_FPU_state();
-  void pop_FPU_state();
-
-  void push_CPU_state();
-  void pop_CPU_state();
-
-  // Sign extension
-  void sign_extend_short(Register reg);
-  void sign_extend_byte(Register reg);
-
-  // Division by power of 2, rounding towards 0
-  void division_with_shift(Register reg, int shift_value);
-
-  // Round up to a power of two
-  void round_to_l(Register reg, int modulus);
-  void round_to_q(Register reg, int modulus);
-
-  // allocation
-  void eden_allocate(
-    Register obj,               // result: pointer to object after
-                                // successful allocation
-    Register var_size_in_bytes, // object size in bytes if unknown at
-                                // compile time; invalid otherwise
-    int con_size_in_bytes,      // object size in bytes if known at
-                                // compile time
-    Register t1,                // temp register
-    Label& slow_case            // continuation point if fast
-                                // allocation fails
-    );
-  void tlab_allocate(
-    Register obj,               // result: pointer to object after
-                                // successful allocation
-    Register var_size_in_bytes, // object size in bytes if unknown at
-                                // compile time; invalid otherwise
-    int con_size_in_bytes,      // object size in bytes if known at
-                                // compile time
-    Register t1,                // temp register
-    Register t2,                // temp register
-    Label& slow_case            // continuation point if fast
-                                // allocation fails
-  );
-  void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
-
-  //----
-
-  // Debugging
-
-  // only if +VerifyOops
-  void verify_oop(Register reg, const char* s = "broken oop");
-  void verify_oop_addr(Address addr, const char * s = "broken oop addr");
-
-  // if heap base register is used - reinit it with the correct value
-  void reinit_heapbase();
-
-  // only if +VerifyFPU
-  void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {}
-
-  // prints msg, dumps registers and stops execution
-  void stop(const char* msg);
-
-  // prints message and continues
-  void warn(const char* msg);
-
-  static void debug(char* msg, int64_t pc, int64_t regs[]);
-
-  void os_breakpoint();
-
-  void untested()
-  {
-    stop("untested");
-  }
-
-  void unimplemented(const char* what = "")
-  {
-    char* b = new char[1024];
-    sprintf(b, "unimplemented: %s", what);
-    stop(b);
-  }
-
-  void should_not_reach_here()
-  {
-    stop("should not reach here");
-  }
-
-  // Stack overflow checking
-  void bang_stack_with_offset(int offset)
-  {
-    // stack grows down, caller passes positive offset
-    assert(offset > 0, "must bang with negative offset");
-    movl(Address(rsp, (-offset)), rax);
-  }
-
-  // Writes to stack successive pages until offset reached to check for
-  // stack overflow + shadow pages.  Also, clobbers tmp
-  void bang_stack_size(Register offset, Register tmp);
-
-  // Support for serializing memory accesses between threads.
-  void serialize_memory(Register thread, Register tmp);
-
-  void verify_tlab();
-
-  // Biased locking support
-  // lock_reg and obj_reg must be loaded up with the appropriate values.
-  // swap_reg must be rax and is killed.
-  // tmp_reg must be supplied and is killed.
-  // If swap_reg_contains_mark is true then the code assumes that the
-  // mark word of the object has already been loaded into swap_reg.
-  // Optional slow case is for implementations (interpreter and C1) which branch to
-  // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
-  // Returns offset of first potentially-faulting instruction for null
-  // check info (currently consumed only by C1). If
-  // swap_reg_contains_mark is true then returns -1 as it is assumed
-  // the calling code has already passed any potential faults.
-  int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
-                           bool swap_reg_contains_mark,
-                           Label& done, Label* slow_case = NULL,
-                           BiasedLockingCounters* counters = NULL);
-  void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
-
-  Condition negate_condition(Condition cond);
-
-  // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
-  // operands. In general the names are modified to avoid hiding the instruction in Assembler
-  // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
-  // here in MacroAssembler. The major exception to this rule is call
-
-  // Arithmetics
-
-  void cmp8(AddressLiteral src1, int8_t imm32);
-
-  void cmp32(AddressLiteral src1, int32_t src2);
-  // compare reg - mem, or reg - &mem
-  void cmp32(Register src1, AddressLiteral src2);
-
-  void cmp32(Register src1, Address src2);
-
-#ifndef _LP64
-  void cmpoop(Address dst, jobject obj);
-  void cmpoop(Register dst, jobject obj);
-#endif // _LP64
-
-  // NOTE src2 must be the lval. This is NOT an mem-mem compare
-  void cmpptr(Address src1, AddressLiteral src2);
-
-  void cmpptr(Register src1, AddressLiteral src);
-
-  // will be cmpreg(?)
-  void cmp64(Register src1, AddressLiteral src);
-
-  void cmpxchgptr(Register reg, Address adr);
-  void cmpxchgptr(Register reg, AddressLiteral adr);
-
-  // Helper functions for statistics gathering.
-  // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
-  void cond_inc32(Condition cond, AddressLiteral counter_addr);
-  // Unconditional atomic increment.
-  void atomic_incl(AddressLiteral counter_addr);
-
-
-  void lea(Register dst, AddressLiteral src);
-  void lea(Register dst, Address src);
-
-
-  // Calls
-  void call(Label& L, relocInfo::relocType rtype);
-  void call(Register entry);
-  void call(AddressLiteral entry);
-
-  // Jumps
-
-  // 32bit can do a case table jump in one instruction but we no longer allow the base
-  // to be installed in the Address class
-  void jump(ArrayAddress entry);
-
-  void jump(AddressLiteral entry);
-  void jump_cc(Condition cc, AddressLiteral dst);
-
-  // Floating
-
-  void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
-  void ldmxcsr(AddressLiteral src);
-
-private:
-  // these are private because users should be doing movflt/movdbl
-
-  void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
-  void movss(Address dst, XMMRegister src)       { Assembler::movss(dst, src); }
-  void movss(XMMRegister dst, Address src)       { Assembler::movss(dst, src); }
-  void movss(XMMRegister dst, AddressLiteral src);
-
-  void movlpd(XMMRegister dst, Address src)      {Assembler::movlpd(dst, src); }
-  void movlpd(XMMRegister dst, AddressLiteral src);
-
-public:
-
-
-  void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); }
-  void xorpd(XMMRegister dst, Address src)       {Assembler::xorpd(dst, src); }
-  void xorpd(XMMRegister dst, AddressLiteral src);
-
-  void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); }
-  void xorps(XMMRegister dst, Address src)       {Assembler::xorps(dst, src); }
-  void xorps(XMMRegister dst, AddressLiteral src);
-
-
-  // Data
-
-  void movoop(Register dst, jobject obj);
-  void movoop(Address dst, jobject obj);
-
-  void movptr(ArrayAddress dst, Register src);
-  void movptr(Register dst, AddressLiteral src);
-
-  void movptr(Register dst, intptr_t src);
-  void movptr(Address dst, intptr_t src);
-
-  void movptr(Register dst, ArrayAddress src);
-
-  // to avoid hiding movl
-  void mov32(AddressLiteral dst, Register src);
-  void mov32(Register dst, AddressLiteral src);
-
-  void pushoop(jobject obj);
-
-  // Can push value or effective address
-  void pushptr(AddressLiteral src);
-
-};
-
-/**
- * class SkipIfEqual:
- *
- * Instantiating this class will result in assembly code being output that will
- * jump around any code emitted between the creation of the instance and it's
- * automatic destruction at the end of a scope block, depending on the value of
- * the flag passed to the constructor, which will be checked at run-time.
- */
-class SkipIfEqual {
- private:
-  MacroAssembler* _masm;
-  Label _label;
-
- public:
-   SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
-   ~SkipIfEqual();
-};
-
-
-#ifdef ASSERT
-inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
-#endif
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.inline.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/*
- * Copyright 2003-2005 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-inline void Assembler::emit_long64(jlong x) {
-  *(jlong*) _code_pos = x;
-  _code_pos += sizeof(jlong);
-  code_section()->set_end(_code_pos);
-}
-
-inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
-  unsigned char op = branch[0];
-  assert(op == 0xE8 /* call */ ||
-         op == 0xE9 /* jmp */ ||
-         op == 0xEB /* short jmp */ ||
-         (op & 0xF0) == 0x70 /* short jcc */ ||
-         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
-         "Invalid opcode at patch point");
-
-  if (op == 0xEB || (op & 0xF0) == 0x70) {
-    // short offset operators (jmp and jcc)
-    char* disp = (char*) &branch[1];
-    int imm8 = target - (address) &disp[1];
-    guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
-    *disp = imm8;
-  } else {
-    int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
-    int imm32 = target - (address) &disp[1];
-    *disp = imm32;
-  }
-}
-
-#ifndef PRODUCT
-inline void MacroAssembler::pd_print_patched_instruction(address branch) {
-  const char* s;
-  unsigned char op = branch[0];
-  if (op == 0xE8) {
-    s = "call";
-  } else if (op == 0xE9 || op == 0xEB) {
-    s = "jmp";
-  } else if ((op & 0xF0) == 0x70) {
-    s = "jcc";
-  } else if (op == 0x0F) {
-    s = "jcc";
-  } else {
-    s = "????";
-  }
-  tty->print("%s (unresolved)", s);
-}
-#endif // ndef PRODUCT
-
-inline void MacroAssembler::movptr(Address dst, intptr_t src) {
-#ifdef _LP64
-  Assembler::mov64(dst, src);
-#else
-  Assembler::movl(dst, src);
-#endif // _LP64
-}
-
-inline void MacroAssembler::movptr(Register dst, intptr_t src) {
-#ifdef _LP64
-  Assembler::mov64(dst, src);
-#else
-  Assembler::movl(dst, src);
-#endif // _LP64
-}
--- a/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -43,11 +43,12 @@
     __ comisd(input()->as_xmm_double_reg(),
               ExternalAddress((address)&double_zero));
   } else {
-    __ pushl(rax);
+    LP64_ONLY(ShouldNotReachHere());
+    __ push(rax);
     __ ftst();
     __ fnstsw_ax();
     __ sahf();
-    __ popl(rax);
+    __ pop(rax);
   }
 
   Label NaN, do_return;
@@ -61,7 +62,7 @@
 
   // input is NaN -> return 0
   __ bind(NaN);
-  __ xorl(result()->as_register(), result()->as_register());
+  __ xorptr(result()->as_register(), result()->as_register());
 
   __ bind(do_return);
   __ jmp(_continuation);
@@ -139,7 +140,7 @@
 void NewInstanceStub::emit_code(LIR_Assembler* ce) {
   assert(__ rsp_offset() == 0, "frame size should be fixed");
   __ bind(_entry);
-  __ movl(rdx, _klass_reg->as_register());
+  __ movptr(rdx, _klass_reg->as_register());
   __ call(RuntimeAddress(Runtime1::entry_for(_stub_id)));
   ce->add_call_info_here(_info);
   ce->verify_oop_map(_info);
@@ -306,10 +307,10 @@
     assert(_obj != noreg, "must be a valid register");
     Register tmp = rax;
     if (_obj == tmp) tmp = rbx;
-    __ pushl(tmp);
+    __ push(tmp);
     __ get_thread(tmp);
-    __ cmpl(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
-    __ popl(tmp);
+    __ cmpptr(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
+    __ pop(tmp);
     __ jcc(Assembler::notEqual, call_patch);
 
     // access_field patches may execute the patched code before it's
@@ -434,7 +435,7 @@
     VMReg r_1 = args[i].first();
     if (r_1->is_stack()) {
       int st_off = r_1->reg2stack() * wordSize;
-      __ movl (Address(rsp, st_off), r[i]);
+      __ movptr (Address(rsp, st_off), r[i]);
     } else {
       assert(r[i] == args[i].first()->as_Register(), "Wrong register for arg ");
     }
@@ -449,7 +450,7 @@
   ce->add_call_info_here(info());
 
 #ifndef PRODUCT
-  __ increment(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
+  __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
 #endif
 
   __ jmp(_continuation);
--- a/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -36,27 +36,34 @@
 
 // registers
 enum {
-  pd_nof_cpu_regs_frame_map = 8,  // number of registers used during code emission
-  pd_nof_fpu_regs_frame_map = 8,  // number of registers used during code emission
-  pd_nof_xmm_regs_frame_map = 8,  // number of registers used during code emission
-  pd_nof_caller_save_cpu_regs_frame_map = 6,  // number of registers killed by calls
-  pd_nof_caller_save_fpu_regs_frame_map = 8,  // number of registers killed by calls
-  pd_nof_caller_save_xmm_regs_frame_map = 8,  // number of registers killed by calls
+  pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
+  pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of registers used during code emission
+  pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers,    // number of registers used during code emission
 
-  pd_nof_cpu_regs_reg_alloc = 6,  // number of registers that are visible to register allocator
+#ifdef _LP64
+  #define UNALLOCATED 4    // rsp, rbp, r15, r10
+#else
+  #define UNALLOCATED 2    // rsp, rbp
+#endif // LP64
+
+  pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED,  // number of registers killed by calls
+  pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map,  // number of registers killed by calls
+  pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map,  // number of registers killed by calls
+
+  pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
   pd_nof_fpu_regs_reg_alloc = 6,  // number of registers that are visible to register allocator
 
-  pd_nof_cpu_regs_linearscan = 8, // number of registers visible to linear scan
-  pd_nof_fpu_regs_linearscan = 8, // number of registers visible to linear scan
-  pd_nof_xmm_regs_linearscan = 8, // number of registers visible to linear scan
+  pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
+  pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
+  pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
   pd_first_cpu_reg = 0,
-  pd_last_cpu_reg = 5,
+  pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
   pd_first_byte_reg = 2,
   pd_last_byte_reg = 5,
   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
   pd_last_fpu_reg =  pd_first_fpu_reg + 7,
   pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
-  pd_last_xmm_reg =  pd_first_xmm_reg + 7
+  pd_last_xmm_reg =  pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
 };
 
 
--- a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -39,10 +39,15 @@
     opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
   } else if (r_1->is_Register()) {
     Register reg = r_1->as_Register();
-    if (r_2->is_Register()) {
+    if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
       Register reg2 = r_2->as_Register();
+#ifdef _LP64
+      assert(reg2 == reg, "must be same register");
+      opr = as_long_opr(reg);
+#else
       opr = as_long_opr(reg2, reg);
-    } else if (type == T_OBJECT) {
+#endif // _LP64
+    } else if (type == T_OBJECT || type == T_ARRAY) {
       opr = as_oop_opr(reg);
     } else {
       opr = as_opr(reg);
@@ -88,18 +93,39 @@
 LIR_Opr FrameMap::rdx_oop_opr;
 LIR_Opr FrameMap::rcx_oop_opr;
 
-LIR_Opr FrameMap::rax_rdx_long_opr;
-LIR_Opr FrameMap::rbx_rcx_long_opr;
+LIR_Opr FrameMap::long0_opr;
+LIR_Opr FrameMap::long1_opr;
 LIR_Opr FrameMap::fpu0_float_opr;
 LIR_Opr FrameMap::fpu0_double_opr;
 LIR_Opr FrameMap::xmm0_float_opr;
 LIR_Opr FrameMap::xmm0_double_opr;
 
+#ifdef _LP64
+
+LIR_Opr  FrameMap::r8_opr;
+LIR_Opr  FrameMap::r9_opr;
+LIR_Opr FrameMap::r10_opr;
+LIR_Opr FrameMap::r11_opr;
+LIR_Opr FrameMap::r12_opr;
+LIR_Opr FrameMap::r13_opr;
+LIR_Opr FrameMap::r14_opr;
+LIR_Opr FrameMap::r15_opr;
+
+// r10 and r15 can never contain oops since they aren't available to
+// the allocator
+LIR_Opr  FrameMap::r8_oop_opr;
+LIR_Opr  FrameMap::r9_oop_opr;
+LIR_Opr FrameMap::r11_oop_opr;
+LIR_Opr FrameMap::r12_oop_opr;
+LIR_Opr FrameMap::r13_oop_opr;
+LIR_Opr FrameMap::r14_oop_opr;
+#endif // _LP64
+
 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
 
-XMMRegister FrameMap::_xmm_regs [8] = { 0, };
+XMMRegister FrameMap::_xmm_regs [] = { 0, };
 
 XMMRegister FrameMap::nr2xmmreg(int rnr) {
   assert(_init_done, "tables not initialized");
@@ -113,18 +139,39 @@
 void FrameMap::init() {
   if (_init_done) return;
 
-  assert(nof_cpu_regs == 8, "wrong number of CPU registers");
-  map_register(0, rsi);  rsi_opr = LIR_OprFact::single_cpu(0);  rsi_oop_opr = LIR_OprFact::single_cpu_oop(0);
-  map_register(1, rdi);  rdi_opr = LIR_OprFact::single_cpu(1);  rdi_oop_opr = LIR_OprFact::single_cpu_oop(1);
-  map_register(2, rbx);  rbx_opr = LIR_OprFact::single_cpu(2);  rbx_oop_opr = LIR_OprFact::single_cpu_oop(2);
-  map_register(3, rax);  rax_opr = LIR_OprFact::single_cpu(3);  rax_oop_opr = LIR_OprFact::single_cpu_oop(3);
-  map_register(4, rdx);  rdx_opr = LIR_OprFact::single_cpu(4);  rdx_oop_opr = LIR_OprFact::single_cpu_oop(4);
-  map_register(5, rcx);  rcx_opr = LIR_OprFact::single_cpu(5);  rcx_oop_opr = LIR_OprFact::single_cpu_oop(5);
-  map_register(6, rsp);  rsp_opr = LIR_OprFact::single_cpu(6);
-  map_register(7, rbp);  rbp_opr = LIR_OprFact::single_cpu(7);
+  assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
+  map_register(0, rsi);  rsi_opr = LIR_OprFact::single_cpu(0);
+  map_register(1, rdi);  rdi_opr = LIR_OprFact::single_cpu(1);
+  map_register(2, rbx);  rbx_opr = LIR_OprFact::single_cpu(2);
+  map_register(3, rax);  rax_opr = LIR_OprFact::single_cpu(3);
+  map_register(4, rdx);  rdx_opr = LIR_OprFact::single_cpu(4);
+  map_register(5, rcx);  rcx_opr = LIR_OprFact::single_cpu(5);
 
-  rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
-  rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+#ifndef _LP64
+  // The unallocatable registers are at the end
+  map_register(6, rsp);
+  map_register(7, rbp);
+#else
+  map_register( 6, r8);    r8_opr = LIR_OprFact::single_cpu(6);
+  map_register( 7, r9);    r9_opr = LIR_OprFact::single_cpu(7);
+  map_register( 8, r11);  r11_opr = LIR_OprFact::single_cpu(8);
+  map_register( 9, r12);  r12_opr = LIR_OprFact::single_cpu(9);
+  map_register(10, r13);  r13_opr = LIR_OprFact::single_cpu(10);
+  map_register(11, r14);  r14_opr = LIR_OprFact::single_cpu(11);
+  // The unallocatable registers are at the end
+  map_register(12, r10);  r10_opr = LIR_OprFact::single_cpu(12);
+  map_register(13, r15);  r15_opr = LIR_OprFact::single_cpu(13);
+  map_register(14, rsp);
+  map_register(15, rbp);
+#endif // _LP64
+
+#ifdef _LP64
+  long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
+  long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
+#else
+  long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
+  long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+#endif // _LP64
   fpu0_float_opr   = LIR_OprFact::single_fpu(0);
   fpu0_double_opr  = LIR_OprFact::double_fpu(0);
   xmm0_float_opr   = LIR_OprFact::single_xmm(0);
@@ -137,6 +184,15 @@
   _caller_save_cpu_regs[4] = rdx_opr;
   _caller_save_cpu_regs[5] = rcx_opr;
 
+#ifdef _LP64
+  _caller_save_cpu_regs[6]  = r8_opr;
+  _caller_save_cpu_regs[7]  = r9_opr;
+  _caller_save_cpu_regs[8]  = r11_opr;
+  _caller_save_cpu_regs[9]  = r12_opr;
+  _caller_save_cpu_regs[10] = r13_opr;
+  _caller_save_cpu_regs[11] = r14_opr;
+#endif // _LP64
+
 
   _xmm_regs[0] = xmm0;
   _xmm_regs[1] = xmm1;
@@ -147,18 +203,51 @@
   _xmm_regs[6] = xmm6;
   _xmm_regs[7] = xmm7;
 
+#ifdef _LP64
+  _xmm_regs[8]   = xmm8;
+  _xmm_regs[9]   = xmm9;
+  _xmm_regs[10]  = xmm10;
+  _xmm_regs[11]  = xmm11;
+  _xmm_regs[12]  = xmm12;
+  _xmm_regs[13]  = xmm13;
+  _xmm_regs[14]  = xmm14;
+  _xmm_regs[15]  = xmm15;
+#endif // _LP64
+
   for (int i = 0; i < 8; i++) {
     _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
+  }
+
+  for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
     _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
   }
 
   _init_done = true;
 
+  rsi_oop_opr = as_oop_opr(rsi);
+  rdi_oop_opr = as_oop_opr(rdi);
+  rbx_oop_opr = as_oop_opr(rbx);
+  rax_oop_opr = as_oop_opr(rax);
+  rdx_oop_opr = as_oop_opr(rdx);
+  rcx_oop_opr = as_oop_opr(rcx);
+
+  rsp_opr = as_pointer_opr(rsp);
+  rbp_opr = as_pointer_opr(rbp);
+
+#ifdef _LP64
+  r8_oop_opr = as_oop_opr(r8);
+  r9_oop_opr = as_oop_opr(r9);
+  r11_oop_opr = as_oop_opr(r11);
+  r12_oop_opr = as_oop_opr(r12);
+  r13_oop_opr = as_oop_opr(r13);
+  r14_oop_opr = as_oop_opr(r14);
+#endif // _LP64
+
   VMRegPair regs;
   BasicType sig_bt = T_OBJECT;
   SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true);
   receiver_opr = as_oop_opr(regs.first()->as_Register());
-  assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx");
+
 }
 
 
--- a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -38,8 +38,13 @@
     nof_xmm_regs = pd_nof_xmm_regs_frame_map,
     nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
     first_available_sp_in_frame = 0,
+#ifndef _LP64
     frame_pad_in_bytes = 8,
     nof_reg_args = 2
+#else
+    frame_pad_in_bytes = 16,
+    nof_reg_args = 6
+#endif // _LP64
   };
 
  private:
@@ -65,17 +70,49 @@
   static LIR_Opr rax_oop_opr;
   static LIR_Opr rdx_oop_opr;
   static LIR_Opr rcx_oop_opr;
+#ifdef _LP64
 
-  static LIR_Opr rax_rdx_long_opr;
-  static LIR_Opr rbx_rcx_long_opr;
+  static LIR_Opr  r8_opr;
+  static LIR_Opr  r9_opr;
+  static LIR_Opr r10_opr;
+  static LIR_Opr r11_opr;
+  static LIR_Opr r12_opr;
+  static LIR_Opr r13_opr;
+  static LIR_Opr r14_opr;
+  static LIR_Opr r15_opr;
+
+  static LIR_Opr  r8_oop_opr;
+  static LIR_Opr  r9_oop_opr;
+
+  static LIR_Opr r11_oop_opr;
+  static LIR_Opr r12_oop_opr;
+  static LIR_Opr r13_oop_opr;
+  static LIR_Opr r14_oop_opr;
+
+#endif // _LP64
+
+  static LIR_Opr long0_opr;
+  static LIR_Opr long1_opr;
   static LIR_Opr fpu0_float_opr;
   static LIR_Opr fpu0_double_opr;
   static LIR_Opr xmm0_float_opr;
   static LIR_Opr xmm0_double_opr;
 
+#ifdef _LP64
+  static LIR_Opr as_long_opr(Register r) {
+    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+  }
+  static LIR_Opr as_pointer_opr(Register r) {
+    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+  }
+#else
   static LIR_Opr as_long_opr(Register r, Register r2) {
     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
   }
+  static LIR_Opr as_pointer_opr(Register r) {
+    return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
+  }
+#endif // _LP64
 
   // VMReg name for spilled physical FPU stack slot n
   static VMReg fpu_regname (int n);
--- a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -113,7 +113,7 @@
 
 
 LIR_Opr LIR_Assembler::receiverOpr() {
-  return FrameMap::rcx_oop_opr;
+  return FrameMap::receiver_opr;
 }
 
 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
@@ -121,7 +121,7 @@
 }
 
 LIR_Opr LIR_Assembler::osrBufferPointer() {
-  return FrameMap::rcx_opr;
+  return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 }
 
 //--------------fpu register translations-----------------------
@@ -181,7 +181,7 @@
   if (opr->is_single_cpu()) {
     __ push_reg(opr->as_register());
   } else if (opr->is_double_cpu()) {
-    __ push_reg(opr->as_register_hi());
+    NOT_LP64(__ push_reg(opr->as_register_hi()));
     __ push_reg(opr->as_register_lo());
   } else if (opr->is_stack()) {
     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
@@ -202,31 +202,45 @@
 
 void LIR_Assembler::pop(LIR_Opr opr) {
   if (opr->is_single_cpu()) {
-    __ pop(opr->as_register());
+    __ pop_reg(opr->as_register());
   } else {
     ShouldNotReachHere();
   }
 }
 
+bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
+  return addr->base()->is_illegal() && addr->index()->is_illegal();
+}
+
 //-------------------------------------------
+
 Address LIR_Assembler::as_Address(LIR_Address* addr) {
+  return as_Address(addr, rscratch1);
+}
+
+Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
   if (addr->base()->is_illegal()) {
     assert(addr->index()->is_illegal(), "must be illegal too");
-    //return Address(addr->disp(), relocInfo::none);
-    // hack for now since this should really return an AddressLiteral
-    // which will have to await 64bit c1 changes.
-    return Address(noreg, addr->disp());
+    AddressLiteral laddr((address)addr->disp(), relocInfo::none);
+    if (! __ reachable(laddr)) {
+      __ movptr(tmp, laddr.addr());
+      Address res(tmp, 0);
+      return res;
+    } else {
+      return __ as_Address(laddr);
+    }
   }
 
-  Register base = addr->base()->as_register();
+  Register base = addr->base()->as_pointer_register();
 
   if (addr->index()->is_illegal()) {
     return Address( base, addr->disp());
-  } else if (addr->index()->is_single_cpu()) {
-    Register index = addr->index()->as_register();
+  } else if (addr->index()->is_cpu_register()) {
+    Register index = addr->index()->as_pointer_register();
     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
   } else if (addr->index()->is_constant()) {
-    int addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+    intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+    assert(Assembler::is_simm32(addr_offset), "must be");
 
     return Address(base, addr_offset);
   } else {
@@ -284,7 +298,7 @@
   // All other registers are dead at this point and the locals will be
   // copied into place by code emitted in the IR.
 
-  Register OSR_buf = osrBufferPointer()->as_register();
+  Register OSR_buf = osrBufferPointer()->as_pointer_register();
   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
     int monitor_offset = BytesPerWord * method()->max_locals() +
       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
@@ -294,16 +308,16 @@
       // verify the interpreter's monitor has a non-null object
       {
         Label L;
-        __ cmpl(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);
+        __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);
         __ jcc(Assembler::notZero, L);
         __ stop("locked object is NULL");
         __ bind(L);
       }
 #endif
-      __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
-      __ movl(frame_map()->address_for_monitor_lock(i), rbx);
-      __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
-      __ movl(frame_map()->address_for_monitor_object(i), rbx);
+      __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
+      __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
+      __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
+      __ movptr(frame_map()->address_for_monitor_object(i), rbx);
     }
   }
 }
@@ -313,10 +327,11 @@
 int LIR_Assembler::check_icache() {
   Register receiver = FrameMap::receiver_opr->as_register();
   Register ic_klass = IC_Klass;
+  const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 
   if (!VerifyOops) {
     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
-    while ((__ offset() + 9) % CodeEntryAlignment != 0) {
+    while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
       __ nop();
     }
   }
@@ -347,7 +362,7 @@
     //       and cannot block => no GC can happen
     // The slow case (MonitorAccessStub) uses the first two stack slots
     // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
-    __ movl (Address(rsp, 2*wordSize), exception);
+    __ movptr (Address(rsp, 2*wordSize), exception);
   }
 
   Register obj_reg  = obj_opr->as_register();
@@ -360,7 +375,7 @@
   lock_reg = new_hdr;
   // compute pointer to BasicLock
   Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
-  __ leal(lock_reg, lock_addr);
+  __ lea(lock_reg, lock_addr);
   // unlock object
   MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
   // _slow_case_stubs->append(slow_case);
@@ -385,14 +400,18 @@
 
   if (exception->is_valid()) {
     // restore exception
-    __ movl (exception, Address(rsp, 2 * wordSize));
+    __ movptr (exception, Address(rsp, 2 * wordSize));
   }
 }
 
 // This specifies the rsp decrement needed to build the frame
 int LIR_Assembler::initial_frame_size_in_bytes() {
   // if rounding, must let FrameMap know!
-  return (frame_map()->framesize() - 2)  * BytesPerWord; // subtract two words to account for return address and link
+
+  // The frame_map records size in slots (32bit word)
+
+  // subtract two words to account for return address and link
+  return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 }
 
 
@@ -495,43 +514,43 @@
 // This is the fast version of java.lang.String.compare; it has not
 // OSR-entry and therefore, we generate a slow version for OSR's
 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
-  __ movl (rbx, rcx); // receiver is in rcx
-  __ movl (rax, arg1->as_register());
+  __ movptr (rbx, rcx); // receiver is in rcx
+  __ movptr (rax, arg1->as_register());
 
   // Get addresses of first characters from both Strings
-  __ movl (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
-  __ movl (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
-  __ leal (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+  __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
+  __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
+  __ lea    (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 
 
   // rbx, may be NULL
   add_debug_info_for_null_check_here(info);
-  __ movl (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
-  __ movl (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
-  __ leal (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+  __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
+  __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
+  __ lea    (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 
   // compute minimum length (in rax) and difference of lengths (on top of stack)
   if (VM_Version::supports_cmov()) {
-    __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
-    __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
-    __ movl (rcx, rbx);
-    __ subl (rbx, rax); // subtract lengths
-    __ pushl(rbx);      // result
-    __ cmovl(Assembler::lessEqual, rax, rcx);
+    __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+    __ movl     (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
+    __ mov      (rcx, rbx);
+    __ subptr   (rbx, rax); // subtract lengths
+    __ push     (rbx);      // result
+    __ cmov     (Assembler::lessEqual, rax, rcx);
   } else {
     Label L;
-    __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
-    __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
-    __ movl (rax, rbx);
-    __ subl (rbx, rcx);
-    __ pushl(rbx);
-    __ jcc  (Assembler::lessEqual, L);
-    __ movl (rax, rcx);
+    __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+    __ movl     (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
+    __ mov      (rax, rbx);
+    __ subptr   (rbx, rcx);
+    __ push     (rbx);
+    __ jcc      (Assembler::lessEqual, L);
+    __ mov      (rax, rcx);
     __ bind (L);
   }
   // is minimum length 0?
   Label noLoop, haveResult;
-  __ testl (rax, rax);
+  __ testptr (rax, rax);
   __ jcc (Assembler::zero, noLoop);
 
   // compare first characters
@@ -546,9 +565,9 @@
   // set rsi.edi to the end of the arrays (arrays have same length)
   // negate the index
 
-  __ leal(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
-  __ leal(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
-  __ negl(rax);
+  __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+  __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+  __ negptr(rax);
 
   // compare the strings in a loop
 
@@ -565,12 +584,12 @@
   // strings are equal up to min length
 
   __ bind(noLoop);
-  __ popl(rax);
+  __ pop(rax);
   return_op(LIR_OprFact::illegalOpr);
 
   __ bind(haveResult);
   // leave instruction is going to discard the TOS value
-  __ movl (rax, rcx); // result of call is in rax,
+  __ mov (rax, rcx); // result of call is in rax,
 }
 
 
@@ -589,6 +608,11 @@
   // the poll sets the condition code, but no data registers
   AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
                               relocInfo::poll_return_type);
+
+  // NOTE: the requires that the polling page be reachable else the reloc
+  // goes to the movq that loads the address and not the faulting instruction
+  // which breaks the signal handler code
+
   __ test32(rax, polling_page);
 
   __ ret(0);
@@ -606,17 +630,22 @@
   }
 
   int offset = __ offset();
+
+  // NOTE: the requires that the polling page be reachable else the reloc
+  // goes to the movq that loads the address and not the faulting instruction
+  // which breaks the signal handler code
+
   __ test32(rax, polling_page);
   return offset;
 }
 
 
 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
-  if (from_reg != to_reg) __ movl(to_reg, from_reg);
+  if (from_reg != to_reg) __ mov(to_reg, from_reg);
 }
 
 void LIR_Assembler::swap_reg(Register a, Register b) {
-  __ xchgl(a, b);
+  __ xchgptr(a, b);
 }
 
 
@@ -634,8 +663,12 @@
 
     case T_LONG: {
       assert(patch_code == lir_patch_none, "no patching handled here");
-      __ movl(dest->as_register_lo(), c->as_jint_lo());
-      __ movl(dest->as_register_hi(), c->as_jint_hi());
+#ifdef _LP64
+      __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
+#else
+      __ movptr(dest->as_register_lo(), c->as_jint_lo());
+      __ movptr(dest->as_register_hi(), c->as_jint_hi());
+#endif // _LP64
       break;
     }
 
@@ -714,10 +747,15 @@
 
     case T_LONG:  // fall through
     case T_DOUBLE:
-      __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
-                                            lo_word_offset_in_bytes), c->as_jint_lo_bits());
-      __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
-                                            hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#ifdef _LP64
+      __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+                                            lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
+#else
+      __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+                                              lo_word_offset_in_bytes), c->as_jint_lo_bits());
+      __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+                                              hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#endif // _LP64
       break;
 
     default:
@@ -731,7 +769,7 @@
   LIR_Const* c = src->as_constant_ptr();
   LIR_Address* addr = dest->as_address_ptr();
 
-  if (info != NULL) add_debug_info_for_null_check_here(info);
+  int null_check_here = code_offset();
   switch (type) {
     case T_INT:    // fall through
     case T_FLOAT:
@@ -741,16 +779,33 @@
     case T_OBJECT:  // fall through
     case T_ARRAY:
       if (c->as_jobject() == NULL) {
-        __ movl(as_Address(addr), NULL_WORD);
+        __ movptr(as_Address(addr), (int32_t)NULL_WORD);
       } else {
-        __ movoop(as_Address(addr), c->as_jobject());
+        if (is_literal_address(addr)) {
+          ShouldNotReachHere();
+          __ movoop(as_Address(addr, noreg), c->as_jobject());
+        } else {
+          __ movoop(as_Address(addr), c->as_jobject());
+        }
       }
       break;
 
     case T_LONG:    // fall through
     case T_DOUBLE:
-      __ movl(as_Address_hi(addr), c->as_jint_hi_bits());
-      __ movl(as_Address_lo(addr), c->as_jint_lo_bits());
+#ifdef _LP64
+      if (is_literal_address(addr)) {
+        ShouldNotReachHere();
+        __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
+      } else {
+        __ movptr(r10, (intptr_t)c->as_jlong_bits());
+        null_check_here = code_offset();
+        __ movptr(as_Address_lo(addr), r10);
+      }
+#else
+      // Always reachable in 32bit so this doesn't produce useless move literal
+      __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
+      __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
+#endif // _LP64
       break;
 
     case T_BOOLEAN: // fall through
@@ -766,6 +821,10 @@
     default:
       ShouldNotReachHere();
   };
+
+  if (info != NULL) {
+    add_debug_info_for_null_check(null_check_here, info);
+  }
 }
 
 
@@ -775,6 +834,13 @@
 
   // move between cpu-registers
   if (dest->is_single_cpu()) {
+#ifdef _LP64
+    if (src->type() == T_LONG) {
+      // Can do LONG -> OBJECT
+      move_regs(src->as_register_lo(), dest->as_register());
+      return;
+    }
+#endif
     assert(src->is_single_cpu(), "must match");
     if (src->type() == T_OBJECT) {
       __ verify_oop(src->as_register());
@@ -782,13 +848,27 @@
     move_regs(src->as_register(), dest->as_register());
 
   } else if (dest->is_double_cpu()) {
+#ifdef _LP64
+    if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
+      // Surprising to me but we can see move of a long to t_object
+      __ verify_oop(src->as_register());
+      move_regs(src->as_register(), dest->as_register_lo());
+      return;
+    }
+#endif
     assert(src->is_double_cpu(), "must match");
     Register f_lo = src->as_register_lo();
     Register f_hi = src->as_register_hi();
     Register t_lo = dest->as_register_lo();
     Register t_hi = dest->as_register_hi();
+#ifdef _LP64
+    assert(f_hi == f_lo, "must be same");
+    assert(t_hi == t_lo, "must be same");
+    move_regs(f_lo, t_lo);
+#else
     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 
+
     if (f_lo == t_hi && f_hi == t_lo) {
       swap_reg(f_lo, f_hi);
     } else if (f_hi == t_lo) {
@@ -800,6 +880,7 @@
       move_regs(f_lo, t_lo);
       move_regs(f_hi, t_hi);
     }
+#endif // LP64
 
     // special moves from fpu-register to xmm-register
     // necessary for method results
@@ -841,14 +922,16 @@
     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
     if (type == T_OBJECT || type == T_ARRAY) {
       __ verify_oop(src->as_register());
+      __ movptr (dst, src->as_register());
+    } else {
+      __ movl (dst, src->as_register());
     }
-    __ movl (dst, src->as_register());
 
   } else if (src->is_double_cpu()) {
     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
-    __ movl (dstLO, src->as_register_lo());
-    __ movl (dstHI, src->as_register_hi());
+    __ movptr (dstLO, src->as_register_lo());
+    NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 
   } else if (src->is_single_xmm()) {
     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
@@ -885,6 +968,8 @@
   }
   if (patch_code != lir_patch_none) {
     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+    Address toa = as_Address(to_addr);
+    assert(toa.disp() != 0, "must have");
   }
   if (info != NULL) {
     add_debug_info_for_null_check_here(info);
@@ -918,6 +1003,10 @@
     case T_ADDRESS: // fall through
     case T_ARRAY:   // fall through
     case T_OBJECT:  // fall through
+#ifdef _LP64
+      __ movptr(as_Address(to_addr), src->as_register());
+      break;
+#endif // _LP64
     case T_INT:
       __ movl(as_Address(to_addr), src->as_register());
       break;
@@ -925,6 +1014,9 @@
     case T_LONG: {
       Register from_lo = src->as_register_lo();
       Register from_hi = src->as_register_hi();
+#ifdef _LP64
+      __ movptr(as_Address_lo(to_addr), from_lo);
+#else
       Register base = to_addr->base()->as_register();
       Register index = noreg;
       if (to_addr->index()->is_register()) {
@@ -950,6 +1042,7 @@
         }
         __ movl(as_Address_hi(to_addr), from_hi);
       }
+#endif // _LP64
       break;
     }
 
@@ -982,16 +1075,18 @@
   assert(dest->is_register(), "should not call otherwise");
 
   if (dest->is_single_cpu()) {
-    __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
     if (type == T_ARRAY || type == T_OBJECT) {
+      __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
       __ verify_oop(dest->as_register());
+    } else {
+      __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
     }
 
   } else if (dest->is_double_cpu()) {
     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
-    __ movl(dest->as_register_hi(), src_addr_HI);
-    __ movl(dest->as_register_lo(), src_addr_LO);
+    __ movptr(dest->as_register_lo(), src_addr_LO);
+    NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
 
   } else if (dest->is_single_xmm()) {
     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
@@ -1019,15 +1114,25 @@
 
 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
   if (src->is_single_stack()) {
-    __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
-    __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+    if (type == T_OBJECT || type == T_ARRAY) {
+      __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
+      __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
+    } else {
+      __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
+      __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+    }
 
   } else if (src->is_double_stack()) {
+#ifdef _LP64
+    __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
+    __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
+#else
     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
-    // push and pop the part at src + 4, adding 4 for the previous push
-    __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 4 + 4));
-    __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 4 + 4));
+    // push and pop the part at src + wordSize, adding wordSize for the previous push
+    __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), wordSize));
+    __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), wordSize));
     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
+#endif // _LP64
 
   } else {
     ShouldNotReachHere();
@@ -1052,7 +1157,7 @@
         // so blow away the value of to_rinfo before loading a
         // partial word into it.  Do it here so that it precedes
         // the potential patch point below.
-        __ xorl(dest->as_register(), dest->as_register());
+        __ xorptr(dest->as_register(), dest->as_register());
       }
       break;
   }
@@ -1060,6 +1165,7 @@
   PatchingStub* patch = NULL;
   if (patch_code != lir_patch_none) {
     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+    assert(from_addr.disp() != 0, "must have");
   }
   if (info != NULL) {
     add_debug_info_for_null_check_here(info);
@@ -1091,13 +1197,21 @@
     case T_ADDRESS: // fall through
     case T_OBJECT:  // fall through
     case T_ARRAY:   // fall through
+#ifdef _LP64
+      __ movptr(dest->as_register(), from_addr);
+      break;
+#endif // _L64
     case T_INT:
-      __ movl(dest->as_register(), from_addr);
+      // %%% could this be a movl? this is safer but longer instruction
+      __ movl2ptr(dest->as_register(), from_addr);
       break;
 
     case T_LONG: {
       Register to_lo = dest->as_register_lo();
       Register to_hi = dest->as_register_hi();
+#ifdef _LP64
+      __ movptr(to_lo, as_Address_lo(addr));
+#else
       Register base = addr->base()->as_register();
       Register index = noreg;
       if (addr->index()->is_register()) {
@@ -1109,7 +1223,7 @@
         // array access so this code will never have to deal with
         // patches or null checks.
         assert(info == NULL && patch == NULL, "must be");
-        __ leal(to_hi, as_Address(addr));
+        __ lea(to_hi, as_Address(addr));
         __ movl(to_lo, Address(to_hi, 0));
         __ movl(to_hi, Address(to_hi, BytesPerWord));
       } else if (base == to_lo || index == to_lo) {
@@ -1132,6 +1246,7 @@
         }
         __ movl(to_hi, as_Address_hi(addr));
       }
+#endif // _LP64
       break;
     }
 
@@ -1140,12 +1255,13 @@
       Register dest_reg = dest->as_register();
       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
-        __ movsxb(dest_reg, from_addr);
+        __ movsbl(dest_reg, from_addr);
       } else {
         __ movb(dest_reg, from_addr);
         __ shll(dest_reg, 24);
         __ sarl(dest_reg, 24);
       }
+      // These are unsigned so the zero extension on 64bit is just what we need
       break;
     }
 
@@ -1153,22 +1269,26 @@
       Register dest_reg = dest->as_register();
       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
-        __ movzxw(dest_reg, from_addr);
+        __ movzwl(dest_reg, from_addr);
       } else {
         __ movw(dest_reg, from_addr);
       }
+      // This is unsigned so the zero extension on 64bit is just what we need
+      // __ movl2ptr(dest_reg, dest_reg);
       break;
     }
 
     case T_SHORT: {
       Register dest_reg = dest->as_register();
       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
-        __ movsxw(dest_reg, from_addr);
+        __ movswl(dest_reg, from_addr);
       } else {
         __ movw(dest_reg, from_addr);
         __ shll(dest_reg, 16);
         __ sarl(dest_reg, 16);
       }
+      // Might not be needed in 64bit but certainly doesn't hurt (except for code size)
+      __ movl2ptr(dest_reg, dest_reg);
       break;
     }
 
@@ -1306,9 +1426,13 @@
 
   switch (op->bytecode()) {
     case Bytecodes::_i2l:
+#ifdef _LP64
+      __ movl2ptr(dest->as_register_lo(), src->as_register());
+#else
       move_regs(src->as_register(), dest->as_register_lo());
       move_regs(src->as_register(), dest->as_register_hi());
       __ sarl(dest->as_register_hi(), 31);
+#endif // LP64
       break;
 
     case Bytecodes::_l2i:
@@ -1346,9 +1470,9 @@
     case Bytecodes::_i2f:
     case Bytecodes::_i2d:
       if (dest->is_single_xmm()) {
-        __ cvtsi2ss(dest->as_xmm_float_reg(), src->as_register());
+        __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
       } else if (dest->is_double_xmm()) {
-        __ cvtsi2sd(dest->as_xmm_double_reg(), src->as_register());
+        __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
       } else {
         assert(dest->fpu() == 0, "result must be on TOS");
         __ movl(Address(rsp, 0), src->as_register());
@@ -1359,9 +1483,9 @@
     case Bytecodes::_f2i:
     case Bytecodes::_d2i:
       if (src->is_single_xmm()) {
-        __ cvttss2si(dest->as_register(), src->as_xmm_float_reg());
+        __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
       } else if (src->is_double_xmm()) {
-        __ cvttsd2si(dest->as_register(), src->as_xmm_double_reg());
+        __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
       } else {
         assert(src->fpu() == 0, "input must be on TOS");
         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
@@ -1382,8 +1506,8 @@
       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
       assert(dest->fpu() == 0, "result must be on TOS");
 
-      __ movl(Address(rsp, 0),            src->as_register_lo());
-      __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
+      __ movptr(Address(rsp, 0),            src->as_register_lo());
+      NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
       __ fild_d(Address(rsp, 0));
       // float result is rounded later through spilling
       break;
@@ -1392,7 +1516,7 @@
     case Bytecodes::_d2l:
       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
       assert(src->fpu() == 0, "input must be on TOS");
-      assert(dest == FrameMap::rax_rdx_long_opr, "runtime stub places result in these registers");
+      assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
 
       // instruction sequence too long to inline it here
       {
@@ -1439,7 +1563,7 @@
     } else if (len == tmp3) {
       // everything is ok
     } else {
-      __ movl(tmp3, len);
+      __ mov(tmp3, len);
     }
     __ allocate_array(op->obj()->as_register(),
                       len,
@@ -1466,31 +1590,32 @@
 
     CodeStub* stub = op->stub();
     Label done;
-    __ cmpl(value, 0);
+    __ cmpptr(value, (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, done);
     add_debug_info_for_null_check_here(op->info_for_exception());
-    __ movl(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
-    __ movl(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
+    __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
+    __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
 
     // get instance klass
-    __ movl(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
+    __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
     // get super_check_offset
     __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
     // See if we get an immediate positive hit
-    __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+    __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
     __ jcc(Assembler::equal, done);
     // check for immediate negative hit
     __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
     __ jcc(Assembler::notEqual, *stub->entry());
     // check for self
-    __ cmpl(klass_RInfo, k_RInfo);
+    __ cmpptr(klass_RInfo, k_RInfo);
     __ jcc(Assembler::equal, done);
 
-    __ pushl(klass_RInfo);
-    __ pushl(k_RInfo);
+    __ push(klass_RInfo);
+    __ push(k_RInfo);
     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-    __ popl(klass_RInfo);
-    __ popl(k_RInfo);
+    __ pop(klass_RInfo);
+    __ pop(k_RInfo);
+    // result is a boolean
     __ cmpl(k_RInfo, 0);
     __ jcc(Assembler::equal, *stub->entry());
     __ bind(done);
@@ -1521,10 +1646,14 @@
     if (!k->is_loaded()) {
       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
     } else {
+#ifdef _LP64
+      __ movoop(k_RInfo, k->encoding());
+#else
       k_RInfo = noreg;
+#endif // _LP64
     }
     assert(obj != k_RInfo, "must be different");
-    __ cmpl(obj, 0);
+    __ cmpptr(obj, (int32_t)NULL_WORD);
     if (op->profiled_method() != NULL) {
       ciMethod* method = op->profiled_method();
       int bci          = op->profiled_bci();
@@ -1556,9 +1685,13 @@
       // get object classo
       // not a safepoint as obj null check happens earlier
       if (k->is_loaded()) {
+#ifdef _LP64
+        __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+#else
         __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+#endif // _LP64
       } else {
-        __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+        __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
 
       }
       __ jcc(Assembler::notEqual, *stub->entry());
@@ -1566,24 +1699,37 @@
     } else {
       // get object class
       // not a safepoint as obj null check happens earlier
-      __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+      __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
       if (k->is_loaded()) {
         // See if we get an immediate positive hit
+#ifdef _LP64
+        __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
+#else
         __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
+#endif // _LP64
         if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
           __ jcc(Assembler::notEqual, *stub->entry());
         } else {
           // See if we get an immediate positive hit
           __ jcc(Assembler::equal, done);
           // check for self
+#ifdef _LP64
+          __ cmpptr(klass_RInfo, k_RInfo);
+#else
           __ cmpoop(klass_RInfo, k->encoding());
+#endif // _LP64
           __ jcc(Assembler::equal, done);
 
-          __ pushl(klass_RInfo);
+          __ push(klass_RInfo);
+#ifdef _LP64
+          __ push(k_RInfo);
+#else
           __ pushoop(k->encoding());
+#endif // _LP64
           __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-          __ popl(klass_RInfo);
-          __ popl(klass_RInfo);
+          __ pop(klass_RInfo);
+          __ pop(klass_RInfo);
+          // result is a boolean
           __ cmpl(klass_RInfo, 0);
           __ jcc(Assembler::equal, *stub->entry());
         }
@@ -1591,20 +1737,21 @@
       } else {
         __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
         // See if we get an immediate positive hit
-        __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+        __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
         __ jcc(Assembler::equal, done);
         // check for immediate negative hit
         __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
         __ jcc(Assembler::notEqual, *stub->entry());
         // check for self
-        __ cmpl(klass_RInfo, k_RInfo);
+        __ cmpptr(klass_RInfo, k_RInfo);
         __ jcc(Assembler::equal, done);
 
-        __ pushl(klass_RInfo);
-        __ pushl(k_RInfo);
+        __ push(klass_RInfo);
+        __ push(k_RInfo);
         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-        __ popl(klass_RInfo);
-        __ popl(k_RInfo);
+        __ pop(klass_RInfo);
+        __ pop(k_RInfo);
+        // result is a boolean
         __ cmpl(k_RInfo, 0);
         __ jcc(Assembler::equal, *stub->entry());
         __ bind(done);
@@ -1612,7 +1759,7 @@
 
     }
     if (dst != obj) {
-      __ movl(dst, obj);
+      __ mov(dst, obj);
     }
   } else if (code == lir_instanceof) {
     Register obj = op->object()->as_register();
@@ -1632,29 +1779,33 @@
     // so let's do it before loading the class
     if (!k->is_loaded()) {
       jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+    } else {
+      LP64_ONLY(__ movoop(k_RInfo, k->encoding()));
     }
     assert(obj != k_RInfo, "must be different");
 
     __ verify_oop(obj);
     if (op->fast_check()) {
-      __ cmpl(obj, 0);
+      __ cmpptr(obj, (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, zero);
       // get object class
       // not a safepoint as obj null check happens earlier
-      if (k->is_loaded()) {
-        __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+      if (LP64_ONLY(false &&) k->is_loaded()) {
+        NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding()));
         k_RInfo = noreg;
       } else {
-        __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+        __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
 
       }
       __ jcc(Assembler::equal, one);
     } else {
       // get object class
       // not a safepoint as obj null check happens earlier
-      __ cmpl(obj, 0);
+      __ cmpptr(obj, (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, zero);
-      __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+      __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+
+#ifndef _LP64
       if (k->is_loaded()) {
         // See if we get an immediate positive hit
         __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
@@ -1663,40 +1814,43 @@
           // check for self
           __ cmpoop(klass_RInfo, k->encoding());
           __ jcc(Assembler::equal, one);
-          __ pushl(klass_RInfo);
+          __ push(klass_RInfo);
           __ pushoop(k->encoding());
           __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-          __ popl(klass_RInfo);
-          __ popl(dst);
+          __ pop(klass_RInfo);
+          __ pop(dst);
           __ jmp(done);
         }
       } else {
+#else
+      { // YUCK
+#endif // LP64
         assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
 
         __ movl(dst, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
         // See if we get an immediate positive hit
-        __ cmpl(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
+        __ cmpptr(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
         __ jcc(Assembler::equal, one);
         // check for immediate negative hit
         __ cmpl(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
         __ jcc(Assembler::notEqual, zero);
         // check for self
-        __ cmpl(klass_RInfo, k_RInfo);
+        __ cmpptr(klass_RInfo, k_RInfo);
         __ jcc(Assembler::equal, one);
 
-        __ pushl(klass_RInfo);
-        __ pushl(k_RInfo);
+        __ push(klass_RInfo);
+        __ push(k_RInfo);
         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
-        __ popl(klass_RInfo);
-        __ popl(dst);
+        __ pop(klass_RInfo);
+        __ pop(dst);
         __ jmp(done);
       }
     }
     __ bind(zero);
-    __ xorl(dst, dst);
+    __ xorptr(dst, dst);
     __ jmp(done);
     __ bind(one);
-    __ movl(dst, 1);
+    __ movptr(dst, 1);
     __ bind(done);
   } else {
     ShouldNotReachHere();
@@ -1706,8 +1860,7 @@
 
 
 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
-  if (op->code() == lir_cas_long) {
-    assert(VM_Version::supports_cx8(), "wrong machine");
+  if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
@@ -1716,10 +1869,11 @@
     if (os::is_MP()) {
       __ lock();
     }
-    __ cmpxchg8(Address(addr, 0));
-
-  } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
-    Register addr = op->addr()->as_register();
+    NOT_LP64(__ cmpxchg8(Address(addr, 0)));
+
+  } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
+    NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
+    Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
     Register newval = op->new_value()->as_register();
     Register cmpval = op->cmp_value()->as_register();
     assert(cmpval == rax, "wrong register");
@@ -1730,7 +1884,28 @@
     if (os::is_MP()) {
       __ lock();
     }
-    __ cmpxchg(newval, Address(addr, 0));
+    if ( op->code() == lir_cas_obj) {
+      __ cmpxchgptr(newval, Address(addr, 0));
+    } else if (op->code() == lir_cas_int) {
+      __ cmpxchgl(newval, Address(addr, 0));
+    } else {
+      LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
+    }
+#ifdef _LP64
+  } else if (op->code() == lir_cas_long) {
+    Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
+    Register newval = op->new_value()->as_register_lo();
+    Register cmpval = op->cmp_value()->as_register_lo();
+    assert(cmpval == rax, "wrong register");
+    assert(newval != NULL, "new val must be register");
+    assert(cmpval != newval, "cmp and new values must be in different registers");
+    assert(cmpval != addr, "cmp and addr must be in different registers");
+    assert(newval != addr, "new value and addr must be in different registers");
+    if (os::is_MP()) {
+      __ lock();
+    }
+    __ cmpxchgq(newval, Address(addr, 0));
+#endif // _LP64
   } else {
     Unimplemented();
   }
@@ -1765,17 +1940,17 @@
     // optimized version that does not require a branch
     if (opr2->is_single_cpu()) {
       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
-      __ cmovl(ncond, result->as_register(), opr2->as_register());
+      __ cmov(ncond, result->as_register(), opr2->as_register());
     } else if (opr2->is_double_cpu()) {
       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
-      __ cmovl(ncond, result->as_register_lo(), opr2->as_register_lo());
-      __ cmovl(ncond, result->as_register_hi(), opr2->as_register_hi());
+      __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
+      NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
     } else if (opr2->is_single_stack()) {
       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
     } else if (opr2->is_double_stack()) {
-      __ cmovl(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
-      __ cmovl(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));
+      __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
+      NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
     } else {
       ShouldNotReachHere();
     }
@@ -1851,23 +2026,28 @@
       // cpu register - cpu register
       Register rreg_lo = right->as_register_lo();
       Register rreg_hi = right->as_register_hi();
-      assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi);
+      NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
+      LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
       switch (code) {
         case lir_add:
-          __ addl(lreg_lo, rreg_lo);
-          __ adcl(lreg_hi, rreg_hi);
+          __ addptr(lreg_lo, rreg_lo);
+          NOT_LP64(__ adcl(lreg_hi, rreg_hi));
           break;
         case lir_sub:
-          __ subl(lreg_lo, rreg_lo);
-          __ sbbl(lreg_hi, rreg_hi);
+          __ subptr(lreg_lo, rreg_lo);
+          NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
           break;
         case lir_mul:
+#ifdef _LP64
+          __ imulq(lreg_lo, rreg_lo);
+#else
           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
           __ imull(lreg_hi, rreg_lo);
           __ imull(rreg_hi, lreg_lo);
           __ addl (rreg_hi, lreg_hi);
           __ mull (rreg_lo);
           __ addl (lreg_hi, rreg_hi);
+#endif // _LP64
           break;
         default:
           ShouldNotReachHere();
@@ -1875,20 +2055,35 @@
 
     } else if (right->is_constant()) {
       // cpu register - constant
+#ifdef _LP64
+      jlong c = right->as_constant_ptr()->as_jlong_bits();
+      __ movptr(r10, (intptr_t) c);
+      switch (code) {
+        case lir_add:
+          __ addptr(lreg_lo, r10);
+          break;
+        case lir_sub:
+          __ subptr(lreg_lo, r10);
+          break;
+        default:
+          ShouldNotReachHere();
+      }
+#else
       jint c_lo = right->as_constant_ptr()->as_jint_lo();
       jint c_hi = right->as_constant_ptr()->as_jint_hi();
       switch (code) {
         case lir_add:
-          __ addl(lreg_lo, c_lo);
+          __ addptr(lreg_lo, c_lo);
           __ adcl(lreg_hi, c_hi);
           break;
         case lir_sub:
-          __ subl(lreg_lo, c_lo);
+          __ subptr(lreg_lo, c_lo);
           __ sbbl(lreg_hi, c_hi);
           break;
         default:
           ShouldNotReachHere();
       }
+#endif // _LP64
 
     } else {
       ShouldNotReachHere();
@@ -2065,11 +2260,11 @@
       jint c = right->as_constant_ptr()->as_jint();
       switch (code) {
         case lir_add: {
-          __ increment(laddr, c);
+          __ incrementl(laddr, c);
           break;
         }
         case lir_sub: {
-          __ decrement(laddr, c);
+          __ decrementl(laddr, c);
           break;
         }
         default: ShouldNotReachHere();
@@ -2211,9 +2406,9 @@
     } else {
       Register rright = right->as_register();
       switch (code) {
-        case lir_logic_and: __ andl (reg, rright); break;
-        case lir_logic_or : __ orl  (reg, rright); break;
-        case lir_logic_xor: __ xorl (reg, rright); break;
+        case lir_logic_and: __ andptr (reg, rright); break;
+        case lir_logic_or : __ orptr  (reg, rright); break;
+        case lir_logic_xor: __ xorptr (reg, rright); break;
         default: ShouldNotReachHere();
       }
     }
@@ -2222,6 +2417,21 @@
     Register l_lo = left->as_register_lo();
     Register l_hi = left->as_register_hi();
     if (right->is_constant()) {
+#ifdef _LP64
+      __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
+      switch (code) {
+        case lir_logic_and:
+          __ andq(l_lo, rscratch1);
+          break;
+        case lir_logic_or:
+          __ orq(l_lo, rscratch1);
+          break;
+        case lir_logic_xor:
+          __ xorq(l_lo, rscratch1);
+          break;
+        default: ShouldNotReachHere();
+      }
+#else
       int r_lo = right->as_constant_ptr()->as_jint_lo();
       int r_hi = right->as_constant_ptr()->as_jint_hi();
       switch (code) {
@@ -2239,22 +2449,23 @@
           break;
         default: ShouldNotReachHere();
       }
+#endif // _LP64
     } else {
       Register r_lo = right->as_register_lo();
       Register r_hi = right->as_register_hi();
       assert(l_lo != r_hi, "overwriting registers");
       switch (code) {
         case lir_logic_and:
-          __ andl(l_lo, r_lo);
-          __ andl(l_hi, r_hi);
+          __ andptr(l_lo, r_lo);
+          NOT_LP64(__ andptr(l_hi, r_hi);)
           break;
         case lir_logic_or:
-          __ orl(l_lo, r_lo);
-          __ orl(l_hi, r_hi);
+          __ orptr(l_lo, r_lo);
+          NOT_LP64(__ orptr(l_hi, r_hi);)
           break;
         case lir_logic_xor:
-          __ xorl(l_lo, r_lo);
-          __ xorl(l_hi, r_hi);
+          __ xorptr(l_lo, r_lo);
+          NOT_LP64(__ xorptr(l_hi, r_hi);)
           break;
         default: ShouldNotReachHere();
       }
@@ -2263,6 +2474,9 @@
     Register dst_lo = dst->as_register_lo();
     Register dst_hi = dst->as_register_hi();
 
+#ifdef _LP64
+    move_regs(l_lo, dst_lo);
+#else
     if (dst_lo == l_hi) {
       assert(dst_hi != l_lo, "overwriting registers");
       move_regs(l_hi, dst_hi);
@@ -2272,6 +2486,7 @@
       move_regs(l_lo, dst_lo);
       move_regs(l_hi, dst_hi);
     }
+#endif // _LP64
   }
 }
 
@@ -2306,7 +2521,7 @@
       move_regs(lreg, dreg);
     } else if (code == lir_irem) {
       Label done;
-      __ movl(dreg, lreg);
+      __ mov(dreg, lreg);
       __ andl(dreg, 0x80000000 | (divisor - 1));
       __ jcc(Assembler::positive, done);
       __ decrement(dreg);
@@ -2340,21 +2555,36 @@
     Register reg1 = opr1->as_register();
     if (opr2->is_single_cpu()) {
       // cpu register - cpu register
-      __ cmpl(reg1, opr2->as_register());
+      if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+        __ cmpptr(reg1, opr2->as_register());
+      } else {
+        assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
+        __ cmpl(reg1, opr2->as_register());
+      }
     } else if (opr2->is_stack()) {
       // cpu register - stack
-      __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+      if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+        __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+      } else {
+        __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+      }
     } else if (opr2->is_constant()) {
       // cpu register - constant
       LIR_Const* c = opr2->as_constant_ptr();
       if (c->type() == T_INT) {
         __ cmpl(reg1, c->as_jint());
-      } else if (c->type() == T_OBJECT) {
+      } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+        // In 64bit oops are single register
         jobject o = c->as_jobject();
         if (o == NULL) {
-          __ cmpl(reg1, NULL_WORD);
+          __ cmpptr(reg1, (int32_t)NULL_WORD);
         } else {
+#ifdef _LP64
+          __ movoop(rscratch1, o);
+          __ cmpptr(reg1, rscratch1);
+#else
           __ cmpoop(reg1, c->as_jobject());
+#endif // _LP64
         }
       } else {
         ShouldNotReachHere();
@@ -2373,6 +2603,9 @@
     Register xlo = opr1->as_register_lo();
     Register xhi = opr1->as_register_hi();
     if (opr2->is_double_cpu()) {
+#ifdef _LP64
+      __ cmpptr(xlo, opr2->as_register_lo());
+#else
       // cpu register - cpu register
       Register ylo = opr2->as_register_lo();
       Register yhi = opr2->as_register_hi();
@@ -2381,11 +2614,16 @@
       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
         __ orl(xhi, xlo);
       }
+#endif // _LP64
     } else if (opr2->is_constant()) {
       // cpu register - constant 0
       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
+#ifdef _LP64
+      __ cmpptr(xlo, (int32_t)opr2->as_jlong());
+#else
       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
       __ orl(xhi, xlo);
+#endif // _LP64
     } else {
       ShouldNotReachHere();
     }
@@ -2438,16 +2676,28 @@
     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
 
   } else if (opr1->is_address() && opr2->is_constant()) {
+    LIR_Const* c = opr2->as_constant_ptr();
+#ifdef _LP64
+    if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+      assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
+      __ movoop(rscratch1, c->as_jobject());
+    }
+#endif // LP64
     if (op->info() != NULL) {
       add_debug_info_for_null_check_here(op->info());
     }
     // special case: address - constant
     LIR_Address* addr = opr1->as_address_ptr();
-    LIR_Const* c = opr2->as_constant_ptr();
     if (c->type() == T_INT) {
       __ cmpl(as_Address(addr), c->as_jint());
-    } else if (c->type() == T_OBJECT) {
+    } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+#ifdef _LP64
+      // %%% Make this explode if addr isn't reachable until we figure out a
+      // better strategy by giving noreg as the temp for as_Address
+      __ cmpptr(rscratch1, as_Address(addr, noreg));
+#else
       __ cmpoop(as_Address(addr), c->as_jobject());
+#endif // _LP64
     } else {
       ShouldNotReachHere();
     }
@@ -2476,11 +2726,27 @@
     }
   } else {
     assert(code == lir_cmp_l2i, "check");
+#ifdef _LP64
+      Register dest = dst->as_register();
+      __ xorptr(dest, dest);
+      Label high, done;
+      __ cmpptr(left->as_register_lo(), right->as_register_lo());
+      __ jcc(Assembler::equal, done);
+      __ jcc(Assembler::greater, high);
+      __ decrement(dest);
+      __ jmp(done);
+      __ bind(high);
+      __ increment(dest);
+
+      __ bind(done);
+
+#else
     __ lcmp2int(left->as_register_hi(),
                 left->as_register_lo(),
                 right->as_register_hi(),
                 right->as_register_lo());
     move_regs(left->as_register_hi(), dst->as_register());
+#endif // _LP64
   }
 }
 
@@ -2551,7 +2817,8 @@
   __ movoop(rbx, (jobject)NULL);
   // must be set to -1 at code generation time
   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
-  __ jump(RuntimeAddress((address)-1));
+  // On 64bit this will die since it will take a movq & jmp, must be only a jmp
+  __ jump(RuntimeAddress(__ pc()));
 
   assert(__ offset() - start <= call_stub_size, "stub too big")
   __ end_a_stub();
@@ -2616,6 +2883,14 @@
     Register lo = left->as_register_lo();
     Register hi = left->as_register_hi();
     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
+#ifdef _LP64
+    switch (code) {
+      case lir_shl:  __ shlptr(lo);        break;
+      case lir_shr:  __ sarptr(lo);        break;
+      case lir_ushr: __ shrptr(lo);        break;
+      default: ShouldNotReachHere();
+    }
+#else
 
     switch (code) {
       case lir_shl:  __ lshl(hi, lo);        break;
@@ -2623,6 +2898,7 @@
       case lir_ushr: __ lshr(hi, lo, false); break;
       default: ShouldNotReachHere();
     }
+#endif // LP64
   } else {
     ShouldNotReachHere();
   }
@@ -2643,7 +2919,21 @@
       default: ShouldNotReachHere();
     }
   } else if (dest->is_double_cpu()) {
+#ifndef _LP64
     Unimplemented();
+#else
+    // first move left into dest so that left is not destroyed by the shift
+    Register value = dest->as_register_lo();
+    count = count & 0x1F; // Java spec
+
+    move_regs(left->as_register_lo(), value);
+    switch (code) {
+      case lir_shl:  __ shlptr(value, count); break;
+      case lir_shr:  __ sarptr(value, count); break;
+      case lir_ushr: __ shrptr(value, count); break;
+      default: ShouldNotReachHere();
+    }
+#endif // _LP64
   } else {
     ShouldNotReachHere();
   }
@@ -2654,7 +2944,7 @@
   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
-  __ movl (Address(rsp, offset_from_rsp_in_bytes), r);
+  __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
 }
 
 
@@ -2662,7 +2952,7 @@
   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
-  __ movl (Address(rsp, offset_from_rsp_in_bytes), c);
+  __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
 }
 
 
@@ -2710,27 +3000,52 @@
     // these are just temporary placements until we need to reload
     store_parameter(src_pos, 3);
     store_parameter(src, 4);
-    assert(src == rcx && src_pos == rdx, "mismatch in calling convention");
+    NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
+
+    address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
 
     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
-    __ pushl(length);
-    __ pushl(dst_pos);
-    __ pushl(dst);
-    __ pushl(src_pos);
-    __ pushl(src);
-    address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
+#ifdef _LP64
+    // The arguments are in java calling convention so we can trivially shift them to C
+    // convention
+    assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
+    __ mov(c_rarg0, j_rarg0);
+    assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
+    __ mov(c_rarg1, j_rarg1);
+    assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
+    __ mov(c_rarg2, j_rarg2);
+    assert_different_registers(c_rarg3, j_rarg4);
+    __ mov(c_rarg3, j_rarg3);
+#ifdef _WIN64
+    // Allocate abi space for args but be sure to keep stack aligned
+    __ subptr(rsp, 6*wordSize);
+    store_parameter(j_rarg4, 4);
+    __ call(RuntimeAddress(entry));
+    __ addptr(rsp, 6*wordSize);
+#else
+    __ mov(c_rarg4, j_rarg4);
+    __ call(RuntimeAddress(entry));
+#endif // _WIN64
+#else
+    __ push(length);
+    __ push(dst_pos);
+    __ push(dst);
+    __ push(src_pos);
+    __ push(src);
     __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
 
+#endif // _LP64
+
     __ cmpl(rax, 0);
     __ jcc(Assembler::equal, *stub->continuation());
 
     // Reload values from the stack so they are where the stub
     // expects them.
-    __ movl (dst,     Address(rsp, 0*BytesPerWord));
-    __ movl (dst_pos, Address(rsp, 1*BytesPerWord));
-    __ movl (length,  Address(rsp, 2*BytesPerWord));
-    __ movl (src_pos, Address(rsp, 3*BytesPerWord));
-    __ movl (src,     Address(rsp, 4*BytesPerWord));
+    __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
+    __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
+    __ movptr   (length,  Address(rsp, 2*BytesPerWord));
+    __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
+    __ movptr   (src,     Address(rsp, 4*BytesPerWord));
     __ jmp(*stub->entry());
 
     __ bind(*stub->continuation());
@@ -2769,13 +3084,15 @@
   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
 
+  // length and pos's are all sign extended at this point on 64bit
+
   // test for NULL
   if (flags & LIR_OpArrayCopy::src_null_check) {
-    __ testl(src, src);
+    __ testptr(src, src);
     __ jcc(Assembler::zero, *stub->entry());
   }
   if (flags & LIR_OpArrayCopy::dst_null_check) {
-    __ testl(dst, dst);
+    __ testptr(dst, dst);
     __ jcc(Assembler::zero, *stub->entry());
   }
 
@@ -2794,19 +3111,19 @@
   }
 
   if (flags & LIR_OpArrayCopy::src_range_check) {
-    __ leal(tmp, Address(src_pos, length, Address::times_1, 0));
+    __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
     __ cmpl(tmp, src_length_addr);
     __ jcc(Assembler::above, *stub->entry());
   }
   if (flags & LIR_OpArrayCopy::dst_range_check) {
-    __ leal(tmp, Address(dst_pos, length, Address::times_1, 0));
+    __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
     __ cmpl(tmp, dst_length_addr);
     __ jcc(Assembler::above, *stub->entry());
   }
 
   if (flags & LIR_OpArrayCopy::type_check) {
-    __ movl(tmp, src_klass_addr);
-    __ cmpl(tmp, dst_klass_addr);
+    __ movptr(tmp, src_klass_addr);
+    __ cmpptr(tmp, dst_klass_addr);
     __ jcc(Assembler::notEqual, *stub->entry());
   }
 
@@ -2822,14 +3139,14 @@
     Label known_ok, halt;
     __ movoop(tmp, default_type->encoding());
     if (basic_type != T_OBJECT) {
-      __ cmpl(tmp, dst_klass_addr);
+      __ cmpptr(tmp, dst_klass_addr);
       __ jcc(Assembler::notEqual, halt);
-      __ cmpl(tmp, src_klass_addr);
+      __ cmpptr(tmp, src_klass_addr);
       __ jcc(Assembler::equal, known_ok);
     } else {
-      __ cmpl(tmp, dst_klass_addr);
+      __ cmpptr(tmp, dst_klass_addr);
       __ jcc(Assembler::equal, known_ok);
-      __ cmpl(src, dst);
+      __ cmpptr(src, dst);
       __ jcc(Assembler::equal, known_ok);
     }
     __ bind(halt);
@@ -2838,14 +3155,24 @@
   }
 #endif
 
-  __ leal(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+  if (shift_amount > 0 && basic_type != T_OBJECT) {
+    __ shlptr(length, shift_amount);
+  }
+
+#ifdef _LP64
+  assert_different_registers(c_rarg0, dst, dst_pos, length);
+  __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+  assert_different_registers(c_rarg1, length);
+  __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+  __ mov(c_rarg2, length);
+
+#else
+  __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
   store_parameter(tmp, 0);
-  __ leal(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+  __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
   store_parameter(tmp, 1);
-  if (shift_amount > 0 && basic_type != T_OBJECT) {
-    __ shll(length, shift_amount);
-  }
   store_parameter(length, 2);
+#endif // _LP64
   if (basic_type == T_OBJECT) {
     __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
   } else {
@@ -2945,13 +3272,13 @@
         }
       }
     } else {
-      __ movl(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
+      __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
       Label update_done;
       uint i;
       for (i = 0; i < VirtualCallData::row_limit(); i++) {
         Label next_test;
         // See if the receiver is receiver[n].
-        __ cmpl(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
+        __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
         __ jcc(Assembler::notEqual, next_test);
         Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
         __ addl(data_addr, DataLayout::counter_increment);
@@ -2963,9 +3290,9 @@
       for (i = 0; i < VirtualCallData::row_limit(); i++) {
         Label next_test;
         Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
-        __ cmpl(recv_addr, NULL_WORD);
+        __ cmpptr(recv_addr, (int32_t)NULL_WORD);
         __ jcc(Assembler::notEqual, next_test);
-        __ movl(recv_addr, recv);
+        __ movptr(recv_addr, recv);
         __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
         if (i < (VirtualCallData::row_limit() - 1)) {
           __ jmp(update_done);
@@ -2985,7 +3312,7 @@
 
 
 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
-  __ leal(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
+  __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
 }
 
 
@@ -3001,6 +3328,11 @@
 
   } else if (left->is_double_cpu()) {
     Register lo = left->as_register_lo();
+#ifdef _LP64
+    Register dst = dest->as_register_lo();
+    __ movptr(dst, lo);
+    __ negptr(dst);
+#else
     Register hi = left->as_register_hi();
     __ lneg(hi, lo);
     if (dest->as_register_lo() == hi) {
@@ -3011,6 +3343,7 @@
       move_regs(lo, dest->as_register_lo());
       move_regs(hi, dest->as_register_hi());
     }
+#endif // _LP64
 
   } else if (dest->is_single_xmm()) {
     if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
@@ -3039,8 +3372,9 @@
 
 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
   assert(addr->is_address() && dest->is_register(), "check");
-  Register reg = dest->as_register();
-  __ leal(dest->as_register(), as_Address(addr->as_address_ptr()));
+  Register reg;
+  reg = dest->as_pointer_register();
+  __ lea(reg, as_Address(addr->as_address_ptr()));
 }
 
 
@@ -3063,9 +3397,13 @@
 
   if (src->is_double_xmm()) {
     if (dest->is_double_cpu()) {
-      __ movd(dest->as_register_lo(), src->as_xmm_double_reg());
+#ifdef _LP64
+      __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
+#else
+      __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
       __ psrlq(src->as_xmm_double_reg(), 32);
-      __ movd(dest->as_register_hi(), src->as_xmm_double_reg());
+      __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
+#endif // _LP64
     } else if (dest->is_double_stack()) {
       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
     } else if (dest->is_address()) {
@@ -3109,7 +3447,8 @@
 
 
 void LIR_Assembler::membar() {
-  __ membar();
+  // QQQ sparc TSO uses this,
+  __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
 }
 
 void LIR_Assembler::membar_acquire() {
@@ -3124,7 +3463,12 @@
 
 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
   assert(result_reg->is_register(), "check");
+#ifdef _LP64
+  // __ get_thread(result_reg->as_register_lo());
+  __ mov(result_reg->as_register(), r15_thread);
+#else
   __ get_thread(result_reg->as_register());
+#endif // _LP64
 }
 
 
--- a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -36,13 +36,20 @@
   address float_constant(float f);
   address double_constant(double d);
 
+  bool is_literal_address(LIR_Address* addr);
+
+  // When we need to use something other than rscratch1 use this
+  // method.
+  Address as_Address(LIR_Address* addr, Register tmp);
+
+
 public:
 
   void store_parameter(Register r, int offset_from_esp_in_words);
   void store_parameter(jint c,     int offset_from_esp_in_words);
   void store_parameter(jobject c,  int offset_from_esp_in_words);
 
-  enum { call_stub_size = 15,
+  enum { call_stub_size = NOT_LP64(15) LP64_ONLY(28),
          exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175),
-         deopt_handler_size = 10
+         deopt_handler_size = NOT_LP64(10) LP64_ONLY(17)
        };
--- a/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -77,7 +77,7 @@
   switch (type->tag()) {
     case intTag:     opr = FrameMap::rax_opr;          break;
     case objectTag:  opr = FrameMap::rax_oop_opr;      break;
-    case longTag:    opr = FrameMap::rax_rdx_long_opr; break;
+    case longTag:    opr = FrameMap::long0_opr;        break;
     case floatTag:   opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr  : FrameMap::fpu0_float_opr;  break;
     case doubleTag:  opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr;  break;
 
@@ -117,12 +117,14 @@
 
 
 bool LIRGenerator::can_inline_as_constant(Value v) const {
+  if (v->type()->tag() == longTag) return false;
   return v->type()->tag() != objectTag ||
     (v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
 }
 
 
 bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
+  if (c->type() == T_LONG) return false;
   return c->type() != T_OBJECT || c->as_jobject() == NULL;
 }
 
@@ -155,6 +157,13 @@
     addr = new LIR_Address(array_opr,
                            offset_in_bytes + index_opr->as_jint() * elem_size, type);
   } else {
+#ifdef _LP64
+    if (index_opr->type() == T_INT) {
+      LIR_Opr tmp = new_register(T_LONG);
+      __ convert(Bytecodes::_i2l, index_opr, tmp);
+      index_opr = tmp;
+    }
+#endif // _LP64
     addr =  new LIR_Address(array_opr,
                             index_opr,
                             LIR_Address::scale(type),
@@ -164,7 +173,7 @@
     // This store will need a precise card mark, so go ahead and
     // compute the full adddres instead of computing once for the
     // store and again for the card mark.
-    LIR_Opr tmp = new_register(T_INT);
+    LIR_Opr tmp = new_pointer_register();
     __ leal(LIR_OprFact::address(addr), tmp);
     return new LIR_Address(tmp, 0, type);
   } else {
@@ -174,9 +183,8 @@
 
 
 void LIRGenerator::increment_counter(address counter, int step) {
-  LIR_Opr temp = new_register(T_INT);
-  LIR_Opr pointer = new_register(T_INT);
-  __ move(LIR_OprFact::intConst((int)counter), pointer);
+  LIR_Opr pointer = new_pointer_register();
+  __ move(LIR_OprFact::intptrConst(counter), pointer);
   LIR_Address* addr = new LIR_Address(pointer, 0, T_INT);
   increment_counter(addr, step);
 }
@@ -481,7 +489,7 @@
     left.load_item();
     right.load_item();
 
-    LIR_Opr reg = FrameMap::rax_rdx_long_opr;
+    LIR_Opr reg = FrameMap::long0_opr;
     arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
     LIR_Opr result = rlock_result(x);
     __ move(reg, result);
@@ -690,10 +698,10 @@
   LIRItem new_value (x->argument_at(2), this);  // replace field with new_value if it matches cmp_value
 
   // compare value must be in rdx,eax (hi,lo); may be destroyed by cmpxchg8 instruction
-  cmp_value.load_item_force(FrameMap::rax_rdx_long_opr);
+  cmp_value.load_item_force(FrameMap::long0_opr);
 
   // new value must be in rcx,ebx (hi,lo)
-  new_value.load_item_force(FrameMap::rbx_rcx_long_opr);
+  new_value.load_item_force(FrameMap::long1_opr);
 
   // object pointer register is overwritten with field address
   obj.load_item();
@@ -720,7 +728,10 @@
   LIRItem val   (x->argument_at(3), this);  // replace field with val if matches cmp
 
   assert(obj.type()->tag() == objectTag, "invalid type");
-  assert(offset.type()->tag() == intTag, "invalid type");
+
+  // In 64bit the type can be long, sparc doesn't have this assert
+  // assert(offset.type()->tag() == intTag, "invalid type");
+
   assert(cmp.type()->tag() == type->tag(), "invalid type");
   assert(val.type()->tag() == type->tag(), "invalid type");
 
@@ -735,8 +746,8 @@
     cmp.load_item_force(FrameMap::rax_opr);
     val.load_item();
   } else if (type == longType) {
-    cmp.load_item_force(FrameMap::rax_rdx_long_opr);
-    val.load_item_force(FrameMap::rbx_rcx_long_opr);
+    cmp.load_item_force(FrameMap::long0_opr);
+    val.load_item_force(FrameMap::long1_opr);
   } else {
     ShouldNotReachHere();
   }
@@ -833,12 +844,33 @@
   // operands for arraycopy must use fixed registers, otherwise
   // LinearScan will fail allocation (because arraycopy always needs a
   // call)
+
+#ifndef _LP64
   src.load_item_force     (FrameMap::rcx_oop_opr);
   src_pos.load_item_force (FrameMap::rdx_opr);
   dst.load_item_force     (FrameMap::rax_oop_opr);
   dst_pos.load_item_force (FrameMap::rbx_opr);
   length.load_item_force  (FrameMap::rdi_opr);
   LIR_Opr tmp =           (FrameMap::rsi_opr);
+#else
+
+  // The java calling convention will give us enough registers
+  // so that on the stub side the args will be perfect already.
+  // On the other slow/special case side we call C and the arg
+  // positions are not similar enough to pick one as the best.
+  // Also because the java calling convention is a "shifted" version
+  // of the C convention we can process the java args trivially into C
+  // args without worry of overwriting during the xfer
+
+  src.load_item_force     (FrameMap::as_oop_opr(j_rarg0));
+  src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
+  dst.load_item_force     (FrameMap::as_oop_opr(j_rarg2));
+  dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
+  length.load_item_force  (FrameMap::as_opr(j_rarg4));
+
+  LIR_Opr tmp =           FrameMap::as_opr(j_rarg5);
+#endif // LP64
+
   set_no_result(x);
 
   int flags;
@@ -857,7 +889,7 @@
     case T_FLOAT:  return FrameMap::fpu0_float_opr;
     case T_DOUBLE: return FrameMap::fpu0_double_opr;
     case T_INT:    return FrameMap::rax_opr;
-    case T_LONG:   return FrameMap::rax_rdx_long_opr;
+    case T_LONG:   return FrameMap::long0_opr;
     default:       ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
   }
 }
@@ -1161,9 +1193,13 @@
 
 
 LIR_Opr LIRGenerator::getThreadPointer() {
+#ifdef _LP64
+  return FrameMap::as_pointer_opr(r15_thread);
+#else
   LIR_Opr result = new_register(T_INT);
   __ get_thread(result);
   return result;
+#endif //
 }
 
 void LIRGenerator::trace_block_entry(BlockBegin* block) {
--- a/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -23,18 +23,29 @@
  */
 
 inline bool LinearScan::is_processed_reg_num(int reg_num) {
+#ifndef _LP64
   // rsp and rbp (numbers 6 ancd 7) are ignored
   assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
   assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
   assert(reg_num >= 0, "invalid reg_num");
 
   return reg_num < 6 || reg_num > 7;
+#else
+  // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
+  assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
+  assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
+  assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
+  assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
+  assert(reg_num >= 0, "invalid reg_num");
+
+  return reg_num < 12 || reg_num > 15;
+#endif // _LP64
 }
 
 inline int LinearScan::num_physical_regs(BasicType type) {
   // Intel requires two cpu registers for long,
   // but requires only one fpu register for double
-  if (type == T_LONG) {
+  if (LP64_ONLY(false &&) type == T_LONG) {
     return 2;
   }
   return 1;
--- a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -26,18 +26,17 @@
 #include "incls/_c1_MacroAssembler_x86.cpp.incl"
 
 int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr, Register scratch, Label& slow_case) {
-  const int aligned_mask = 3;
+  const int aligned_mask = BytesPerWord -1;
   const int hdr_offset = oopDesc::mark_offset_in_bytes();
   assert(hdr == rax, "hdr must be rax, for the cmpxchg instruction");
   assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
-  assert(BytesPerWord == 4, "adjust aligned_mask and code");
   Label done;
   int null_check_offset = -1;
 
   verify_oop(obj);
 
   // save object being locked into the BasicObjectLock
-  movl(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
+  movptr(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
 
   if (UseBiasedLocking) {
     assert(scratch != noreg, "should have scratch register at this point");
@@ -47,16 +46,16 @@
   }
 
   // Load object header
-  movl(hdr, Address(obj, hdr_offset));
+  movptr(hdr, Address(obj, hdr_offset));
   // and mark it as unlocked
-  orl(hdr, markOopDesc::unlocked_value);
+  orptr(hdr, markOopDesc::unlocked_value);
   // save unlocked object header into the displaced header location on the stack
-  movl(Address(disp_hdr, 0), hdr);
+  movptr(Address(disp_hdr, 0), hdr);
   // test if object header is still the same (i.e. unlocked), and if so, store the
   // displaced header address in the object header - if it is not the same, get the
   // object header instead
   if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
-  cmpxchg(disp_hdr, Address(obj, hdr_offset));
+  cmpxchgptr(disp_hdr, Address(obj, hdr_offset));
   // if the object header was the same, we're done
   if (PrintBiasedLockingStatistics) {
     cond_inc32(Assembler::equal,
@@ -76,11 +75,11 @@
   //
   // assuming both the stack pointer and page_size have their least
   // significant 2 bits cleared and page_size is a power of 2
-  subl(hdr, rsp);
-  andl(hdr, aligned_mask - os::vm_page_size());
+  subptr(hdr, rsp);
+  andptr(hdr, aligned_mask - os::vm_page_size());
   // for recursive locking, the result is zero => save it in the displaced header
   // location (NULL in the displaced hdr location indicates recursive locking)
-  movl(Address(disp_hdr, 0), hdr);
+  movptr(Address(disp_hdr, 0), hdr);
   // otherwise we don't care about the result and handle locking via runtime call
   jcc(Assembler::notZero, slow_case);
   // done
@@ -90,35 +89,34 @@
 
 
 void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_hdr, Label& slow_case) {
-  const int aligned_mask = 3;
+  const int aligned_mask = BytesPerWord -1;
   const int hdr_offset = oopDesc::mark_offset_in_bytes();
   assert(disp_hdr == rax, "disp_hdr must be rax, for the cmpxchg instruction");
   assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
-  assert(BytesPerWord == 4, "adjust aligned_mask and code");
   Label done;
 
   if (UseBiasedLocking) {
     // load object
-    movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+    movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
     biased_locking_exit(obj, hdr, done);
   }
 
   // load displaced header
-  movl(hdr, Address(disp_hdr, 0));
+  movptr(hdr, Address(disp_hdr, 0));
   // if the loaded hdr is NULL we had recursive locking
-  testl(hdr, hdr);
+  testptr(hdr, hdr);
   // if we had recursive locking, we are done
   jcc(Assembler::zero, done);
   if (!UseBiasedLocking) {
     // load object
-    movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+    movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
   }
   verify_oop(obj);
   // test if object header is pointing to the displaced header, and if so, restore
   // the displaced header in the object - if the object header is not pointing to
   // the displaced header, get the object header instead
   if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
-  cmpxchg(hdr, Address(obj, hdr_offset));
+  cmpxchgptr(hdr, Address(obj, hdr_offset));
   // if the object header was not pointing to the displaced header,
   // we do unlocking via runtime call
   jcc(Assembler::notEqual, slow_case);
@@ -141,13 +139,14 @@
   assert_different_registers(obj, klass, len);
   if (UseBiasedLocking && !len->is_valid()) {
     assert_different_registers(obj, klass, len, t1, t2);
-    movl(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-    movl(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
+    movptr(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+    movptr(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
   } else {
-    movl(Address(obj, oopDesc::mark_offset_in_bytes ()), (int)markOopDesc::prototype());
+    // This assumes that all prototype bits fit in an int32_t
+    movptr(Address(obj, oopDesc::mark_offset_in_bytes ()), (int32_t)(intptr_t)markOopDesc::prototype());
   }
 
-  movl(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
+  movptr(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
   if (len->is_valid()) {
     movl(Address(obj, arrayOopDesc::length_offset_in_bytes()), len);
   }
@@ -160,25 +159,27 @@
   assert(obj != len_in_bytes && obj != t1 && t1 != len_in_bytes, "registers must be different");
   assert((hdr_size_in_bytes & (BytesPerWord - 1)) == 0, "header size is not a multiple of BytesPerWord");
   Register index = len_in_bytes;
-  subl(index, hdr_size_in_bytes);
+  // index is positive and ptr sized
+  subptr(index, hdr_size_in_bytes);
   jcc(Assembler::zero, done);
   // initialize topmost word, divide index by 2, check if odd and test if zero
   // note: for the remaining code to work, index must be a multiple of BytesPerWord
 #ifdef ASSERT
   { Label L;
-    testl(index, BytesPerWord - 1);
+    testptr(index, BytesPerWord - 1);
     jcc(Assembler::zero, L);
     stop("index is not a multiple of BytesPerWord");
     bind(L);
   }
 #endif
-  xorl(t1, t1);      // use _zero reg to clear memory (shorter code)
+  xorptr(t1, t1);    // use _zero reg to clear memory (shorter code)
   if (UseIncDec) {
-    shrl(index, 3);  // divide by 8 and set carry flag if bit 2 was set
+    shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
   } else {
-    shrl(index, 2);  // use 2 instructions to avoid partial flag stall
-    shrl(index, 1);
+    shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
+    shrptr(index, 1);
   }
+#ifndef _LP64
   // index could have been not a multiple of 8 (i.e., bit 2 was set)
   { Label even;
     // note: if index was a multiple of 8, than it cannot
@@ -186,16 +187,17 @@
     //       => if it is even, we don't need to check for 0 again
     jcc(Assembler::carryClear, even);
     // clear topmost word (no jump needed if conditional assignment would work here)
-    movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
+    movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
     // index could be 0 now, need to check again
     jcc(Assembler::zero, done);
     bind(even);
   }
+#endif // !_LP64
   // initialize remaining object fields: rdx is a multiple of 2 now
   { Label loop;
     bind(loop);
-    movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
-    movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);
+    movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
+    NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);)
     decrement(index);
     jcc(Assembler::notZero, loop);
   }
@@ -227,30 +229,30 @@
   const Register index = t2;
   const int threshold = 6 * BytesPerWord;   // approximate break even point for code size (see comments below)
   if (var_size_in_bytes != noreg) {
-    movl(index, var_size_in_bytes);
+    mov(index, var_size_in_bytes);
     initialize_body(obj, index, hdr_size_in_bytes, t1_zero);
   } else if (con_size_in_bytes <= threshold) {
     // use explicit null stores
     // code size = 2 + 3*n bytes (n = number of fields to clear)
-    xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+    xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
     for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += BytesPerWord)
-      movl(Address(obj, i), t1_zero);
+      movptr(Address(obj, i), t1_zero);
   } else if (con_size_in_bytes > hdr_size_in_bytes) {
     // use loop to null out the fields
     // code size = 16 bytes for even n (n = number of fields to clear)
     // initialize last object field first if odd number of fields
-    xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
-    movl(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
+    xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+    movptr(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
     // initialize last object field if constant size is odd
     if (((con_size_in_bytes - hdr_size_in_bytes) & 4) != 0)
-      movl(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
+      movptr(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
     // initialize remaining object fields: rdx is a multiple of 2
     { Label loop;
       bind(loop);
-      movl(Address(obj, index, Address::times_8,
-        hdr_size_in_bytes - (1*BytesPerWord)), t1_zero);
-      movl(Address(obj, index, Address::times_8,
-        hdr_size_in_bytes - (2*BytesPerWord)), t1_zero);
+      movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (1*BytesPerWord)),
+             t1_zero);
+      NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)),
+             t1_zero);)
       decrement(index);
       jcc(Assembler::notZero, loop);
     }
@@ -269,17 +271,17 @@
   assert_different_registers(obj, len, t1, t2, klass);
 
   // determine alignment mask
-  assert(BytesPerWord == 4, "must be a multiple of 2 for masking code to work");
+  assert(!(BytesPerWord & 1), "must be a multiple of 2 for masking code to work");
 
   // check for negative or excessive length
-  cmpl(len, max_array_allocation_length);
+  cmpptr(len, (int32_t)max_array_allocation_length);
   jcc(Assembler::above, slow_case);
 
   const Register arr_size = t2; // okay to be the same
   // align object end
-  movl(arr_size, header_size * BytesPerWord + MinObjAlignmentInBytesMask);
-  leal(arr_size, Address(arr_size, len, f));
-  andl(arr_size, ~MinObjAlignmentInBytesMask);
+  movptr(arr_size, (int32_t)header_size * BytesPerWord + MinObjAlignmentInBytesMask);
+  lea(arr_size, Address(arr_size, len, f));
+  andptr(arr_size, ~MinObjAlignmentInBytesMask);
 
   try_allocate(obj, arr_size, 0, t1, t2, slow_case);
 
@@ -305,12 +307,13 @@
   // check against inline cache
   assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), "must add explicit null check");
   int start_offset = offset();
-  cmpl(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
+  cmpptr(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
   // if icache check fails, then jump to runtime routine
   // Note: RECEIVER must still contain the receiver!
   jump_cc(Assembler::notEqual,
           RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
-  assert(offset() - start_offset == 9, "check alignment in emit_method_entry");
+  const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
+  assert(offset() - start_offset == ic_cmp_size, "check alignment in emit_method_entry");
 }
 
 
@@ -364,7 +367,7 @@
 void C1_MacroAssembler::verify_not_null_oop(Register r) {
   if (!VerifyOops) return;
   Label not_null;
-  testl(r, r);
+  testptr(r, r);
   jcc(Assembler::notZero, not_null);
   stop("non-null oop required");
   bind(not_null);
@@ -373,12 +376,12 @@
 
 void C1_MacroAssembler::invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) {
 #ifdef ASSERT
-  if (inv_rax) movl(rax, 0xDEAD);
-  if (inv_rbx) movl(rbx, 0xDEAD);
-  if (inv_rcx) movl(rcx, 0xDEAD);
-  if (inv_rdx) movl(rdx, 0xDEAD);
-  if (inv_rsi) movl(rsi, 0xDEAD);
-  if (inv_rdi) movl(rdi, 0xDEAD);
+  if (inv_rax) movptr(rax, 0xDEAD);
+  if (inv_rbx) movptr(rbx, 0xDEAD);
+  if (inv_rcx) movptr(rcx, 0xDEAD);
+  if (inv_rdx) movptr(rdx, 0xDEAD);
+  if (inv_rsi) movptr(rsi, 0xDEAD);
+  if (inv_rdi) movptr(rdi, 0xDEAD);
 #endif
 }
 
--- a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -94,16 +94,17 @@
   // Note: NEVER push values directly, but only through following push_xxx functions;
   //       This helps us to track the rsp changes compared to the entry rsp (->_rsp_offset)
 
-  void push_jint (jint i)     { _rsp_offset++; pushl(i); }
+  void push_jint (jint i)     { _rsp_offset++; push(i); }
   void push_oop  (jobject o)  { _rsp_offset++; pushoop(o); }
-  void push_addr (Address a)  { _rsp_offset++; pushl(a); }
-  void push_reg  (Register r) { _rsp_offset++; pushl(r); }
-  void pop       (Register r) { _rsp_offset--; popl (r); assert(_rsp_offset >= 0, "stack offset underflow"); }
+  // Seems to always be in wordSize
+  void push_addr (Address a)  { _rsp_offset++; pushptr(a); }
+  void push_reg  (Register r) { _rsp_offset++; push(r); }
+  void pop_reg   (Register r) { _rsp_offset--; pop(r); assert(_rsp_offset >= 0, "stack offset underflow"); }
 
   void dec_stack (int nof_words) {
     _rsp_offset -= nof_words;
     assert(_rsp_offset >= 0, "stack offset underflow");
-    addl(rsp, wordSize * nof_words);
+    addptr(rsp, wordSize * nof_words);
   }
 
   void dec_stack_after_call (int nof_words) {
--- a/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -30,52 +30,58 @@
 
 int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, int args_size) {
   // setup registers
-  const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
+  const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
   assert(!(oop_result1->is_valid() || oop_result2->is_valid()) || oop_result1 != oop_result2, "registers must be different");
   assert(oop_result1 != thread && oop_result2 != thread, "registers must be different");
   assert(args_size >= 0, "illegal args_size");
 
+#ifdef _LP64
+  mov(c_rarg0, thread);
+  set_num_rt_args(0); // Nothing on stack
+#else
   set_num_rt_args(1 + args_size);
 
   // push java thread (becomes first argument of C function)
   get_thread(thread);
-  pushl(thread);
+  push(thread);
+#endif // _LP64
 
   set_last_Java_frame(thread, noreg, rbp, NULL);
+
   // do the call
   call(RuntimeAddress(entry));
   int call_offset = offset();
   // verify callee-saved register
 #ifdef ASSERT
   guarantee(thread != rax, "change this code");
-  pushl(rax);
+  push(rax);
   { Label L;
     get_thread(rax);
-    cmpl(thread, rax);
+    cmpptr(thread, rax);
     jcc(Assembler::equal, L);
     int3();
     stop("StubAssembler::call_RT: rdi not callee saved?");
     bind(L);
   }
-  popl(rax);
+  pop(rax);
 #endif
   reset_last_Java_frame(thread, true, false);
 
   // discard thread and arguments
-  addl(rsp, (1 + args_size)*BytesPerWord);
+  NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
 
   // check for pending exceptions
   { Label L;
-    cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     jcc(Assembler::equal, L);
     // exception pending => remove activation and forward to exception handler
-    movl(rax, Address(thread, Thread::pending_exception_offset()));
+    movptr(rax, Address(thread, Thread::pending_exception_offset()));
     // make sure that the vm_results are cleared
     if (oop_result1->is_valid()) {
-      movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+      movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
     }
     if (oop_result2->is_valid()) {
-      movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+      movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
     }
     if (frame_size() == no_frame_size) {
       leave();
@@ -89,13 +95,13 @@
   }
   // get oop results if there are any and reset the values in the thread
   if (oop_result1->is_valid()) {
-    movl(oop_result1, Address(thread, JavaThread::vm_result_offset()));
-    movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+    movptr(oop_result1, Address(thread, JavaThread::vm_result_offset()));
+    movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
     verify_oop(oop_result1);
   }
   if (oop_result2->is_valid()) {
-    movl(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
-    movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+    movptr(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
+    movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
     verify_oop(oop_result2);
   }
   return call_offset;
@@ -103,22 +109,58 @@
 
 
 int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {
-  pushl(arg1);
+#ifdef _LP64
+  mov(c_rarg1, arg1);
+#else
+  push(arg1);
+#endif // _LP64
   return call_RT(oop_result1, oop_result2, entry, 1);
 }
 
 
 int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {
-  pushl(arg2);
-  pushl(arg1);
+#ifdef _LP64
+  if (c_rarg1 == arg2) {
+    if (c_rarg2 == arg1) {
+      xchgq(arg1, arg2);
+    } else {
+      mov(c_rarg2, arg2);
+      mov(c_rarg1, arg1);
+    }
+  } else {
+    mov(c_rarg1, arg1);
+    mov(c_rarg2, arg2);
+  }
+#else
+  push(arg2);
+  push(arg1);
+#endif // _LP64
   return call_RT(oop_result1, oop_result2, entry, 2);
 }
 
 
 int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {
-  pushl(arg3);
-  pushl(arg2);
-  pushl(arg1);
+#ifdef _LP64
+  // if there is any conflict use the stack
+  if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
+      arg2 == c_rarg1 || arg1 == c_rarg3 ||
+      arg3 == c_rarg1 || arg1 == c_rarg2) {
+    push(arg3);
+    push(arg2);
+    push(arg1);
+    pop(c_rarg1);
+    pop(c_rarg2);
+    pop(c_rarg3);
+  } else {
+    mov(c_rarg1, arg1);
+    mov(c_rarg2, arg2);
+    mov(c_rarg3, arg3);
+  }
+#else
+  push(arg3);
+  push(arg2);
+  push(arg1);
+#endif // _LP64
   return call_RT(oop_result1, oop_result2, entry, 3);
 }
 
@@ -154,7 +196,7 @@
   //     + 3: argument with offset 1
   //     + 4: ...
 
-  __ movl(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
+  __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
 }
 
 
@@ -170,8 +212,8 @@
 
 #define __ sasm->
 
-const int float_regs_as_doubles_size_in_words = 16;
-const int xmm_regs_as_doubles_size_in_words = 16;
+const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
+const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
 
 // Stack layout for saving/restoring  all the registers needed during a runtime
 // call (this includes deoptimization)
@@ -180,29 +222,61 @@
 // but the code in save_live_registers will take the argument count into
 // account.
 //
+#ifdef _LP64
+  #define SLOT2(x) x,
+  #define SLOT_PER_WORD 2
+#else
+  #define SLOT2(x)
+  #define SLOT_PER_WORD 1
+#endif // _LP64
+
 enum reg_save_layout {
-  dummy1,
-  dummy2,
+  // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
+  // happen and will assert if the stack size we create is misaligned
+#ifdef _LP64
+  align_dummy_0, align_dummy_1,
+#endif // _LP64
+  dummy1, SLOT2(dummy1H)                                                                    // 0, 4
+  dummy2, SLOT2(dummy2H)                                                                    // 8, 12
   // Two temps to be used as needed by users of save/restore callee registers
-  temp_2_off,
-  temp_1_off,
-  xmm_regs_as_doubles_off,
-  float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_words,
-  fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_words,
-  fpu_state_end_off = fpu_state_off + FPUStateSizeInWords,
-  marker = fpu_state_end_off,
-  extra_space_offset,
+  temp_2_off, SLOT2(temp_2H_off)                                                            // 16, 20
+  temp_1_off, SLOT2(temp_1H_off)                                                            // 24, 28
+  xmm_regs_as_doubles_off,                                                                  // 32
+  float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots,  // 160
+  fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots,          // 224
+  // fpu_state_end_off is exclusive
+  fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD),                // 352
+  marker = fpu_state_end_off, SLOT2(markerH)                                                // 352, 356
+  extra_space_offset,                                                                       // 360
+#ifdef _LP64
+  r15_off = extra_space_offset, r15H_off,                                                   // 360, 364
+  r14_off, r14H_off,                                                                        // 368, 372
+  r13_off, r13H_off,                                                                        // 376, 380
+  r12_off, r12H_off,                                                                        // 384, 388
+  r11_off, r11H_off,                                                                        // 392, 396
+  r10_off, r10H_off,                                                                        // 400, 404
+  r9_off, r9H_off,                                                                          // 408, 412
+  r8_off, r8H_off,                                                                          // 416, 420
+  rdi_off, rdiH_off,                                                                        // 424, 428
+#else
   rdi_off = extra_space_offset,
-  rsi_off,
-  rbp_off,
-  rsp_off,
-  rbx_off,
-  rdx_off,
-  rcx_off,
-  rax_off,
-  saved_rbp_off,
-  return_off,
-  reg_save_frame_size,  // As noted: neglects any parameters to runtime
+#endif // _LP64
+  rsi_off, SLOT2(rsiH_off)                                                                  // 432, 436
+  rbp_off, SLOT2(rbpH_off)                                                                  // 440, 444
+  rsp_off, SLOT2(rspH_off)                                                                  // 448, 452
+  rbx_off, SLOT2(rbxH_off)                                                                  // 456, 460
+  rdx_off, SLOT2(rdxH_off)                                                                  // 464, 468
+  rcx_off, SLOT2(rcxH_off)                                                                  // 472, 476
+  rax_off, SLOT2(raxH_off)                                                                  // 480, 484
+  saved_rbp_off, SLOT2(saved_rbpH_off)                                                      // 488, 492
+  return_off, SLOT2(returnH_off)                                                            // 496, 500
+  reg_save_frame_size,  // As noted: neglects any parameters to runtime                     // 504
+
+#ifdef _WIN64
+  c_rarg0_off = rcx_off,
+#else
+  c_rarg0_off = rdi_off,
+#endif // WIN64
 
   // equates
 
@@ -229,18 +303,49 @@
 
 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
                                 bool save_fpu_registers = true) {
-  int frame_size = reg_save_frame_size + num_rt_args; // args + thread
-  sasm->set_frame_size(frame_size);
+
+  // In 64bit all the args are in regs so there are no additional stack slots
+  LP64_ONLY(num_rt_args = 0);
+  LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
+  int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
+  sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
 
   // record saved value locations in an OopMap
   // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
-  OopMap* map = new OopMap(frame_size, 0);
+  OopMap* map = new OopMap(frame_size_in_slots, 0);
   map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
   map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
   map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
   map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
   map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
   map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
+#ifdef _LP64
+  map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args),  r8->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args),  r9->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
+  map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
+
+  // This is stupid but needed.
+  map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
+
+  map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args),  r8->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args),  r9->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
+  map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
+#endif // _LP64
 
   if (save_fpu_registers) {
     if (UseSSE < 2) {
@@ -288,30 +393,31 @@
                                    bool save_fpu_registers = true) {
   __ block_comment("save_live_registers");
 
-  int frame_size = reg_save_frame_size + num_rt_args; // args + thread
+  // 64bit passes the args in regs to the c++ runtime
+  int frame_size_in_slots = reg_save_frame_size NOT_LP64(+ num_rt_args); // args + thread
   // frame_size = round_to(frame_size, 4);
-  sasm->set_frame_size(frame_size);
+  sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
 
-  __ pushad();         // integer registers
+  __ pusha();         // integer registers
 
   // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
   // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
 
-  __ subl(rsp, extra_space_offset * wordSize);
+  __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
 
 #ifdef ASSERT
-  __ movl(Address(rsp, marker * wordSize), 0xfeedbeef);
+  __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
 #endif
 
   if (save_fpu_registers) {
     if (UseSSE < 2) {
       // save FPU stack
-      __ fnsave(Address(rsp, fpu_state_off * wordSize));
+      __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
       __ fwait();
 
 #ifdef ASSERT
       Label ok;
-      __ cmpw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
+      __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
       __ jccb(Assembler::equal, ok);
       __ stop("corrupted control word detected");
       __ bind(ok);
@@ -321,18 +427,18 @@
       // since fstp_d can cause FPU stack underflow exceptions.  Write it
       // into the on stack copy and then reload that to make sure that the
       // current and future values are correct.
-      __ movw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
-      __ frstor(Address(rsp, fpu_state_off * wordSize));
+      __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
+      __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
 
       // Save the FPU registers in de-opt-able form
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord +  0));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord +  8));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 16));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 24));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 32));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 40));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 48));
-      __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 56));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+      __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
     }
 
     if (UseSSE >= 2) {
@@ -341,24 +447,34 @@
       // so always save them as doubles.
       // note that float values are _not_ converted automatically, so for float values
       // the second word contains only garbage data.
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize +  0), xmm0);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize +  8), xmm1);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
-      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0), xmm0);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8), xmm1);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
+#ifdef _LP64
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
+      __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
+#endif // _LP64
     } else if (UseSSE == 1) {
       // save XMM registers as float because double not supported without SSE2
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize +  0), xmm0);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize +  8), xmm1);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
-      __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0), xmm0);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8), xmm1);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+      __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
     }
   }
 
@@ -373,28 +489,38 @@
   if (restore_fpu_registers) {
     if (UseSSE >= 2) {
       // restore XMM registers
-      __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize +  0));
-      __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize +  8));
-      __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
-      __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
-      __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
-      __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
-      __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
-      __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+      __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0));
+      __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8));
+      __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+      __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+      __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+      __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+      __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+      __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
+#ifdef _LP64
+      __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
+      __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
+      __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
+      __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
+      __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
+      __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
+      __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
+      __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
+#endif // _LP64
     } else if (UseSSE == 1) {
       // restore XMM registers
-      __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize +  0));
-      __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize +  8));
-      __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
-      __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
-      __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
-      __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
-      __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
-      __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+      __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  0));
+      __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size +  8));
+      __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+      __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+      __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+      __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+      __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+      __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
     }
 
     if (UseSSE < 2) {
-      __ frstor(Address(rsp, fpu_state_off * wordSize));
+      __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
     } else {
       // check that FPU stack is really empty
       __ verify_FPU(0, "restore_live_registers");
@@ -408,14 +534,14 @@
 #ifdef ASSERT
   {
     Label ok;
-    __ cmpl(Address(rsp, marker * wordSize), 0xfeedbeef);
+    __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
     __ jcc(Assembler::equal, ok);
     __ stop("bad offsets in frame");
     __ bind(ok);
   }
-#endif
+#endif // ASSERT
 
-  __ addl(rsp, extra_space_offset * wordSize);
+  __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
 }
 
 
@@ -423,7 +549,7 @@
   __ block_comment("restore_live_registers");
 
   restore_fpu(sasm, restore_fpu_registers);
-  __ popad();
+  __ popa();
 }
 
 
@@ -432,14 +558,35 @@
 
   restore_fpu(sasm, restore_fpu_registers);
 
-  __ popl(rdi);
-  __ popl(rsi);
-  __ popl(rbp);
-  __ popl(rbx); // skip this value
-  __ popl(rbx);
-  __ popl(rdx);
-  __ popl(rcx);
-  __ addl(rsp, 4);
+#ifdef _LP64
+  __ movptr(r15, Address(rsp, 0));
+  __ movptr(r14, Address(rsp, wordSize));
+  __ movptr(r13, Address(rsp, 2 * wordSize));
+  __ movptr(r12, Address(rsp, 3 * wordSize));
+  __ movptr(r11, Address(rsp, 4 * wordSize));
+  __ movptr(r10, Address(rsp, 5 * wordSize));
+  __ movptr(r9,  Address(rsp, 6 * wordSize));
+  __ movptr(r8,  Address(rsp, 7 * wordSize));
+  __ movptr(rdi, Address(rsp, 8 * wordSize));
+  __ movptr(rsi, Address(rsp, 9 * wordSize));
+  __ movptr(rbp, Address(rsp, 10 * wordSize));
+  // skip rsp
+  __ movptr(rbx, Address(rsp, 12 * wordSize));
+  __ movptr(rdx, Address(rsp, 13 * wordSize));
+  __ movptr(rcx, Address(rsp, 14 * wordSize));
+
+  __ addptr(rsp, 16 * wordSize);
+#else
+
+  __ pop(rdi);
+  __ pop(rsi);
+  __ pop(rbp);
+  __ pop(rbx); // skip this value
+  __ pop(rbx);
+  __ pop(rdx);
+  __ pop(rcx);
+  __ addptr(rsp, BytesPerWord);
+#endif // _LP64
 }
 
 
@@ -465,10 +612,13 @@
 
   // load argument for exception that is passed as an argument into the stub
   if (has_argument) {
-    __ movl(temp_reg, Address(rbp, 2*BytesPerWord));
-    __ pushl(temp_reg);
+#ifdef _LP64
+    __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
+#else
+    __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
+    __ push(temp_reg);
+#endif // _LP64
   }
-
   int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
 
   OopMapSet* oop_maps = new OopMapSet();
@@ -486,7 +636,7 @@
   const Register exception_pc = rdx;
   // other registers used in this stub
   const Register real_return_addr = rbx;
-  const Register thread = rdi;
+  const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
 
   __ block_comment("generate_handle_exception");
 
@@ -503,19 +653,19 @@
   __ verify_not_null_oop(exception_oop);
 
   // load address of JavaThread object for thread-local data
-  __ get_thread(thread);
+  NOT_LP64(__ get_thread(thread);)
 
 #ifdef ASSERT
   // check that fields in JavaThread for exception oop and issuing pc are
   // empty before writing to them
   Label oop_empty;
-  __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+  __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
   __ jcc(Assembler::equal, oop_empty);
   __ stop("exception oop already set");
   __ bind(oop_empty);
 
   Label pc_empty;
-  __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+  __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
   __ jcc(Assembler::equal, pc_empty);
   __ stop("exception pc already set");
   __ bind(pc_empty);
@@ -523,15 +673,15 @@
 
   // save exception oop and issuing pc into JavaThread
   // (exception handler will load it from here)
-  __ movl(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
-  __ movl(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
+  __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
+  __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
 
   // save real return address (pc that called this stub)
-  __ movl(real_return_addr, Address(rbp, 1*BytesPerWord));
-  __ movl(Address(rsp, temp_1_off * BytesPerWord), real_return_addr);
+  __ movptr(real_return_addr, Address(rbp, 1*BytesPerWord));
+  __ movptr(Address(rsp, temp_1_off * VMRegImpl::stack_slot_size), real_return_addr);
 
   // patch throwing pc into return address (has bci & oop map)
-  __ movl(Address(rbp, 1*BytesPerWord), exception_pc);
+  __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
 
   // compute the exception handler.
   // the exception oop and the throwing pc are read from the fields in JavaThread
@@ -548,12 +698,12 @@
   // Do we have an exception handler in the nmethod?
   Label no_handler;
   Label done;
-  __ testl(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, no_handler);
 
   // exception handler found
   // patch the return address -> the stub will directly return to the exception handler
-  __ movl(Address(rbp, 1*BytesPerWord), rax);
+  __ movptr(Address(rbp, 1*BytesPerWord), rax);
 
   // restore registers
   restore_live_registers(sasm, save_fpu_registers);
@@ -568,18 +718,18 @@
   // there is no need to restore the registers
 
   // restore the real return address that was saved before the RT-call
-  __ movl(real_return_addr, Address(rsp, temp_1_off * BytesPerWord));
-  __ movl(Address(rbp, 1*BytesPerWord), real_return_addr);
+  __ movptr(real_return_addr, Address(rsp, temp_1_off * VMRegImpl::stack_slot_size));
+  __ movptr(Address(rbp, 1*BytesPerWord), real_return_addr);
 
   // load address of JavaThread object for thread-local data
-  __ get_thread(thread);
+  NOT_LP64(__ get_thread(thread);)
   // restore exception oop into rax, (convention for unwind code)
-  __ movl(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
+  __ movptr(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
 
   // clear exception fields in JavaThread because they are no longer needed
   // (fields must be cleared because they are processed by GC otherwise)
-  __ movl(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
-  __ movl(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
+  __ movptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
+  __ movptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
 
   // pop the stub frame off
   __ leave();
@@ -595,22 +745,22 @@
   // other registers used in this stub
   const Register exception_pc = rdx;
   const Register handler_addr = rbx;
-  const Register thread = rdi;
+  const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
 
   // verify that only rax, is valid at this time
   __ invalidate_registers(false, true, true, true, true, true);
 
 #ifdef ASSERT
   // check that fields in JavaThread for exception oop and issuing pc are empty
-  __ get_thread(thread);
+  NOT_LP64(__ get_thread(thread);)
   Label oop_empty;
-  __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+  __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
   __ jcc(Assembler::equal, oop_empty);
   __ stop("exception oop must be empty");
   __ bind(oop_empty);
 
   Label pc_empty;
-  __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+  __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
   __ jcc(Assembler::equal, pc_empty);
   __ stop("exception pc must be empty");
   __ bind(pc_empty);
@@ -622,12 +772,12 @@
   // leave activation of nmethod
   __ leave();
   // store return address (is on top of stack after leave)
-  __ movl(exception_pc, Address(rsp, 0));
+  __ movptr(exception_pc, Address(rsp, 0));
 
   __ verify_oop(exception_oop);
 
   // save exception oop from rax, to stack before call
-  __ pushl(exception_oop);
+  __ push(exception_oop);
 
   // search the exception handler address of the caller (using the return address)
   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), exception_pc);
@@ -637,17 +787,17 @@
   __ invalidate_registers(false, true, true, true, true, true);
 
   // move result of call into correct register
-  __ movl(handler_addr, rax);
+  __ movptr(handler_addr, rax);
 
   // restore exception oop in rax, (required convention of exception handler)
-  __ popl(exception_oop);
+  __ pop(exception_oop);
 
   __ verify_oop(exception_oop);
 
   // get throwing pc (= return address).
   // rdx has been destroyed by the call, so it must be set again
   // the pop is also necessary to simulate the effect of a ret(0)
-  __ popl(exception_pc);
+  __ pop(exception_pc);
 
   // verify that that there is really a valid exception in rax,
   __ verify_not_null_oop(exception_oop);
@@ -677,12 +827,18 @@
 
   OopMap* oop_map = save_live_registers(sasm, num_rt_args);
 
-  __ pushl(rax); // push dummy
+#ifdef _LP64
+  const Register thread = r15_thread;
+  // No need to worry about dummy
+  __ mov(c_rarg0, thread);
+#else
+  __ push(rax); // push dummy
 
   const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
   // push java thread (becomes first argument of C function)
   __ get_thread(thread);
-  __ pushl(thread);
+  __ push(thread);
+#endif // _LP64
   __ set_last_Java_frame(thread, noreg, rbp, NULL);
   // do the call
   __ call(RuntimeAddress(target));
@@ -691,27 +847,29 @@
   // verify callee-saved register
 #ifdef ASSERT
   guarantee(thread != rax, "change this code");
-  __ pushl(rax);
+  __ push(rax);
   { Label L;
     __ get_thread(rax);
-    __ cmpl(thread, rax);
+    __ cmpptr(thread, rax);
     __ jcc(Assembler::equal, L);
-    __ stop("StubAssembler::call_RT: rdi not callee saved?");
+    __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
     __ bind(L);
   }
-  __ popl(rax);
+  __ pop(rax);
 #endif
   __ reset_last_Java_frame(thread, true, false);
-  __ popl(rcx); // discard thread arg
-  __ popl(rcx); // discard dummy
+#ifndef _LP64
+  __ pop(rcx); // discard thread arg
+  __ pop(rcx); // discard dummy
+#endif // _LP64
 
   // check for pending exceptions
   { Label L;
-    __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, L);
     // exception pending => remove activation and forward to exception handler
 
-    __ testl(rax, rax);                                   // have we deoptimized?
+    __ testptr(rax, rax);                                   // have we deoptimized?
     __ jump_cc(Assembler::equal,
                RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
 
@@ -719,38 +877,38 @@
     // JavaThread, so copy and clear pending exception.
 
     // load and clear pending exception
-    __ movl(rax, Address(thread, Thread::pending_exception_offset()));
-    __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
+    __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
 
     // check that there is really a valid exception
     __ verify_not_null_oop(rax);
 
     // load throwing pc: this is the return address of the stub
-    __ movl(rdx, Address(rsp, return_off * BytesPerWord));
+    __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
 
 #ifdef ASSERT
     // check that fields in JavaThread for exception oop and issuing pc are empty
     Label oop_empty;
-    __ cmpoop(Address(thread, JavaThread::exception_oop_offset()), 0);
+    __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, oop_empty);
     __ stop("exception oop must be empty");
     __ bind(oop_empty);
 
     Label pc_empty;
-    __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+    __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, pc_empty);
     __ stop("exception pc must be empty");
     __ bind(pc_empty);
 #endif
 
     // store exception oop and throwing pc to JavaThread
-    __ movl(Address(thread, JavaThread::exception_oop_offset()), rax);
-    __ movl(Address(thread, JavaThread::exception_pc_offset()), rdx);
+    __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
+    __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
 
     restore_live_registers(sasm);
 
     __ leave();
-    __ addl(rsp, 4);  // remove return address from stack
+    __ addptr(rsp, BytesPerWord);  // remove return address from stack
 
     // Forward the exception directly to deopt blob. We can blow no
     // registers and must leave throwing pc on the stack.  A patch may
@@ -767,7 +925,7 @@
 
   Label reexecuteEntry, cont;
 
-  __ testl(rax, rax);                                   // have we deoptimized?
+  __ testptr(rax, rax);                                 // have we deoptimized?
   __ jcc(Assembler::equal, cont);                       // no
 
   // Will reexecute. Proper return address is already on the stack we just restore
@@ -806,21 +964,21 @@
         // dispatch to the handler if found.  Otherwise unwind and
         // dispatch to the callers exception handler.
 
-        const Register thread = rdi;
+        const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
         const Register exception_oop = rax;
         const Register exception_pc = rdx;
 
         // load pending exception oop into rax,
-        __ movl(exception_oop, Address(thread, Thread::pending_exception_offset()));
+        __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
         // clear pending exception
-        __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+        __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
 
         // load issuing PC (the return address for this stub) into rdx
-        __ movl(exception_pc, Address(rbp, 1*BytesPerWord));
+        __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
 
         // make sure that the vm_results are cleared (may be unnecessary)
-        __ movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
-        __ movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+        __ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+        __ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
 
         // verify that that there is really a valid exception in rax,
         __ verify_not_null_oop(exception_oop);
@@ -857,8 +1015,8 @@
           Register t2       = rsi;
           assert_different_registers(klass, obj, obj_size, t1, t2);
 
-          __ pushl(rdi);
-          __ pushl(rbx);
+          __ push(rdi);
+          __ push(rbx);
 
           if (id == fast_new_instance_init_check_id) {
             // make sure the klass is initialized
@@ -889,28 +1047,28 @@
 
           __ bind(retry_tlab);
 
-          // get the instance size
+          // get the instance size (size is postive so movl is fine for 64bit)
           __ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
           __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
           __ initialize_object(obj, klass, obj_size, 0, t1, t2);
           __ verify_oop(obj);
-          __ popl(rbx);
-          __ popl(rdi);
+          __ pop(rbx);
+          __ pop(rdi);
           __ ret(0);
 
           __ bind(try_eden);
-          // get the instance size
+          // get the instance size (size is postive so movl is fine for 64bit)
           __ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
           __ eden_allocate(obj, obj_size, 0, t1, slow_path);
           __ initialize_object(obj, klass, obj_size, 0, t1, t2);
           __ verify_oop(obj);
-          __ popl(rbx);
-          __ popl(rdi);
+          __ pop(rbx);
+          __ pop(rdi);
           __ ret(0);
 
           __ bind(slow_path);
-          __ popl(rbx);
-          __ popl(rdi);
+          __ pop(rbx);
+          __ pop(rdi);
         }
 
         __ enter();
@@ -996,15 +1154,17 @@
           __ bind(retry_tlab);
 
           // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+          // since size is postive movl does right thing on 64bit
           __ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+          // since size is postive movl does right thing on 64bit
           __ movl(arr_size, length);
           assert(t1 == rcx, "fixed register usage");
-          __ shll(arr_size /* by t1=rcx, mod 32 */);
-          __ shrl(t1, Klass::_lh_header_size_shift);
-          __ andl(t1, Klass::_lh_header_size_mask);
-          __ addl(arr_size, t1);
-          __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
-          __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+          __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+          __ shrptr(t1, Klass::_lh_header_size_shift);
+          __ andptr(t1, Klass::_lh_header_size_mask);
+          __ addptr(arr_size, t1);
+          __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+          __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
 
           __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path);  // preserves arr_size
 
@@ -1012,24 +1172,26 @@
           __ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
           assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
           assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
-          __ andl(t1, Klass::_lh_header_size_mask);
-          __ subl(arr_size, t1);  // body length
-          __ addl(t1, obj);       // body start
+          __ andptr(t1, Klass::_lh_header_size_mask);
+          __ subptr(arr_size, t1);  // body length
+          __ addptr(t1, obj);       // body start
           __ initialize_body(t1, arr_size, 0, t2);
           __ verify_oop(obj);
           __ ret(0);
 
           __ bind(try_eden);
           // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+          // since size is postive movl does right thing on 64bit
           __ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+          // since size is postive movl does right thing on 64bit
           __ movl(arr_size, length);
           assert(t1 == rcx, "fixed register usage");
-          __ shll(arr_size /* by t1=rcx, mod 32 */);
-          __ shrl(t1, Klass::_lh_header_size_shift);
-          __ andl(t1, Klass::_lh_header_size_mask);
-          __ addl(arr_size, t1);
-          __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
-          __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+          __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+          __ shrptr(t1, Klass::_lh_header_size_shift);
+          __ andptr(t1, Klass::_lh_header_size_mask);
+          __ addptr(arr_size, t1);
+          __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+          __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
 
           __ eden_allocate(obj, arr_size, 0, t1, slow_path);  // preserves arr_size
 
@@ -1037,9 +1199,9 @@
           __ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
           assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
           assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
-          __ andl(t1, Klass::_lh_header_size_mask);
-          __ subl(arr_size, t1);  // body length
-          __ addl(t1, obj);       // body start
+          __ andptr(t1, Klass::_lh_header_size_mask);
+          __ subptr(arr_size, t1);  // body length
+          __ addptr(t1, obj);       // body start
           __ initialize_body(t1, arr_size, 0, t2);
           __ verify_oop(obj);
           __ ret(0);
@@ -1089,15 +1251,23 @@
       {
         __ set_info("register_finalizer", dont_gc_arguments);
 
+        // This is called via call_runtime so the arguments
+        // will be place in C abi locations
+
+#ifdef _LP64
+        __ verify_oop(c_rarg0);
+        __ mov(rax, c_rarg0);
+#else
         // The object is passed on the stack and we haven't pushed a
         // frame yet so it's one work away from top of stack.
-        __ movl(rax, Address(rsp, 1 * BytesPerWord));
+        __ movptr(rax, Address(rsp, 1 * BytesPerWord));
         __ verify_oop(rax);
+#endif // _LP64
 
         // load the klass and check the has finalizer flag
         Label register_finalizer;
         Register t = rsi;
-        __ movl(t, Address(rax, oopDesc::klass_offset_in_bytes()));
+        __ movptr(t, Address(rax, oopDesc::klass_offset_in_bytes()));
         __ movl(t, Address(t, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc)));
         __ testl(t, JVM_ACC_HAS_FINALIZER);
         __ jcc(Assembler::notZero, register_finalizer);
@@ -1185,46 +1355,49 @@
     case slow_subtype_check_id:
       {
         enum layout {
-          rax_off,
-          rcx_off,
-          rsi_off,
-          rdi_off,
-          saved_rbp_off,
-          return_off,
-          sub_off,
-          super_off,
+          rax_off, SLOT2(raxH_off)
+          rcx_off, SLOT2(rcxH_off)
+          rsi_off, SLOT2(rsiH_off)
+          rdi_off, SLOT2(rdiH_off)
+          // saved_rbp_off, SLOT2(saved_rbpH_off)
+          return_off, SLOT2(returnH_off)
+          sub_off, SLOT2(subH_off)
+          super_off, SLOT2(superH_off)
           framesize
         };
 
         __ set_info("slow_subtype_check", dont_gc_arguments);
-        __ pushl(rdi);
-        __ pushl(rsi);
-        __ pushl(rcx);
-        __ pushl(rax);
-        __ movl(rsi, Address(rsp, (super_off - 1) * BytesPerWord)); // super
-        __ movl(rax, Address(rsp, (sub_off   - 1) * BytesPerWord)); // sub
+        __ push(rdi);
+        __ push(rsi);
+        __ push(rcx);
+        __ push(rax);
 
-        __ movl(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
-        __ movl(rcx,Address(rdi,arrayOopDesc::length_offset_in_bytes()));
-        __ addl(rdi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+        // This is called by pushing args and not with C abi
+        __ movptr(rsi, Address(rsp, (super_off) * VMRegImpl::stack_slot_size)); // super
+        __ movptr(rax, Address(rsp, (sub_off  ) * VMRegImpl::stack_slot_size)); // sub
+
+        __ movptr(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
+        // since size is postive movl does right thing on 64bit
+        __ movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
+        __ addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
 
         Label miss;
         __ repne_scan();
         __ jcc(Assembler::notEqual, miss);
-        __ movl(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
-        __ movl(Address(rsp, (super_off   - 1) * BytesPerWord), 1); // result
-        __ popl(rax);
-        __ popl(rcx);
-        __ popl(rsi);
-        __ popl(rdi);
+        __ movptr(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
+        __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 1); // result
+        __ pop(rax);
+        __ pop(rcx);
+        __ pop(rsi);
+        __ pop(rdi);
         __ ret(0);
 
         __ bind(miss);
-        __ movl(Address(rsp, (super_off   - 1) * BytesPerWord), 0); // result
-        __ popl(rax);
-        __ popl(rcx);
-        __ popl(rsi);
-        __ popl(rdi);
+        __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 0); // result
+        __ pop(rax);
+        __ pop(rcx);
+        __ pop(rsi);
+        __ pop(rdi);
         __ ret(0);
       }
       break;
@@ -1237,6 +1410,8 @@
         StubFrame f(sasm, "monitorenter", dont_gc_arguments);
         OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
 
+        // Called with store_parameter and not C abi
+
         f.load_argument(1, rax); // rax,: object
         f.load_argument(0, rbx); // rbx,: lock address
 
@@ -1256,6 +1431,8 @@
         StubFrame f(sasm, "monitorexit", dont_gc_arguments);
         OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
 
+        // Called with store_parameter and not C abi
+
         f.load_argument(0, rax); // rax,: lock address
 
         // note: really a leaf routine but must setup last java sp
@@ -1304,9 +1481,9 @@
         // the live registers get saved.
         save_live_registers(sasm, 1);
 
-        __ pushl(rax);
+        __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
         __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
-        __ popl(rax);
+        NOT_LP64(__ pop(rax));
 
         restore_live_registers(sasm);
       }
@@ -1316,18 +1493,19 @@
       {
         // rax, and rdx are destroyed, but should be free since the result is returned there
         // preserve rsi,ecx
-        __ pushl(rsi);
-        __ pushl(rcx);
+        __ push(rsi);
+        __ push(rcx);
+        LP64_ONLY(__ push(rdx);)
 
         // check for NaN
         Label return0, do_return, return_min_jlong, do_convert;
 
-        Address value_high_word(rsp, 8);
-        Address value_low_word(rsp, 4);
-        Address result_high_word(rsp, 16);
-        Address result_low_word(rsp, 12);
+        Address value_high_word(rsp, wordSize + 4);
+        Address value_low_word(rsp, wordSize);
+        Address result_high_word(rsp, 3*wordSize + 4);
+        Address result_low_word(rsp, 3*wordSize);
 
-        __ subl(rsp, 20);
+        __ subptr(rsp, 32);                    // more than enough on 32bit
         __ fst_d(value_low_word);
         __ movl(rax, value_high_word);
         __ andl(rax, 0x7ff00000);
@@ -1340,7 +1518,7 @@
 
         __ bind(do_convert);
         __ fnstcw(Address(rsp, 0));
-        __ movzxw(rax, Address(rsp, 0));
+        __ movzwl(rax, Address(rsp, 0));
         __ orl(rax, 0xc00);
         __ movw(Address(rsp, 2), rax);
         __ fldcw(Address(rsp, 2));
@@ -1348,9 +1526,11 @@
         __ fistp_d(result_low_word);
         __ fldcw(Address(rsp, 0));
         __ fwait();
-        __ movl(rax, result_low_word);
+        // This gets the entire long in rax on 64bit
+        __ movptr(rax, result_low_word);
+        // testing of high bits
         __ movl(rdx, result_high_word);
-        __ movl(rcx, rax);
+        __ mov(rcx, rax);
         // What the heck is the point of the next instruction???
         __ xorl(rcx, 0x0);
         __ movl(rsi, 0x80000000);
@@ -1360,34 +1540,52 @@
         __ fldz();
         __ fcomp_d(value_low_word);
         __ fnstsw_ax();
+#ifdef _LP64
+        __ testl(rax, 0x4100);  // ZF & CF == 0
+        __ jcc(Assembler::equal, return_min_jlong);
+#else
         __ sahf();
         __ jcc(Assembler::above, return_min_jlong);
+#endif // _LP64
         // return max_jlong
+#ifndef _LP64
         __ movl(rdx, 0x7fffffff);
         __ movl(rax, 0xffffffff);
+#else
+        __ mov64(rax, CONST64(0x7fffffffffffffff));
+#endif // _LP64
         __ jmp(do_return);
 
         __ bind(return_min_jlong);
+#ifndef _LP64
         __ movl(rdx, 0x80000000);
         __ xorl(rax, rax);
+#else
+        __ mov64(rax, CONST64(0x8000000000000000));
+#endif // _LP64
         __ jmp(do_return);
 
         __ bind(return0);
         __ fpop();
-        __ xorl(rdx,rdx);
-        __ xorl(rax,rax);
+#ifndef _LP64
+        __ xorptr(rdx,rdx);
+        __ xorptr(rax,rax);
+#else
+        __ xorptr(rax, rax);
+#endif // _LP64
 
         __ bind(do_return);
-        __ addl(rsp, 20);
-        __ popl(rcx);
-        __ popl(rsi);
+        __ addptr(rsp, 32);
+        LP64_ONLY(__ pop(rdx);)
+        __ pop(rcx);
+        __ pop(rsi);
         __ ret(0);
       }
       break;
 
     default:
       { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
-        __ movl(rax, (int)id);
+        __ movptr(rax, (int)id);
         __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
         __ should_not_reach_here();
       }
--- a/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -44,6 +44,14 @@
 Label fast_accessor_slow_entry_path;  // fast accessor methods need to be able to jmp to unsynchronized
                                       // c++ interpreter entry point this holds that entry point label.
 
+// default registers for state and sender_sp
+// state and sender_sp are the same on 32bit because we have no choice.
+// state could be rsi on 64bit but it is an arg reg and not callee save
+// so r13 is better choice.
+
+const Register state = NOT_LP64(rsi) LP64_ONLY(r13);
+const Register sender_sp_on_entry = NOT_LP64(rsi) LP64_ONLY(r13);
+
 // NEEDED for JVMTI?
 // address AbstractInterpreter::_remove_activation_preserving_args_entry;
 
@@ -88,7 +96,6 @@
 
 
 address CppInterpreterGenerator::generate_result_handler_for(BasicType type) {
-  const Register state   = rsi;                                    // current activation object, valid on entry
   address entry = __ pc();
   switch (type) {
     case T_BOOLEAN: __ c2bool(rax);            break;
@@ -98,19 +105,22 @@
     case T_VOID   : // fall thru
     case T_LONG   : // fall thru
     case T_INT    : /* nothing to do */        break;
+
     case T_DOUBLE :
     case T_FLOAT  :
-      { const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
-        __ popl(t);                            // remove return address first
-        __ pop_dtos_to_rsp();
+      {
+        const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
+        __ pop(t);                            // remove return address first
         // Must return a result for interpreter or compiler. In SSE
         // mode, results are returned in xmm0 and the FPU stack must
         // be empty.
         if (type == T_FLOAT && UseSSE >= 1) {
+#ifndef _LP64
           // Load ST0
           __ fld_d(Address(rsp, 0));
           // Store as float and empty fpu stack
           __ fstp_s(Address(rsp, 0));
+#endif // !_LP64
           // and reload
           __ movflt(xmm0, Address(rsp, 0));
         } else if (type == T_DOUBLE && UseSSE >= 2 ) {
@@ -120,13 +130,13 @@
           __ fld_d(Address(rsp, 0));
         }
         // and pop the temp
-        __ addl(rsp, 2 * wordSize);
-        __ pushl(t);                           // restore return address
+        __ addptr(rsp, 2 * wordSize);
+        __ push(t);                            // restore return address
       }
       break;
     case T_OBJECT :
       // retrieve result from frame
-      __ movl(rax, STATE(_oop_temp));
+      __ movptr(rax, STATE(_oop_temp));
       // and verify it
       __ verify_oop(rax);
       break;
@@ -146,7 +156,7 @@
   address entry = __ pc();
 
   const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
-  __ popl(t);                            // remove return address first
+  __ pop(t);                            // remove return address first
   switch (type) {
     case T_VOID:
        break;
@@ -154,53 +164,53 @@
 #ifdef EXTEND
       __ c2bool(rax);
 #endif
-      __ pushl(rax);
+      __ push(rax);
       break;
     case T_CHAR   :
 #ifdef EXTEND
       __ andl(rax, 0xFFFF);
 #endif
-      __ pushl(rax);
+      __ push(rax);
       break;
     case T_BYTE   :
 #ifdef EXTEND
       __ sign_extend_byte (rax);
 #endif
-      __ pushl(rax);
+      __ push(rax);
       break;
     case T_SHORT  :
 #ifdef EXTEND
       __ sign_extend_short(rax);
 #endif
-      __ pushl(rax);
+      __ push(rax);
       break;
     case T_LONG    :
-      __ pushl(rdx);
-      __ pushl(rax);
+      __ push(rdx);                             // pushes useless junk on 64bit
+      __ push(rax);
       break;
     case T_INT    :
-      __ pushl(rax);
+      __ push(rax);
       break;
     case T_FLOAT  :
-      // Result is in ST(0)
+      // Result is in ST(0)/xmm0
+      __ subptr(rsp, wordSize);
       if ( UseSSE < 1) {
-        __ push(ftos);                           // and save it
+        __ fstp_s(Address(rsp, 0));
       } else {
-        __ subl(rsp, wordSize);
         __ movflt(Address(rsp, 0), xmm0);
       }
       break;
     case T_DOUBLE  :
+      __ subptr(rsp, 2*wordSize);
       if ( UseSSE < 2 ) {
-        __ push(dtos);                           // put ST0 on java stack
+        __ fstp_d(Address(rsp, 0));
       } else {
-        __ subl(rsp, 2*wordSize);
         __ movdbl(Address(rsp, 0), xmm0);
       }
       break;
     case T_OBJECT :
       __ verify_oop(rax);                      // verify it
-      __ pushl(rax);
+      __ push(rax);
       break;
     default       : ShouldNotReachHere();
   }
@@ -212,7 +222,7 @@
   // A result is in the java expression stack of the interpreted method that has just
   // returned. Place this result on the java expression stack of the caller.
   //
-  // The current interpreter activation in rsi is for the method just returning its
+  // The current interpreter activation in rsi/r13 is for the method just returning its
   // result. So we know that the result of this method is on the top of the current
   // execution stack (which is pre-pushed) and will be return to the top of the caller
   // stack. The top of the callers stack is the bottom of the locals of the current
@@ -222,20 +232,19 @@
   // of the calling activation. This enable this routine to leave the return address
   // to the frame manager on the stack and do a vanilla return.
   //
-  // On entry: rsi - interpreter state of activation returning a (potential) result
-  // On Return: rsi - unchanged
+  // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+  // On Return: rsi/r13 - unchanged
   //            rax - new stack top for caller activation (i.e. activation in _prev_link)
   //
   // Can destroy rdx, rcx.
   //
 
   address entry = __ pc();
-  const Register state   = rsi;                                    // current activation object, valid on entry
   const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
   switch (type) {
     case T_VOID:
-      __ movl(rax, STATE(_locals));                                     // pop parameters get new stack value
-      __ addl(rax, wordSize);                                           // account for prepush before we return
+      __ movptr(rax, STATE(_locals));                                   // pop parameters get new stack value
+      __ addptr(rax, wordSize);                                         // account for prepush before we return
       break;
     case T_FLOAT  :
     case T_BOOLEAN:
@@ -244,10 +253,10 @@
     case T_SHORT  :
     case T_INT    :
       // 1 word result
-      __ movl(rdx, STATE(_stack));
-      __ movl(rax, STATE(_locals));                                     // address for result
+      __ movptr(rdx, STATE(_stack));
+      __ movptr(rax, STATE(_locals));                                   // address for result
       __ movl(rdx, Address(rdx, wordSize));                             // get result
-      __ movl(Address(rax, 0), rdx);                                    // and store it
+      __ movptr(Address(rax, 0), rdx);                                  // and store it
       break;
     case T_LONG    :
     case T_DOUBLE  :
@@ -256,20 +265,20 @@
       // except we allocated one extra word for this intepretState so we won't overwrite it
       // when we return a two word result.
 
-      __ movl(rax, STATE(_locals));                                     // address for result
-      __ movl(rcx, STATE(_stack));
-      __ subl(rax, wordSize);                                           // need addition word besides locals[0]
-      __ movl(rdx, Address(rcx, 2*wordSize));                           // get result word
-      __ movl(Address(rax, wordSize), rdx);                             // and store it
-      __ movl(rdx, Address(rcx, wordSize));                             // get result word
-      __ movl(Address(rax, 0), rdx);                                    // and store it
+      __ movptr(rax, STATE(_locals));                                   // address for result
+      __ movptr(rcx, STATE(_stack));
+      __ subptr(rax, wordSize);                                         // need addition word besides locals[0]
+      __ movptr(rdx, Address(rcx, 2*wordSize));                         // get result word (junk in 64bit)
+      __ movptr(Address(rax, wordSize), rdx);                           // and store it
+      __ movptr(rdx, Address(rcx, wordSize));                           // get result word
+      __ movptr(Address(rax, 0), rdx);                                  // and store it
       break;
     case T_OBJECT :
-      __ movl(rdx, STATE(_stack));
-      __ movl(rax, STATE(_locals));                                     // address for result
-      __ movl(rdx, Address(rdx, wordSize));                             // get result
+      __ movptr(rdx, STATE(_stack));
+      __ movptr(rax, STATE(_locals));                                   // address for result
+      __ movptr(rdx, Address(rdx, wordSize));                           // get result
       __ verify_oop(rdx);                                               // verify it
-      __ movl(Address(rax, 0), rdx);                                    // and store it
+      __ movptr(Address(rax, 0), rdx);                                  // and store it
       break;
     default       : ShouldNotReachHere();
   }
@@ -285,12 +294,11 @@
   // frame manager execept in this situation the caller is native code (c1/c2/call_stub)
   // and so rather than return result onto caller's java expression stack we return the
   // result in the expected location based on the native abi.
-  // On entry: rsi - interpreter state of activation returning a (potential) result
-  // On Return: rsi - unchanged
+  // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+  // On Return: rsi/r13 - unchanged
   // Other registers changed [rax/rdx/ST(0) as needed for the result returned]
 
   address entry = __ pc();
-  const Register state   = rsi;                                    // current activation object, valid on entry
   switch (type) {
     case T_VOID:
        break;
@@ -299,17 +307,16 @@
     case T_BYTE   :
     case T_SHORT  :
     case T_INT    :
-      __ movl(rdx, STATE(_stack));                                      // get top of stack
+      __ movptr(rdx, STATE(_stack));                                    // get top of stack
       __ movl(rax, Address(rdx, wordSize));                             // get result word 1
       break;
     case T_LONG    :
-      __ movl(rdx, STATE(_stack));                                      // get top of stack
-      __ movl(rax, Address(rdx, wordSize));                             // get result low word
-      __ movl(rdx, Address(rdx, 2*wordSize));                           // get result high word
-      break;
+      __ movptr(rdx, STATE(_stack));                                    // get top of stack
+      __ movptr(rax, Address(rdx, wordSize));                           // get result low word
+      NOT_LP64(__ movl(rdx, Address(rdx, 2*wordSize));)                 // get result high word
       break;
     case T_FLOAT  :
-      __ movl(rdx, STATE(_stack));                                      // get top of stack
+      __ movptr(rdx, STATE(_stack));                                    // get top of stack
       if ( UseSSE >= 1) {
         __ movflt(xmm0, Address(rdx, wordSize));
       } else {
@@ -317,7 +324,7 @@
       }
       break;
     case T_DOUBLE  :
-      __ movl(rdx, STATE(_stack));                                      // get top of stack
+      __ movptr(rdx, STATE(_stack));                                    // get top of stack
       if ( UseSSE > 1) {
         __ movdbl(xmm0, Address(rdx, wordSize));
       } else {
@@ -325,8 +332,8 @@
       }
       break;
     case T_OBJECT :
-      __ movl(rdx, STATE(_stack));                                      // get top of stack
-      __ movl(rax, Address(rdx, wordSize));                             // get result word 1
+      __ movptr(rdx, STATE(_stack));                                    // get top of stack
+      __ movptr(rax, Address(rdx, wordSize));                           // get result word 1
       __ verify_oop(rax);                                               // verify it
       break;
     default       : ShouldNotReachHere();
@@ -408,54 +415,58 @@
 
   if (!native) {
 #ifdef PRODUCT
-    __ subl(rsp, 2*wordSize);
+    __ subptr(rsp, 2*wordSize);
 #else /* PRODUCT */
-    __ pushl((int)NULL);
-    __ pushl(state);                         // make it look like a real argument
+    __ push((int32_t)NULL_WORD);
+    __ push(state);                         // make it look like a real argument
 #endif /* PRODUCT */
   }
 
   // Now that we are assure of space for stack result, setup typical linkage
 
-  __ pushl(rax);
+  __ push(rax);
   __ enter();
 
-  __ movl(rax, state);                                 // save current state
-
-  __ leal(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
-  __ movl(state, rsp);
-
-  // rsi == state/locals rax == prevstate
+  __ mov(rax, state);                                  // save current state
+
+  __ lea(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
+  __ mov(state, rsp);
+
+  // rsi/r13 == state/locals rax == prevstate
 
   // initialize the "shadow" frame so that use since C++ interpreter not directly
   // recursive. Simpler to recurse but we can't trim expression stack as we call
   // new methods.
-  __ movl(STATE(_locals), locals);                      // state->_locals = locals()
-  __ movl(STATE(_self_link), state);                    // point to self
-  __ movl(STATE(_prev_link), rax);                      // state->_link = state on entry (NULL or previous state)
-  __ movl(STATE(_sender_sp), sender_sp);                // state->_sender_sp = sender_sp
+  __ movptr(STATE(_locals), locals);                    // state->_locals = locals()
+  __ movptr(STATE(_self_link), state);                  // point to self
+  __ movptr(STATE(_prev_link), rax);                    // state->_link = state on entry (NULL or previous state)
+  __ movptr(STATE(_sender_sp), sender_sp);              // state->_sender_sp = sender_sp
+#ifdef _LP64
+  __ movptr(STATE(_thread), r15_thread);                // state->_bcp = codes()
+#else
   __ get_thread(rax);                                   // get vm's javathread*
-  __ movl(STATE(_thread), rax);                         // state->_bcp = codes()
-  __ movl(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
-  __ leal(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
+  __ movptr(STATE(_thread), rax);                       // state->_bcp = codes()
+#endif // _LP64
+  __ movptr(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
+  __ lea(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
   if (native) {
-    __ movl(STATE(_bcp), (intptr_t)NULL);               // state->_bcp = NULL
+    __ movptr(STATE(_bcp), (int32_t)NULL_WORD);         // state->_bcp = NULL
   } else {
-    __ movl(STATE(_bcp), rdx);                          // state->_bcp = codes()
+    __ movptr(STATE(_bcp), rdx);                        // state->_bcp = codes()
   }
-  __ xorl(rdx, rdx);
-  __ movl(STATE(_oop_temp), rdx);                       // state->_oop_temp = NULL (only really needed for native)
-  __ movl(STATE(_mdx), rdx);                            // state->_mdx = NULL
-  __ movl(rdx, Address(rbx, methodOopDesc::constants_offset()));
-  __ movl(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
-  __ movl(STATE(_constants), rdx);                      // state->_constants = constants()
-
-  __ movl(STATE(_method), rbx);                         // state->_method = method()
-  __ movl(STATE(_msg), (int) BytecodeInterpreter::method_entry);   // state->_msg = initial method entry
-  __ movl(STATE(_result._to_call._callee), (int) NULL); // state->_result._to_call._callee_callee = NULL
-
-
-  __ movl(STATE(_monitor_base), rsp);                   // set monitor block bottom (grows down) this would point to entry [0]
+  __ xorptr(rdx, rdx);
+  __ movptr(STATE(_oop_temp), rdx);                     // state->_oop_temp = NULL (only really needed for native)
+  __ movptr(STATE(_mdx), rdx);                          // state->_mdx = NULL
+  __ movptr(rdx, Address(rbx, methodOopDesc::constants_offset()));
+  __ movptr(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
+  __ movptr(STATE(_constants), rdx);                    // state->_constants = constants()
+
+  __ movptr(STATE(_method), rbx);                       // state->_method = method()
+  __ movl(STATE(_msg), (int32_t) BytecodeInterpreter::method_entry);   // state->_msg = initial method entry
+  __ movptr(STATE(_result._to_call._callee), (int32_t) NULL_WORD); // state->_result._to_call._callee_callee = NULL
+
+
+  __ movptr(STATE(_monitor_base), rsp);                 // set monitor block bottom (grows down) this would point to entry [0]
                                                         // entries run from -1..x where &monitor[x] ==
 
   {
@@ -479,36 +490,44 @@
     const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
     __ movl(rax, access_flags);
     __ testl(rax, JVM_ACC_STATIC);
-    __ movl(rax, Address(locals, 0));                     // get receiver (assume this is frequent case)
+    __ movptr(rax, Address(locals, 0));                   // get receiver (assume this is frequent case)
     __ jcc(Assembler::zero, done);
-    __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
-    __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movl(rax, Address(rax, mirror_offset));
+    __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(rax, Address(rax, mirror_offset));
     __ bind(done);
     // add space for monitor & lock
-    __ subl(rsp, entry_size);                                             // add space for a monitor entry
-    __ movl(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax);   // store object
+    __ subptr(rsp, entry_size);                                           // add space for a monitor entry
+    __ movptr(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
     __ bind(not_synced);
   }
 
-  __ movl(STATE(_stack_base), rsp);                                     // set expression stack base ( == &monitors[-count])
+  __ movptr(STATE(_stack_base), rsp);                                     // set expression stack base ( == &monitors[-count])
   if (native) {
-    __ movl(STATE(_stack), rsp);                                          // set current expression stack tos
-    __ movl(STATE(_stack_limit), rsp);
+    __ movptr(STATE(_stack), rsp);                                        // set current expression stack tos
+    __ movptr(STATE(_stack_limit), rsp);
   } else {
-    __ subl(rsp, wordSize);                                               // pre-push stack
-    __ movl(STATE(_stack), rsp);                                          // set current expression stack tos
+    __ subptr(rsp, wordSize);                                             // pre-push stack
+    __ movptr(STATE(_stack), rsp);                                        // set current expression stack tos
 
     // compute full expression stack limit
 
     const Address size_of_stack    (rbx, methodOopDesc::max_stack_offset());
     __ load_unsigned_word(rdx, size_of_stack);                            // get size of expression stack in words
-    __ negl(rdx);                                                         // so we can subtract in next step
+    __ negptr(rdx);                                                       // so we can subtract in next step
     // Allocate expression stack
-    __ leal(rsp, Address(rsp, rdx, Address::times_4));
-    __ movl(STATE(_stack_limit), rsp);
+    __ lea(rsp, Address(rsp, rdx, Address::times_ptr));
+    __ movptr(STATE(_stack_limit), rsp);
   }
 
+#ifdef _LP64
+  // Make sure stack is properly aligned and sized for the abi
+  __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+  __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+#endif // _LP64
+
+
+
 }
 
 // Helpers for commoning out cases in the various type of method entries.
@@ -528,7 +547,7 @@
   const Address backedge_counter  (rbx, methodOopDesc::backedge_counter_offset() + InvocationCounter::counter_offset());
 
   if (ProfileInterpreter) { // %%% Merge this into methodDataOop
-    __ increment(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
+    __ incrementl(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
   }
   // Update standard invocation counters
   __ movl(rax, backedge_counter);               // load backedge counter
@@ -552,7 +571,7 @@
 void InterpreterGenerator::generate_counter_overflow(Label* do_continue) {
 
   // C++ interpreter on entry
-  // rsi - new interpreter state pointer
+  // rsi/r13 - new interpreter state pointer
   // rbp - interpreter frame pointer
   // rbx - method
 
@@ -563,7 +582,7 @@
   // rsp - sender_sp
 
   // C++ interpreter only
-  // rsi - previous interpreter state pointer
+  // rsi/r13 - previous interpreter state pointer
 
   const Address size_of_parameters(rbx, methodOopDesc::size_of_parameters_offset());
 
@@ -571,16 +590,14 @@
   // indicating if the counter overflow occurs at a backwards branch (non-NULL bcp).
   // The call returns the address of the verified entry point for the method or NULL
   // if the compilation did not complete (either went background or bailed out).
-  __ movl(rax, (int)false);
+  __ movptr(rax, (int32_t)false);
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), rax);
 
   // for c++ interpreter can rsi really be munged?
-  __ leal(rsi, Address(rbp, -sizeof(BytecodeInterpreter)));                                // restore state
-  __ movl(rbx, Address(rsi, byte_offset_of(BytecodeInterpreter, _method)));                // restore method
-  __ movl(rdi, Address(rsi, byte_offset_of(BytecodeInterpreter, _locals)));                // get locals pointer
-
-  // Preserve invariant that rsi/rdi contain bcp/locals of sender frame
-  // and jump to the interpreted entry.
+  __ lea(state, Address(rbp, -sizeof(BytecodeInterpreter)));                               // restore state
+  __ movptr(rbx, Address(state, byte_offset_of(BytecodeInterpreter, _method)));            // restore method
+  __ movptr(rdi, Address(state, byte_offset_of(BytecodeInterpreter, _locals)));            // get locals pointer
+
   __ jmp(*do_continue, relocInfo::none);
 
 }
@@ -597,7 +614,7 @@
   // rbx,: methodOop
 
   // C++ Interpreter
-  // rsi: previous interpreter frame state object
+  // rsi/r13: previous interpreter frame state object
   // rdi: &locals[0]
   // rcx: # of locals
   // rdx: number of additional locals this frame needs (what we must check)
@@ -628,11 +645,11 @@
 
   // save rsi == caller's bytecode ptr (c++ previous interp. state)
   // QQQ problem here?? rsi overload????
-  __ pushl(rsi);
-
-  const Register thread = rsi;
-
-  __ get_thread(thread);
+  __ push(state);
+
+  const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rsi);
+
+  NOT_LP64(__ get_thread(thread));
 
   const Address stack_base(thread, Thread::stack_base_offset());
   const Address stack_size(thread, Thread::stack_size_offset());
@@ -643,26 +660,26 @@
     // Any additional monitors need a check when moving the expression stack
     const one_monitor = frame::interpreter_frame_monitor_size() * wordSize;
   __ load_unsigned_word(rax, size_of_stack);                            // get size of expression stack in words
-  __ leal(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
-  __ leal(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
+  __ lea(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
+  __ lea(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
 
 #ifdef ASSERT
   Label stack_base_okay, stack_size_okay;
   // verify that thread stack base is non-zero
-  __ cmpl(stack_base, 0);
+  __ cmpptr(stack_base, (int32_t)0);
   __ jcc(Assembler::notEqual, stack_base_okay);
   __ stop("stack base is zero");
   __ bind(stack_base_okay);
   // verify that thread stack size is non-zero
-  __ cmpl(stack_size, 0);
+  __ cmpptr(stack_size, (int32_t)0);
   __ jcc(Assembler::notEqual, stack_size_okay);
   __ stop("stack size is zero");
   __ bind(stack_size_okay);
 #endif
 
   // Add stack base to locals and subtract stack size
-  __ addl(rax, stack_base);
-  __ subl(rax, stack_size);
+  __ addptr(rax, stack_base);
+  __ subptr(rax, stack_size);
 
   // We should have a magic number here for the size of the c++ interpreter frame.
   // We can't actually tell this ahead of time. The debug version size is around 3k
@@ -674,20 +691,20 @@
                                                                               (StackRedPages+StackYellowPages);
   // Only need this if we are stack banging which is temporary while
   // we're debugging.
-  __ addl(rax, slop + 2*max_pages * page_size);
+  __ addptr(rax, slop + 2*max_pages * page_size);
 
   // check against the current stack bottom
-  __ cmpl(rsp, rax);
+  __ cmpptr(rsp, rax);
   __ jcc(Assembler::above, after_frame_check_pop);
 
-  __ popl(rsi);  // get saved bcp / (c++ prev state ).
+  __ pop(state);  //  get c++ prev state.
 
      // throw exception return address becomes throwing pc
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_StackOverflowError));
 
   // all done with frame size check
   __ bind(after_frame_check_pop);
-  __ popl(rsi);
+  __ pop(state);
 
   __ bind(after_frame_check);
 }
@@ -696,17 +713,18 @@
 // rbx - methodOop
 //
 void InterpreterGenerator::lock_method(void) {
-  // assumes state == rsi == pointer to current interpreterState
-  // minimally destroys rax, rdx, rdi
+  // assumes state == rsi/r13 == pointer to current interpreterState
+  // minimally destroys rax, rdx|c_rarg1, rdi
   //
   // synchronize method
-  const Register state = rsi;
   const int entry_size            = frame::interpreter_frame_monitor_size() * wordSize;
   const Address access_flags      (rbx, methodOopDesc::access_flags_offset());
 
+  const Register monitor  = NOT_LP64(rdx) LP64_ONLY(c_rarg1);
+
   // find initial monitor i.e. monitors[-1]
-  __ movl(rdx, STATE(_monitor_base));                                   // get monitor bottom limit
-  __ subl(rdx, entry_size);                                             // point to initial monitor
+  __ movptr(monitor, STATE(_monitor_base));                                   // get monitor bottom limit
+  __ subptr(monitor, entry_size);                                             // point to initial monitor
 
 #ifdef ASSERT
   { Label L;
@@ -721,35 +739,34 @@
   { Label done;
     const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
     __ movl(rax, access_flags);
-    __ movl(rdi, STATE(_locals));                                       // prepare to get receiver (assume common case)
+    __ movptr(rdi, STATE(_locals));                                     // prepare to get receiver (assume common case)
     __ testl(rax, JVM_ACC_STATIC);
-    __ movl(rax, Address(rdi, 0));                                      // get receiver (assume this is frequent case)
+    __ movptr(rax, Address(rdi, 0));                                    // get receiver (assume this is frequent case)
     __ jcc(Assembler::zero, done);
-    __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
-    __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movl(rax, Address(rax, mirror_offset));
+    __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(rax, Address(rax, mirror_offset));
     __ bind(done);
   }
 #ifdef ASSERT
   { Label L;
-    __ cmpl(rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));   // correct object?
+    __ cmpptr(rax, Address(monitor, BasicObjectLock::obj_offset_in_bytes()));   // correct object?
     __ jcc(Assembler::equal, L);
     __ stop("wrong synchronization lobject");
     __ bind(L);
   }
 #endif // ASSERT
-  // can destroy rax, rdx, rcx, and (via call_VM) rdi!
-  __ lock_object(rdx);
+  // can destroy rax, rdx|c_rarg1, rcx, and (via call_VM) rdi!
+  __ lock_object(monitor);
 }
 
 // Call an accessor method (assuming it is resolved, otherwise drop into vanilla (slow path) entry
 
 address InterpreterGenerator::generate_accessor_entry(void) {
 
-  // rbx,: methodOop
-  // rcx: receiver (preserve for slow entry into asm interpreter)
-
-  // rsi: senderSP must preserved for slow path, set SP to it on fast path
+  // rbx: methodOop
+
+  // rsi/r13: senderSP must preserved for slow path, set SP to it on fast path
 
   Label xreturn_path;
 
@@ -772,21 +789,21 @@
     //       these conditions first and use slow path if necessary.
     // rbx,: method
     // rcx: receiver
-    __ movl(rax, Address(rsp, wordSize));
+    __ movptr(rax, Address(rsp, wordSize));
 
     // check if local 0 != NULL and read field
-    __ testl(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, slow_path);
 
-    __ movl(rdi, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rdi, Address(rbx, methodOopDesc::constants_offset()));
     // read first instruction word and extract bytecode @ 1 and index @ 2
-    __ movl(rdx, Address(rbx, methodOopDesc::const_offset()));
+    __ movptr(rdx, Address(rbx, methodOopDesc::const_offset()));
     __ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
     // Shift codes right to get the index on the right.
     // The bytecode fetched looks like <index><0xb4><0x2a>
     __ shrl(rdx, 2*BitsPerByte);
     __ shll(rdx, exact_log2(in_words(ConstantPoolCacheEntry::size())));
-    __ movl(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
+    __ movptr(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
 
     // rax,: local 0
     // rbx,: method
@@ -794,7 +811,7 @@
     // rcx: scratch
     // rdx: constant pool cache index
     // rdi: constant pool cache
-    // rsi: sender sp
+    // rsi/r13: sender sp
 
     // check if getfield has been resolved and read constant pool cache entry
     // check the validity of the cache entry by testing whether _indices field
@@ -803,21 +820,21 @@
     __ movl(rcx,
             Address(rdi,
                     rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
     __ shrl(rcx, 2*BitsPerByte);
     __ andl(rcx, 0xFF);
     __ cmpl(rcx, Bytecodes::_getfield);
     __ jcc(Assembler::notEqual, slow_path);
 
     // Note: constant pool entry is not valid before bytecode is resolved
-    __ movl(rcx,
+    __ movptr(rcx,
             Address(rdi,
                     rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
     __ movl(rdx,
             Address(rdi,
                     rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
 
     Label notByte, notShort, notChar;
     const Address field_address (rax, rcx, Address::times_1);
@@ -828,6 +845,16 @@
     __ shrl(rdx, ConstantPoolCacheEntry::tosBits);
     // Make sure we don't need to mask rdx for tosBits after the above shift
     ConstantPoolCacheEntry::verify_tosBits();
+#ifdef _LP64
+    Label notObj;
+    __ cmpl(rdx, atos);
+    __ jcc(Assembler::notEqual, notObj);
+    // atos
+    __ movptr(rax, field_address);
+    __ jmp(xreturn_path);
+
+    __ bind(notObj);
+#endif // _LP64
     __ cmpl(rdx, btos);
     __ jcc(Assembler::notEqual, notByte);
     __ load_signed_byte(rax, field_address);
@@ -848,8 +875,10 @@
     __ bind(notChar);
 #ifdef ASSERT
     Label okay;
+#ifndef _LP64
     __ cmpl(rdx, atos);
     __ jcc(Assembler::equal, okay);
+#endif // _LP64
     __ cmpl(rdx, itos);
     __ jcc(Assembler::equal, okay);
     __ stop("what type is this?");
@@ -861,8 +890,8 @@
     __ bind(xreturn_path);
 
     // _ireturn/_areturn
-    __ popl(rdi);                              // get return address
-    __ movl(rsp, rsi);                         // set sp to sender sp
+    __ pop(rdi);                               // get return address
+    __ mov(rsp, sender_sp_on_entry);           // set sp to sender sp
     __ jmp(rdi);
 
     // generate a vanilla interpreter entry as the slow path
@@ -894,8 +923,8 @@
 
   // rbx: methodOop
   // rcx: receiver (unused)
-  // rsi: previous interpreter state (if called from C++ interpreter) must preserve
-  //      in any case. If called via c1/c2/call_stub rsi is junk (to use) but harmless
+  // rsi/r13: previous interpreter state (if called from C++ interpreter) must preserve
+  //      in any case. If called via c1/c2/call_stub rsi/r13 is junk (to use) but harmless
   //      to save/restore.
   address entry_point = __ pc();
 
@@ -904,8 +933,7 @@
   const Address invocation_counter(rbx, methodOopDesc::invocation_counter_offset() + InvocationCounter::counter_offset());
   const Address access_flags      (rbx, methodOopDesc::access_flags_offset());
 
-  // rsi == state/locals rdi == prevstate
-  const Register state = rsi;
+  // rsi/r13 == state/locals rdi == prevstate
   const Register locals = rdi;
 
   // get parameter size (always needed)
@@ -913,11 +941,11 @@
 
   // rbx: methodOop
   // rcx: size of parameters
-  __ popl(rax);                                       // get return address
+  __ pop(rax);                                       // get return address
   // for natives the size of locals is zero
 
   // compute beginning of parameters /locals
-  __ leal(locals, Address(rsp, rcx, Address::times_4, -wordSize));
+  __ lea(locals, Address(rsp, rcx, Address::times_ptr, -wordSize));
 
   // initialize fixed part of activation frame
 
@@ -931,15 +959,20 @@
   // OUT(rsp) -> bottom of methods expression stack
 
   // save sender_sp
-  __ movl(rcx, rsi);
+  __ mov(rcx, sender_sp_on_entry);
   // start with NULL previous state
-  __ movl(state, 0);
+  __ movptr(state, (int32_t)NULL_WORD);
   generate_compute_interpreter_state(state, locals, rcx, true);
 
 #ifdef ASSERT
   { Label L;
-    __ movl(rax, STATE(_stack_base));
-    __ cmpl(rax, rsp);
+    __ movptr(rax, STATE(_stack_base));
+#ifdef _LP64
+    // duplicate the alignment rsp got after setting stack_base
+    __ subptr(rax, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rax, -16); // must be 16 byte boundry (see amd64 ABI)
+#endif // _LP64
+    __ cmpptr(rax, rsp);
     __ jcc(Assembler::equal, L);
     __ stop("broken stack frame setup in interpreter");
     __ bind(L);
@@ -948,14 +981,15 @@
 
   if (inc_counter) __ movl(rcx, invocation_counter);  // (pre-)fetch invocation count
 
-  __ movl(rax, STATE(_thread));                       // get thread
+  const Register unlock_thread = LP64_ONLY(r15_thread) NOT_LP64(rax);
+  NOT_LP64(__ movptr(unlock_thread, STATE(_thread));) // get thread
   // Since at this point in the method invocation the exception handler
   // would try to exit the monitor of synchronized methods which hasn't
   // been entered yet, we set the thread local variable
   // _do_not_unlock_if_synchronized to true. The remove_activation will
   // check this flag.
 
-  const Address do_not_unlock_if_synchronized(rax,
+  const Address do_not_unlock_if_synchronized(unlock_thread,
         in_bytes(JavaThread::do_not_unlock_if_synchronized_offset()));
   __ movbool(do_not_unlock_if_synchronized, true);
 
@@ -991,7 +1025,7 @@
   bang_stack_shadow_pages(true);
 
   // reset the _do_not_unlock_if_synchronized flag
-  __ movl(rax, STATE(_thread));                       // get thread
+  NOT_LP64(__ movl(rax, STATE(_thread));)                       // get thread
   __ movbool(do_not_unlock_if_synchronized, false);
 
 
@@ -1022,62 +1056,81 @@
 
   // work registers
   const Register method = rbx;
-  const Register thread = rdi;
-  const Register t      = rcx;
+  const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rdi);
+  const Register t      = InterpreterRuntime::SignatureHandlerGenerator::temp();    // rcx|rscratch1
 
   // allocate space for parameters
-  __ movl(method, STATE(_method));
+  __ movptr(method, STATE(_method));
   __ verify_oop(method);
   __ load_unsigned_word(t, Address(method, methodOopDesc::size_of_parameters_offset()));
   __ shll(t, 2);
-  __ addl(t, 2*wordSize);     // allocate two more slots for JNIEnv and possible mirror
-  __ subl(rsp, t);
-  __ andl(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
+#ifdef _LP64
+  __ subptr(rsp, t);
+  __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+  __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+#else
+  __ addptr(t, 2*wordSize);     // allocate two more slots for JNIEnv and possible mirror
+  __ subptr(rsp, t);
+  __ andptr(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
+#endif // _LP64
 
   // get signature handler
     Label pending_exception_present;
 
   { Label L;
-    __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
-    __ testl(t, t);
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ testptr(t, t);
     __ jcc(Assembler::notZero, L);
     __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method, false);
-    __ movl(method, STATE(_method));
-    __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ movptr(method, STATE(_method));
+    __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::notEqual, pending_exception_present);
     __ verify_oop(method);
-    __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
     __ bind(L);
   }
 #ifdef ASSERT
   {
     Label L;
-    __ pushl(t);
+    __ push(t);
     __ get_thread(t);                                   // get vm's javathread*
-    __ cmpl(t, STATE(_thread));
+    __ cmpptr(t, STATE(_thread));
     __ jcc(Assembler::equal, L);
     __ int3();
     __ bind(L);
-    __ popl(t);
+    __ pop(t);
   }
 #endif //
 
+  const Register from_ptr = InterpreterRuntime::SignatureHandlerGenerator::from();
   // call signature handler
-  assert(InterpreterRuntime::SignatureHandlerGenerator::from() == rdi, "adjust this code");
   assert(InterpreterRuntime::SignatureHandlerGenerator::to  () == rsp, "adjust this code");
-  assert(InterpreterRuntime::SignatureHandlerGenerator::temp() == t  , "adjust this code");
+
   // The generated handlers do not touch RBX (the method oop).
   // However, large signatures cannot be cached and are generated
   // each time here.  The slow-path generator will blow RBX
   // sometime, so we must reload it after the call.
-  __ movl(rdi, STATE(_locals));  // get the from pointer
+  __ movptr(from_ptr, STATE(_locals));  // get the from pointer
   __ call(t);
-  __ movl(method, STATE(_method));
+  __ movptr(method, STATE(_method));
   __ verify_oop(method);
 
   // result handler is in rax
   // set result handler
-  __ movl(STATE(_result_handler), rax);
+  __ movptr(STATE(_result_handler), rax);
+
+
+  // get native function entry point
+  { Label L;
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ testptr(rax, rax);
+    __ jcc(Assembler::notZero, L);
+    __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
+    __ movptr(method, STATE(_method));
+    __ verify_oop(method);
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ bind(L);
+  }
 
   // pass mirror handle if static call
   { Label L;
@@ -1086,55 +1139,53 @@
     __ testl(t, JVM_ACC_STATIC);
     __ jcc(Assembler::zero, L);
     // get mirror
-    __ movl(t, Address(method, methodOopDesc:: constants_offset()));
-    __ movl(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movl(t, Address(t, mirror_offset));
+    __ movptr(t, Address(method, methodOopDesc:: constants_offset()));
+    __ movptr(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(t, Address(t, mirror_offset));
     // copy mirror into activation object
-    __ movl(STATE(_oop_temp), t);
+    __ movptr(STATE(_oop_temp), t);
     // pass handle to mirror
-    __ leal(t, STATE(_oop_temp));
-    __ movl(Address(rsp, wordSize), t);
+#ifdef _LP64
+    __ lea(c_rarg1, STATE(_oop_temp));
+#else
+    __ lea(t, STATE(_oop_temp));
+    __ movptr(Address(rsp, wordSize), t);
+#endif // _LP64
     __ bind(L);
   }
 #ifdef ASSERT
   {
     Label L;
-    __ pushl(t);
+    __ push(t);
     __ get_thread(t);                                   // get vm's javathread*
-    __ cmpl(t, STATE(_thread));
+    __ cmpptr(t, STATE(_thread));
     __ jcc(Assembler::equal, L);
     __ int3();
     __ bind(L);
-    __ popl(t);
+    __ pop(t);
   }
 #endif //
 
-  // get native function entry point
-  { Label L;
-    __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
-    __ testl(rax, rax);
-    __ jcc(Assembler::notZero, L);
-    __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
-    __ movl(method, STATE(_method));
-    __ verify_oop(method);
-    __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
-    __ bind(L);
-  }
-
   // pass JNIEnv
-  __ movl(thread, STATE(_thread));                       // get thread
-  __ leal(t, Address(thread, JavaThread::jni_environment_offset()));
-  __ movl(Address(rsp, 0), t);
+#ifdef _LP64
+  __ lea(c_rarg0, Address(thread, JavaThread::jni_environment_offset()));
+#else
+  __ movptr(thread, STATE(_thread));          // get thread
+  __ lea(t, Address(thread, JavaThread::jni_environment_offset()));
+
+  __ movptr(Address(rsp, 0), t);
+#endif // _LP64
+
 #ifdef ASSERT
   {
     Label L;
-    __ pushl(t);
+    __ push(t);
     __ get_thread(t);                                   // get vm's javathread*
-    __ cmpl(t, STATE(_thread));
+    __ cmpptr(t, STATE(_thread));
     __ jcc(Assembler::equal, L);
     __ int3();
     __ bind(L);
-    __ popl(t);
+    __ pop(t);
   }
 #endif //
 
@@ -1159,8 +1210,8 @@
   __ call(rax);
 
   // result potentially in rdx:rax or ST0
-  __ movl(method, STATE(_method));
-  __ movl(thread, STATE(_thread));                       // get thread
+  __ movptr(method, STATE(_method));
+  NOT_LP64(__ movptr(thread, STATE(_thread));)                  // get thread
 
   // The potential result is in ST(0) & rdx:rax
   // With C++ interpreter we leave any possible result in ST(0) until we are in result handler and then
@@ -1170,7 +1221,7 @@
   // It is safe to do these pushes because state is _thread_in_native and return address will be found
   // via _last_native_pc and not via _last_jave_sp
 
-    // Must save the value of ST(0) since it could be destroyed before we get to result handler
+    // Must save the value of ST(0)/xmm0 since it could be destroyed before we get to result handler
     { Label Lpush, Lskip;
       ExternalAddress float_handler(AbstractInterpreter::result_handler(T_FLOAT));
       ExternalAddress double_handler(AbstractInterpreter::result_handler(T_DOUBLE));
@@ -1179,11 +1230,20 @@
       __ cmpptr(STATE(_result_handler), double_handler.addr());
       __ jcc(Assembler::notEqual, Lskip);
       __ bind(Lpush);
-      __ push(dtos);
+      __ subptr(rsp, 2*wordSize);
+      if ( UseSSE < 2 ) {
+        __ fstp_d(Address(rsp, 0));
+      } else {
+        __ movdbl(Address(rsp, 0), xmm0);
+      }
       __ bind(Lskip);
     }
 
-  __ push(ltos);           // save rax:rdx for potential use by result handler.
+  // save rax:rdx for potential use by result handler.
+  __ push(rax);
+#ifndef _LP64
+  __ push(rdx);
+#endif // _LP64
 
   // Either restore the MXCSR register after returning from the JNI Call
   // or verify that it wasn't changed.
@@ -1192,15 +1252,17 @@
       __ ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
     }
     else if (CheckJNICalls ) {
-      __ call(RuntimeAddress(StubRoutines::i486::verify_mxcsr_entry()));
+      __ call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
     }
   }
 
+#ifndef _LP64
   // Either restore the x87 floating pointer control word after returning
   // from the JNI call or verify that it wasn't changed.
   if (CheckJNICalls) {
-    __ call(RuntimeAddress(StubRoutines::i486::verify_fpu_cntrl_wrd_entry()));
+    __ call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
   }
+#endif // _LP64
 
 
   // change thread state
@@ -1231,17 +1293,16 @@
     // Don't use call_VM as it will see a possible pending exception and forward it
     // and never return here preventing us from clearing _last_native_pc down below.
     // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
-    // preserved and correspond to the bcp/locals pointers. So we do a runtime call
-    // by hand.
+    // preserved and correspond to the bcp/locals pointers.
     //
-    __ pushl(thread);
-    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
-                                            JavaThread::check_special_condition_for_native_trans)));
+
+    ((MacroAssembler*)_masm)->call_VM_leaf(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
+                          thread);
     __ increment(rsp, wordSize);
 
-    __ movl(method, STATE(_method));
+    __ movptr(method, STATE(_method));
     __ verify_oop(method);
-    __ movl(thread, STATE(_thread));                       // get thread
+    __ movptr(thread, STATE(_thread));                       // get thread
 
     __ bind(Continue);
   }
@@ -1252,8 +1313,8 @@
   __ reset_last_Java_frame(thread, true, true);
 
   // reset handle block
-  __ movl(t, Address(thread, JavaThread::active_handles_offset()));
-  __ movl(Address(t, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
+  __ movptr(t, Address(thread, JavaThread::active_handles_offset()));
+  __ movptr(Address(t, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
 
   // If result was an oop then unbox and save it in the frame
   { Label L;
@@ -1261,15 +1322,21 @@
       ExternalAddress oop_handler(AbstractInterpreter::result_handler(T_OBJECT));
     __ cmpptr(STATE(_result_handler), oop_handler.addr());
     __ jcc(Assembler::notEqual, no_oop);
-    __ pop(ltos);
-    __ testl(rax, rax);
+#ifndef _LP64
+    __ pop(rdx);
+#endif // _LP64
+    __ pop(rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, store_result);
     // unbox
-    __ movl(rax, Address(rax, 0));
+    __ movptr(rax, Address(rax, 0));
     __ bind(store_result);
-    __ movl(STATE(_oop_temp), rax);
+    __ movptr(STATE(_oop_temp), rax);
     // keep stack depth as expected by pushing oop which will eventually be discarded
-    __ push(ltos);
+    __ push(rax);
+#ifndef _LP64
+    __ push(rdx);
+#endif // _LP64
     __ bind(no_oop);
   }
 
@@ -1278,9 +1345,9 @@
      __ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
      __ jcc(Assembler::notEqual, no_reguard);
 
-     __ pushad();
+     __ pusha();
      __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
-     __ popad();
+     __ popa();
 
      __ bind(no_reguard);
    }
@@ -1295,7 +1362,7 @@
 
   // handle exceptions (exception handling will handle unlocking!)
   { Label L;
-    __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::zero, L);
     __ bind(pending_exception_present);
 
@@ -1307,12 +1374,12 @@
 
     // remove activation
 
-    __ movl(t, STATE(_sender_sp));
+    __ movptr(t, STATE(_sender_sp));
     __ leave();                                  // remove frame anchor
-    __ popl(rdi);                                // get return address
-    __ movl(state, STATE(_prev_link));           // get previous state for return
-    __ movl(rsp, t);                             // set sp to sender sp
-    __ pushl(rdi);                               // [ush throwing pc
+    __ pop(rdi);                                 // get return address
+    __ movptr(state, STATE(_prev_link));         // get previous state for return
+    __ mov(rsp, t);                              // set sp to sender sp
+    __ push(rdi);                                // push throwing pc
     // The skips unlocking!! This seems to be what asm interpreter does but seems
     // very wrong. Not clear if this violates the spec.
     __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
@@ -1326,13 +1393,14 @@
     __ jcc(Assembler::zero, L);
     // the code below should be shared with interpreter macro assembler implementation
     { Label unlock;
+    const Register monitor = NOT_LP64(rdx) LP64_ONLY(c_rarg1);
       // BasicObjectLock will be first in list, since this is a synchronized method. However, need
       // to check that the object has not been unlocked by an explicit monitorexit bytecode.
-      __ movl(rdx, STATE(_monitor_base));
-      __ subl(rdx, frame::interpreter_frame_monitor_size() * wordSize);  // address of initial monitor
-
-      __ movl(t, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
-      __ testl(t, t);
+      __ movptr(monitor, STATE(_monitor_base));
+      __ subptr(monitor, frame::interpreter_frame_monitor_size() * wordSize);  // address of initial monitor
+
+      __ movptr(t, Address(monitor, BasicObjectLock::obj_offset_in_bytes()));
+      __ testptr(t, t);
       __ jcc(Assembler::notZero, unlock);
 
       // Entry already unlocked, need to throw exception
@@ -1340,9 +1408,9 @@
       __ should_not_reach_here();
 
       __ bind(unlock);
-      __ unlock_object(rdx);
+      __ unlock_object(monitor);
       // unlock can blow rbx so restore it for path that needs it below
-      __ movl(method, STATE(_method));
+      __ movptr(method, STATE(_method));
     }
     __ bind(L);
   }
@@ -1355,18 +1423,21 @@
   __ notify_method_exit(vtos, InterpreterMacroAssembler::NotifyJVMTI);
 
   // restore potential result in rdx:rax, call result handler to restore potential result in ST0 & handle result
-  __ pop(ltos);                               // restore rax/rdx floating result if present still on stack
-  __ movl(t, STATE(_result_handler));         // get result handler
+#ifndef _LP64
+  __ pop(rdx);
+#endif // _LP64
+  __ pop(rax);
+  __ movptr(t, STATE(_result_handler));       // get result handler
   __ call(t);                                 // call result handler to convert to tosca form
 
   // remove activation
 
-  __ movl(t, STATE(_sender_sp));
+  __ movptr(t, STATE(_sender_sp));
 
   __ leave();                                  // remove frame anchor
-  __ popl(rdi);                                // get return address
-  __ movl(state, STATE(_prev_link));           // get previous state for return (if c++ interpreter was caller)
-  __ movl(rsp, t);                             // set sp to sender sp
+  __ pop(rdi);                                 // get return address
+  __ movptr(state, STATE(_prev_link));         // get previous state for return (if c++ interpreter was caller)
+  __ mov(rsp, t);                              // set sp to sender sp
   __ jmp(rdi);
 
   // invocation counter overflow
@@ -1382,7 +1453,6 @@
 // Generate entries that will put a result type index into rcx
 void CppInterpreterGenerator::generate_deopt_handling() {
 
-  const Register state = rsi;
   Label return_from_deopt_common;
 
   // Generate entries that will put a result type index into rcx
@@ -1449,51 +1519,50 @@
   //
   __ bind(return_from_deopt_common);
 
-  __ leal(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
+  __ lea(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
 
   // setup rsp so we can push the "result" as needed.
-  __ movl(rsp, STATE(_stack));                                     // trim stack (is prepushed)
-  __ addl(rsp, wordSize);                                          // undo prepush
+  __ movptr(rsp, STATE(_stack));                                   // trim stack (is prepushed)
+  __ addptr(rsp, wordSize);                                        // undo prepush
 
   ExternalAddress tosca_to_stack((address)CppInterpreter::_tosca_to_stack);
-  // Address index(noreg, rcx, Address::times_4);
-  __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_4)));
-  // __ movl(rcx, Address(noreg, rcx, Address::times_4, int(AbstractInterpreter::_tosca_to_stack)));
+  // Address index(noreg, rcx, Address::times_ptr);
+  __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_ptr)));
+  // __ movl(rcx, Address(noreg, rcx, Address::times_ptr, int(AbstractInterpreter::_tosca_to_stack)));
   __ call(rcx);                                                   // call result converter
 
   __ movl(STATE(_msg), (int)BytecodeInterpreter::deopt_resume);
-  __ leal(rsp, Address(rsp, -wordSize));                           // prepush stack (result if any already present)
-  __ movl(STATE(_stack), rsp);                                     // inform interpreter of new stack depth (parameters removed,
+  __ lea(rsp, Address(rsp, -wordSize));                            // prepush stack (result if any already present)
+  __ movptr(STATE(_stack), rsp);                                   // inform interpreter of new stack depth (parameters removed,
                                                                    // result if any on stack already )
-  __ movl(rsp, STATE(_stack_limit));                               // restore expression stack to full depth
+  __ movptr(rsp, STATE(_stack_limit));                             // restore expression stack to full depth
 }
 
 // Generate the code to handle a more_monitors message from the c++ interpreter
 void CppInterpreterGenerator::generate_more_monitors() {
 
-  const Register state = rsi;
 
   Label entry, loop;
   const int entry_size = frame::interpreter_frame_monitor_size() * wordSize;
-  // 1. compute new pointers                   // rsp: old expression stack top
-  __ movl(rdx, STATE(_stack_base));            // rdx: old expression stack bottom
-  __ subl(rsp, entry_size);                    // move expression stack top limit
-  __ subl(STATE(_stack), entry_size);          // update interpreter stack top
-  __ movl(STATE(_stack_limit), rsp);           // inform interpreter
-  __ subl(rdx, entry_size);                    // move expression stack bottom
-  __ movl(STATE(_stack_base), rdx);            // inform interpreter
-  __ movl(rcx, STATE(_stack));                 // set start value for copy loop
+  // 1. compute new pointers                     // rsp: old expression stack top
+  __ movptr(rdx, STATE(_stack_base));            // rdx: old expression stack bottom
+  __ subptr(rsp, entry_size);                    // move expression stack top limit
+  __ subptr(STATE(_stack), entry_size);          // update interpreter stack top
+  __ subptr(STATE(_stack_limit), entry_size);    // inform interpreter
+  __ subptr(rdx, entry_size);                    // move expression stack bottom
+  __ movptr(STATE(_stack_base), rdx);            // inform interpreter
+  __ movptr(rcx, STATE(_stack));                 // set start value for copy loop
   __ jmp(entry);
   // 2. move expression stack contents
   __ bind(loop);
-  __ movl(rbx, Address(rcx, entry_size));      // load expression stack word from old location
-  __ movl(Address(rcx, 0), rbx);               // and store it at new location
-  __ addl(rcx, wordSize);                      // advance to next word
+  __ movptr(rbx, Address(rcx, entry_size));      // load expression stack word from old location
+  __ movptr(Address(rcx, 0), rbx);               // and store it at new location
+  __ addptr(rcx, wordSize);                      // advance to next word
   __ bind(entry);
-  __ cmpl(rcx, rdx);                           // check if bottom reached
-  __ jcc(Assembler::notEqual, loop);           // if not at bottom then copy next word
+  __ cmpptr(rcx, rdx);                           // check if bottom reached
+  __ jcc(Assembler::notEqual, loop);             // if not at bottom then copy next word
   // now zero the slot so we can find it.
-  __ movl(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), (int) NULL);
+  __ movptr(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), (int32_t) NULL_WORD);
   __ movl(STATE(_msg), (int)BytecodeInterpreter::got_monitors);
 }
 
@@ -1517,7 +1586,7 @@
 //
 // rbx: methodOop
 // rcx: receiver - unused (retrieved from stack as needed)
-// rsi: previous frame manager state (NULL from the call_stub/c1/c2)
+// rsi/r13: previous frame manager state (NULL from the call_stub/c1/c2)
 //
 //
 // Stack layout at entry
@@ -1539,7 +1608,7 @@
 address InterpreterGenerator::generate_normal_entry(bool synchronized) {
 
   // rbx: methodOop
-  // rsi: sender sp
+  // rsi/r13: sender sp
 
   // Because we redispatch "recursive" interpreter entries thru this same entry point
   // the "input" register usage is a little strange and not what you expect coming
@@ -1562,12 +1631,11 @@
   if (UseFastAccessorMethods && !synchronized) __ bind(fast_accessor_slow_entry_path);
 
   Label dispatch_entry_2;
-  __ movl(rcx, rsi);
-  __ movl(rsi, 0);                                                 // no current activation
+  __ movptr(rcx, sender_sp_on_entry);
+  __ movptr(state, (int32_t)NULL_WORD);                              // no current activation
 
   __ jmp(dispatch_entry_2);
 
-  const Register state   = rsi;                                    // current activation object, valid on entry
   const Register locals  = rdi;
 
   Label re_dispatch;
@@ -1575,12 +1643,12 @@
   __ bind(re_dispatch);
 
   // save sender sp (doesn't include return address
-  __ leal(rcx, Address(rsp, wordSize));
+  __ lea(rcx, Address(rsp, wordSize));
 
   __ bind(dispatch_entry_2);
 
   // save sender sp
-  __ pushl(rcx);
+  __ push(rcx);
 
   const Address size_of_parameters(rbx, methodOopDesc::size_of_parameters_offset());
   const Address size_of_locals    (rbx, methodOopDesc::size_of_locals_offset());
@@ -1597,7 +1665,7 @@
   // rcx: size of parameters
   __ load_unsigned_word(rdx, size_of_locals);                      // get size of locals in words
 
-  __ subl(rdx, rcx);                                               // rdx = no. of additional locals
+  __ subptr(rdx, rcx);                                             // rdx = no. of additional locals
 
   // see if we've got enough room on the stack for locals plus overhead.
   generate_stack_overflow_check();                                 // C++
@@ -1609,26 +1677,26 @@
 
 
   // compute beginning of parameters (rdi)
-  __ leal(locals, Address(rsp, rcx, Address::times_4, wordSize));
+  __ lea(locals, Address(rsp, rcx, Address::times_ptr, wordSize));
 
   // save sender's sp
   // __ movl(rcx, rsp);
 
   // get sender's sp
-  __ popl(rcx);
+  __ pop(rcx);
 
   // get return address
-  __ popl(rax);
+  __ pop(rax);
 
   // rdx - # of additional locals
   // allocate space for locals
   // explicitly initialize locals
   {
     Label exit, loop;
-    __ testl(rdx, rdx);
+    __ testl(rdx, rdx);                               // (32bit ok)
     __ jcc(Assembler::lessEqual, exit);               // do nothing if rdx <= 0
     __ bind(loop);
-    __ pushl((int)NULL);                              // initialize local variables
+    __ push((int32_t)NULL_WORD);                      // initialize local variables
     __ decrement(rdx);                                // until everything initialized
     __ jcc(Assembler::greater, loop);
     __ bind(exit);
@@ -1664,17 +1732,21 @@
   __ bind(call_interpreter_2);
 
   {
-    const Register thread  = rcx;
-
-    __ pushl(state);                                                 // push arg to interpreter
-    __ movl(thread, STATE(_thread));
+    const Register thread  = NOT_LP64(rcx) LP64_ONLY(r15_thread);
+
+#ifdef _LP64
+    __ mov(c_rarg0, state);
+#else
+    __ push(state);                                                 // push arg to interpreter
+    __ movptr(thread, STATE(_thread));
+#endif // _LP64
 
     // We can setup the frame anchor with everything we want at this point
     // as we are thread_in_Java and no safepoints can occur until we go to
     // vm mode. We do have to clear flags on return from vm but that is it
     //
-    __ movl(Address(thread, JavaThread::last_Java_fp_offset()), rbp);
-    __ movl(Address(thread, JavaThread::last_Java_sp_offset()), rsp);
+    __ movptr(Address(thread, JavaThread::last_Java_fp_offset()), rbp);
+    __ movptr(Address(thread, JavaThread::last_Java_sp_offset()), rsp);
 
     // Call the interpreter
 
@@ -1682,14 +1754,14 @@
     RuntimeAddress checking(CAST_FROM_FN_PTR(address, BytecodeInterpreter::runWithChecks));
 
     __ call(JvmtiExport::can_post_interpreter_events() ? checking : normal);
-    __ popl(rax);                                                  // discard parameter to run
+    NOT_LP64(__ pop(rax);)                                          // discard parameter to run
     //
     // state is preserved since it is callee saved
     //
 
     // reset_last_Java_frame
 
-    __ movl(thread, STATE(_thread));
+    NOT_LP64(__ movl(thread, STATE(_thread));)
     __ reset_last_Java_frame(thread, true, true);
   }
 
@@ -1703,15 +1775,15 @@
   Label bad_msg;
   Label do_OSR;
 
-  __ cmpl(rdx, (int)BytecodeInterpreter::call_method);
+  __ cmpl(rdx, (int32_t)BytecodeInterpreter::call_method);
   __ jcc(Assembler::equal, call_method);
-  __ cmpl(rdx, (int)BytecodeInterpreter::return_from_method);
+  __ cmpl(rdx, (int32_t)BytecodeInterpreter::return_from_method);
   __ jcc(Assembler::equal, return_from_interpreted_method);
-  __ cmpl(rdx, (int)BytecodeInterpreter::do_osr);
+  __ cmpl(rdx, (int32_t)BytecodeInterpreter::do_osr);
   __ jcc(Assembler::equal, do_OSR);
-  __ cmpl(rdx, (int)BytecodeInterpreter::throwing_exception);
+  __ cmpl(rdx, (int32_t)BytecodeInterpreter::throwing_exception);
   __ jcc(Assembler::equal, throw_exception);
-  __ cmpl(rdx, (int)BytecodeInterpreter::more_monitors);
+  __ cmpl(rdx, (int32_t)BytecodeInterpreter::more_monitors);
   __ jcc(Assembler::notEqual, bad_msg);
 
   // Allocate more monitor space, shuffle expression stack....
@@ -1724,8 +1796,8 @@
   unctrap_frame_manager_entry  = __ pc();
   //
   // Load the registers we need.
-  __ leal(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
-  __ movl(rsp, STATE(_stack_limit));                               // restore expression stack to full depth
+  __ lea(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
+  __ movptr(rsp, STATE(_stack_limit));                             // restore expression stack to full depth
   __ jmp(call_interpreter_2);
 
 
@@ -1757,13 +1829,17 @@
   Label unwind_and_forward;
 
   // restore state pointer.
-  __ leal(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
-
-  __ movl(rbx, STATE(_method));                       // get method
+  __ lea(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
+
+  __ movptr(rbx, STATE(_method));                       // get method
+#ifdef _LP64
+  __ movptr(Address(r15_thread, Thread::pending_exception_offset()), rax);
+#else
   __ movl(rcx, STATE(_thread));                       // get thread
 
   // Store exception with interpreter will expect it
-  __ movl(Address(rcx, Thread::pending_exception_offset()), rax);
+  __ movptr(Address(rcx, Thread::pending_exception_offset()), rax);
+#endif // _LP64
 
   // is current frame vanilla or native?
 
@@ -1779,11 +1855,11 @@
 
   // unwind rbp, return stack to unextended value and re-push return address
 
-  __ movl(rcx, STATE(_sender_sp));
+  __ movptr(rcx, STATE(_sender_sp));
   __ leave();
-  __ popl(rdx);
-  __ movl(rsp, rcx);
-  __ pushl(rdx);
+  __ pop(rdx);
+  __ mov(rsp, rcx);
+  __ push(rdx);
   __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
 
   // Return point from a call which returns a result in the native abi
@@ -1801,8 +1877,8 @@
 
   // The FPU stack is clean if UseSSE >= 2 but must be cleaned in other cases
   if (UseSSE < 2) {
-    __ leal(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
-    __ movl(rbx, STATE(_result._to_call._callee));                     // get method just executed
+    __ lea(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
+    __ movptr(rbx, STATE(_result._to_call._callee));                   // get method just executed
     __ movl(rcx, Address(rbx, methodOopDesc::result_index_offset()));
     __ cmpl(rcx, AbstractInterpreter::BasicType_as_index(T_FLOAT));    // Result stub address array index
     __ jcc(Assembler::equal, do_float);
@@ -1832,10 +1908,12 @@
     __ jmp(done_conv);
   }
 
+#if 0
   // emit a sentinel we can test for when converting an interpreter
   // entry point to a compiled entry point.
   __ a_long(Interpreter::return_sentinel);
   __ a_long((int)compiled_entry);
+#endif
 
   // Return point to interpreter from compiled/native method
 
@@ -1848,33 +1926,37 @@
   // calling convention left it (i.e. params may or may not be present)
   // Copy the result from tosca and place it on java expression stack.
 
-  // Restore rsi as compiled code may not preserve it
-
-  __ leal(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
+  // Restore rsi/r13 as compiled code may not preserve it
+
+  __ lea(state, Address(rbp,  -sizeof(BytecodeInterpreter)));
 
   // restore stack to what we had when we left (in case i2c extended it)
 
-  __ movl(rsp, STATE(_stack));
-  __ leal(rsp, Address(rsp, wordSize));
+  __ movptr(rsp, STATE(_stack));
+  __ lea(rsp, Address(rsp, wordSize));
 
   // If there is a pending exception then we don't really have a result to process
 
-  __ movl(rcx, STATE(_thread));                       // get thread
-  __ cmpl(Address(rcx, Thread::pending_exception_offset()), (int)NULL);
+#ifdef _LP64
+  __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
+#else
+  __ movptr(rcx, STATE(_thread));                       // get thread
+  __ cmpptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
+#endif / __LP64
   __ jcc(Assembler::notZero, return_with_exception);
 
   // get method just executed
-  __ movl(rbx, STATE(_result._to_call._callee));
+  __ movptr(rbx, STATE(_result._to_call._callee));
 
   // callee left args on top of expression stack, remove them
   __ load_unsigned_word(rcx, Address(rbx, methodOopDesc::size_of_parameters_offset()));
-  __ leal(rsp, Address(rsp, rcx, Address::times_4));
+  __ lea(rsp, Address(rsp, rcx, Address::times_ptr));
 
   __ movl(rcx, Address(rbx, methodOopDesc::result_index_offset()));
   ExternalAddress tosca_to_stack((address)CppInterpreter::_tosca_to_stack);
-  // Address index(noreg, rax, Address::times_4);
-  __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_4)));
-  // __ movl(rcx, Address(noreg, rcx, Address::times_4, int(AbstractInterpreter::_tosca_to_stack)));
+  // Address index(noreg, rax, Address::times_ptr);
+  __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_ptr)));
+  // __ movl(rcx, Address(noreg, rcx, Address::times_ptr, int(AbstractInterpreter::_tosca_to_stack)));
   __ call(rcx);                                               // call result converter
   __ jmp(resume_interpreter);
 
@@ -1884,7 +1966,7 @@
   __ bind(return_with_exception);
 
   // Exception present, empty stack
-  __ movl(rsp, STATE(_stack_base));
+  __ movptr(rsp, STATE(_stack_base));
   __ jmp(resume_interpreter);
 
   // Return from interpreted method we return result appropriate to the caller (i.e. "recursive"
@@ -1895,17 +1977,17 @@
 
   Label return_to_initial_caller;
 
-  __ movl(rbx, STATE(_method));                                     // get method just executed
-  __ cmpl(STATE(_prev_link), (int)NULL);                            // returning from "recursive" interpreter call?
+  __ movptr(rbx, STATE(_method));                                   // get method just executed
+  __ cmpptr(STATE(_prev_link), (int32_t)NULL_WORD);                 // returning from "recursive" interpreter call?
   __ movl(rax, Address(rbx, methodOopDesc::result_index_offset())); // get result type index
   __ jcc(Assembler::equal, return_to_initial_caller);               // back to native code (call_stub/c1/c2)
 
   // Copy result to callers java stack
   ExternalAddress stack_to_stack((address)CppInterpreter::_stack_to_stack);
-  // Address index(noreg, rax, Address::times_4);
-
-  __ movptr(rax, ArrayAddress(stack_to_stack, Address(noreg, rax, Address::times_4)));
-  // __ movl(rax, Address(noreg, rax, Address::times_4, int(AbstractInterpreter::_stack_to_stack)));
+  // Address index(noreg, rax, Address::times_ptr);
+
+  __ movptr(rax, ArrayAddress(stack_to_stack, Address(noreg, rax, Address::times_ptr)));
+  // __ movl(rax, Address(noreg, rax, Address::times_ptr, int(AbstractInterpreter::_stack_to_stack)));
   __ call(rax);                                                     // call result converter
 
   Label unwind_recursive_activation;
@@ -1915,9 +1997,9 @@
   // result converter left rax pointing to top of the java stack for method we are returning
   // to. Now all we must do is unwind the state from the completed call
 
-  __ movl(state, STATE(_prev_link));                                // unwind state
+  __ movptr(state, STATE(_prev_link));                              // unwind state
   __ leave();                                                       // pop the frame
-  __ movl(rsp, rax);                                                // unwind stack to remove args
+  __ mov(rsp, rax);                                                 // unwind stack to remove args
 
   // Resume the interpreter. The current frame contains the current interpreter
   // state object.
@@ -1928,10 +2010,10 @@
   // state == interpreterState object for method we are resuming
 
   __ movl(STATE(_msg), (int)BytecodeInterpreter::method_resume);
-  __ leal(rsp, Address(rsp, -wordSize));                           // prepush stack (result if any already present)
-  __ movl(STATE(_stack), rsp);                                     // inform interpreter of new stack depth (parameters removed,
+  __ lea(rsp, Address(rsp, -wordSize));                            // prepush stack (result if any already present)
+  __ movptr(STATE(_stack), rsp);                                   // inform interpreter of new stack depth (parameters removed,
                                                                    // result if any on stack already )
-  __ movl(rsp, STATE(_stack_limit));                               // restore expression stack to full depth
+  __ movptr(rsp, STATE(_stack_limit));                             // restore expression stack to full depth
   __ jmp(call_interpreter_2);                                      // No need to bang
 
   // interpreter returning to native code (call_stub/c1/c2)
@@ -1940,9 +2022,9 @@
 
   __ bind(return_to_initial_caller);
   ExternalAddress stack_to_native((address)CppInterpreter::_stack_to_native_abi);
-  // Address index(noreg, rax, Address::times_4);
-
-  __ movptr(rax, ArrayAddress(stack_to_native, Address(noreg, rax, Address::times_4)));
+  // Address index(noreg, rax, Address::times_ptr);
+
+  __ movptr(rax, ArrayAddress(stack_to_native, Address(noreg, rax, Address::times_ptr)));
   __ call(rax);                                                    // call result converter
 
   Label unwind_initial_activation;
@@ -1964,11 +2046,11 @@
 
   // return restoring the stack to the original sender_sp value
 
-  __ movl(rcx, STATE(_sender_sp));
+  __ movptr(rcx, STATE(_sender_sp));
   __ leave();
-  __ popl(rdi);                                                     // get return address
+  __ pop(rdi);                                                        // get return address
   // set stack to sender's sp
-  __ movl(rsp, rcx);
+  __ mov(rsp, rcx);
   __ jmp(rdi);                                                        // return to call_stub
 
   // OSR request, adjust return address to make current frame into adapter frame
@@ -1982,17 +2064,16 @@
   // it or is it callstub/compiled?
 
   // Move buffer to the expected parameter location
-  __ movl(rcx, STATE(_result._osr._osr_buf));
-
-  __ movl(rax, STATE(_result._osr._osr_entry));
-
-  __ cmpl(STATE(_prev_link), (int)NULL);                       // returning from "recursive" interpreter call?
+  __ movptr(rcx, STATE(_result._osr._osr_buf));
+
+  __ movptr(rax, STATE(_result._osr._osr_entry));
+
+  __ cmpptr(STATE(_prev_link), (int32_t)NULL_WORD);            // returning from "recursive" interpreter call?
   __ jcc(Assembler::equal, remove_initial_frame);              // back to native code (call_stub/c1/c2)
 
-  // __ movl(state, STATE(_prev_link));                           // unwind state
-  __ movl(rsi, STATE(_sender_sp));                             // get sender's sp in expected register
+  __ movptr(sender_sp_on_entry, STATE(_sender_sp));            // get sender's sp in expected register
   __ leave();                                                  // pop the frame
-  __ movl(rsp, rsi);                                           // trim any stack expansion
+  __ mov(rsp, sender_sp_on_entry);                             // trim any stack expansion
 
 
   // We know we are calling compiled so push specialized return
@@ -2006,14 +2087,14 @@
 
   __ bind(remove_initial_frame);
 
-  __ movl(rdx, STATE(_sender_sp));
+  __ movptr(rdx, STATE(_sender_sp));
   __ leave();
   // get real return
-  __ popl(rsi);
+  __ pop(rsi);
   // set stack to sender's sp
-  __ movl(rsp, rdx);
+  __ mov(rsp, rdx);
   // repush real return
-  __ pushl(rsi);
+  __ push(rsi);
   // Enter OSR nmethod
   __ jmp(rax);
 
@@ -2028,10 +2109,10 @@
   // stack points to next free location and not top element on expression stack
   // method expects sp to be pointing to topmost element
 
-  __ movl(rsp, STATE(_stack));                                       // pop args to c++ interpreter, set sp to java stack top
-  __ leal(rsp, Address(rsp, wordSize));
-
-  __ movl(rbx, STATE(_result._to_call._callee));                     // get method to execute
+  __ movptr(rsp, STATE(_stack));                                     // pop args to c++ interpreter, set sp to java stack top
+  __ lea(rsp, Address(rsp, wordSize));
+
+  __ movptr(rbx, STATE(_result._to_call._callee));                   // get method to execute
 
   // don't need a return address if reinvoking interpreter
 
@@ -2047,13 +2128,13 @@
   __ cmpptr(STATE(_result._to_call._callee_entry_point), entry.addr()); // returning to interpreter?
   __ jcc(Assembler::equal, re_dispatch);                             // yes
 
-  __ popl(rax);                                                      // pop dummy address
+  __ pop(rax);                                                       // pop dummy address
 
 
   // get specialized entry
-  __ movl(rax, STATE(_result._to_call._callee_entry_point));
+  __ movptr(rax, STATE(_result._to_call._callee_entry_point));
   // set sender SP
-  __ movl(rsi, rsp);
+  __ mov(sender_sp_on_entry, rsp);
 
   // method uses specialized entry, push a return so we look like call stub setup
   // this path will handle fact that result is returned in registers and not
@@ -2073,10 +2154,10 @@
   Label unwind_initial_with_pending_exception;
 
   __ bind(throw_exception);
-  __ cmpl(STATE(_prev_link), (int)NULL);                            // returning from recursive interpreter call?
+  __ cmpptr(STATE(_prev_link), (int32_t)NULL_WORD);                 // returning from recursive interpreter call?
   __ jcc(Assembler::equal, unwind_initial_with_pending_exception);  // no, back to native code (call_stub/c1/c2)
-  __ movl(rax, STATE(_locals));                                     // pop parameters get new stack value
-  __ addl(rax, wordSize);                                           // account for prepush before we return
+  __ movptr(rax, STATE(_locals));                                   // pop parameters get new stack value
+  __ addptr(rax, wordSize);                                         // account for prepush before we return
   __ jmp(unwind_recursive_activation);
 
   __ bind(unwind_initial_with_pending_exception);
--- a/hotspot/src/cpu/x86/vm/dump_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/dump_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -98,24 +98,24 @@
   // table.
 
 #ifdef WIN32
-  __ pushl(rcx);                        // save "this"
+  __ push(rcx);                         // save "this"
 #endif
-  __ movl(rcx, rax);
-  __ shrl(rcx, 8);                      // isolate vtable identifier.
-  __ shll(rcx, LogBytesPerWord);
+  __ mov(rcx, rax);
+  __ shrptr(rcx, 8);                    // isolate vtable identifier.
+  __ shlptr(rcx, LogBytesPerWord);
   Address index(noreg, rcx,  Address::times_1);
   ExternalAddress vtbl((address)vtbl_list);
   __ movptr(rdx, ArrayAddress(vtbl, index)); // get correct vtable address.
 #ifdef WIN32
-  __ popl(rcx);                         // restore "this"
+  __ pop(rcx);                          // restore "this"
 #else
-  __ movl(rcx, Address(rsp, 4));        // fetch "this"
+  __ movptr(rcx, Address(rsp, BytesPerWord));   // fetch "this"
 #endif
-  __ movl(Address(rcx, 0), rdx);        // update vtable pointer.
+  __ movptr(Address(rcx, 0), rdx);      // update vtable pointer.
 
-  __ andl(rax, 0x00ff);                 // isolate vtable method index
-  __ shll(rax, LogBytesPerWord);
-  __ addl(rax, rdx);                    // address of real method pointer.
+  __ andptr(rax, 0x00ff);                       // isolate vtable method index
+  __ shlptr(rax, LogBytesPerWord);
+  __ addptr(rax, rdx);                  // address of real method pointer.
   __ jmp(Address(rax, 0));              // get real method pointer.
 
   __ flush();
--- a/hotspot/src/cpu/x86/vm/dump_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/dump_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -90,22 +90,22 @@
   // are on the stack and the "this" pointer is in c_rarg0. In addition, rax
   // was set (above) to the offset of the method in the table.
 
-  __ pushq(c_rarg1);                    // save & free register
-  __ pushq(c_rarg0);                    // save "this"
-  __ movq(c_rarg0, rax);
-  __ shrq(c_rarg0, 8);                  // isolate vtable identifier.
-  __ shlq(c_rarg0, LogBytesPerWord);
+  __ push(c_rarg1);                     // save & free register
+  __ push(c_rarg0);                     // save "this"
+  __ mov(c_rarg0, rax);
+  __ shrptr(c_rarg0, 8);                // isolate vtable identifier.
+  __ shlptr(c_rarg0, LogBytesPerWord);
   __ lea(c_rarg1, ExternalAddress((address)vtbl_list)); // ptr to correct vtable list.
-  __ addq(c_rarg1, c_rarg0);            // ptr to list entry.
-  __ movq(c_rarg1, Address(c_rarg1, 0));        // get correct vtable address.
-  __ popq(c_rarg0);                     // restore "this"
-  __ movq(Address(c_rarg0, 0), c_rarg1);        // update vtable pointer.
+  __ addptr(c_rarg1, c_rarg0);          // ptr to list entry.
+  __ movptr(c_rarg1, Address(c_rarg1, 0));      // get correct vtable address.
+  __ pop(c_rarg0);                      // restore "this"
+  __ movptr(Address(c_rarg0, 0), c_rarg1);      // update vtable pointer.
 
-  __ andq(rax, 0x00ff);                 // isolate vtable method index
-  __ shlq(rax, LogBytesPerWord);
-  __ addq(rax, c_rarg1);                // address of real method pointer.
-  __ popq(c_rarg1);                     // restore register.
-  __ movq(rax, Address(rax, 0));        // get real method pointer.
+  __ andptr(rax, 0x00ff);                       // isolate vtable method index
+  __ shlptr(rax, LogBytesPerWord);
+  __ addptr(rax, c_rarg1);              // address of real method pointer.
+  __ pop(c_rarg1);                      // restore register.
+  __ movptr(rax, Address(rax, 0));      // get real method pointer.
   __ jmp(rax);                          // jump to the real method.
 
   __ flush();
--- a/hotspot/src/cpu/x86/vm/frame_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/frame_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -217,7 +217,8 @@
 
 void frame::patch_pc(Thread* thread, address pc) {
   if (TracePcPatching) {
-    tty->print_cr("patch_pc at address  0x%x [0x%x -> 0x%x] ", &((address *)sp())[-1], ((address *)sp())[-1], pc);
+    tty->print_cr("patch_pc at address" INTPTR_FORMAT " [" INTPTR_FORMAT " -> " INTPTR_FORMAT "] ",
+                  &((address *)sp())[-1], ((address *)sp())[-1], pc);
   }
   ((address *)sp())[-1] = pc;
   _cb = CodeCache::find_blob(pc);
--- a/hotspot/src/cpu/x86/vm/frame_x86.inline.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/frame_x86.inline.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -159,7 +159,7 @@
 
 inline intptr_t* frame::interpreter_frame_bcx_addr() const {
   assert(is_interpreted_frame(), "must be interpreted");
-  return (jint*) &(get_interpreterState()->_bcp);
+  return (intptr_t*) &(get_interpreterState()->_bcp);
 }
 
 
@@ -179,7 +179,7 @@
 
 inline intptr_t* frame::interpreter_frame_mdx_addr() const {
   assert(is_interpreted_frame(), "must be interpreted");
-  return (jint*) &(get_interpreterState()->_mdx);
+  return (intptr_t*) &(get_interpreterState()->_mdx);
 }
 
 // top of expression stack
--- a/hotspot/src/cpu/x86/vm/icache_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/icache_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -48,7 +48,7 @@
 
   __ bind(flush_line);
   __ clflush(Address(addr, 0));
-  __ addq(addr, ICache::line_size);
+  __ addptr(addr, ICache::line_size);
   __ decrementl(lines);
   __ jcc(Assembler::notZero, flush_line);
 
@@ -60,7 +60,7 @@
   const Address magic(rsp, 3*wordSize);
   __ lock(); __ addl(Address(rsp, 0), 0);
 #endif // AMD64
-  __ movl(rax, magic); // Handshake with caller to make sure it happened!
+  __ movptr(rax, magic); // Handshake with caller to make sure it happened!
   __ ret(0);
 
   // Must be set here so StubCodeMark destructor can call the flush stub.
--- a/hotspot/src/cpu/x86/vm/interp_masm_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interp_masm_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -29,8 +29,8 @@
 // Implementation of InterpreterMacroAssembler
 #ifdef CC_INTERP
 void InterpreterMacroAssembler::get_method(Register reg) {
-  movl(reg, Address(rbp, -(sizeof(BytecodeInterpreter) + 2 * wordSize)));
-  movl(reg, Address(reg, byte_offset_of(BytecodeInterpreter, _method)));
+  movptr(reg, Address(rbp, -(sizeof(BytecodeInterpreter) + 2 * wordSize)));
+  movptr(reg, Address(reg, byte_offset_of(BytecodeInterpreter, _method)));
 }
 #endif // CC_INTERP
 
@@ -53,7 +53,7 @@
   // when jvm built with ASSERTs.
 #ifdef ASSERT
   { Label L;
-    cmpl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_leaf_base: last_sp != NULL");
     bind(L);
@@ -79,7 +79,7 @@
 ) {
 #ifdef ASSERT
   { Label L;
-    cmpl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_base: last_sp != NULL");
     bind(L);
@@ -132,10 +132,11 @@
   const Address val_addr1(rcx, JvmtiThreadState::earlyret_value_offset()
                              + in_ByteSize(wordSize));
   switch (state) {
-    case atos: movl(rax, oop_addr);
-               movl(oop_addr, NULL_WORD);
+    case atos: movptr(rax, oop_addr);
+               movptr(oop_addr, (int32_t)NULL_WORD);
                verify_oop(rax, state);                break;
-    case ltos: movl(rdx, val_addr1);               // fall through
+    case ltos:
+               movl(rdx, val_addr1);               // fall through
     case btos:                                     // fall through
     case ctos:                                     // fall through
     case stos:                                     // fall through
@@ -146,9 +147,9 @@
     default  : ShouldNotReachHere();
   }
   // Clean up tos value in the thread object
-  movl(tos_addr,  (int) ilgl);
-  movl(val_addr,  NULL_WORD);
-  movl(val_addr1, NULL_WORD);
+  movl(tos_addr,  (int32_t) ilgl);
+  movptr(val_addr,  (int32_t)NULL_WORD);
+  NOT_LP64(movl(val_addr1, (int32_t)NULL_WORD));
 }
 
 
@@ -156,8 +157,8 @@
   if (JvmtiExport::can_force_early_return()) {
     Label L;
     Register tmp = java_thread;
-    movl(tmp, Address(tmp, JavaThread::jvmti_thread_state_offset()));
-    testl(tmp, tmp);
+    movptr(tmp, Address(tmp, JavaThread::jvmti_thread_state_offset()));
+    testptr(tmp, tmp);
     jcc(Assembler::zero, L); // if (thread->jvmti_thread_state() == NULL) exit;
 
     // Initiate earlyret handling only if it is not already being processed.
@@ -170,7 +171,7 @@
     // Call Interpreter::remove_activation_early_entry() to get the address of the
     // same-named entrypoint in the generated interpreter code.
     get_thread(java_thread);
-    movl(tmp, Address(java_thread, JavaThread::jvmti_thread_state_offset()));
+    movptr(tmp, Address(java_thread, JavaThread::jvmti_thread_state_offset()));
     pushl(Address(tmp, JvmtiThreadState::earlyret_tos_offset()));
     call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), 1);
     jmp(rax);
@@ -183,7 +184,7 @@
 void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset) {
   assert(bcp_offset >= 0, "bcp is still pointing to start of bytecode");
   movl(reg, Address(rsi, bcp_offset));
-  bswap(reg);
+  bswapl(reg);
   shrl(reg, 16);
 }
 
@@ -192,9 +193,9 @@
   assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");
   assert(cache != index, "must use different registers");
   load_unsigned_word(index, Address(rsi, bcp_offset));
-  movl(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
+  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
   assert(sizeof(ConstantPoolCacheEntry) == 4*wordSize, "adjust code below");
-  shll(index, 2); // convert from field index to ConstantPoolCacheEntry index
+  shlptr(index, 2); // convert from field index to ConstantPoolCacheEntry index
 }
 
 
@@ -206,10 +207,10 @@
                                // convert from field index to ConstantPoolCacheEntry index
                                // and from word offset to byte offset
   shll(tmp, 2 + LogBytesPerWord);
-  movl(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
+  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
                                // skip past the header
-  addl(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
-  addl(cache, tmp);            // construct pointer to cache entry
+  addptr(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
+  addptr(cache, tmp);            // construct pointer to cache entry
 }
 
 
@@ -232,22 +233,22 @@
   // if the super-klass is an interface or exceptionally deep in the Java
   // hierarchy and we have to scan the secondary superclass list the hard way.
   // See if we get an immediate positive hit
-  cmpl( rax, Address(Rsub_klass,rcx,Address::times_1) );
+  cmpptr( rax, Address(Rsub_klass,rcx,Address::times_1) );
   jcc( Assembler::equal,ok_is_subtype );
 
   // Check for immediate negative hit
   cmpl( rcx, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() );
   jcc( Assembler::notEqual, not_subtype );
   // Check for self
-  cmpl( Rsub_klass, rax );
+  cmpptr( Rsub_klass, rax );
   jcc( Assembler::equal, ok_is_subtype );
 
   // Now do a linear scan of the secondary super-klass chain.
-  movl( rdi, Address(Rsub_klass, sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()) );
+  movptr( rdi, Address(Rsub_klass, sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()) );
   // EDI holds the objArrayOop of secondary supers.
   movl( rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));// Load the array length
   // Skip to start of data; also clear Z flag incase ECX is zero
-  addl( rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT) );
+  addptr( rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT) );
   // Scan ECX words at [EDI] for occurance of EAX
   // Set NZ/Z based on last compare
   repne_scan();
@@ -255,7 +256,7 @@
   // Not equal?
   jcc( Assembler::notEqual, not_subtype );
   // Must be equal but missed in cache.  Update cache.
-  movl( Address(Rsub_klass, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax );
+  movptr( Address(Rsub_klass, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax );
   jmp( ok_is_subtype );
 
   bind(not_subtype);
@@ -276,7 +277,6 @@
     fld_d(Address(rsp, 0));
   }
 }
-#endif // CC_INTERP
 
 // Java Expression Stack
 
@@ -284,11 +284,11 @@
 void InterpreterMacroAssembler::verify_stack_tag(frame::Tag t) {
   if (TaggedStackInterpreter) {
     Label okay;
-    cmpl(Address(rsp, wordSize), (int)t);
+    cmpptr(Address(rsp, wordSize), (int32_t)t);
     jcc(Assembler::equal, okay);
     // Also compare if the stack value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpl(Address(rsp, 0), 0);
+    cmpptr(Address(rsp, 0), 0);
     jcc(Assembler::equal, okay);
     stop("Java Expression stack tag value is bad");
     bind(okay);
@@ -298,43 +298,43 @@
 
 void InterpreterMacroAssembler::pop_ptr(Register r) {
   debug_only(verify_stack_tag(frame::TagReference));
-  popl(r);
-  if (TaggedStackInterpreter) addl(rsp, 1 * wordSize);
+  pop(r);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_ptr(Register r, Register tag) {
-  popl(r);
+  pop(r);
   // Tag may not be reference for jsr, can be returnAddress
-  if (TaggedStackInterpreter) popl(tag);
+  if (TaggedStackInterpreter) pop(tag);
 }
 
 void InterpreterMacroAssembler::pop_i(Register r) {
   debug_only(verify_stack_tag(frame::TagValue));
-  popl(r);
-  if (TaggedStackInterpreter) addl(rsp, 1 * wordSize);
+  pop(r);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_l(Register lo, Register hi) {
   debug_only(verify_stack_tag(frame::TagValue));
-  popl(lo);
-  if (TaggedStackInterpreter) addl(rsp, 1 * wordSize);
+  pop(lo);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
   debug_only(verify_stack_tag(frame::TagValue));
-  popl(hi);
-  if (TaggedStackInterpreter) addl(rsp, 1 * wordSize);
+  pop(hi);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_f() {
   debug_only(verify_stack_tag(frame::TagValue));
   fld_s(Address(rsp, 0));
-  addl(rsp, 1 * wordSize);
-  if (TaggedStackInterpreter) addl(rsp, 1 * wordSize);
+  addptr(rsp, 1 * wordSize);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_d() {
   // Write double to stack contiguously and load into ST0
   pop_dtos_to_rsp();
   fld_d(Address(rsp, 0));
-  addl(rsp, 2 * wordSize);
+  addptr(rsp, 2 * wordSize);
 }
 
 
@@ -344,22 +344,22 @@
   if (TaggedStackInterpreter) {
     // Pop double value into scratch registers
     debug_only(verify_stack_tag(frame::TagValue));
-    popl(rax);
-    addl(rsp, 1* wordSize);
+    pop(rax);
+    addptr(rsp, 1* wordSize);
     debug_only(verify_stack_tag(frame::TagValue));
-    popl(rdx);
-    addl(rsp, 1* wordSize);
-    pushl(rdx);
-    pushl(rax);
+    pop(rdx);
+    addptr(rsp, 1* wordSize);
+    push(rdx);
+    push(rax);
   }
 }
 
 void InterpreterMacroAssembler::pop_ftos_to_rsp() {
   if (TaggedStackInterpreter) {
     debug_only(verify_stack_tag(frame::TagValue));
-    popl(rax);
-    addl(rsp, 1 * wordSize);
-    pushl(rax);  // ftos is at rsp
+    pop(rax);
+    addptr(rsp, 1 * wordSize);
+    push(rax);  // ftos is at rsp
   }
 }
 
@@ -380,31 +380,31 @@
 }
 
 void InterpreterMacroAssembler::push_ptr(Register r) {
-  if (TaggedStackInterpreter) pushl(frame::TagReference);
-  pushl(r);
+  if (TaggedStackInterpreter) push(frame::TagReference);
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_ptr(Register r, Register tag) {
-  if (TaggedStackInterpreter) pushl(tag);  // tag first
-  pushl(r);
+  if (TaggedStackInterpreter) push(tag);  // tag first
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_i(Register r) {
-  if (TaggedStackInterpreter) pushl(frame::TagValue);
-  pushl(r);
+  if (TaggedStackInterpreter) push(frame::TagValue);
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_l(Register lo, Register hi) {
-  if (TaggedStackInterpreter) pushl(frame::TagValue);
-  pushl(hi);
-  if (TaggedStackInterpreter) pushl(frame::TagValue);
-  pushl(lo);
+  if (TaggedStackInterpreter) push(frame::TagValue);
+  push(hi);
+  if (TaggedStackInterpreter) push(frame::TagValue);
+  push(lo);
 }
 
 void InterpreterMacroAssembler::push_f() {
-  if (TaggedStackInterpreter) pushl(frame::TagValue);
+  if (TaggedStackInterpreter) push(frame::TagValue);
   // Do not schedule for no AGI! Never write beyond rsp!
-  subl(rsp, 1 * wordSize);
+  subptr(rsp, 1 * wordSize);
   fstp_s(Address(rsp, 0));
 }
 
@@ -415,8 +415,8 @@
     //   high
     //   tag
     //   low
-    pushl(frame::TagValue);
-    subl(rsp, 3 * wordSize);
+    push(frame::TagValue);
+    subptr(rsp, 3 * wordSize);
     fstp_d(Address(rsp, 0));
     // move high word up to slot n-1
     movl(r, Address(rsp, 1*wordSize));
@@ -425,7 +425,7 @@
     movl(Address(rsp, 1*wordSize), frame::TagValue);
   } else {
     // Do not schedule for no AGI! Never write beyond rsp!
-    subl(rsp, 2 * wordSize);
+    subptr(rsp, 2 * wordSize);
     fstp_d(Address(rsp, 0));
   }
 }
@@ -447,22 +447,21 @@
   }
 }
 
-#ifndef CC_INTERP
 
 // Tagged stack helpers for swap and dup
 void InterpreterMacroAssembler::load_ptr_and_tag(int n, Register val,
                                                  Register tag) {
-  movl(val, Address(rsp, Interpreter::expr_offset_in_bytes(n)));
+  movptr(val, Address(rsp, Interpreter::expr_offset_in_bytes(n)));
   if (TaggedStackInterpreter) {
-    movl(tag, Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)));
+    movptr(tag, Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)));
   }
 }
 
 void InterpreterMacroAssembler::store_ptr_and_tag(int n, Register val,
                                                   Register tag) {
-  movl(Address(rsp, Interpreter::expr_offset_in_bytes(n)), val);
+  movptr(Address(rsp, Interpreter::expr_offset_in_bytes(n)), val);
   if (TaggedStackInterpreter) {
-    movl(Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)), tag);
+    movptr(Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)), tag);
   }
 }
 
@@ -471,10 +470,10 @@
 void InterpreterMacroAssembler::tag_local(frame::Tag tag, int n) {
   if (TaggedStackInterpreter) {
     if (tag == frame::TagCategory2) {
-      movl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n+1)), (int)frame::TagValue);
-      movl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int)frame::TagValue);
+      movptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n+1)), (int32_t)frame::TagValue);
+      movptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int32_t)frame::TagValue);
     } else {
-      movl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int)tag);
+      movptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int32_t)tag);
     }
   }
 }
@@ -482,13 +481,13 @@
 void InterpreterMacroAssembler::tag_local(frame::Tag tag, Register idx) {
   if (TaggedStackInterpreter) {
     if (tag == frame::TagCategory2) {
-      movl(Address(rdi, idx, Interpreter::stackElementScale(),
-                  Interpreter::local_tag_offset_in_bytes(1)), (int)frame::TagValue);
-      movl(Address(rdi, idx, Interpreter::stackElementScale(),
-                  Interpreter::local_tag_offset_in_bytes(0)), (int)frame::TagValue);
+      movptr(Address(rdi, idx, Interpreter::stackElementScale(),
+                  Interpreter::local_tag_offset_in_bytes(1)), (int32_t)frame::TagValue);
+      movptr(Address(rdi, idx, Interpreter::stackElementScale(),
+                    Interpreter::local_tag_offset_in_bytes(0)), (int32_t)frame::TagValue);
     } else {
-      movl(Address(rdi, idx, Interpreter::stackElementScale(),
-                             Interpreter::local_tag_offset_in_bytes(0)), (int)tag);
+      movptr(Address(rdi, idx, Interpreter::stackElementScale(),
+                               Interpreter::local_tag_offset_in_bytes(0)), (int32_t)tag);
     }
   }
 }
@@ -496,7 +495,7 @@
 void InterpreterMacroAssembler::tag_local(Register tag, Register idx) {
   if (TaggedStackInterpreter) {
     // can only be TagValue or TagReference
-    movl(Address(rdi, idx, Interpreter::stackElementScale(),
+    movptr(Address(rdi, idx, Interpreter::stackElementScale(),
                            Interpreter::local_tag_offset_in_bytes(0)), tag);
   }
 }
@@ -505,7 +504,7 @@
 void InterpreterMacroAssembler::tag_local(Register tag, int n) {
   if (TaggedStackInterpreter) {
     // can only be TagValue or TagReference
-    movl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), tag);
+    movptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), tag);
   }
 }
 
@@ -516,17 +515,17 @@
     if (tag == frame::TagCategory2) {
       Label nbl;
       t = frame::TagValue;  // change to what is stored in locals
-      cmpl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n+1)), (int)t);
+      cmpptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n+1)), (int32_t)t);
       jcc(Assembler::equal, nbl);
       stop("Local tag is bad for long/double");
       bind(nbl);
     }
     Label notBad;
-    cmpl(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int)t);
+    cmpptr(Address(rdi, Interpreter::local_tag_offset_in_bytes(n)), (int32_t)t);
     jcc(Assembler::equal, notBad);
     // Also compare if the local value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpl(Address(rdi, Interpreter::local_offset_in_bytes(n)), 0);
+    cmpptr(Address(rdi, Interpreter::local_offset_in_bytes(n)), 0);
     jcc(Assembler::equal, notBad);
     stop("Local tag is bad");
     bind(notBad);
@@ -539,19 +538,19 @@
     if (tag == frame::TagCategory2) {
       Label nbl;
       t = frame::TagValue;  // change to what is stored in locals
-      cmpl(Address(rdi, idx, Interpreter::stackElementScale(),
-                  Interpreter::local_tag_offset_in_bytes(1)), (int)t);
+      cmpptr(Address(rdi, idx, Interpreter::stackElementScale(),
+                  Interpreter::local_tag_offset_in_bytes(1)), (int32_t)t);
       jcc(Assembler::equal, nbl);
       stop("Local tag is bad for long/double");
       bind(nbl);
     }
     Label notBad;
     cmpl(Address(rdi, idx, Interpreter::stackElementScale(),
-                  Interpreter::local_tag_offset_in_bytes(0)), (int)t);
+                  Interpreter::local_tag_offset_in_bytes(0)), (int32_t)t);
     jcc(Assembler::equal, notBad);
     // Also compare if the local value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpl(Address(rdi, idx, Interpreter::stackElementScale(),
+    cmpptr(Address(rdi, idx, Interpreter::stackElementScale(),
                   Interpreter::local_offset_in_bytes(0)), 0);
     jcc(Assembler::equal, notBad);
     stop("Local tag is bad");
@@ -567,22 +566,22 @@
 
 
 void InterpreterMacroAssembler::super_call_VM_leaf(address entry_point, Register arg_1) {
-  pushl(arg_1);
+  push(arg_1);
   MacroAssembler::call_VM_leaf_base(entry_point, 1);
 }
 
 
 void InterpreterMacroAssembler::super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
-  pushl(arg_2);
-  pushl(arg_1);
+  push(arg_2);
+  push(arg_1);
   MacroAssembler::call_VM_leaf_base(entry_point, 2);
 }
 
 
 void InterpreterMacroAssembler::super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
-  pushl(arg_3);
-  pushl(arg_2);
-  pushl(arg_1);
+  push(arg_3);
+  push(arg_2);
+  push(arg_1);
   MacroAssembler::call_VM_leaf_base(entry_point, 3);
 }
 
@@ -591,9 +590,9 @@
 // in this thread in which case we must call the i2i entry
 void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {
   // set sender sp
-  leal(rsi, Address(rsp, wordSize));
+  lea(rsi, Address(rsp, wordSize));
   // record last_sp
-  movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), rsi);
+  movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), rsi);
 
   if (JvmtiExport::can_post_interpreter_events()) {
     Label run_compiled_code;
@@ -629,16 +628,16 @@
   verify_FPU(1, state);
   if (VerifyActivationFrameSize) {
     Label L;
-    movl(rcx, rbp);
-    subl(rcx, rsp);
+    mov(rcx, rbp);
+    subptr(rcx, rsp);
     int min_frame_size = (frame::link_offset - frame::interpreter_frame_initial_sp_offset) * wordSize;
-    cmpl(rcx, min_frame_size);
+    cmpptr(rcx, min_frame_size);
     jcc(Assembler::greaterEqual, L);
     stop("broken stack frame");
     bind(L);
   }
   if (verifyoop) verify_oop(rax, state);
-  Address index(noreg, rbx, Address::times_4);
+  Address index(noreg, rbx, Address::times_ptr);
   ExternalAddress tbl((address)table);
   ArrayAddress dispatch(tbl, index);
   jump(dispatch);
@@ -700,10 +699,10 @@
     in_bytes(JavaThread::do_not_unlock_if_synchronized_offset()));
 
   movbool(rbx, do_not_unlock_if_synchronized);
-  movl(rdi,rbx);
+  mov(rdi,rbx);
   movbool(do_not_unlock_if_synchronized, false); // reset the flag
 
-  movl(rbx, Address(rbp, frame::interpreter_frame_method_offset * wordSize)); // get method access flags
+  movptr(rbx, Address(rbp, frame::interpreter_frame_method_offset * wordSize)); // get method access flags
   movl(rcx, Address(rbx, methodOopDesc::access_flags_offset()));
 
   testl(rcx, JVM_ACC_SYNCHRONIZED);
@@ -711,7 +710,7 @@
 
   // Don't unlock anything if the _do_not_unlock_if_synchronized flag
   // is set.
-  movl(rcx,rdi);
+  mov(rcx,rdi);
   testbool(rcx);
   jcc(Assembler::notZero, no_unlock);
 
@@ -721,11 +720,11 @@
   // BasicObjectLock will be first in list, since this is a synchronized method. However, need
   // to check that the object has not been unlocked by an explicit monitorexit bytecode.
   const Address monitor(rbp, frame::interpreter_frame_initial_sp_offset * wordSize - (int)sizeof(BasicObjectLock));
-  leal  (rdx, monitor);                          // address of first monitor
+  lea   (rdx, monitor);                          // address of first monitor
 
-  movl  (rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
-  testl (rax, rax);
-  jcc   (Assembler::notZero, unlock);
+  movptr (rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
+  testptr(rax, rax);
+  jcc    (Assembler::notZero, unlock);
 
   pop(state);
   if (throw_monitor_exception) {
@@ -762,8 +761,8 @@
     const Address monitor_block_bot(rbp, frame::interpreter_frame_initial_sp_offset        * wordSize);
 
     bind(restart);
-    movl(rcx, monitor_block_top);             // points to current entry, starting with top-most entry
-    leal(rbx, monitor_block_bot);             // points to word before bottom of monitor block
+    movptr(rcx, monitor_block_top);           // points to current entry, starting with top-most entry
+    lea(rbx, monitor_block_bot);              // points to word before bottom of monitor block
     jmp(entry);
 
     // Entry already locked, need to throw exception
@@ -780,7 +779,7 @@
       // Unlock does not block, so don't have to worry about the frame
 
       push(state);
-      movl(rdx, rcx);
+      mov(rdx, rcx);
       unlock_object(rdx);
       pop(state);
 
@@ -793,12 +792,12 @@
     }
 
     bind(loop);
-    cmpl(Address(rcx, BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);  // check if current entry is used
+    cmpptr(Address(rcx, BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);  // check if current entry is used
     jcc(Assembler::notEqual, exception);
 
-    addl(rcx, entry_size);                       // otherwise advance to next entry
+    addptr(rcx, entry_size);                     // otherwise advance to next entry
     bind(entry);
-    cmpl(rcx, rbx);                              // check if bottom reached
+    cmpptr(rcx, rbx);                            // check if bottom reached
     jcc(Assembler::notEqual, loop);              // if not at bottom then check this entry
   }
 
@@ -812,22 +811,22 @@
   }
 
   // remove activation
-  movl(rbx, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
+  movptr(rbx, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
   leave();                                     // remove frame anchor
-  popl(ret_addr);                              // get return address
-  movl(rsp, rbx);                              // set sp to sender sp
+  pop(ret_addr);                               // get return address
+  mov(rsp, rbx);                               // set sp to sender sp
   if (UseSSE) {
     // float and double are returned in xmm register in SSE-mode
     if (state == ftos && UseSSE >= 1) {
-      subl(rsp, wordSize);
+      subptr(rsp, wordSize);
       fstp_s(Address(rsp, 0));
       movflt(xmm0, Address(rsp, 0));
-      addl(rsp, wordSize);
+      addptr(rsp, wordSize);
     } else if (state == dtos && UseSSE >= 2) {
-      subl(rsp, 2*wordSize);
+      subptr(rsp, 2*wordSize);
       fstp_d(Address(rsp, 0));
       movdbl(xmm0, Address(rsp, 0));
-      addl(rsp, 2*wordSize);
+      addptr(rsp, 2*wordSize);
     }
   }
 }
@@ -858,7 +857,7 @@
     Label slow_case;
 
     // Load object pointer into obj_reg %rcx
-    movl(obj_reg, Address(lock_reg, obj_offset));
+    movptr(obj_reg, Address(lock_reg, obj_offset));
 
     if (UseBiasedLocking) {
       // Note: we use noreg for the temporary register since it's hard
@@ -867,19 +866,19 @@
     }
 
     // Load immediate 1 into swap_reg %rax,
-    movl(swap_reg, 1);
+    movptr(swap_reg, (int32_t)1);
 
     // Load (object->mark() | 1) into swap_reg %rax,
-    orl(swap_reg, Address(obj_reg, 0));
+    orptr(swap_reg, Address(obj_reg, 0));
 
     // Save (object->mark() | 1) into BasicLock's displaced header
-    movl(Address(lock_reg, mark_offset), swap_reg);
+    movptr(Address(lock_reg, mark_offset), swap_reg);
 
     assert(lock_offset == 0, "displached header must be first word in BasicObjectLock");
     if (os::is_MP()) {
       lock();
     }
-    cmpxchg(lock_reg, Address(obj_reg, 0));
+    cmpxchgptr(lock_reg, Address(obj_reg, 0));
     if (PrintBiasedLockingStatistics) {
       cond_inc32(Assembler::zero,
                  ExternalAddress((address) BiasedLocking::fast_path_entry_count_addr()));
@@ -895,11 +894,11 @@
     // assuming both stack pointer and pagesize have their
     // least significant 2 bits clear.
     // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
-    subl(swap_reg, rsp);
-    andl(swap_reg, 3 - os::vm_page_size());
+    subptr(swap_reg, rsp);
+    andptr(swap_reg, 3 - os::vm_page_size());
 
     // Save the test result, for recursive case, the result is zero
-    movl(Address(lock_reg, mark_offset), swap_reg);
+    movptr(Address(lock_reg, mark_offset), swap_reg);
 
     if (PrintBiasedLockingStatistics) {
       cond_inc32(Assembler::zero,
@@ -939,36 +938,36 @@
 
     // Convert from BasicObjectLock structure to object and BasicLock structure
     // Store the BasicLock address into %rax,
-    leal(swap_reg, Address(lock_reg, BasicObjectLock::lock_offset_in_bytes()));
+    lea(swap_reg, Address(lock_reg, BasicObjectLock::lock_offset_in_bytes()));
 
     // Load oop into obj_reg(%rcx)
-    movl(obj_reg, Address(lock_reg, BasicObjectLock::obj_offset_in_bytes ()));
+    movptr(obj_reg, Address(lock_reg, BasicObjectLock::obj_offset_in_bytes ()));
 
     // Free entry
-    movl(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);
+    movptr(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);
 
     if (UseBiasedLocking) {
       biased_locking_exit(obj_reg, header_reg, done);
     }
 
     // Load the old header from BasicLock structure
-    movl(header_reg, Address(swap_reg, BasicLock::displaced_header_offset_in_bytes()));
+    movptr(header_reg, Address(swap_reg, BasicLock::displaced_header_offset_in_bytes()));
 
     // Test for recursion
-    testl(header_reg, header_reg);
+    testptr(header_reg, header_reg);
 
     // zero for recursive case
     jcc(Assembler::zero, done);
 
     // Atomic swap back the old header
     if (os::is_MP()) lock();
-    cmpxchg(header_reg, Address(obj_reg, 0));
+    cmpxchgptr(header_reg, Address(obj_reg, 0));
 
     // zero for recursive case
     jcc(Assembler::zero, done);
 
     // Call the runtime routine for slow case.
-    movl(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), obj_reg); // restore obj
+    movptr(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), obj_reg); // restore obj
     call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), lock_reg);
 
     bind(done);
@@ -983,8 +982,8 @@
 // Test ImethodDataPtr.  If it is null, continue at the specified label
 void InterpreterMacroAssembler::test_method_data_pointer(Register mdp, Label& zero_continue) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  movl(mdp, Address(rbp, frame::interpreter_frame_mdx_offset * wordSize));
-  testl(mdp, mdp);
+  movptr(mdp, Address(rbp, frame::interpreter_frame_mdx_offset * wordSize));
+  testptr(mdp, mdp);
   jcc(Assembler::zero, zero_continue);
 }
 
@@ -993,13 +992,13 @@
 void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Label zero_continue;
-  pushl(rax);
-  pushl(rbx);
+  push(rax);
+  push(rbx);
 
   get_method(rbx);
   // Test MDO to avoid the call if it is NULL.
-  movl(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-  testl(rax, rax);
+  movptr(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+  testptr(rax, rax);
   jcc(Assembler::zero, zero_continue);
 
   // rbx,: method
@@ -1007,53 +1006,55 @@
   call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), rbx, rsi);
   // rax,: mdi
 
-  movl(rbx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-  testl(rbx, rbx);
+  movptr(rbx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+  testptr(rbx, rbx);
   jcc(Assembler::zero, zero_continue);
-  addl(rbx, in_bytes(methodDataOopDesc::data_offset()));
-  addl(rbx, rax);
-  movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rbx);
+  addptr(rbx, in_bytes(methodDataOopDesc::data_offset()));
+  addptr(rbx, rax);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rbx);
 
   bind(zero_continue);
-  popl(rbx);
-  popl(rax);
+  pop(rbx);
+  pop(rax);
 }
 
 void InterpreterMacroAssembler::verify_method_data_pointer() {
   assert(ProfileInterpreter, "must be profiling interpreter");
 #ifdef ASSERT
   Label verify_continue;
-  pushl(rax);
-  pushl(rbx);
-  pushl(rcx);
-  pushl(rdx);
+  push(rax);
+  push(rbx);
+  push(rcx);
+  push(rdx);
   test_method_data_pointer(rcx, verify_continue); // If mdp is zero, continue
   get_method(rbx);
 
   // If the mdp is valid, it will point to a DataLayout header which is
   // consistent with the bcp.  The converse is highly probable also.
   load_unsigned_word(rdx, Address(rcx, in_bytes(DataLayout::bci_offset())));
-  addl(rdx, Address(rbx, methodOopDesc::const_offset()));
-  leal(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
-  cmpl(rdx, rsi);
+  addptr(rdx, Address(rbx, methodOopDesc::const_offset()));
+  lea(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
+  cmpptr(rdx, rsi);
   jcc(Assembler::equal, verify_continue);
   // rbx,: method
   // rsi: bcp
   // rcx: mdp
   call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp), rbx, rsi, rcx);
   bind(verify_continue);
-  popl(rdx);
-  popl(rcx);
-  popl(rbx);
-  popl(rax);
+  pop(rdx);
+  pop(rcx);
+  pop(rbx);
+  pop(rax);
 #endif // ASSERT
 }
 
 
 void InterpreterMacroAssembler::set_mdp_data_at(Register mdp_in, int constant, Register value) {
+  // %%% this seems to be used to store counter data which is surely 32bits
+  // however 64bit side stores 64 bits which seems wrong
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address data(mdp_in, constant);
-  movl(data, value);
+  movptr(data, value);
 }
 
 
@@ -1073,6 +1074,7 @@
   assert( DataLayout::counter_increment==1, "flow-free idiom only works with 1" );
   assert(ProfileInterpreter, "must be profiling interpreter");
 
+  // %%% 64bit treats this as 64 bit which seems unlikely
   if (decrement) {
     // Decrement the register.  Set condition codes.
     addl(data, -DataLayout::counter_increment);
@@ -1119,11 +1121,11 @@
                                                  Label& not_equal_continue) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   if (test_value_out == noreg) {
-    cmpl(value, Address(mdp_in, offset));
+    cmpptr(value, Address(mdp_in, offset));
   } else {
     // Put the test value into a register, so caller can use it:
-    movl(test_value_out, Address(mdp_in, offset));
-    cmpl(test_value_out, value);
+    movptr(test_value_out, Address(mdp_in, offset));
+    cmpptr(test_value_out, value);
   }
   jcc(Assembler::notEqual, not_equal_continue);
 }
@@ -1132,31 +1134,31 @@
 void InterpreterMacroAssembler::update_mdp_by_offset(Register mdp_in, int offset_of_disp) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address disp_address(mdp_in, offset_of_disp);
-  addl(mdp_in,disp_address);
-  movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in,disp_address);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
 void InterpreterMacroAssembler::update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address disp_address(mdp_in, reg, Address::times_1, offset_of_disp);
-  addl(mdp_in, disp_address);
-  movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in, disp_address);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
 void InterpreterMacroAssembler::update_mdp_by_constant(Register mdp_in, int constant) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  addl(mdp_in, constant);
-  movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in, constant);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
 void InterpreterMacroAssembler::update_mdp_for_ret(Register return_bci) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  pushl(return_bci);             // save/restore across call_VM
+  push(return_bci);             // save/restore across call_VM
   call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::update_mdp_for_ret), return_bci);
-  popl(return_bci);
+  pop(return_bci);
 }
 
 
@@ -1172,6 +1174,8 @@
     // We inline increment_mdp_data_at to return bumped_count in a register
     //increment_mdp_data_at(mdp, in_bytes(JumpData::taken_offset()));
     Address data(mdp, in_bytes(JumpData::taken_offset()));
+
+    // %%% 64bit treats these cells as 64 bit but they seem to be 32 bit
     movl(bumped_count,data);
     assert( DataLayout::counter_increment==1, "flow-free idiom only works with 1" );
     addl(bumped_count, DataLayout::counter_increment);
@@ -1289,7 +1293,7 @@
 
     if (row == start_row) {
       // Failed the equality check on receiver[n]...  Test for null.
-      testl(reg2, reg2);
+      testptr(reg2, reg2);
       if (start_row == last_row) {
         // The only thing left to do is handle the null case.
         jcc(Assembler::notZero, done);
@@ -1315,7 +1319,7 @@
   int recvr_offset = in_bytes(VirtualCallData::receiver_offset(start_row));
   set_mdp_data_at(mdp, recvr_offset, receiver);
   int count_offset = in_bytes(VirtualCallData::receiver_count_offset(start_row));
-  movl(reg2, DataLayout::counter_increment);
+  movptr(reg2, (int32_t)DataLayout::counter_increment);
   set_mdp_data_at(mdp, count_offset, reg2);
   jmp(done);
 }
@@ -1454,9 +1458,11 @@
     test_method_data_pointer(mdp, profile_continue);
 
     // Build the base (index * per_case_size_in_bytes()) + case_array_offset_in_bytes()
-    movl(reg2, in_bytes(MultiBranchData::per_case_size()));
-    imull(index, reg2);
-    addl(index, in_bytes(MultiBranchData::case_array_offset()));
+    movptr(reg2, (int32_t)in_bytes(MultiBranchData::per_case_size()));
+    // index is positive and so should have correct value if this code were
+    // used on 64bits
+    imulptr(index, reg2);
+    addptr(index, in_bytes(MultiBranchData::case_array_offset()));
 
     // Update the case count
     increment_mdp_data_at(mdp, index, in_bytes(MultiBranchData::relative_count_offset()));
@@ -1535,12 +1541,12 @@
 
   {
     SkipIfEqual skip_if(this, &DTraceMethodProbes, 0);
-    push(state);
+    NOT_CC_INTERP(push(state));
     get_thread(rbx);
     get_method(rcx);
     call_VM_leaf(
       CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
       rbx, rcx);
-    pop(state);
+    NOT_CC_INTERP(pop(state));
   }
 }
--- a/hotspot/src/cpu/x86/vm/interp_masm_x86_32.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interp_masm_x86_32.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -65,15 +65,15 @@
 
 #else
 
-  void save_bcp()                                          { movl(Address(rbp, frame::interpreter_frame_bcx_offset * wordSize), rsi); }
-  void restore_bcp()                                       { movl(rsi, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize)); }
-  void restore_locals()                                    { movl(rdi, Address(rbp, frame::interpreter_frame_locals_offset * wordSize)); }
+  void save_bcp()                                          { movptr(Address(rbp, frame::interpreter_frame_bcx_offset * wordSize), rsi); }
+  void restore_bcp()                                       { movptr(rsi, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize)); }
+  void restore_locals()                                    { movptr(rdi, Address(rbp, frame::interpreter_frame_locals_offset * wordSize)); }
 
   // Helpers for runtime call arguments/results
-  void get_method(Register reg)                            { movl(reg, Address(rbp, frame::interpreter_frame_method_offset * wordSize)); }
-  void get_constant_pool(Register reg)                     { get_method(reg); movl(reg, Address(reg, methodOopDesc::constants_offset())); }
-  void get_constant_pool_cache(Register reg)               { get_constant_pool(reg); movl(reg, Address(reg, constantPoolOopDesc::cache_offset_in_bytes())); }
-  void get_cpool_and_tags(Register cpool, Register tags)   { get_constant_pool(cpool); movl(tags, Address(cpool, constantPoolOopDesc::tags_offset_in_bytes()));
+  void get_method(Register reg)                            { movptr(reg, Address(rbp, frame::interpreter_frame_method_offset * wordSize)); }
+  void get_constant_pool(Register reg)                     { get_method(reg); movptr(reg, Address(reg, methodOopDesc::constants_offset())); }
+  void get_constant_pool_cache(Register reg)               { get_constant_pool(reg); movptr(reg, Address(reg, constantPoolOopDesc::cache_offset_in_bytes())); }
+  void get_cpool_and_tags(Register cpool, Register tags)   { get_constant_pool(cpool); movptr(tags, Address(cpool, constantPoolOopDesc::tags_offset_in_bytes()));
   }
   void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset);
   void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset);
@@ -82,8 +82,6 @@
   // Expression stack
   void f2ieee();                                           // truncate ftos to 32bits
   void d2ieee();                                           // truncate dtos to 64bits
-#endif // CC_INTERP
-
 
   void pop_ptr(Register r = rax);
   void pop_ptr(Register r, Register tag);
@@ -104,14 +102,25 @@
   void pop(TosState state);        // transition vtos -> state
   void push(TosState state);       // transition state -> vtos
 
+  void pop(Register r ) { ((MacroAssembler*)this)->pop(r); }
+
+  void push(Register r ) { ((MacroAssembler*)this)->push(r); }
+  void push(int32_t imm ) { ((MacroAssembler*)this)->push(imm); }
+
+  // These are dummies to prevent surprise implicit conversions to Register
+  void pop(void* v ); // Add unimplemented ambiguous method
+  void push(void* v );   // Add unimplemented ambiguous method
+
   DEBUG_ONLY(void verify_stack_tag(frame::Tag t);)
 
+#endif // CC_INTERP
+
 #ifndef CC_INTERP
 
   void empty_expression_stack()                            {
-       movl(rsp, Address(rbp, frame::interpreter_frame_monitor_block_top_offset * wordSize));
+       movptr(rsp, Address(rbp, frame::interpreter_frame_monitor_block_top_offset * wordSize));
       // NULL last_sp until next java call
-      movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+      movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   }
 
   // Tagged stack helpers for swap and dup
--- a/hotspot/src/cpu/x86/vm/interp_masm_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interp_masm_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -28,6 +28,15 @@
 
 // Implementation of InterpreterMacroAssembler
 
+#ifdef CC_INTERP
+void InterpreterMacroAssembler::get_method(Register reg) {
+  movptr(reg, Address(rbp, -(sizeof(BytecodeInterpreter) + 2 * wordSize)));
+  movptr(reg, Address(reg, byte_offset_of(BytecodeInterpreter, _method)));
+}
+#endif // CC_INTERP
+
+#ifndef CC_INTERP
+
 void InterpreterMacroAssembler::call_VM_leaf_base(address entry_point,
                                                   int number_of_arguments) {
   // interpreter specific
@@ -39,7 +48,7 @@
   save_bcp();
   {
     Label L;
-    cmpq(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int)NULL_WORD);
+    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_leaf_base:"
          " last_sp != NULL");
@@ -52,7 +61,7 @@
 #ifdef ASSERT
   {
     Label L;
-    cmpq(r13, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize));
+    cmpptr(r13, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize));
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_leaf_base:"
          " r13 not callee saved?");
@@ -60,7 +69,7 @@
   }
   {
     Label L;
-    cmpq(r14, Address(rbp, frame::interpreter_frame_locals_offset * wordSize));
+    cmpptr(r14, Address(rbp, frame::interpreter_frame_locals_offset * wordSize));
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_leaf_base:"
          " r14 not callee saved?");
@@ -86,7 +95,7 @@
 #ifdef ASSERT
   {
     Label L;
-    cmpq(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int)NULL_WORD);
+    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
     jcc(Assembler::equal, L);
     stop("InterpreterMacroAssembler::call_VM_leaf_base:"
          " last_sp != NULL");
@@ -127,15 +136,15 @@
 
 
 void InterpreterMacroAssembler::load_earlyret_value(TosState state) {
-  movq(rcx, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
+  movptr(rcx, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
   const Address tos_addr(rcx, JvmtiThreadState::earlyret_tos_offset());
   const Address oop_addr(rcx, JvmtiThreadState::earlyret_oop_offset());
   const Address val_addr(rcx, JvmtiThreadState::earlyret_value_offset());
   switch (state) {
-    case atos: movq(rax, oop_addr);
-               movptr(oop_addr, NULL_WORD);
+    case atos: movptr(rax, oop_addr);
+               movptr(oop_addr, (int32_t)NULL_WORD);
                verify_oop(rax, state);              break;
-    case ltos: movq(rax, val_addr);                 break;
+    case ltos: movptr(rax, val_addr);                 break;
     case btos:                                   // fall through
     case ctos:                                   // fall through
     case stos:                                   // fall through
@@ -147,15 +156,15 @@
   }
   // Clean up tos value in the thread object
   movl(tos_addr,  (int) ilgl);
-  movl(val_addr,  (int) NULL_WORD);
+  movl(val_addr,  (int32_t) NULL_WORD);
 }
 
 
 void InterpreterMacroAssembler::check_and_handle_earlyret(Register java_thread) {
   if (JvmtiExport::can_force_early_return()) {
     Label L;
-    movq(c_rarg0, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
-    testq(c_rarg0, c_rarg0);
+    movptr(c_rarg0, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
+    testptr(c_rarg0, c_rarg0);
     jcc(Assembler::zero, L); // if (thread->jvmti_thread_state() == NULL) exit;
 
     // Initiate earlyret handling only if it is not already being processed.
@@ -167,7 +176,7 @@
 
     // Call Interpreter::remove_activation_early_entry() to get the address of the
     // same-named entrypoint in the generated interpreter code.
-    movq(c_rarg0, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
+    movptr(c_rarg0, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
     movl(c_rarg0, Address(c_rarg0, JvmtiThreadState::earlyret_tos_offset()));
     call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), c_rarg0);
     jmp(rax);
@@ -192,7 +201,7 @@
   assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");
   assert(cache != index, "must use different registers");
   load_unsigned_word(index, Address(r13, bcp_offset));
-  movq(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
+  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
   assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");
   // convert from field index to ConstantPoolCacheEntry index
   shll(index, 2);
@@ -209,10 +218,10 @@
   // convert from field index to ConstantPoolCacheEntry index
   // and from word offset to byte offset
   shll(tmp, 2 + LogBytesPerWord);
-  movq(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
+  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
   // skip past the header
-  addq(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
-  addq(cache, tmp);  // construct pointer to cache entry
+  addptr(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
+  addptr(cache, tmp);  // construct pointer to cache entry
 }
 
 
@@ -247,24 +256,24 @@
   // exceptionally deep in the Java hierarchy and we have to scan the
   // secondary superclass list the hard way.  See if we get an
   // immediate positive hit
-  cmpq(rax, Address(Rsub_klass, rcx, Address::times_1));
+  cmpptr(rax, Address(Rsub_klass, rcx, Address::times_1));
   jcc(Assembler::equal,ok_is_subtype);
 
   // Check for immediate negative hit
   cmpl(rcx, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
   jcc( Assembler::notEqual, not_subtype );
   // Check for self
-  cmpq(Rsub_klass, rax);
+  cmpptr(Rsub_klass, rax);
   jcc(Assembler::equal, ok_is_subtype);
 
   // Now do a linear scan of the secondary super-klass chain.
-  movq(rdi, Address(Rsub_klass, sizeof(oopDesc) +
-                    Klass::secondary_supers_offset_in_bytes()));
+  movptr(rdi, Address(Rsub_klass, sizeof(oopDesc) +
+                      Klass::secondary_supers_offset_in_bytes()));
   // rdi holds the objArrayOop of secondary supers.
   // Load the array length
   movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
   // Skip to start of data; also clear Z flag incase rcx is zero
-  addq(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+  addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
   // Scan rcx words at [rdi] for occurance of rax
   // Set NZ/Z based on last compare
 
@@ -272,30 +281,31 @@
   // and we store values in objArrays always encoded, thus we need to encode value
   // before repne
   if (UseCompressedOops) {
-    pushq(rax);
+    push(rax);
     encode_heap_oop(rax);
     repne_scanl();
     // Not equal?
     jcc(Assembler::notEqual, not_subtype_pop);
     // restore heap oop here for movq
-    popq(rax);
+    pop(rax);
   } else {
-    repne_scanq();
+    repne_scan();
     jcc(Assembler::notEqual, not_subtype);
   }
   // Must be equal but missed in cache.  Update cache.
-  movq(Address(Rsub_klass, sizeof(oopDesc) +
+  movptr(Address(Rsub_klass, sizeof(oopDesc) +
                Klass::secondary_super_cache_offset_in_bytes()), rax);
   jmp(ok_is_subtype);
 
   bind(not_subtype_pop);
   // restore heap oop here for miss
-  if (UseCompressedOops) popq(rax);
+  if (UseCompressedOops) pop(rax);
   bind(not_subtype);
   profile_typecheck_failed(rcx); // blows rcx
 }
 
 
+
 // Java Expression Stack
 
 #ifdef ASSERT
@@ -307,17 +317,17 @@
     if (t == frame::TagCategory2) {
       tag = frame::TagValue;
       Label hokay;
-      cmpq(Address(rsp, 3*wordSize), (int)tag);
+      cmpptr(Address(rsp, 3*wordSize), (int32_t)tag);
       jcc(Assembler::equal, hokay);
       stop("Java Expression stack tag high value is bad");
       bind(hokay);
     }
     Label okay;
-    cmpq(Address(rsp, wordSize), (int)tag);
+    cmpptr(Address(rsp, wordSize), (int32_t)tag);
     jcc(Assembler::equal, okay);
     // Also compare if the stack value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpq(Address(rsp, 0), 0);
+    cmpptr(Address(rsp, 0), 0);
     jcc(Assembler::equal, okay);
     stop("Java Expression stack tag value is bad");
     bind(okay);
@@ -327,83 +337,83 @@
 
 void InterpreterMacroAssembler::pop_ptr(Register r) {
   debug_only(verify_stack_tag(frame::TagReference));
-  popq(r);
-  if (TaggedStackInterpreter) addq(rsp, 1 * wordSize);
+  pop(r);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_ptr(Register r, Register tag) {
-  popq(r);
-  if (TaggedStackInterpreter) popq(tag);
+  pop(r);
+  if (TaggedStackInterpreter) pop(tag);
 }
 
 void InterpreterMacroAssembler::pop_i(Register r) {
-  // XXX can't use popq currently, upper half non clean
+  // XXX can't use pop currently, upper half non clean
   debug_only(verify_stack_tag(frame::TagValue));
   movl(r, Address(rsp, 0));
-  addq(rsp, wordSize);
-  if (TaggedStackInterpreter) addq(rsp, 1 * wordSize);
+  addptr(rsp, wordSize);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_l(Register r) {
   debug_only(verify_stack_tag(frame::TagCategory2));
   movq(r, Address(rsp, 0));
-  addq(rsp, 2 * Interpreter::stackElementSize());
+  addptr(rsp, 2 * Interpreter::stackElementSize());
 }
 
 void InterpreterMacroAssembler::pop_f(XMMRegister r) {
   debug_only(verify_stack_tag(frame::TagValue));
   movflt(r, Address(rsp, 0));
-  addq(rsp, wordSize);
-  if (TaggedStackInterpreter) addq(rsp, 1 * wordSize);
+  addptr(rsp, wordSize);
+  if (TaggedStackInterpreter) addptr(rsp, 1 * wordSize);
 }
 
 void InterpreterMacroAssembler::pop_d(XMMRegister r) {
   debug_only(verify_stack_tag(frame::TagCategory2));
   movdbl(r, Address(rsp, 0));
-  addq(rsp, 2 * Interpreter::stackElementSize());
+  addptr(rsp, 2 * Interpreter::stackElementSize());
 }
 
 void InterpreterMacroAssembler::push_ptr(Register r) {
-  if (TaggedStackInterpreter) pushq(frame::TagReference);
-  pushq(r);
+  if (TaggedStackInterpreter) push(frame::TagReference);
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_ptr(Register r, Register tag) {
-  if (TaggedStackInterpreter) pushq(tag);
-  pushq(r);
+  if (TaggedStackInterpreter) push(tag);
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_i(Register r) {
-  if (TaggedStackInterpreter) pushq(frame::TagValue);
-  pushq(r);
+  if (TaggedStackInterpreter) push(frame::TagValue);
+  push(r);
 }
 
 void InterpreterMacroAssembler::push_l(Register r) {
   if (TaggedStackInterpreter) {
-    pushq(frame::TagValue);
-    subq(rsp, 1 * wordSize);
-    pushq(frame::TagValue);
-    subq(rsp, 1 * wordSize);
+    push(frame::TagValue);
+    subptr(rsp, 1 * wordSize);
+    push(frame::TagValue);
+    subptr(rsp, 1 * wordSize);
   } else {
-    subq(rsp, 2 * wordSize);
+    subptr(rsp, 2 * wordSize);
   }
   movq(Address(rsp, 0), r);
 }
 
 void InterpreterMacroAssembler::push_f(XMMRegister r) {
-  if (TaggedStackInterpreter) pushq(frame::TagValue);
-  subq(rsp, wordSize);
+  if (TaggedStackInterpreter) push(frame::TagValue);
+  subptr(rsp, wordSize);
   movflt(Address(rsp, 0), r);
 }
 
 void InterpreterMacroAssembler::push_d(XMMRegister r) {
   if (TaggedStackInterpreter) {
-    pushq(frame::TagValue);
-    subq(rsp, 1 * wordSize);
-    pushq(frame::TagValue);
-    subq(rsp, 1 * wordSize);
+    push(frame::TagValue);
+    subptr(rsp, 1 * wordSize);
+    push(frame::TagValue);
+    subptr(rsp, 1 * wordSize);
   } else {
-    subq(rsp, 2 * wordSize);
+    subptr(rsp, 2 * wordSize);
   }
   movdbl(Address(rsp, 0), r);
 }
@@ -441,20 +451,22 @@
 }
 
 
+
+
 // Tagged stack helpers for swap and dup
 void InterpreterMacroAssembler::load_ptr_and_tag(int n, Register val,
                                                  Register tag) {
-  movq(val, Address(rsp, Interpreter::expr_offset_in_bytes(n)));
+  movptr(val, Address(rsp, Interpreter::expr_offset_in_bytes(n)));
   if (TaggedStackInterpreter) {
-    movq(tag, Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)));
+    movptr(tag, Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)));
   }
 }
 
 void InterpreterMacroAssembler::store_ptr_and_tag(int n, Register val,
                                                   Register tag) {
-  movq(Address(rsp, Interpreter::expr_offset_in_bytes(n)), val);
+  movptr(Address(rsp, Interpreter::expr_offset_in_bytes(n)), val);
   if (TaggedStackInterpreter) {
-    movq(Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)), tag);
+    movptr(Address(rsp, Interpreter::expr_tag_offset_in_bytes(n)), tag);
   }
 }
 
@@ -463,12 +475,12 @@
 void InterpreterMacroAssembler::tag_local(frame::Tag tag, int n) {
   if (TaggedStackInterpreter) {
     if (tag == frame::TagCategory2) {
-      mov64(Address(r14, Interpreter::local_tag_offset_in_bytes(n+1)),
-           (intptr_t)frame::TagValue);
-      mov64(Address(r14, Interpreter::local_tag_offset_in_bytes(n)),
-           (intptr_t)frame::TagValue);
+      movptr(Address(r14, Interpreter::local_tag_offset_in_bytes(n+1)),
+           (int32_t)frame::TagValue);
+      movptr(Address(r14, Interpreter::local_tag_offset_in_bytes(n)),
+           (int32_t)frame::TagValue);
     } else {
-      mov64(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), (intptr_t)tag);
+      movptr(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), (int32_t)tag);
     }
   }
 }
@@ -476,13 +488,13 @@
 void InterpreterMacroAssembler::tag_local(frame::Tag tag, Register idx) {
   if (TaggedStackInterpreter) {
     if (tag == frame::TagCategory2) {
-      mov64(Address(r14, idx, Address::times_8,
-                  Interpreter::local_tag_offset_in_bytes(1)), (intptr_t)frame::TagValue);
-      mov64(Address(r14, idx, Address::times_8,
-                  Interpreter::local_tag_offset_in_bytes(0)), (intptr_t)frame::TagValue);
+      movptr(Address(r14, idx, Address::times_8,
+                  Interpreter::local_tag_offset_in_bytes(1)), (int32_t)frame::TagValue);
+      movptr(Address(r14, idx, Address::times_8,
+                  Interpreter::local_tag_offset_in_bytes(0)), (int32_t)frame::TagValue);
     } else {
-      mov64(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)),
-           (intptr_t)tag);
+      movptr(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)),
+           (int32_t)tag);
     }
   }
 }
@@ -490,7 +502,7 @@
 void InterpreterMacroAssembler::tag_local(Register tag, Register idx) {
   if (TaggedStackInterpreter) {
     // can only be TagValue or TagReference
-    movq(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)), tag);
+    movptr(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)), tag);
   }
 }
 
@@ -498,7 +510,7 @@
 void InterpreterMacroAssembler::tag_local(Register tag, int n) {
   if (TaggedStackInterpreter) {
     // can only be TagValue or TagReference
-    movq(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), tag);
+    movptr(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), tag);
   }
 }
 
@@ -509,17 +521,17 @@
     if (tag == frame::TagCategory2) {
       Label nbl;
       t = frame::TagValue;  // change to what is stored in locals
-      cmpq(Address(r14, Interpreter::local_tag_offset_in_bytes(n+1)), (int)t);
+      cmpptr(Address(r14, Interpreter::local_tag_offset_in_bytes(n+1)), (int32_t)t);
       jcc(Assembler::equal, nbl);
       stop("Local tag is bad for long/double");
       bind(nbl);
     }
     Label notBad;
-    cmpq(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), (int)t);
+    cmpq(Address(r14, Interpreter::local_tag_offset_in_bytes(n)), (int32_t)t);
     jcc(Assembler::equal, notBad);
     // Also compare if the local value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpq(Address(r14, Interpreter::local_offset_in_bytes(n)), 0);
+    cmpptr(Address(r14, Interpreter::local_offset_in_bytes(n)), 0);
     jcc(Assembler::equal, notBad);
     stop("Local tag is bad");
     bind(notBad);
@@ -532,17 +544,17 @@
     if (tag == frame::TagCategory2) {
       Label nbl;
       t = frame::TagValue;  // change to what is stored in locals
-      cmpq(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(1)), (int)t);
+      cmpptr(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(1)), (int32_t)t);
       jcc(Assembler::equal, nbl);
       stop("Local tag is bad for long/double");
       bind(nbl);
     }
     Label notBad;
-    cmpq(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)), (int)t);
+    cmpptr(Address(r14, idx, Address::times_8, Interpreter::local_tag_offset_in_bytes(0)), (int32_t)t);
     jcc(Assembler::equal, notBad);
     // Also compare if the local value is zero, then the tag might
     // not have been set coming from deopt.
-    cmpq(Address(r14, idx, Address::times_8, Interpreter::local_offset_in_bytes(0)), 0);
+    cmpptr(Address(r14, idx, Address::times_8, Interpreter::local_offset_in_bytes(0)), 0);
     jcc(Assembler::equal, notBad);
     stop("Local tag is bad");
     bind(notBad);
@@ -559,7 +571,7 @@
 void InterpreterMacroAssembler::super_call_VM_leaf(address entry_point,
                                                    Register arg_1) {
   if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
+    mov(c_rarg0, arg_1);
   }
   MacroAssembler::call_VM_leaf_base(entry_point, 1);
 }
@@ -571,10 +583,10 @@
   assert(c_rarg0 != arg_2, "smashed argument");
   assert(c_rarg1 != arg_1, "smashed argument");
   if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
+    mov(c_rarg0, arg_1);
   }
   if (c_rarg1 != arg_2) {
-    movq(c_rarg1, arg_2);
+    mov(c_rarg1, arg_2);
   }
   MacroAssembler::call_VM_leaf_base(entry_point, 2);
 }
@@ -590,13 +602,13 @@
   assert(c_rarg2 != arg_1, "smashed argument");
   assert(c_rarg2 != arg_2, "smashed argument");
   if (c_rarg0 != arg_1) {
-    movq(c_rarg0, arg_1);
+    mov(c_rarg0, arg_1);
   }
   if (c_rarg1 != arg_2) {
-    movq(c_rarg1, arg_2);
+    mov(c_rarg1, arg_2);
   }
   if (c_rarg2 != arg_3) {
-    movq(c_rarg2, arg_3);
+    mov(c_rarg2, arg_3);
   }
   MacroAssembler::call_VM_leaf_base(entry_point, 3);
 }
@@ -605,9 +617,9 @@
 // in this thread in which case we must call the i2i entry
 void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {
   // set sender sp
-  leaq(r13, Address(rsp, wordSize));
+  lea(r13, Address(rsp, wordSize));
   // record last_sp
-  movq(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), r13);
+  movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), r13);
 
   if (JvmtiExport::can_post_interpreter_events()) {
     Label run_compiled_code;
@@ -644,12 +656,12 @@
   verify_FPU(1, state);
   if (VerifyActivationFrameSize) {
     Label L;
-    movq(rcx, rbp);
-    subq(rcx, rsp);
-    int min_frame_size =
+    mov(rcx, rbp);
+    subptr(rcx, rsp);
+    int32_t min_frame_size =
       (frame::link_offset - frame::interpreter_frame_initial_sp_offset) *
       wordSize;
-    cmpq(rcx, min_frame_size);
+    cmpptr(rcx, (int32_t)min_frame_size);
     jcc(Assembler::greaterEqual, L);
     stop("broken stack frame");
     bind(L);
@@ -678,7 +690,7 @@
   // load next bytecode (load before advancing r13 to prevent AGI)
   load_unsigned_byte(rbx, Address(r13, step));
   // advance r13
-  incrementq(r13, step);
+  increment(r13, step);
   dispatch_base(state, Interpreter::dispatch_table(state));
 }
 
@@ -718,7 +730,7 @@
   movbool(do_not_unlock_if_synchronized, false); // reset the flag
 
  // get method access flags
-  movq(rbx, Address(rbp, frame::interpreter_frame_method_offset * wordSize));
+  movptr(rbx, Address(rbp, frame::interpreter_frame_method_offset * wordSize));
   movl(rcx, Address(rbx, methodOopDesc::access_flags_offset()));
   testl(rcx, JVM_ACC_SYNCHRONIZED);
   jcc(Assembler::zero, unlocked);
@@ -738,10 +750,10 @@
                         wordSize - (int) sizeof(BasicObjectLock));
   // We use c_rarg1 so that if we go slow path it will be the correct
   // register for unlock_object to pass to VM directly
-  leaq(c_rarg1, monitor); // address of first monitor
+  lea(c_rarg1, monitor); // address of first monitor
 
-  movq(rax, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
-  testq(rax, rax);
+  movptr(rax, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
+  testptr(rax, rax);
   jcc(Assembler::notZero, unlock);
 
   pop(state);
@@ -783,9 +795,9 @@
     bind(restart);
     // We use c_rarg1 so that if we go slow path it will be the correct
     // register for unlock_object to pass to VM directly
-    movq(c_rarg1, monitor_block_top); // points to current entry, starting
+    movptr(c_rarg1, monitor_block_top); // points to current entry, starting
                                   // with top-most entry
-    leaq(rbx, monitor_block_bot); // points to word before bottom of
+    lea(rbx, monitor_block_bot);  // points to word before bottom of
                                   // monitor block
     jmp(entry);
 
@@ -818,12 +830,12 @@
 
     bind(loop);
     // check if current entry is used
-    cmpq(Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()), (int) NULL);
+    cmpptr(Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()), (int32_t) NULL);
     jcc(Assembler::notEqual, exception);
 
-    addq(c_rarg1, entry_size); // otherwise advance to next entry
+    addptr(c_rarg1, entry_size); // otherwise advance to next entry
     bind(entry);
-    cmpq(c_rarg1, rbx); // check if bottom reached
+    cmpptr(c_rarg1, rbx); // check if bottom reached
     jcc(Assembler::notEqual, loop); // if not at bottom then check this entry
   }
 
@@ -838,13 +850,15 @@
 
   // remove activation
   // get sender sp
-  movq(rbx,
-       Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize));
+  movptr(rbx,
+         Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize));
   leave();                           // remove frame anchor
-  popq(ret_addr);                    // get return address
-  movq(rsp, rbx);                    // set sp to sender sp
+  pop(ret_addr);                     // get return address
+  mov(rsp, rbx);                     // set sp to sender sp
 }
 
+#endif // C_INTERP
+
 // Lock object
 //
 // Args:
@@ -875,7 +889,7 @@
     Label slow_case;
 
     // Load object pointer into obj_reg %c_rarg3
-    movq(obj_reg, Address(lock_reg, obj_offset));
+    movptr(obj_reg, Address(lock_reg, obj_offset));
 
     if (UseBiasedLocking) {
       biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, done, &slow_case);
@@ -885,16 +899,16 @@
     movl(swap_reg, 1);
 
     // Load (object->mark() | 1) into swap_reg %rax
-    orq(swap_reg, Address(obj_reg, 0));
+    orptr(swap_reg, Address(obj_reg, 0));
 
     // Save (object->mark() | 1) into BasicLock's displaced header
-    movq(Address(lock_reg, mark_offset), swap_reg);
+    movptr(Address(lock_reg, mark_offset), swap_reg);
 
     assert(lock_offset == 0,
            "displached header must be first word in BasicObjectLock");
 
     if (os::is_MP()) lock();
-    cmpxchgq(lock_reg, Address(obj_reg, 0));
+    cmpxchgptr(lock_reg, Address(obj_reg, 0));
     if (PrintBiasedLockingStatistics) {
       cond_inc32(Assembler::zero,
                  ExternalAddress((address) BiasedLocking::fast_path_entry_count_addr()));
@@ -910,11 +924,11 @@
     // assuming both stack pointer and pagesize have their
     // least significant 3 bits clear.
     // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
-    subq(swap_reg, rsp);
-    andq(swap_reg, 7 - os::vm_page_size());
+    subptr(swap_reg, rsp);
+    andptr(swap_reg, 7 - os::vm_page_size());
 
     // Save the test result, for recursive case, the result is zero
-    movq(Address(lock_reg, mark_offset), swap_reg);
+    movptr(Address(lock_reg, mark_offset), swap_reg);
 
     if (PrintBiasedLockingStatistics) {
       cond_inc32(Assembler::zero,
@@ -963,37 +977,37 @@
 
     // Convert from BasicObjectLock structure to object and BasicLock
     // structure Store the BasicLock address into %rax
-    leaq(swap_reg, Address(lock_reg, BasicObjectLock::lock_offset_in_bytes()));
+    lea(swap_reg, Address(lock_reg, BasicObjectLock::lock_offset_in_bytes()));
 
     // Load oop into obj_reg(%c_rarg3)
-    movq(obj_reg, Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()));
+    movptr(obj_reg, Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()));
 
     // Free entry
-    movptr(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);
+    movptr(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);
 
     if (UseBiasedLocking) {
       biased_locking_exit(obj_reg, header_reg, done);
     }
 
     // Load the old header from BasicLock structure
-    movq(header_reg, Address(swap_reg,
-                             BasicLock::displaced_header_offset_in_bytes()));
+    movptr(header_reg, Address(swap_reg,
+                               BasicLock::displaced_header_offset_in_bytes()));
 
     // Test for recursion
-    testq(header_reg, header_reg);
+    testptr(header_reg, header_reg);
 
     // zero for recursive case
     jcc(Assembler::zero, done);
 
     // Atomic swap back the old header
     if (os::is_MP()) lock();
-    cmpxchgq(header_reg, Address(obj_reg, 0));
+    cmpxchgptr(header_reg, Address(obj_reg, 0));
 
     // zero for recursive case
     jcc(Assembler::zero, done);
 
     // Call the runtime routine for slow case.
-    movq(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()),
+    movptr(Address(lock_reg, BasicObjectLock::obj_offset_in_bytes()),
          obj_reg); // restore obj
     call_VM(noreg,
             CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit),
@@ -1005,12 +1019,13 @@
   }
 }
 
+#ifndef CC_INTERP
 
 void InterpreterMacroAssembler::test_method_data_pointer(Register mdp,
                                                          Label& zero_continue) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  movq(mdp, Address(rbp, frame::interpreter_frame_mdx_offset * wordSize));
-  testq(mdp, mdp);
+  movptr(mdp, Address(rbp, frame::interpreter_frame_mdx_offset * wordSize));
+  testptr(mdp, mdp);
   jcc(Assembler::zero, zero_continue);
 }
 
@@ -1019,13 +1034,13 @@
 void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Label zero_continue;
-  pushq(rax);
-  pushq(rbx);
+  push(rax);
+  push(rbx);
 
   get_method(rbx);
   // Test MDO to avoid the call if it is NULL.
-  movq(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-  testq(rax, rax);
+  movptr(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+  testptr(rax, rax);
   jcc(Assembler::zero, zero_continue);
 
   // rbx: method
@@ -1033,26 +1048,26 @@
   call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), rbx, r13);
   // rax: mdi
 
-  movq(rbx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-  testq(rbx, rbx);
+  movptr(rbx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+  testptr(rbx, rbx);
   jcc(Assembler::zero, zero_continue);
-  addq(rbx, in_bytes(methodDataOopDesc::data_offset()));
-  addq(rbx, rax);
-  movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rbx);
+  addptr(rbx, in_bytes(methodDataOopDesc::data_offset()));
+  addptr(rbx, rax);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rbx);
 
   bind(zero_continue);
-  popq(rbx);
-  popq(rax);
+  pop(rbx);
+  pop(rax);
 }
 
 void InterpreterMacroAssembler::verify_method_data_pointer() {
   assert(ProfileInterpreter, "must be profiling interpreter");
 #ifdef ASSERT
   Label verify_continue;
-  pushq(rax);
-  pushq(rbx);
-  pushq(c_rarg3);
-  pushq(c_rarg2);
+  push(rax);
+  push(rbx);
+  push(c_rarg3);
+  push(c_rarg2);
   test_method_data_pointer(c_rarg3, verify_continue); // If mdp is zero, continue
   get_method(rbx);
 
@@ -1060,9 +1075,9 @@
   // consistent with the bcp.  The converse is highly probable also.
   load_unsigned_word(c_rarg2,
                      Address(c_rarg3, in_bytes(DataLayout::bci_offset())));
-  addq(c_rarg2, Address(rbx, methodOopDesc::const_offset()));
-  leaq(c_rarg2, Address(c_rarg2, constMethodOopDesc::codes_offset()));
-  cmpq(c_rarg2, r13);
+  addptr(c_rarg2, Address(rbx, methodOopDesc::const_offset()));
+  lea(c_rarg2, Address(c_rarg2, constMethodOopDesc::codes_offset()));
+  cmpptr(c_rarg2, r13);
   jcc(Assembler::equal, verify_continue);
   // rbx: method
   // r13: bcp
@@ -1070,10 +1085,10 @@
   call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp),
                rbx, r13, c_rarg3);
   bind(verify_continue);
-  popq(c_rarg2);
-  popq(c_rarg3);
-  popq(rbx);
-  popq(rax);
+  pop(c_rarg2);
+  pop(c_rarg3);
+  pop(rbx);
+  pop(rax);
 #endif // ASSERT
 }
 
@@ -1083,7 +1098,7 @@
                                                 Register value) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address data(mdp_in, constant);
-  movq(data, value);
+  movptr(data, value);
 }
 
 
@@ -1099,22 +1114,24 @@
 void InterpreterMacroAssembler::increment_mdp_data_at(Address data,
                                                       bool decrement) {
   assert(ProfileInterpreter, "must be profiling interpreter");
+  // %%% this does 64bit counters at best it is wasting space
+  // at worst it is a rare bug when counters overflow
 
   if (decrement) {
     // Decrement the register.  Set condition codes.
-    addq(data, -DataLayout::counter_increment);
+    addptr(data, (int32_t) -DataLayout::counter_increment);
     // If the decrement causes the counter to overflow, stay negative
     Label L;
     jcc(Assembler::negative, L);
-    addq(data, DataLayout::counter_increment);
+    addptr(data, (int32_t) DataLayout::counter_increment);
     bind(L);
   } else {
     assert(DataLayout::counter_increment == 1,
            "flow-free idiom only works with 1");
     // Increment the register.  Set carry flag.
-    addq(data, DataLayout::counter_increment);
+    addptr(data, DataLayout::counter_increment);
     // If the increment causes the counter to overflow, pull back by 1.
-    sbbq(data, 0);
+    sbbptr(data, (int32_t)0);
   }
 }
 
@@ -1146,11 +1163,11 @@
                                                  Label& not_equal_continue) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   if (test_value_out == noreg) {
-    cmpq(value, Address(mdp_in, offset));
+    cmpptr(value, Address(mdp_in, offset));
   } else {
     // Put the test value into a register, so caller can use it:
-    movq(test_value_out, Address(mdp_in, offset));
-    cmpq(test_value_out, value);
+    movptr(test_value_out, Address(mdp_in, offset));
+    cmpptr(test_value_out, value);
   }
   jcc(Assembler::notEqual, not_equal_continue);
 }
@@ -1160,8 +1177,8 @@
                                                      int offset_of_disp) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address disp_address(mdp_in, offset_of_disp);
-  addq(mdp_in, disp_address);
-  movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in, disp_address);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
@@ -1170,26 +1187,26 @@
                                                      int offset_of_disp) {
   assert(ProfileInterpreter, "must be profiling interpreter");
   Address disp_address(mdp_in, reg, Address::times_1, offset_of_disp);
-  addq(mdp_in, disp_address);
-  movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in, disp_address);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
 void InterpreterMacroAssembler::update_mdp_by_constant(Register mdp_in,
                                                        int constant) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  addq(mdp_in, constant);
-  movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
+  addptr(mdp_in, constant);
+  movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), mdp_in);
 }
 
 
 void InterpreterMacroAssembler::update_mdp_for_ret(Register return_bci) {
   assert(ProfileInterpreter, "must be profiling interpreter");
-  pushq(return_bci); // save/restore across call_VM
+  push(return_bci); // save/restore across call_VM
   call_VM(noreg,
           CAST_FROM_FN_PTR(address, InterpreterRuntime::update_mdp_for_ret),
           return_bci);
-  popq(return_bci);
+  pop(return_bci);
 }
 
 
@@ -1206,12 +1223,12 @@
     // We inline increment_mdp_data_at to return bumped_count in a register
     //increment_mdp_data_at(mdp, in_bytes(JumpData::taken_offset()));
     Address data(mdp, in_bytes(JumpData::taken_offset()));
-    movq(bumped_count, data);
+    movptr(bumped_count, data);
     assert(DataLayout::counter_increment == 1,
             "flow-free idiom only works with 1");
-    addq(bumped_count, DataLayout::counter_increment);
-    sbbq(bumped_count, 0);
-    movq(data, bumped_count); // Store back out
+    addptr(bumped_count, DataLayout::counter_increment);
+    sbbptr(bumped_count, 0);
+    movptr(data, bumped_count); // Store back out
 
     // The method data pointer needs to be updated to reflect the new target.
     update_mdp_by_offset(mdp, in_bytes(JumpData::displacement_offset()));
@@ -1339,7 +1356,7 @@
 
     if (test_for_null_also) {
       // Failed the equality check on receiver[n]...  Test for null.
-      testq(reg2, reg2);
+      testptr(reg2, reg2);
       if (start_row == last_row) {
         // The only thing left to do is handle the null case.
         jcc(Assembler::notZero, done);
@@ -1535,8 +1552,8 @@
     // Build the base (index * per_case_size_in_bytes()) +
     // case_array_offset_in_bytes()
     movl(reg2, in_bytes(MultiBranchData::per_case_size()));
-    imulq(index, reg2); // XXX l ?
-    addq(index, in_bytes(MultiBranchData::case_array_offset())); // XXX l ?
+    imulptr(index, reg2); // XXX l ?
+    addptr(index, in_bytes(MultiBranchData::case_array_offset())); // XXX l ?
 
     // Update the case count
     increment_mdp_data_at(mdp,
@@ -1554,6 +1571,7 @@
 }
 
 
+
 void InterpreterMacroAssembler::verify_oop(Register reg, TosState state) {
   if (state == atos) {
     MacroAssembler::verify_oop(reg);
@@ -1562,6 +1580,7 @@
 
 void InterpreterMacroAssembler::verify_FPU(int stack_depth, TosState state) {
 }
+#endif // !CC_INTERP
 
 
 void InterpreterMacroAssembler::notify_method_entry() {
@@ -1598,22 +1617,25 @@
     // method result is saved across the call to post_method_exit. If this
     // is changed then the interpreter_frame_result implementation will
     // need to be updated too.
-    push(state);
+
+    // For c++ interpreter the result is always stored at a known location in the frame
+    // template interpreter will leave it on the top of the stack.
+    NOT_CC_INTERP(push(state);)
     movl(rdx, Address(r15_thread, JavaThread::interp_only_mode_offset()));
     testl(rdx, rdx);
     jcc(Assembler::zero, L);
     call_VM(noreg,
             CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_exit));
     bind(L);
-    pop(state);
+    NOT_CC_INTERP(pop(state));
   }
 
   {
     SkipIfEqual skip(this, &DTraceMethodProbes, false);
-    push(state);
+    NOT_CC_INTERP(push(state));
     get_method(c_rarg1);
     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
                  r15_thread, c_rarg1);
-    pop(state);
+    NOT_CC_INTERP(pop(state));
   }
 }
--- a/hotspot/src/cpu/x86/vm/interp_masm_x86_64.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interp_masm_x86_64.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -25,8 +25,8 @@
 // This file specializes the assember with interpreter-specific macros
 
 
-class InterpreterMacroAssembler
-  : public MacroAssembler {
+class InterpreterMacroAssembler: public MacroAssembler {
+#ifndef CC_INTERP
  protected:
   // Interpreter specific version of call_VM_base
   virtual void call_VM_leaf_base(address entry_point,
@@ -44,52 +44,53 @@
 
   // base routine for all dispatches
   void dispatch_base(TosState state, address* table, bool verifyoop = true);
+#endif // CC_INTERP
 
  public:
-  InterpreterMacroAssembler(CodeBuffer* code)
-    : MacroAssembler(code)
-  {}
+  InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code) {}
 
   void load_earlyret_value(TosState state);
 
+#ifdef CC_INTERP
+  void save_bcp()                                          { /*  not needed in c++ interpreter and harmless */ }
+  void restore_bcp()                                       { /*  not needed in c++ interpreter and harmless */ }
+
+  // Helpers for runtime call arguments/results
+  void get_method(Register reg);
+
+#else
+
   // Interpreter-specific registers
-  void save_bcp()
-  {
-    movq(Address(rbp, frame::interpreter_frame_bcx_offset * wordSize), r13);
+  void save_bcp() {
+    movptr(Address(rbp, frame::interpreter_frame_bcx_offset * wordSize), r13);
   }
 
-  void restore_bcp()
-  {
-    movq(r13, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize));
+  void restore_bcp() {
+    movptr(r13, Address(rbp, frame::interpreter_frame_bcx_offset * wordSize));
   }
 
-  void restore_locals()
-  {
-    movq(r14, Address(rbp, frame::interpreter_frame_locals_offset * wordSize));
+  void restore_locals() {
+    movptr(r14, Address(rbp, frame::interpreter_frame_locals_offset * wordSize));
   }
 
   // Helpers for runtime call arguments/results
-  void get_method(Register reg)
-  {
-    movq(reg, Address(rbp, frame::interpreter_frame_method_offset * wordSize));
+  void get_method(Register reg) {
+    movptr(reg, Address(rbp, frame::interpreter_frame_method_offset * wordSize));
   }
 
-  void get_constant_pool(Register reg)
-  {
+  void get_constant_pool(Register reg) {
     get_method(reg);
-    movq(reg, Address(reg, methodOopDesc::constants_offset()));
+    movptr(reg, Address(reg, methodOopDesc::constants_offset()));
   }
 
-  void get_constant_pool_cache(Register reg)
-  {
+  void get_constant_pool_cache(Register reg) {
     get_constant_pool(reg);
-    movq(reg, Address(reg, constantPoolOopDesc::cache_offset_in_bytes()));
+    movptr(reg, Address(reg, constantPoolOopDesc::cache_offset_in_bytes()));
   }
 
-  void get_cpool_and_tags(Register cpool, Register tags)
-  {
+  void get_cpool_and_tags(Register cpool, Register tags) {
     get_constant_pool(cpool);
-    movq(tags, Address(cpool, constantPoolOopDesc::tags_offset_in_bytes()));
+    movptr(tags, Address(cpool, constantPoolOopDesc::tags_offset_in_bytes()));
   }
 
   void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset);
@@ -98,6 +99,7 @@
   void get_cache_entry_pointer_at_bcp(Register cache, Register tmp,
                                       int bcp_offset);
 
+
   void pop_ptr(Register r = rax);
   void pop_i(Register r = rax);
   void pop_l(Register r = rax);
@@ -109,15 +111,23 @@
   void push_f(XMMRegister r = xmm0);
   void push_d(XMMRegister r = xmm0);
 
+  void pop(Register r ) { ((MacroAssembler*)this)->pop(r); }
+
+  void push(Register r ) { ((MacroAssembler*)this)->push(r); }
+  void push(int32_t imm ) { ((MacroAssembler*)this)->push(imm); }
+
   void pop(TosState state); // transition vtos -> state
   void push(TosState state); // transition state -> vtos
 
   // Tagged stack support, pop and push both tag and value.
   void pop_ptr(Register r, Register tag);
   void push_ptr(Register r, Register tag);
+#endif // CC_INTERP
 
   DEBUG_ONLY(void verify_stack_tag(frame::Tag t);)
 
+#ifndef CC_INTERP
+
   // Tagged stack helpers for swap and dup
   void load_ptr_and_tag(int n, Register val, Register tag);
   void store_ptr_and_tag(int n, Register val, Register tag);
@@ -133,12 +143,12 @@
   void verify_local_tag(frame::Tag tag, Register idx);
 #endif // ASSERT
 
+
   void empty_expression_stack()
   {
-    movq(rsp, Address(rbp, frame::interpreter_frame_monitor_block_top_offset *
-                      wordSize));
+    movptr(rsp, Address(rbp, frame::interpreter_frame_monitor_block_top_offset * wordSize));
     // NULL last_sp until next java call
-    movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+    movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   }
 
   // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls
@@ -185,11 +195,14 @@
                          bool throw_monitor_exception = true,
                          bool install_monitor_exception = true,
                          bool notify_jvmdi = true);
+#endif // CC_INTERP
 
   // Object locking
   void lock_object  (Register lock_reg);
   void unlock_object(Register lock_reg);
 
+#ifndef CC_INTERP
+
   // Interpreter profiling operations
   void set_method_data_pointer_for_bcp();
   void test_method_data_pointer(Register mdp, Label& zero_continue);
@@ -237,6 +250,8 @@
   // only if +VerifyFPU  && (state == ftos || state == dtos)
   void verify_FPU(int stack_depth, TosState state = ftos);
 
+#endif // !CC_INTERP
+
   typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode;
 
   // support for jvmti/dtrace
--- a/hotspot/src/cpu/x86/vm/interpreterRT_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interpreterRT_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -50,13 +50,13 @@
 
 
 void InterpreterRuntime::SignatureHandlerGenerator::box(int from_offset, int to_offset) {
-  __ leal(temp(), Address(from(), Interpreter::local_offset_in_bytes(from_offset)));
-  __ cmpl(Address(from(), Interpreter::local_offset_in_bytes(from_offset)), 0); // do not use temp() to avoid AGI
+  __ lea(temp(), Address(from(), Interpreter::local_offset_in_bytes(from_offset)));
+  __ cmpptr(Address(from(), Interpreter::local_offset_in_bytes(from_offset)), (int32_t)NULL_WORD); // do not use temp() to avoid AGI
   Label L;
   __ jcc(Assembler::notZero, L);
-  __ movl(temp(), 0);
+  __ movptr(temp(), ((int32_t)NULL_WORD));
   __ bind(L);
-  __ movl(Address(to(), to_offset * wordSize), temp());
+  __ movptr(Address(to(), to_offset * wordSize), temp());
 }
 
 
--- a/hotspot/src/cpu/x86/vm/interpreterRT_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interpreterRT_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -93,49 +93,49 @@
 #ifdef _WIN64
   switch (_num_args) {
   case 0:
-    __ movq(c_rarg1, src);
+    __ movptr(c_rarg1, src);
     _num_args++;
     break;
   case 1:
-    __ movq(c_rarg2, src);
+    __ movptr(c_rarg2, src);
     _num_args++;
     break;
   case 2:
-    __ movq(c_rarg3, src);
+    __ movptr(c_rarg3, src);
     _num_args++;
     break;
   case 3:
   default:
-    __ movq(rax, src);
-    __ movq(Address(to(), _stack_offset), rax);
+    __ movptr(rax, src);
+    __ movptr(Address(to(), _stack_offset), rax);
     _stack_offset += wordSize;
     break;
   }
 #else
   switch (_num_int_args) {
   case 0:
-    __ movq(c_rarg1, src);
+    __ movptr(c_rarg1, src);
     _num_int_args++;
     break;
   case 1:
-    __ movq(c_rarg2, src);
+    __ movptr(c_rarg2, src);
     _num_int_args++;
     break;
   case 2:
-    __ movq(c_rarg3, src);
+    __ movptr(c_rarg3, src);
     _num_int_args++;
     break;
   case 3:
-    __ movq(c_rarg4, src);
+    __ movptr(c_rarg4, src);
     _num_int_args++;
     break;
   case 4:
-    __ movq(c_rarg5, src);
+    __ movptr(c_rarg5, src);
     _num_int_args++;
     break;
   default:
-    __ movq(rax, src);
-    __ movq(Address(to(), _stack_offset), rax);
+    __ movptr(rax, src);
+    __ movptr(Address(to(), _stack_offset), rax);
     _stack_offset += wordSize;
     break;
   }
@@ -171,16 +171,16 @@
   if (_num_args < Argument::n_float_register_parameters_c-1) {
     __ movdbl(as_XMMRegister(++_num_args), src);
   } else {
-    __ movq(rax, src);
-    __ movq(Address(to(), _stack_offset), rax);
+    __ movptr(rax, src);
+    __ movptr(Address(to(), _stack_offset), rax);
     _stack_offset += wordSize;
   }
 #else
   if (_num_fp_args < Argument::n_float_register_parameters_c) {
     __ movdbl(as_XMMRegister(_num_fp_args++), src);
   } else {
-    __ movq(rax, src);
-    __ movq(Address(to(), _stack_offset), rax);
+    __ movptr(rax, src);
+    __ movptr(Address(to(), _stack_offset), rax);
     _stack_offset += wordSize;
   }
 #endif
@@ -193,29 +193,29 @@
   switch (_num_args) {
   case 0:
     assert(offset() == 0, "argument register 1 can only be (non-null) receiver");
-    __ leaq(c_rarg1, src);
+    __ lea(c_rarg1, src);
     _num_args++;
     break;
   case 1:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg2, c_rarg2);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg2, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg2, rax);
     _num_args++;
     break;
   case 2:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg3, c_rarg3);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg3, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg3, rax);
     _num_args++;
     break;
   default:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(temp(), temp());
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, temp(), rax);
-    __ movq(Address(to(), _stack_offset), temp());
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, temp(), rax);
+    __ movptr(Address(to(), _stack_offset), temp());
     _stack_offset += wordSize;
     break;
   }
@@ -223,43 +223,43 @@
   switch (_num_int_args) {
   case 0:
     assert(offset() == 0, "argument register 1 can only be (non-null) receiver");
-    __ leaq(c_rarg1, src);
+    __ lea(c_rarg1, src);
     _num_int_args++;
     break;
   case 1:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg2, c_rarg2);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg2, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg2, rax);
     _num_int_args++;
     break;
   case 2:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg3, c_rarg3);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg3, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg3, rax);
     _num_int_args++;
     break;
   case 3:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg4, c_rarg4);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg4, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg4, rax);
     _num_int_args++;
     break;
   case 4:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(c_rarg5, c_rarg5);
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, c_rarg5, rax);
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, c_rarg5, rax);
     _num_int_args++;
     break;
   default:
-    __ leaq(rax, src);
+    __ lea(rax, src);
     __ xorl(temp(), temp());
-    __ cmpq(src, 0);
-    __ cmovq(Assembler::notEqual, temp(), rax);
-    __ movq(Address(to(), _stack_offset), temp());
+    __ cmpptr(src, 0);
+    __ cmov(Assembler::notEqual, temp(), rax);
+    __ movptr(Address(to(), _stack_offset), temp());
     _stack_offset += wordSize;
     break;
   }
--- a/hotspot/src/cpu/x86/vm/interpreter_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interpreter_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -38,7 +38,7 @@
   // rcx: temporary
   // rdi: pointer to locals
   // rsp: end of copied parameters area
-  __ movl(rcx, rsp);
+  __ mov(rcx, rsp);
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::slow_signature_handler), rbx, rdi, rcx);
   __ ret(0);
   return entry;
@@ -75,8 +75,8 @@
   // Code: _return
   // _return
   // return w/o popping parameters
-  __ popl(rax);
-  __ movl(rsp, rsi);
+  __ pop(rax);
+  __ mov(rsp, rsi);
   __ jmp(rax);
 
   __ bind(slow_path);
@@ -135,7 +135,7 @@
     __ pushl(Address(rsp, 3*wordSize));  // push hi (and note rsp -= wordSize)
     __ pushl(Address(rsp, 2*wordSize));  // push lo
     __ fld_d(Address(rsp, 0));           // get double in ST0
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
   } else {
     __ fld_d(Address(rsp, 1*wordSize));
   }
@@ -173,15 +173,15 @@
 
   // return double result in xmm0 for interpreter and compilers.
   if (UseSSE >= 2) {
-    __ subl(rsp, 2*wordSize);
+    __ subptr(rsp, 2*wordSize);
     __ fstp_d(Address(rsp, 0));
     __ movdbl(xmm0, Address(rsp, 0));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
   }
 
   // done, result in FPU ST(0) or XMM0
-  __ popl(rdi);                              // get return address
-  __ movl(rsp, rsi);                         // set sp to sender sp
+  __ pop(rdi);                               // get return address
+  __ mov(rsp, rsi);                          // set sp to sender sp
   __ jmp(rdi);
 
   return entry_point;
@@ -202,10 +202,10 @@
 
   // abstract method entry
   // remove return address. Not really needed, since exception handling throws away expression stack
-  __ popl(rbx);
+  __ pop(rbx);
 
   // adjust stack to what a normal return would do
-  __ movl(rsp, rsi);
+  __ mov(rsp, rsi);
   // throw exception
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_AbstractMethodError));
   // the call_VM checks for exception, so we should never return here.
--- a/hotspot/src/cpu/x86/vm/interpreter_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/interpreter_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -35,9 +35,9 @@
   // rbx: method
   // r14: pointer to locals
   // c_rarg3: first stack arg - wordSize
-  __ movq(c_rarg3, rsp);
+  __ mov(c_rarg3, rsp);
   // adjust rsp
-  __ subq(rsp, 4 * wordSize);
+  __ subptr(rsp, 4 * wordSize);
   __ call_VM(noreg,
              CAST_FROM_FN_PTR(address,
                               InterpreterRuntime::slow_signature_handler),
@@ -70,13 +70,13 @@
       case 0:
         __ movl(rscratch1, Address(rbx, methodOopDesc::access_flags_offset()));
         __ testl(rscratch1, JVM_ACC_STATIC);
-        __ cmovq(Assembler::zero, c_rarg1, Address(rsp, 0));
+        __ cmovptr(Assembler::zero, c_rarg1, Address(rsp, 0));
         break;
       case 1:
-        __ movq(c_rarg2, Address(rsp, wordSize));
+        __ movptr(c_rarg2, Address(rsp, wordSize));
         break;
       case 2:
-        __ movq(c_rarg3, Address(rsp, 2 * wordSize));
+        __ movptr(c_rarg3, Address(rsp, 2 * wordSize));
         break;
       default:
         break;
@@ -101,7 +101,7 @@
 
 
   // restore rsp
-  __ addq(rsp, 4 * wordSize);
+  __ addptr(rsp, 4 * wordSize);
 
   __ ret(0);
 
@@ -114,9 +114,9 @@
   // rbx: method
   // r14: pointer to locals
   // c_rarg3: first stack arg - wordSize
-  __ movq(c_rarg3, rsp);
+  __ mov(c_rarg3, rsp);
   // adjust rsp
-  __ subq(rsp, 14 * wordSize);
+  __ subptr(rsp, 14 * wordSize);
   __ call_VM(noreg,
              CAST_FROM_FN_PTR(address,
                               InterpreterRuntime::slow_signature_handler),
@@ -155,15 +155,15 @@
   // Now handle integrals.  Only do c_rarg1 if not static.
   __ movl(c_rarg3, Address(rbx, methodOopDesc::access_flags_offset()));
   __ testl(c_rarg3, JVM_ACC_STATIC);
-  __ cmovq(Assembler::zero, c_rarg1, Address(rsp, 0));
+  __ cmovptr(Assembler::zero, c_rarg1, Address(rsp, 0));
 
-  __ movq(c_rarg2, Address(rsp, wordSize));
-  __ movq(c_rarg3, Address(rsp, 2 * wordSize));
-  __ movq(c_rarg4, Address(rsp, 3 * wordSize));
-  __ movq(c_rarg5, Address(rsp, 4 * wordSize));
+  __ movptr(c_rarg2, Address(rsp, wordSize));
+  __ movptr(c_rarg3, Address(rsp, 2 * wordSize));
+  __ movptr(c_rarg4, Address(rsp, 3 * wordSize));
+  __ movptr(c_rarg5, Address(rsp, 4 * wordSize));
 
   // restore rsp
-  __ addq(rsp, 14 * wordSize);
+  __ addptr(rsp, 14 * wordSize);
 
   __ ret(0);
 
@@ -176,15 +176,14 @@
 // Various method entries
 //
 
-address InterpreterGenerator::generate_math_entry(
-  AbstractInterpreter::MethodKind kind) {
-  // rbx: methodOop
+address InterpreterGenerator::generate_math_entry(AbstractInterpreter::MethodKind kind) {
+
+  // rbx,: methodOop
+  // rcx: scratrch
+  // r13: sender sp
 
   if (!InlineIntrinsics) return NULL; // Generate a vanilla entry
 
-  assert(kind == Interpreter::java_lang_math_sqrt,
-         "Other intrinsics are not special");
-
   address entry_point = __ pc();
 
   // These don't need a safepoint check because they aren't virtually
@@ -197,6 +196,11 @@
   // in order to avoid monotonicity bugs when switching
   // from interpreter to compiler in the middle of some
   // computation)
+  //
+  // stack: [ ret adr ] <-- rsp
+  //        [ lo(arg) ]
+  //        [ hi(arg) ]
+  //
 
   // Note: For JDK 1.2 StrictMath doesn't exist and Math.sin/cos/sqrt are
   //       native methods. Interpreter::method_kind(...) does a check for
@@ -218,10 +222,46 @@
   // Note: For JDK 1.3 StrictMath exists and Math.sin/cos/sqrt are
   //       java methods.  Interpreter::method_kind(...) will select
   //       this entry point for the corresponding methods in JDK 1.3.
-  __ sqrtsd(xmm0, Address(rsp, wordSize));
+  // get argument
 
-  __ popq(rax);
-  __ movq(rsp, r13);
+  if (kind == Interpreter::java_lang_math_sqrt) {
+    __ sqrtsd(xmm0, Address(rsp, wordSize));
+  } else {
+    __ fld_d(Address(rsp, wordSize));
+    switch (kind) {
+      case Interpreter::java_lang_math_sin :
+          __ trigfunc('s');
+          break;
+      case Interpreter::java_lang_math_cos :
+          __ trigfunc('c');
+          break;
+      case Interpreter::java_lang_math_tan :
+          __ trigfunc('t');
+          break;
+      case Interpreter::java_lang_math_abs:
+          __ fabs();
+          break;
+      case Interpreter::java_lang_math_log:
+          __ flog();
+          break;
+      case Interpreter::java_lang_math_log10:
+          __ flog10();
+          break;
+      default                              :
+          ShouldNotReachHere();
+    }
+
+    // return double result in xmm0 for interpreter and compilers.
+    __ subptr(rsp, 2*wordSize);
+    // Round to 64bit precision
+    __ fstp_d(Address(rsp, 0));
+    __ movdbl(xmm0, Address(rsp, 0));
+    __ addptr(rsp, 2*wordSize);
+  }
+
+
+  __ pop(rax);
+  __ mov(rsp, r13);
   __ jmp(rax);
 
   return entry_point;
@@ -239,10 +279,10 @@
   // abstract method entry
   // remove return address. Not really needed, since exception
   // handling throws away expression stack
-  __ popq(rbx);
+  __ pop(rbx);
 
   // adjust stack to what a normal return would do
-  __ movq(rsp, r13);
+  __ mov(rsp, r13);
 
   // throw exception
   __ call_VM(noreg, CAST_FROM_FN_PTR(address,
@@ -276,8 +316,8 @@
   // Code: _return
   // _return
   // return w/o popping parameters
-  __ popq(rax);
-  __ movq(rsp, r13);
+  __ pop(rax);
+  __ mov(rsp, r13);
   __ jmp(rax);
 
   __ bind(slow_path);
@@ -286,148 +326,6 @@
 
 }
 
-// Call an accessor method (assuming it is resolved, otherwise drop
-// into vanilla (slow path) entry
-address InterpreterGenerator::generate_accessor_entry(void) {
-  // rbx: methodOop
-
-  // r13: senderSP must preserver for slow path, set SP to it on fast path
-
-  address entry_point = __ pc();
-  Label xreturn_path;
-
-  // do fastpath for resolved accessor methods
-  if (UseFastAccessorMethods) {
-    // Code: _aload_0, _(i|a)getfield, _(i|a)return or any rewrites
-    //       thereof; parameter size = 1
-    // Note: We can only use this code if the getfield has been resolved
-    //       and if we don't have a null-pointer exception => check for
-    //       these conditions first and use slow path if necessary.
-    Label slow_path;
-    // If we need a safepoint check, generate full interpreter entry.
-    __ cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
-             SafepointSynchronize::_not_synchronized);
-
-    __ jcc(Assembler::notEqual, slow_path);
-    // rbx: method
-    __ movq(rax, Address(rsp, wordSize));
-
-    // check if local 0 != NULL and read field
-    __ testq(rax, rax);
-    __ jcc(Assembler::zero, slow_path);
-
-    __ movq(rdi, Address(rbx, methodOopDesc::constants_offset()));
-    // read first instruction word and extract bytecode @ 1 and index @ 2
-    __ movq(rdx, Address(rbx, methodOopDesc::const_offset()));
-    __ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
-    // Shift codes right to get the index on the right.
-    // The bytecode fetched looks like <index><0xb4><0x2a>
-    __ shrl(rdx, 2 * BitsPerByte);
-    __ shll(rdx, exact_log2(in_words(ConstantPoolCacheEntry::size())));
-    __ movq(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
-
-    // rax: local 0
-    // rbx: method
-    // rdx: constant pool cache index
-    // rdi: constant pool cache
-
-    // check if getfield has been resolved and read constant pool cache entry
-    // check the validity of the cache entry by testing whether _indices field
-    // contains Bytecode::_getfield in b1 byte.
-    assert(in_words(ConstantPoolCacheEntry::size()) == 4,
-           "adjust shift below");
-    __ movl(rcx,
-            Address(rdi,
-                    rdx,
-                    Address::times_8,
-                    constantPoolCacheOopDesc::base_offset() +
-                    ConstantPoolCacheEntry::indices_offset()));
-    __ shrl(rcx, 2 * BitsPerByte);
-    __ andl(rcx, 0xFF);
-    __ cmpl(rcx, Bytecodes::_getfield);
-    __ jcc(Assembler::notEqual, slow_path);
-
-    // Note: constant pool entry is not valid before bytecode is resolved
-    __ movq(rcx,
-            Address(rdi,
-                    rdx,
-                    Address::times_8,
-                    constantPoolCacheOopDesc::base_offset() +
-                    ConstantPoolCacheEntry::f2_offset()));
-    // edx: flags
-    __ movl(rdx,
-            Address(rdi,
-                    rdx,
-                    Address::times_8,
-                    constantPoolCacheOopDesc::base_offset() +
-                    ConstantPoolCacheEntry::flags_offset()));
-
-    Label notObj, notInt, notByte, notShort;
-    const Address field_address(rax, rcx, Address::times_1);
-
-    // Need to differentiate between igetfield, agetfield, bgetfield etc.
-    // because they are different sizes.
-    // Use the type from the constant pool cache
-    __ shrl(rdx, ConstantPoolCacheEntry::tosBits);
-    // Make sure we don't need to mask edx for tosBits after the above shift
-    ConstantPoolCacheEntry::verify_tosBits();
-
-    __ cmpl(rdx, atos);
-    __ jcc(Assembler::notEqual, notObj);
-    // atos
-    __ load_heap_oop(rax, field_address);
-    __ jmp(xreturn_path);
-
-    __ bind(notObj);
-    __ cmpl(rdx, itos);
-    __ jcc(Assembler::notEqual, notInt);
-    // itos
-    __ movl(rax, field_address);
-    __ jmp(xreturn_path);
-
-    __ bind(notInt);
-    __ cmpl(rdx, btos);
-    __ jcc(Assembler::notEqual, notByte);
-    // btos
-    __ load_signed_byte(rax, field_address);
-    __ jmp(xreturn_path);
-
-    __ bind(notByte);
-    __ cmpl(rdx, stos);
-    __ jcc(Assembler::notEqual, notShort);
-    // stos
-    __ load_signed_word(rax, field_address);
-    __ jmp(xreturn_path);
-
-    __ bind(notShort);
-#ifdef ASSERT
-    Label okay;
-    __ cmpl(rdx, ctos);
-    __ jcc(Assembler::equal, okay);
-    __ stop("what type is this?");
-    __ bind(okay);
-#endif
-    // ctos
-    __ load_unsigned_word(rax, field_address);
-
-    __ bind(xreturn_path);
-
-    // _ireturn/_areturn
-    __ popq(rdi);
-    __ movq(rsp, r13);
-    __ jmp(rdi);
-    __ ret(0);
-
-    // generate a vanilla interpreter entry as the slow path
-    __ bind(slow_path);
-    (void) generate_normal_entry(false);
-  } else {
-    (void) generate_normal_entry(false);
-  }
-
-  return entry_point;
-}
-
 // This method tells the deoptimizer how big an interpreted frame must be:
 int AbstractInterpreter::size_activation(methodOop method,
                                          int tempcount,
--- a/hotspot/src/cpu/x86/vm/jniFastGetField_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/jniFastGetField_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -72,25 +72,25 @@
   __ testb (rcx, 1);
   __ jcc (Assembler::notZero, slow);
   if (os::is_MP()) {
-    __ movl (rax, rcx);
-    __ andl (rax, 1);                         // rax, must end up 0
-    __ movl (rdx, Address(rsp, rax, Address::times_1, 2*wordSize));
+    __ mov(rax, rcx);
+    __ andptr(rax, 1);                         // rax, must end up 0
+    __ movptr(rdx, Address(rsp, rax, Address::times_1, 2*wordSize));
                                               // obj, notice rax, is 0.
                                               // rdx is data dependent on rcx.
   } else {
-    __ movl (rdx, Address(rsp, 2*wordSize));  // obj
+    __ movptr (rdx, Address(rsp, 2*wordSize));  // obj
   }
-  __ movl (rax, Address(rsp, 3*wordSize));  // jfieldID
-  __ movl (rdx, Address(rdx, 0));           // *obj
-  __ shrl (rax, 2);                         // offset
+  __ movptr(rax, Address(rsp, 3*wordSize));  // jfieldID
+  __ movptr(rdx, Address(rdx, 0));           // *obj
+  __ shrptr (rax, 2);                         // offset
 
   assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
   speculative_load_pclist[count] = __ pc();
   switch (type) {
-    case T_BOOLEAN: __ movzxb (rax, Address(rdx, rax, Address::times_1)); break;
-    case T_BYTE:    __ movsxb (rax, Address(rdx, rax, Address::times_1)); break;
-    case T_CHAR:    __ movzxw (rax, Address(rdx, rax, Address::times_1)); break;
-    case T_SHORT:   __ movsxw (rax, Address(rdx, rax, Address::times_1)); break;
+    case T_BOOLEAN: __ movzbl (rax, Address(rdx, rax, Address::times_1)); break;
+    case T_BYTE:    __ movsbl (rax, Address(rdx, rax, Address::times_1)); break;
+    case T_CHAR:    __ movzwl (rax, Address(rdx, rax, Address::times_1)); break;
+    case T_SHORT:   __ movswl (rax, Address(rdx, rax, Address::times_1)); break;
     case T_INT:     __ movl   (rax, Address(rdx, rax, Address::times_1)); break;
     default:        ShouldNotReachHere();
   }
@@ -98,8 +98,8 @@
   Address ca1;
   if (os::is_MP()) {
     __ lea(rdx, counter);
-    __ xorl(rdx, rax);
-    __ xorl(rdx, rax);
+    __ xorptr(rdx, rax);
+    __ xorptr(rdx, rax);
     __ cmp32(rcx, Address(rdx, 0));
     // ca1 is the same as ca because
     // rax, ^ counter_addr ^ rax, = address
@@ -184,35 +184,37 @@
 
   ExternalAddress counter(SafepointSynchronize::safepoint_counter_addr());
 
-  __ pushl (rsi);
+  __ push  (rsi);
   __ mov32 (rcx, counter);
   __ testb (rcx, 1);
   __ jcc (Assembler::notZero, slow);
   if (os::is_MP()) {
-    __ movl (rax, rcx);
-    __ andl (rax, 1);                         // rax, must end up 0
-    __ movl (rdx, Address(rsp, rax, Address::times_1, 3*wordSize));
+    __ mov(rax, rcx);
+    __ andptr(rax, 1);                         // rax, must end up 0
+    __ movptr(rdx, Address(rsp, rax, Address::times_1, 3*wordSize));
                                               // obj, notice rax, is 0.
                                               // rdx is data dependent on rcx.
   } else {
-    __ movl (rdx, Address(rsp, 3*wordSize));  // obj
+    __ movptr(rdx, Address(rsp, 3*wordSize));  // obj
   }
-  __ movl (rsi, Address(rsp, 4*wordSize));  // jfieldID
-  __ movl (rdx, Address(rdx, 0));           // *obj
-  __ shrl (rsi, 2);                         // offset
+  __ movptr(rsi, Address(rsp, 4*wordSize));  // jfieldID
+  __ movptr(rdx, Address(rdx, 0));           // *obj
+  __ shrptr(rsi, 2);                         // offset
 
   assert(count < LIST_CAPACITY-1, "LIST_CAPACITY too small");
   speculative_load_pclist[count++] = __ pc();
-  __ movl (rax, Address(rdx, rsi, Address::times_1));
+  __ movptr(rax, Address(rdx, rsi, Address::times_1));
+#ifndef _LP64
   speculative_load_pclist[count] = __ pc();
-  __ movl (rdx, Address(rdx, rsi, Address::times_1, 4));
+  __ movl(rdx, Address(rdx, rsi, Address::times_1, 4));
+#endif // _LP64
 
   if (os::is_MP()) {
-    __ lea  (rsi, counter);
-    __ xorl (rsi, rdx);
-    __ xorl (rsi, rax);
-    __ xorl (rsi, rdx);
-    __ xorl (rsi, rax);
+    __ lea(rsi, counter);
+    __ xorptr(rsi, rdx);
+    __ xorptr(rsi, rax);
+    __ xorptr(rsi, rdx);
+    __ xorptr(rsi, rax);
     __ cmp32(rcx, Address(rsi, 0));
     // ca1 is the same as ca because
     // rax, ^ rdx ^ counter_addr ^ rax, ^ rdx = address
@@ -222,7 +224,7 @@
   }
   __ jcc (Assembler::notEqual, slow);
 
-  __ popl (rsi);
+  __ pop (rsi);
 
 #ifndef _WINDOWS
   __ ret (0);
@@ -234,7 +236,7 @@
   slowcase_entry_pclist[count-1] = __ pc();
   slowcase_entry_pclist[count++] = __ pc();
   __ bind (slow);
-  __ popl (rsi);
+  __ pop  (rsi);
   address slow_case_addr = jni_GetLongField_addr();;
   // tail call
   __ jump (ExternalAddress(slow_case_addr));
@@ -276,23 +278,28 @@
   __ testb (rcx, 1);
   __ jcc (Assembler::notZero, slow);
   if (os::is_MP()) {
-    __ movl (rax, rcx);
-    __ andl (rax, 1);                         // rax, must end up 0
-    __ movl (rdx, Address(rsp, rax, Address::times_1, 2*wordSize));
+    __ mov(rax, rcx);
+    __ andptr(rax, 1);                         // rax, must end up 0
+    __ movptr(rdx, Address(rsp, rax, Address::times_1, 2*wordSize));
                                               // obj, notice rax, is 0.
                                               // rdx is data dependent on rcx.
   } else {
-    __ movl (rdx, Address(rsp, 2*wordSize)); // obj
+    __ movptr(rdx, Address(rsp, 2*wordSize)); // obj
   }
-  __ movl (rax, Address(rsp, 3*wordSize));  // jfieldID
-  __ movl (rdx, Address(rdx, 0));           // *obj
-  __ shrl (rax, 2);                         // offset
+  __ movptr(rax, Address(rsp, 3*wordSize));  // jfieldID
+  __ movptr(rdx, Address(rdx, 0));           // *obj
+  __ shrptr(rax, 2);                         // offset
 
   assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
   speculative_load_pclist[count] = __ pc();
   switch (type) {
+#ifndef _LP64
     case T_FLOAT:  __ fld_s (Address(rdx, rax, Address::times_1)); break;
     case T_DOUBLE: __ fld_d (Address(rdx, rax, Address::times_1)); break;
+#else
+    case T_FLOAT:  __ movflt (xmm0, Address(robj, roffset, Address::times_1)); break;
+    case T_DOUBLE: __ movdbl (xmm0, Address(robj, roffset, Address::times_1)); break;
+#endif // _LP64
     default:       ShouldNotReachHere();
   }
 
@@ -301,8 +308,9 @@
     __ fst_s (Address(rsp, -4));
     __ lea(rdx, counter);
     __ movl (rax, Address(rsp, -4));
-    __ xorl(rdx, rax);
-    __ xorl(rdx, rax);
+    // garbage hi-order bits on 64bit are harmless.
+    __ xorptr(rdx, rax);
+    __ xorptr(rdx, rax);
     __ cmp32(rcx, Address(rdx, 0));
                                           // rax, ^ counter_addr ^ rax, = address
                                           // ca1 is data dependent on the field
--- a/hotspot/src/cpu/x86/vm/jniFastGetField_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/jniFastGetField_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -67,18 +67,18 @@
 
   ExternalAddress counter(SafepointSynchronize::safepoint_counter_addr());
   __ mov32 (rcounter, counter);
-  __ movq (robj, c_rarg1);
+  __ mov   (robj, c_rarg1);
   __ testb (rcounter, 1);
   __ jcc (Assembler::notZero, slow);
   if (os::is_MP()) {
-    __ xorq (robj, rcounter);
-    __ xorq (robj, rcounter);                   // obj, since
+    __ xorptr(robj, rcounter);
+    __ xorptr(robj, rcounter);                   // obj, since
                                                 // robj ^ rcounter ^ rcounter == robj
                                                 // robj is data dependent on rcounter.
   }
-  __ movq (robj, Address(robj, 0));             // *obj
-  __ movq (roffset, c_rarg2);
-  __ shrq (roffset, 2);                         // offset
+  __ movptr(robj, Address(robj, 0));             // *obj
+  __ mov   (roffset, c_rarg2);
+  __ shrptr(roffset, 2);                         // offset
 
   assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
   speculative_load_pclist[count] = __ pc();
@@ -95,8 +95,8 @@
   if (os::is_MP()) {
     __ lea(rcounter_addr, counter);
     // ca is data dependent on rax.
-    __ xorq (rcounter_addr, rax);
-    __ xorq (rcounter_addr, rax);
+    __ xorptr(rcounter_addr, rax);
+    __ xorptr(rcounter_addr, rax);
     __ cmpl (rcounter, Address(rcounter_addr, 0));
   } else {
     __ cmp32 (rcounter, counter);
@@ -165,18 +165,18 @@
 
   ExternalAddress counter(SafepointSynchronize::safepoint_counter_addr());
   __ mov32 (rcounter, counter);
-  __ movq (robj, c_rarg1);
+  __ mov   (robj, c_rarg1);
   __ testb (rcounter, 1);
   __ jcc (Assembler::notZero, slow);
   if (os::is_MP()) {
-    __ xorq (robj, rcounter);
-    __ xorq (robj, rcounter);                   // obj, since
+    __ xorptr(robj, rcounter);
+    __ xorptr(robj, rcounter);                   // obj, since
                                                 // robj ^ rcounter ^ rcounter == robj
                                                 // robj is data dependent on rcounter.
   }
-  __ movq (robj, Address(robj, 0));             // *obj
-  __ movq (roffset, c_rarg2);
-  __ shrq (roffset, 2);                         // offset
+  __ movptr(robj, Address(robj, 0));             // *obj
+  __ mov   (roffset, c_rarg2);
+  __ shrptr(roffset, 2);                         // offset
 
   assert(count < LIST_CAPACITY, "LIST_CAPACITY too small");
   speculative_load_pclist[count] = __ pc();
@@ -190,8 +190,8 @@
     __ lea(rcounter_addr, counter);
     __ movdq (rax, xmm0);
     // counter address is data dependent on xmm0.
-    __ xorq (rcounter_addr, rax);
-    __ xorq (rcounter_addr, rax);
+    __ xorptr(rcounter_addr, rax);
+    __ xorptr(rcounter_addr, rax);
     __ cmpl (rcounter, Address(rcounter_addr, 0));
   } else {
     __ cmp32 (rcounter, counter);
--- a/hotspot/src/cpu/x86/vm/nativeInst_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/nativeInst_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -223,49 +223,150 @@
 
 //-------------------------------------------------------------------
 
-#ifndef AMD64
+int NativeMovRegMem::instruction_start() const {
+  int off = 0;
+  u_char instr_0 = ubyte_at(off);
+
+  // First check to see if we have a (prefixed or not) xor
+  if ( instr_0 >= instruction_prefix_wide_lo &&      // 0x40
+       instr_0 <= instruction_prefix_wide_hi) { // 0x4f
+    off++;
+    instr_0 = ubyte_at(off);
+  }
+
+  if (instr_0 == instruction_code_xor) {
+    off += 2;
+    instr_0 = ubyte_at(off);
+  }
+
+  // Now look for the real instruction and the many prefix/size specifiers.
+
+  if (instr_0 == instruction_operandsize_prefix ) {  // 0x66
+    off++; // Not SSE instructions
+    instr_0 = ubyte_at(off);
+  }
 
-void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
-  int inst_size = instruction_size;
+  if ( instr_0 == instruction_code_xmm_ss_prefix ||      // 0xf3
+       instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
+    off++;
+    instr_0 = ubyte_at(off);
+  }
+
+  if ( instr_0 >= instruction_prefix_wide_lo &&      // 0x40
+       instr_0 <= instruction_prefix_wide_hi) { // 0x4f
+    off++;
+    instr_0 = ubyte_at(off);
+  }
+
+
+  if (instr_0 == instruction_extended_prefix ) {  // 0x0f
+    off++;
+  }
+
+  return off;
+}
+
+address NativeMovRegMem::instruction_address() const {
+  return addr_at(instruction_start());
+}
+
+address NativeMovRegMem::next_instruction_address() const {
+  address ret = instruction_address() + instruction_size;
+  u_char instr_0 =  *(u_char*) instruction_address();
+  switch (instr_0) {
+  case instruction_operandsize_prefix:
+
+    fatal("should have skipped instruction_operandsize_prefix");
+    break;
 
-  // See if there's an instruction size prefix override.
-  if ( *(address(this))   == instruction_operandsize_prefix &&
-       *(address(this)+1) != instruction_code_xmm_code ) { // Not SSE instr
-    inst_size += 1;
+  case instruction_extended_prefix:
+    fatal("should have skipped instruction_extended_prefix");
+    break;
+
+  case instruction_code_mem2reg_movslq: // 0x63
+  case instruction_code_mem2reg_movzxb: // 0xB6
+  case instruction_code_mem2reg_movsxb: // 0xBE
+  case instruction_code_mem2reg_movzxw: // 0xB7
+  case instruction_code_mem2reg_movsxw: // 0xBF
+  case instruction_code_reg2mem:        // 0x89 (q/l)
+  case instruction_code_mem2reg:        // 0x8B (q/l)
+  case instruction_code_reg2memb:       // 0x88
+  case instruction_code_mem2regb:       // 0x8a
+
+  case instruction_code_float_s:        // 0xd9 fld_s a
+  case instruction_code_float_d:        // 0xdd fld_d a
+
+  case instruction_code_xmm_load:       // 0x10
+  case instruction_code_xmm_store:      // 0x11
+  case instruction_code_xmm_lpd:        // 0x12
+    {
+      // If there is an SIB then instruction is longer than expected
+      u_char mod_rm = *(u_char*)(instruction_address() + 1);
+      if ((mod_rm & 7) == 0x4) {
+        ret++;
+      }
+    }
+  case instruction_code_xor:
+    fatal("should have skipped xor lead in");
+    break;
+
+  default:
+    fatal("not a NativeMovRegMem");
   }
-  if ( *(address(this)) == instruction_extended_prefix ) inst_size += 1;
+  return ret;
+
+}
 
-  for (int i = 0; i < instruction_size; i++) {
-    *(new_instruction_address + i) = *(address(this) + i);
+int NativeMovRegMem::offset() const{
+  int off = data_offset + instruction_start();
+  u_char mod_rm = *(u_char*)(instruction_address() + 1);
+  // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
+  // the encoding to use an SIB byte. Which will have the nnnn
+  // field off by one byte
+  if ((mod_rm & 7) == 0x4) {
+    off++;
   }
+  return int_at(off);
+}
+
+void NativeMovRegMem::set_offset(int x) {
+  int off = data_offset + instruction_start();
+  u_char mod_rm = *(u_char*)(instruction_address() + 1);
+  // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
+  // the encoding to use an SIB byte. Which will have the nnnn
+  // field off by one byte
+  if ((mod_rm & 7) == 0x4) {
+    off++;
+  }
+  set_int_at(off, x);
 }
 
 void NativeMovRegMem::verify() {
   // make sure code pattern is actually a mov [reg+offset], reg instruction
   u_char test_byte = *(u_char*)instruction_address();
-  if ( ! ( (test_byte == instruction_code_reg2memb)
-      || (test_byte == instruction_code_mem2regb)
-      || (test_byte == instruction_code_mem2regl)
-      || (test_byte == instruction_code_reg2meml)
-      || (test_byte == instruction_code_mem2reg_movzxb )
-      || (test_byte == instruction_code_mem2reg_movzxw )
-      || (test_byte == instruction_code_mem2reg_movsxb )
-      || (test_byte == instruction_code_mem2reg_movsxw )
-      || (test_byte == instruction_code_float_s)
-      || (test_byte == instruction_code_float_d)
-      || (test_byte == instruction_code_long_volatile) ) )
-  {
-    u_char byte1 = ((u_char*)instruction_address())[1];
-    u_char byte2 = ((u_char*)instruction_address())[2];
-    if ((test_byte != instruction_code_xmm_ss_prefix &&
-         test_byte != instruction_code_xmm_sd_prefix &&
-         test_byte != instruction_operandsize_prefix) ||
-        byte1 != instruction_code_xmm_code ||
-        (byte2 != instruction_code_xmm_load &&
-         byte2 != instruction_code_xmm_lpd  &&
-         byte2 != instruction_code_xmm_store)) {
+  switch (test_byte) {
+    case instruction_code_reg2memb:  // 0x88 movb a, r
+    case instruction_code_reg2mem:   // 0x89 movl a, r (can be movq in 64bit)
+    case instruction_code_mem2regb:  // 0x8a movb r, a
+    case instruction_code_mem2reg:   // 0x8b movl r, a (can be movq in 64bit)
+      break;
+
+    case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
+    case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
+    case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
+    case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
+    case instruction_code_mem2reg_movsxw: // 0xbf  movswl r, a (movsxw)
+      break;
+
+    case instruction_code_float_s:   // 0xd9 fld_s a
+    case instruction_code_float_d:   // 0xdd fld_d a
+    case instruction_code_xmm_load:  // 0x10 movsd xmm, a
+    case instruction_code_xmm_store: // 0x11 movsd a, xmm
+    case instruction_code_xmm_lpd:   // 0x12 movlpd xmm, a
+      break;
+
+    default:
           fatal ("not a mov [reg+offs], reg instruction");
-    }
   }
 }
 
@@ -279,7 +380,14 @@
 void NativeLoadAddress::verify() {
   // make sure code pattern is actually a mov [reg+offset], reg instruction
   u_char test_byte = *(u_char*)instruction_address();
-  if ( ! (test_byte == instruction_code) ) {
+#ifdef _LP64
+  if ( (test_byte == instruction_prefix_wide ||
+        test_byte == instruction_prefix_wide_extended) ) {
+    test_byte = *(u_char*)(instruction_address() + 1);
+  }
+#endif // _LP64
+  if ( ! ((test_byte == lea_instruction_code)
+          LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) {
     fatal ("not a lea reg, [reg+offs] instruction");
   }
 }
@@ -289,8 +397,6 @@
   tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
 }
 
-#endif // !AMD64
-
 //--------------------------------------------------------------------------------
 
 void NativeJump::verify() {
--- a/hotspot/src/cpu/x86/vm/nativeInst_x86.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/nativeInst_x86.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -235,16 +235,15 @@
   }
 };
 
-#ifndef AMD64
-
 // An interface for accessing/manipulating native moves of the form:
-//      mov[b/w/l] [reg + offset], reg   (instruction_code_reg2mem)
-//      mov[b/w/l] reg, [reg+offset]     (instruction_code_mem2reg
-//      mov[s/z]x[w/b] [reg + offset], reg
+//      mov[b/w/l/q] [reg + offset], reg   (instruction_code_reg2mem)
+//      mov[b/w/l/q] reg, [reg+offset]     (instruction_code_mem2reg
+//      mov[s/z]x[w/b/q] [reg + offset], reg
 //      fld_s  [reg+offset]
 //      fld_d  [reg+offset]
 //      fstp_s [reg + offset]
 //      fstp_d [reg + offset]
+//      mov_literal64  scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
 //
 // Warning: These routines must be able to handle any instruction sequences
 // that are generated as a result of the load/store byte,word,long
@@ -255,15 +254,18 @@
 class NativeMovRegMem: public NativeInstruction {
  public:
   enum Intel_specific_constants {
+    instruction_prefix_wide_lo          = Assembler::REX,
+    instruction_prefix_wide_hi          = Assembler::REX_WRXB,
     instruction_code_xor                = 0x33,
     instruction_extended_prefix         = 0x0F,
+    instruction_code_mem2reg_movslq     = 0x63,
     instruction_code_mem2reg_movzxb     = 0xB6,
     instruction_code_mem2reg_movsxb     = 0xBE,
     instruction_code_mem2reg_movzxw     = 0xB7,
     instruction_code_mem2reg_movsxw     = 0xBF,
     instruction_operandsize_prefix      = 0x66,
-    instruction_code_reg2meml           = 0x89,
-    instruction_code_mem2regl           = 0x8b,
+    instruction_code_reg2mem            = 0x89,
+    instruction_code_mem2reg            = 0x8b,
     instruction_code_reg2memb           = 0x88,
     instruction_code_mem2regb           = 0x8a,
     instruction_code_float_s            = 0xd9,
@@ -282,73 +284,18 @@
     next_instruction_offset             = 4
   };
 
-  address instruction_address() const {
-    if (*addr_at(instruction_offset)   == instruction_operandsize_prefix &&
-        *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
-      return addr_at(instruction_offset+1); // Not SSE instructions
-    }
-    else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
-      return addr_at(instruction_offset+1);
-    }
-    else if (*addr_at(instruction_offset) == instruction_code_xor) {
-      return addr_at(instruction_offset+2);
-    }
-    else return addr_at(instruction_offset);
-  }
+  // helper
+  int instruction_start() const;
+
+  address instruction_address() const;
 
-  address next_instruction_address() const {
-    switch (*addr_at(instruction_offset)) {
-    case instruction_operandsize_prefix:
-      if (*addr_at(instruction_offset+1) == instruction_code_xmm_code)
-        return instruction_address() + instruction_size; // SSE instructions
-    case instruction_extended_prefix:
-      return instruction_address() + instruction_size + 1;
-    case instruction_code_reg2meml:
-    case instruction_code_mem2regl:
-    case instruction_code_reg2memb:
-    case instruction_code_mem2regb:
-    case instruction_code_xor:
-      return instruction_address() + instruction_size + 2;
-    default:
-      return instruction_address() + instruction_size;
-    }
-  }
-  int   offset() const{
-    if (*addr_at(instruction_offset)   == instruction_operandsize_prefix &&
-        *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
-      return int_at(data_offset+1); // Not SSE instructions
-    }
-    else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
-      return int_at(data_offset+1);
-    }
-    else if (*addr_at(instruction_offset) == instruction_code_xor ||
-             *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
-             *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
-             *addr_at(instruction_offset) == instruction_operandsize_prefix) {
-      return int_at(data_offset+2);
-    }
-    else return int_at(data_offset);
-  }
+  address next_instruction_address() const;
 
-  void  set_offset(int x) {
-    if (*addr_at(instruction_offset)   == instruction_operandsize_prefix &&
-        *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
-      set_int_at(data_offset+1, x); // Not SSE instructions
-    }
-    else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
-      set_int_at(data_offset+1, x);
-    }
-    else if (*addr_at(instruction_offset) == instruction_code_xor ||
-             *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
-             *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
-             *addr_at(instruction_offset) == instruction_operandsize_prefix) {
-      set_int_at(data_offset+2, x);
-    }
-    else set_int_at(data_offset, x);
-  }
+  int   offset() const;
+
+  void  set_offset(int x);
 
   void  add_offset_in_bytes(int add_offset)     { set_offset ( ( offset() + add_offset ) ); }
-  void  copy_instruction_to(address new_instruction_address);
 
   void verify();
   void print ();
@@ -385,9 +332,19 @@
 //        leal reg, [reg + offset]
 
 class NativeLoadAddress: public NativeMovRegMem {
+#ifdef AMD64
+  static const bool has_rex = true;
+  static const int rex_size = 1;
+#else
+  static const bool has_rex = false;
+  static const int rex_size = 0;
+#endif // AMD64
  public:
   enum Intel_specific_constants {
-    instruction_code            = 0x8D
+    instruction_prefix_wide             = Assembler::REX_W,
+    instruction_prefix_wide_extended    = Assembler::REX_WB,
+    lea_instruction_code                = 0x8D,
+    mov64_instruction_code              = 0xB8
   };
 
   void verify();
@@ -406,8 +363,6 @@
   }
 };
 
-#endif // AMD64
-
 // jump rel32off
 
 class NativeJump: public NativeInstruction {
@@ -424,22 +379,23 @@
   address next_instruction_address() const  { return addr_at(next_instruction_offset); }
   address jump_destination() const          {
      address dest = (int_at(data_offset)+next_instruction_address());
-#ifdef AMD64 // What is this about?
+     // 32bit used to encode unresolved jmp as jmp -1
+     // 64bit can't produce this so it used jump to self.
+     // Now 32bit and 64bit use jump to self as the unresolved address
+     // which the inline cache code (and relocs) know about
+
      // return -1 if jump to self
     dest = (dest == (address) this) ? (address) -1 : dest;
-#endif // AMD64
     return dest;
   }
 
   void  set_jump_destination(address dest)  {
     intptr_t val = dest - next_instruction_address();
-#ifdef AMD64
-    if (dest == (address) -1) { // can't encode jump to -1
+    if (dest == (address) -1) {
       val = -5; // jump to self
-    } else {
-      assert((labs(val)  & 0xFFFFFFFF00000000) == 0,
-             "must be 32bit offset");
     }
+#ifdef AMD64
+    assert((labs(val)  & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
 #endif // AMD64
     set_int_at(data_offset, (jint)val);
   }
@@ -568,11 +524,15 @@
                                                           (ubyte_at(0) & 0xF0) == 0x70;  /* short jump */ }
 inline bool NativeInstruction::is_safepoint_poll() {
 #ifdef AMD64
-  return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
-         ubyte_at(1) == 0x05 && // 00 rax 101
-         ((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page();
+  if ( ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
+       ubyte_at(1) == 0x05 ) { // 00 rax 101
+     address fault = addr_at(6) + int_at(2);
+     return os::is_poll_address(fault);
+  } else {
+    return false;
+  }
 #else
-  return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl ||
+  return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
            ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
            (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
            (os::is_poll_address((address)int_at(2)));
--- a/hotspot/src/cpu/x86/vm/relocInfo_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/relocInfo_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -30,11 +30,11 @@
 #ifdef AMD64
   x += o;
   typedef Assembler::WhichOperand WhichOperand;
-  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm64, call32, narrow oop
+  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm, call32, narrow oop
   assert(which == Assembler::disp32_operand ||
          which == Assembler::narrow_oop_operand ||
-         which == Assembler::imm64_operand, "format unpacks ok");
-  if (which == Assembler::imm64_operand) {
+         which == Assembler::imm_operand, "format unpacks ok");
+  if (which == Assembler::imm_operand) {
     *pd_address_in_code() = x;
   } else if (which == Assembler::narrow_oop_operand) {
     address disp = Assembler::locate_operand(addr(), which);
@@ -81,11 +81,16 @@
     nativeCall_at(addr())->set_destination(x);
   } else if (ni->is_jump()) {
     NativeJump* nj = nativeJump_at(addr());
-#ifdef AMD64
+
+    // Unresolved jumps are recognized by a destination of -1
+    // However 64bit can't actually produce such an address
+    // and encodes a jump to self but jump_destination will
+    // return a -1 as the signal. We must not relocate this
+    // jmp or the ic code will not see it as unresolved.
+
     if (nj->jump_destination() == (address) -1) {
-      x = (address) -1; // retain jump to self
+      x = addr(); // jump to self
     }
-#endif // AMD64
     nj->set_jump_destination(x);
   } else if (ni->is_cond_jump()) {
     // %%%% kludge this, for now, until we get a jump_destination method
@@ -106,19 +111,19 @@
   // we must parse the instruction a bit to find the embedded word.
   assert(is_data(), "must be a DataRelocation");
   typedef Assembler::WhichOperand WhichOperand;
-  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm64/imm32
+  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm/imm32
 #ifdef AMD64
   assert(which == Assembler::disp32_operand ||
          which == Assembler::call32_operand ||
-         which == Assembler::imm64_operand, "format unpacks ok");
-  if (which != Assembler::imm64_operand) {
+         which == Assembler::imm_operand, "format unpacks ok");
+  if (which != Assembler::imm_operand) {
     // The "address" in the code is a displacement can't return it as
     // and address* since it is really a jint*
     ShouldNotReachHere();
     return NULL;
   }
 #else
-  assert(which == Assembler::disp32_operand || which == Assembler::imm32_operand, "format unpacks ok");
+  assert(which == Assembler::disp32_operand || which == Assembler::imm_operand, "format unpacks ok");
 #endif // AMD64
   return (address*) Assembler::locate_operand(addr(), which);
 }
@@ -131,11 +136,11 @@
   // we must parse the instruction a bit to find the embedded word.
   assert(is_data(), "must be a DataRelocation");
   typedef Assembler::WhichOperand WhichOperand;
-  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm64/imm32
+  WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm/imm32
   assert(which == Assembler::disp32_operand ||
          which == Assembler::call32_operand ||
-         which == Assembler::imm64_operand, "format unpacks ok");
-  if (which != Assembler::imm64_operand) {
+         which == Assembler::imm_operand, "format unpacks ok");
+  if (which != Assembler::imm_operand) {
     address ip = addr();
     address disp = Assembler::locate_operand(ip, which);
     address next_ip = Assembler::locate_next_instruction(ip);
@@ -169,3 +174,44 @@
   NativeInstruction* ni = nativeInstruction_at(x);
   *(short*)ni->addr_at(0) = instrs[0];
 }
+
+void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+#ifdef _LP64
+  typedef Assembler::WhichOperand WhichOperand;
+  WhichOperand which = (WhichOperand) format();
+  // This format is imm but it is really disp32
+  which = Assembler::disp32_operand;
+  address orig_addr = old_addr_for(addr(), src, dest);
+  NativeInstruction* oni = nativeInstruction_at(orig_addr);
+  int32_t* orig_disp = (int32_t*) Assembler::locate_operand(orig_addr, which);
+  // This poll_addr is incorrect by the size of the instruction it is irrelevant
+  intptr_t poll_addr = (intptr_t)oni + *orig_disp;
+
+  NativeInstruction* ni = nativeInstruction_at(addr());
+  intptr_t new_disp = poll_addr - (intptr_t) ni;
+
+  int32_t* disp = (int32_t*) Assembler::locate_operand(addr(), which);
+  * disp = (int32_t)new_disp;
+
+#endif // _LP64
+}
+
+void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+#ifdef _LP64
+  typedef Assembler::WhichOperand WhichOperand;
+  WhichOperand which = (WhichOperand) format();
+  // This format is imm but it is really disp32
+  which = Assembler::disp32_operand;
+  address orig_addr = old_addr_for(addr(), src, dest);
+  NativeInstruction* oni = nativeInstruction_at(orig_addr);
+  int32_t* orig_disp = (int32_t*) Assembler::locate_operand(orig_addr, which);
+  // This poll_addr is incorrect by the size of the instruction it is irrelevant
+  intptr_t poll_addr = (intptr_t)oni + *orig_disp;
+
+  NativeInstruction* ni = nativeInstruction_at(addr());
+  intptr_t new_disp = poll_addr - (intptr_t) ni;
+
+  int32_t* disp = (int32_t*) Assembler::locate_operand(addr(), which);
+  * disp = (int32_t)new_disp;
+#endif // _LP64
+}
--- a/hotspot/src/cpu/x86/vm/runtime_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/runtime_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -78,18 +78,18 @@
 
   address start = __ pc();
 
-  __ pushl(rdx);
-  __ subl(rsp, return_off * wordSize);   // Prolog!
+  __ push(rdx);
+  __ subptr(rsp, return_off * wordSize);   // Prolog!
 
   // rbp, location is implicitly known
-  __ movl(Address(rsp,rbp_off  *wordSize),rbp);
+  __ movptr(Address(rsp,rbp_off  *wordSize), rbp);
 
   // Store exception in Thread object. We cannot pass any arguments to the
   // handle_exception call, since we do not want to make any assumption
   // about the size of the frame where the exception happened in.
   __ get_thread(rcx);
-  __ movl(Address(rcx, JavaThread::exception_oop_offset()), rax);
-  __ movl(Address(rcx, JavaThread::exception_pc_offset()),  rdx);
+  __ movptr(Address(rcx, JavaThread::exception_oop_offset()), rax);
+  __ movptr(Address(rcx, JavaThread::exception_pc_offset()),  rdx);
 
   // This call does all the hard work.  It checks if an exception handler
   // exists in the method.
@@ -97,7 +97,7 @@
   // If not, it prepares for stack-unwinding, restoring the callee-save
   // registers of the frame being removed.
   //
-  __ movl(Address(rsp, thread_off * wordSize), rcx); // Thread is first argument
+  __ movptr(Address(rsp, thread_off * wordSize), rcx); // Thread is first argument
   __ set_last_Java_frame(rcx, noreg, noreg, NULL);
 
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
@@ -108,10 +108,10 @@
   __ reset_last_Java_frame(rcx, false, false);
 
   // Restore callee-saved registers
-  __ movl(rbp, Address(rsp, rbp_off * wordSize));
+  __ movptr(rbp, Address(rsp, rbp_off * wordSize));
 
-  __ addl(rsp, return_off * wordSize);   // Epilog!
-  __ popl(rdx); // Exception pc
+  __ addptr(rsp, return_off * wordSize);   // Epilog!
+  __ pop(rdx); // Exception pc
 
 
   // rax,: exception handler for given <exception oop/exception pc>
@@ -119,23 +119,23 @@
   // We have a handler in rax, (could be deopt blob)
   // rdx - throwing pc, deopt blob will need it.
 
-  __ pushl(rax);
+  __ push(rax);
 
   // rcx contains handler address
 
   __ get_thread(rcx);           // TLS
   // Get the exception
-  __ movl(rax, Address(rcx, JavaThread::exception_oop_offset()));
+  __ movptr(rax, Address(rcx, JavaThread::exception_oop_offset()));
   // Get the exception pc in case we are deoptimized
-  __ movl(rdx, Address(rcx, JavaThread::exception_pc_offset()));
+  __ movptr(rdx, Address(rcx, JavaThread::exception_pc_offset()));
 #ifdef ASSERT
-  __ movl(Address(rcx, JavaThread::exception_handler_pc_offset()), 0);
-  __ movl(Address(rcx, JavaThread::exception_pc_offset()), 0);
+  __ movptr(Address(rcx, JavaThread::exception_handler_pc_offset()), (int32_t)NULL_WORD);
+  __ movptr(Address(rcx, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
 #endif
   // Clear the exception oop so GC no longer processes it as a root.
-  __ movl(Address(rcx, JavaThread::exception_oop_offset()), 0);
+  __ movptr(Address(rcx, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
 
-  __ popl(rcx);
+  __ pop(rcx);
 
   // rax,: exception oop
   // rcx: exception handler
--- a/hotspot/src/cpu/x86/vm/sharedRuntime_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/sharedRuntime_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -118,12 +118,12 @@
   // save registers, fpu state, and flags
   // We assume caller has already has return address slot on the stack
   // We push epb twice in this sequence because we want the real rbp,
-  // to be under the return like a normal enter and we want to use pushad
+  // to be under the return like a normal enter and we want to use pusha
   // We push by hand instead of pusing push
   __ enter();
-  __ pushad();
-  __ pushfd();
-  __ subl(rsp,FPU_regs_live*sizeof(jdouble)); // Push FPU registers space
+  __ pusha();
+  __ pushf();
+  __ subptr(rsp,FPU_regs_live*sizeof(jdouble)); // Push FPU registers space
   __ push_FPU_state();          // Save FPU state & init
 
   if (verify_fpu) {
@@ -270,12 +270,12 @@
     __ movdbl(xmm7,Address(rsp,xmm7_off*wordSize));
   }
   __ pop_FPU_state();
-  __ addl(rsp,FPU_regs_live*sizeof(jdouble)); // Pop FPU registers
-
-  __ popfd();
-  __ popad();
+  __ addptr(rsp, FPU_regs_live*sizeof(jdouble)); // Pop FPU registers
+
+  __ popf();
+  __ popa();
   // Get the rbp, described implicitly by the frame sender code (no oopMap)
-  __ popl(rbp);
+  __ pop(rbp);
 
 }
 
@@ -296,10 +296,10 @@
   } else if( UseSSE >= 2 ) {
     __ movdbl(xmm0, Address(rsp, xmm0_off*wordSize));
   }
-  __ movl(rax, Address(rsp, rax_off*wordSize));
-  __ movl(rdx, Address(rsp, rdx_off*wordSize));
+  __ movptr(rax, Address(rsp, rax_off*wordSize));
+  __ movptr(rdx, Address(rsp, rdx_off*wordSize));
   // Pop all of the register save are off the stack except the return address
-  __ addl(rsp, return_off * wordSize);
+  __ addptr(rsp, return_off * wordSize);
 }
 
 // The java_calling_convention describes stack locations as ideal slots on
@@ -448,22 +448,22 @@
 static void patch_callers_callsite(MacroAssembler *masm) {
   Label L;
   __ verify_oop(rbx);
-  __ cmpl(Address(rbx, in_bytes(methodOopDesc::code_offset())), NULL_WORD);
+  __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
   __ jcc(Assembler::equal, L);
   // Schedule the branch target address early.
   // Call into the VM to patch the caller, then jump to compiled callee
   // rax, isn't live so capture return address while we easily can
-  __ movl(rax, Address(rsp, 0));
-  __ pushad();
-  __ pushfd();
+  __ movptr(rax, Address(rsp, 0));
+  __ pusha();
+  __ pushf();
 
   if (UseSSE == 1) {
-    __ subl(rsp, 2*wordSize);
+    __ subptr(rsp, 2*wordSize);
     __ movflt(Address(rsp, 0), xmm0);
     __ movflt(Address(rsp, wordSize), xmm1);
   }
   if (UseSSE >= 2) {
-    __ subl(rsp, 4*wordSize);
+    __ subptr(rsp, 4*wordSize);
     __ movdbl(Address(rsp, 0), xmm0);
     __ movdbl(Address(rsp, 2*wordSize), xmm1);
   }
@@ -477,26 +477,26 @@
 #endif /* COMPILER2 */
 
   // VM needs caller's callsite
-  __ pushl(rax);
+  __ push(rax);
   // VM needs target method
-  __ pushl(rbx);
+  __ push(rbx);
   __ verify_oop(rbx);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
-  __ addl(rsp, 2*wordSize);
+  __ addptr(rsp, 2*wordSize);
 
   if (UseSSE == 1) {
     __ movflt(xmm0, Address(rsp, 0));
     __ movflt(xmm1, Address(rsp, wordSize));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
   }
   if (UseSSE >= 2) {
     __ movdbl(xmm0, Address(rsp, 0));
     __ movdbl(xmm1, Address(rsp, 2*wordSize));
-    __ addl(rsp, 4*wordSize);
+    __ addptr(rsp, 4*wordSize);
   }
 
-  __ popfd();
-  __ popad();
+  __ popf();
+  __ popa();
   __ bind(L);
 }
 
@@ -506,13 +506,13 @@
   if (TaggedStackInterpreter) {
     int tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(0);
     if (sig == T_OBJECT || sig == T_ARRAY) {
-      __ movl(Address(rsp, tag_offset), frame::TagReference);
+      __ movptr(Address(rsp, tag_offset), frame::TagReference);
     } else if (sig == T_LONG || sig == T_DOUBLE) {
       int next_tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(1);
-      __ movl(Address(rsp, next_tag_offset), frame::TagValue);
-      __ movl(Address(rsp, tag_offset), frame::TagValue);
+      __ movptr(Address(rsp, next_tag_offset), frame::TagValue);
+      __ movptr(Address(rsp, tag_offset), frame::TagValue);
     } else {
-      __ movl(Address(rsp, tag_offset), frame::TagValue);
+      __ movptr(Address(rsp, tag_offset), frame::TagValue);
     }
   }
 }
@@ -561,12 +561,12 @@
   int extraspace = total_args_passed * Interpreter::stackElementSize();
 
   // Get return address
-  __ popl(rax);
+  __ pop(rax);
 
   // set senderSP value
-  __ movl(rsi, rsp);
-
-  __ subl(rsp, extraspace);
+  __ movptr(rsi, rsp);
+
+  __ subptr(rsp, extraspace);
 
   // Now write the args into the outgoing interpreter space
   for (int i = 0; i < total_args_passed; i++) {
@@ -577,6 +577,8 @@
 
     // st_off points to lowest address on stack.
     int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize();
+    int next_off = st_off - Interpreter::stackElementSize();
+
     // Say 4 args:
     // i   st_off
     // 0   12 T_LONG
@@ -596,18 +598,25 @@
 
       if (!r_2->is_valid()) {
         __ movl(rdi, Address(rsp, ld_off));
-        __ movl(Address(rsp, st_off), rdi);
+        __ movptr(Address(rsp, st_off), rdi);
         tag_stack(masm, sig_bt[i], st_off);
       } else {
 
         // ld_off == LSW, ld_off+VMRegImpl::stack_slot_size == MSW
         // st_off == MSW, st_off-wordSize == LSW
 
-        int next_off = st_off - Interpreter::stackElementSize();
-        __ movl(rdi, Address(rsp, ld_off));
-        __ movl(Address(rsp, next_off), rdi);
-        __ movl(rdi, Address(rsp, ld_off + wordSize));
-        __ movl(Address(rsp, st_off), rdi);
+        __ movptr(rdi, Address(rsp, ld_off));
+        __ movptr(Address(rsp, next_off), rdi);
+#ifndef _LP64
+        __ movptr(rdi, Address(rsp, ld_off + wordSize));
+        __ movptr(Address(rsp, st_off), rdi);
+#else
+#ifdef ASSERT
+        // Overwrite the unused slot with known junk
+        __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
+        __ movptr(Address(rsp, st_off), rax);
+#endif /* ASSERT */
+#endif // _LP64
         tag_stack(masm, sig_bt[i], next_off);
       }
     } else if (r_1->is_Register()) {
@@ -617,7 +626,22 @@
         tag_stack(masm, sig_bt[i], st_off);
       } else {
         // long/double in gpr
-        ShouldNotReachHere();
+        NOT_LP64(ShouldNotReachHere());
+        // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
+        // T_DOUBLE and T_LONG use two slots in the interpreter
+        if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
+          // long/double in gpr
+#ifdef ASSERT
+          // Overwrite the unused slot with known junk
+          LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
+          __ movptr(Address(rsp, st_off), rax);
+#endif /* ASSERT */
+          __ movptr(Address(rsp, next_off), r);
+          tag_stack(masm, sig_bt[i], next_off);
+        } else {
+          __ movptr(Address(rsp, st_off), r);
+          tag_stack(masm, sig_bt[i], st_off);
+        }
       }
     } else {
       assert(r_1->is_XMMRegister(), "");
@@ -632,9 +656,9 @@
   }
 
   // Schedule the branch target address early.
-  __ movl(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
+  __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
   // And repush original return address
-  __ pushl(rax);
+  __ push(rax);
   __ jmp(rcx);
 }
 
@@ -645,11 +669,11 @@
   int next_val_off = ld_off - Interpreter::stackElementSize();
   if (TaggedStackInterpreter) {
     // use tag slot temporarily for MSW
-    __ movl(rsi, Address(saved_sp, ld_off));
-    __ movl(Address(saved_sp, next_val_off+wordSize), rsi);
+    __ movptr(rsi, Address(saved_sp, ld_off));
+    __ movptr(Address(saved_sp, next_val_off+wordSize), rsi);
     __ movdbl(r, Address(saved_sp, next_val_off));
     // restore tag
-    __ movl(Address(saved_sp, next_val_off+wordSize), frame::TagValue);
+    __ movptr(Address(saved_sp, next_val_off+wordSize), frame::TagValue);
   } else {
     __ movdbl(r, Address(saved_sp, next_val_off));
   }
@@ -685,7 +709,7 @@
   // code goes non-entrant while we get args ready.
 
   // Pick up the return address
-  __ movl(rax, Address(rsp, 0));
+  __ movptr(rax, Address(rsp, 0));
 
   // If UseSSE >= 2 then no cleanup is needed on the return to the
   // interpreter so skip fixing up the return entry point unless
@@ -696,10 +720,10 @@
     // cleanup than if the interpreter returned to the call stub.
 
     ExternalAddress stub_return_address(StubRoutines::_call_stub_return_address);
-    __ cmp32(rax, stub_return_address.addr());
+    __ cmpptr(rax, stub_return_address.addr());
     __ jcc(Assembler::notEqual, chk_int);
-    assert(StubRoutines::i486::get_call_stub_compiled_return() != NULL, "must be set");
-    __ lea(rax, ExternalAddress(StubRoutines::i486::get_call_stub_compiled_return()));
+    assert(StubRoutines::x86::get_call_stub_compiled_return() != NULL, "must be set");
+    __ lea(rax, ExternalAddress(StubRoutines::x86::get_call_stub_compiled_return()));
     __ jmp(skip);
 
     // It must be the interpreter since we never get here via a c2i (unlike Azul)
@@ -708,13 +732,13 @@
 #ifdef ASSERT
     {
       Label ok;
-      __ cmpl(Address(rax, -8), Interpreter::return_sentinel);
+      __ cmpl(Address(rax, -2*wordSize), Interpreter::return_sentinel);
       __ jcc(Assembler::equal, ok);
       __ int3();
       __ bind(ok);
     }
 #endif // ASSERT
-    __ movl(rax, Address(rax, -4));
+    __ movptr(rax, Address(rax, -wordSize));
     __ bind(skip);
   }
 
@@ -723,7 +747,7 @@
 
   // Must preserve original SP for loading incoming arguments because
   // we need to align the outgoing SP for compiled code.
-  __ movl(rdi, rsp);
+  __ movptr(rdi, rsp);
 
   // Cut-out for having no stack args.  Since up to 2 int/oop args are passed
   // in registers, we will occasionally have no stack args.
@@ -737,24 +761,24 @@
     comp_words_on_stack = round_to(comp_args_on_stack*4, wordSize)>>LogBytesPerWord;
     // Round up to miminum stack alignment, in wordSize
     comp_words_on_stack = round_to(comp_words_on_stack, 2);
-    __ subl(rsp, comp_words_on_stack * wordSize);
+    __ subptr(rsp, comp_words_on_stack * wordSize);
   }
 
   // Align the outgoing SP
-  __ andl(rsp, -(StackAlignmentInBytes));
+  __ andptr(rsp, -(StackAlignmentInBytes));
 
   // push the return address on the stack (note that pushing, rather
   // than storing it, yields the correct frame alignment for the callee)
-  __ pushl(rax);
+  __ push(rax);
 
   // Put saved SP in another register
   const Register saved_sp = rax;
-  __ movl(saved_sp, rdi);
+  __ movptr(saved_sp, rdi);
 
 
   // Will jump to the compiled code just as if compiled code was doing it.
   // Pre-load the register-jump target early, to schedule it better.
-  __ movl(rdi, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
+  __ movptr(rdi, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
 
   // Now generate the shuffle code.  Pick up all register args and move the
   // rest through the floating point stack top.
@@ -794,7 +818,7 @@
         // __ fld_s(Address(saved_sp, ld_off));
         // __ fstp_s(Address(rsp, st_off));
         __ movl(rsi, Address(saved_sp, ld_off));
-        __ movl(Address(rsp, st_off), rsi);
+        __ movptr(Address(rsp, st_off), rsi);
       } else {
         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
         // are accessed as negative so LSW is at LOW address
@@ -803,20 +827,44 @@
         // st_off is LSW (i.e. reg.first())
         // __ fld_d(Address(saved_sp, next_off));
         // __ fstp_d(Address(rsp, st_off));
-        __ movl(rsi, Address(saved_sp, next_off));
-        __ movl(Address(rsp, st_off), rsi);
-        __ movl(rsi, Address(saved_sp, ld_off));
-        __ movl(Address(rsp, st_off + wordSize), rsi);
+        //
+        // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
+        // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
+        // So we must adjust where to pick up the data to match the interpreter.
+        //
+        // Interpreter local[n] == MSW, local[n+1] == LSW however locals
+        // are accessed as negative so LSW is at LOW address
+
+        // ld_off is MSW so get LSW
+        const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
+                           next_off : ld_off;
+        __ movptr(rsi, Address(saved_sp, offset));
+        __ movptr(Address(rsp, st_off), rsi);
+#ifndef _LP64
+        __ movptr(rsi, Address(saved_sp, ld_off));
+        __ movptr(Address(rsp, st_off + wordSize), rsi);
+#endif // _LP64
       }
     } else if (r_1->is_Register()) {  // Register argument
       Register r = r_1->as_Register();
       assert(r != rax, "must be different");
       if (r_2->is_valid()) {
+        //
+        // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
+        // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
+        // So we must adjust where to pick up the data to match the interpreter.
+
+        const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
+                           next_off : ld_off;
+
+        // this can be a misaligned move
+        __ movptr(r, Address(saved_sp, offset));
+#ifndef _LP64
         assert(r_2->as_Register() != rax, "need another temporary register");
         // Remember r_1 is low address (and LSB on x86)
         // So r_2 gets loaded from high address regardless of the platform
-        __ movl(r_2->as_Register(), Address(saved_sp, ld_off));
-        __ movl(r, Address(saved_sp, next_off));
+        __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
+#endif // _LP64
       } else {
         __ movl(r, Address(saved_sp, ld_off));
       }
@@ -841,13 +889,13 @@
   // and the vm will find there should this case occur.
 
   __ get_thread(rax);
-  __ movl(Address(rax, JavaThread::callee_target_offset()), rbx);
+  __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
 
   // move methodOop to rax, in case we end up in an c2i adapter.
   // the c2i adapters expect methodOop in rax, (c2) because c2's
   // resolve stubs return the result (the method) in rax,.
   // I'd love to fix this.
-  __ movl(rax, rbx);
+  __ mov(rax, rbx);
 
   __ jmp(rdi);
 }
@@ -883,16 +931,16 @@
     Label missed;
 
     __ verify_oop(holder);
-    __ movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
+    __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
     __ verify_oop(temp);
 
-    __ cmpl(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
-    __ movl(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
+    __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
+    __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
     __ jcc(Assembler::notEqual, missed);
     // Method might have been compiled since the call site was patched to
     // interpreted if that is the case treat it as a miss so we can get
     // the call site corrected.
-    __ cmpl(Address(rbx, in_bytes(methodOopDesc::code_offset())), NULL_WORD);
+    __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, skip_fixup);
 
     __ bind(missed);
@@ -953,17 +1001,20 @@
       // stack to stack
       // __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
       // __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
-      __ movl(rax, Address(rbp, reg2offset_in(src.first())));
-      __ movl(Address(rsp, reg2offset_out(dst.first())), rax);
+      __ movl2ptr(rax, Address(rbp, reg2offset_in(src.first())));
+      __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
     } else {
       // stack to reg
-      __ movl(dst.first()->as_Register(),  Address(rbp, reg2offset_in(src.first())));
+      __ movl2ptr(dst.first()->as_Register(),  Address(rbp, reg2offset_in(src.first())));
     }
   } else if (dst.first()->is_stack()) {
     // reg to stack
-    __ movl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
+    // no need to sign extend on 64bit
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
   } else {
-    __ movl(dst.first()->as_Register(), src.first()->as_Register());
+    if (dst.first() != src.first()) {
+      __ mov(dst.first()->as_Register(), src.first()->as_Register());
+    }
   }
 }
 
@@ -987,12 +1038,12 @@
     // Oop is already on the stack as an argument
     Register rHandle = rax;
     Label nil;
-    __ xorl(rHandle, rHandle);
-    __ cmpl(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
+    __ xorptr(rHandle, rHandle);
+    __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, nil);
-    __ leal(rHandle, Address(rbp, reg2offset_in(src.first())));
+    __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
     __ bind(nil);
-    __ movl(Address(rsp, reg2offset_out(dst.first())), rHandle);
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
 
     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
@@ -1007,15 +1058,15 @@
     int oop_slot = (rOop == rcx ? 0 : 1) * VMRegImpl::slots_per_word + oop_handle_offset;
     int offset = oop_slot*VMRegImpl::stack_slot_size;
     Label skip;
-    __ movl(Address(rsp, offset), rOop);
+    __ movptr(Address(rsp, offset), rOop);
     map->set_oop(VMRegImpl::stack2reg(oop_slot));
-    __ xorl(rHandle, rHandle);
-    __ cmpl(rOop, NULL_WORD);
+    __ xorptr(rHandle, rHandle);
+    __ cmpptr(rOop, (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, skip);
-    __ leal(rHandle, Address(rsp, offset));
+    __ lea(rHandle, Address(rsp, offset));
     __ bind(skip);
     // Store the handle parameter
-    __ movl(Address(rsp, reg2offset_out(dst.first())), rHandle);
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
     if (is_receiver) {
       *receiver_offset = offset;
     }
@@ -1033,7 +1084,7 @@
 
   if (src.first()->is_stack()) {
     __ movl(rax, Address(rbp, reg2offset_in(src.first())));
-    __ movl(Address(rsp, reg2offset_out(dst.first())), rax);
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
   } else {
     // reg to stack
     __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
@@ -1050,10 +1101,10 @@
 
   if (src.first()->is_stack() && dst.first()->is_stack()) {
     assert(src.second()->is_stack() && dst.second()->is_stack(), "must be all stack");
-    __ movl(rax, Address(rbp, reg2offset_in(src.first())));
-    __ movl(rbx, Address(rbp, reg2offset_in(src.second())));
-    __ movl(Address(rsp, reg2offset_out(dst.first())), rax);
-    __ movl(Address(rsp, reg2offset_out(dst.second())), rbx);
+    __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
+    NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
+    NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
   } else {
     ShouldNotReachHere();
   }
@@ -1074,10 +1125,10 @@
 
   if (src.first()->is_stack()) {
     // source is all stack
-    __ movl(rax, Address(rbp, reg2offset_in(src.first())));
-    __ movl(rbx, Address(rbp, reg2offset_in(src.second())));
-    __ movl(Address(rsp, reg2offset_out(dst.first())), rax);
-    __ movl(Address(rsp, reg2offset_out(dst.second())), rbx);
+    __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
+    NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
+    NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
   } else {
     // reg to stack
     // No worries about stack alignment
@@ -1098,11 +1149,11 @@
     break;
   case T_VOID:  break;
   case T_LONG:
-    __ movl(Address(rbp, -wordSize), rax);
-    __ movl(Address(rbp, -2*wordSize), rdx);
+    __ movptr(Address(rbp, -wordSize), rax);
+    NOT_LP64(__ movptr(Address(rbp, -2*wordSize), rdx));
     break;
   default: {
-    __ movl(Address(rbp, -wordSize), rax);
+    __ movptr(Address(rbp, -wordSize), rax);
     }
   }
 }
@@ -1118,12 +1169,12 @@
     __ fld_d(Address(rbp, -2*wordSize));
     break;
   case T_LONG:
-    __ movl(rax, Address(rbp, -wordSize));
-    __ movl(rdx, Address(rbp, -2*wordSize));
+    __ movptr(rax, Address(rbp, -wordSize));
+    NOT_LP64(__ movptr(rdx, Address(rbp, -2*wordSize)));
     break;
   case T_VOID:  break;
   default: {
-    __ movl(rax, Address(rbp, -wordSize));
+    __ movptr(rax, Address(rbp, -wordSize));
     }
   }
 }
@@ -1268,7 +1319,7 @@
 
 
   __ verify_oop(receiver);
-  __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
+  __ cmpptr(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
   __ jcc(Assembler::equal, hit);
 
   __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
@@ -1291,23 +1342,23 @@
     Label slowCase;
     Register receiver = rcx;
     Register result = rax;
-    __ movl(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
+    __ movptr(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
 
     // check if locked
-    __ testl (result, markOopDesc::unlocked_value);
+    __ testptr(result, markOopDesc::unlocked_value);
     __ jcc (Assembler::zero, slowCase);
 
     if (UseBiasedLocking) {
       // Check if biased and fall through to runtime if so
-      __ testl (result, markOopDesc::biased_lock_bit_in_place);
+      __ testptr(result, markOopDesc::biased_lock_bit_in_place);
       __ jcc (Assembler::notZero, slowCase);
     }
 
     // get hash
-    __ andl (result, markOopDesc::hash_mask_in_place);
+    __ andptr(result, markOopDesc::hash_mask_in_place);
     // test if hashCode exists
     __ jcc  (Assembler::zero, slowCase);
-    __ shrl (result, markOopDesc::hash_shift);
+    __ shrptr(result, markOopDesc::hash_shift);
     __ ret(0);
     __ bind (slowCase);
   }
@@ -1329,7 +1380,7 @@
   // Generate a new frame for the wrapper.
   __ enter();
   // -2 because return address is already present and so is saved rbp,
-  __ subl(rsp, stack_size - 2*wordSize);
+  __ subptr(rsp, stack_size - 2*wordSize);
 
   // Frame is now completed as far a size and linkage.
 
@@ -1450,13 +1501,13 @@
     __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
 
     // Now handlize the static class mirror it's known not-null.
-    __ movl(Address(rsp, klass_offset), oop_handle_reg);
+    __ movptr(Address(rsp, klass_offset), oop_handle_reg);
     map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
 
     // Now get the handle
-    __ leal(oop_handle_reg, Address(rsp, klass_offset));
+    __ lea(oop_handle_reg, Address(rsp, klass_offset));
     // store the klass handle as second argument
-    __ movl(Address(rsp, wordSize), oop_handle_reg);
+    __ movptr(Address(rsp, wordSize), oop_handle_reg);
   }
 
   // Change state to native (we save the return address in the thread, since it might not
@@ -1497,14 +1548,14 @@
     const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
 
     // Get the handle (the 2nd argument)
-    __ movl(oop_handle_reg, Address(rsp, wordSize));
+    __ movptr(oop_handle_reg, Address(rsp, wordSize));
 
     // Get address of the box
 
-    __ leal(lock_reg, Address(rbp, lock_slot_rbp_offset));
+    __ lea(lock_reg, Address(rbp, lock_slot_rbp_offset));
 
     // Load the oop from the handle
-    __ movl(obj_reg, Address(oop_handle_reg, 0));
+    __ movptr(obj_reg, Address(oop_handle_reg, 0));
 
     if (UseBiasedLocking) {
       // Note that oop_handle_reg is trashed during this call
@@ -1512,13 +1563,13 @@
     }
 
     // Load immediate 1 into swap_reg %rax,
-    __ movl(swap_reg, 1);
+    __ movptr(swap_reg, 1);
 
     // Load (object->mark() | 1) into swap_reg %rax,
-    __ orl(swap_reg, Address(obj_reg, 0));
+    __ orptr(swap_reg, Address(obj_reg, 0));
 
     // Save (object->mark() | 1) into BasicLock's displaced header
-    __ movl(Address(lock_reg, mark_word_offset), swap_reg);
+    __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
 
     if (os::is_MP()) {
       __ lock();
@@ -1526,7 +1577,7 @@
 
     // src -> dest iff dest == rax, else rax, <- dest
     // *obj_reg = lock_reg iff *obj_reg == rax, else rax, = *(obj_reg)
-    __ cmpxchg(lock_reg, Address(obj_reg, 0));
+    __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
     __ jcc(Assembler::equal, lock_done);
 
     // Test if the oopMark is an obvious stack pointer, i.e.,
@@ -1538,18 +1589,18 @@
     // least significant 2 bits clear.
     // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
 
-    __ subl(swap_reg, rsp);
-    __ andl(swap_reg, 3 - os::vm_page_size());
+    __ subptr(swap_reg, rsp);
+    __ andptr(swap_reg, 3 - os::vm_page_size());
 
     // Save the test result, for recursive case, the result is zero
-    __ movl(Address(lock_reg, mark_word_offset), swap_reg);
+    __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
     __ jcc(Assembler::notEqual, slow_path_lock);
     // Slow path will re-enter here
     __ bind(lock_done);
 
     if (UseBiasedLocking) {
       // Re-fetch oop_handle_reg as we trashed it above
-      __ movl(oop_handle_reg, Address(rsp, wordSize));
+      __ movptr(oop_handle_reg, Address(rsp, wordSize));
     }
   }
 
@@ -1559,8 +1610,8 @@
 
   // get JNIEnv* which is first argument to native
 
-  __ leal(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
-  __ movl(Address(rsp, 0), rdx);
+  __ lea(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
+  __ movptr(Address(rsp, 0), rdx);
 
   // Now set thread in native
   __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native);
@@ -1575,7 +1626,7 @@
   // Unpack native results.
   switch (ret_type) {
   case T_BOOLEAN: __ c2bool(rax);            break;
-  case T_CHAR   : __ andl(rax, 0xFFFF);      break;
+  case T_CHAR   : __ andptr(rax, 0xFFFF);    break;
   case T_BYTE   : __ sign_extend_byte (rax); break;
   case T_SHORT  : __ sign_extend_short(rax); break;
   case T_INT    : /* nothing to do */        break;
@@ -1602,7 +1653,10 @@
 
   if(os::is_MP()) {
     if (UseMembar) {
-      __ membar(); // Force this write out before the read below
+      // Force this write out before the read below
+      __ membar(Assembler::Membar_mask_bits(
+           Assembler::LoadLoad | Assembler::LoadStore |
+           Assembler::StoreLoad | Assembler::StoreStore));
     } else {
       // Write serialization page so VM thread can do a pseudo remote membar.
       // We use the current thread pointer to calculate a thread specific
@@ -1636,7 +1690,7 @@
     // by hand.
     //
     save_native_result(masm, ret_type, stack_slots);
-    __ pushl(thread);
+    __ push(thread);
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
                                             JavaThread::check_special_condition_for_native_trans)));
     __ increment(rsp, wordSize);
@@ -1669,7 +1723,7 @@
     Label done;
 
     // Get locked oop from the handle we passed to jni
-    __ movl(obj_reg, Address(oop_handle_reg, 0));
+    __ movptr(obj_reg, Address(oop_handle_reg, 0));
 
     if (UseBiasedLocking) {
       __ biased_locking_exit(obj_reg, rbx, done);
@@ -1677,7 +1731,7 @@
 
     // Simple recursive lock?
 
-    __ cmpl(Address(rbp, lock_slot_rbp_offset), NULL_WORD);
+    __ cmpptr(Address(rbp, lock_slot_rbp_offset), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, done);
 
     // Must save rax, if if it is live now because cmpxchg must use it
@@ -1686,10 +1740,10 @@
     }
 
     //  get old displaced header
-    __ movl(rbx, Address(rbp, lock_slot_rbp_offset));
+    __ movptr(rbx, Address(rbp, lock_slot_rbp_offset));
 
     // get address of the stack lock
-    __ leal(rax, Address(rbp, lock_slot_rbp_offset));
+    __ lea(rax, Address(rbp, lock_slot_rbp_offset));
 
     // Atomic swap old header if oop still contains the stack lock
     if (os::is_MP()) {
@@ -1698,7 +1752,7 @@
 
     // src -> dest iff dest == rax, else rax, <- dest
     // *obj_reg = rbx, iff *obj_reg == rax, else rax, = *(obj_reg)
-    __ cmpxchg(rbx, Address(obj_reg, 0));
+    __ cmpxchgptr(rbx, Address(obj_reg, 0));
     __ jcc(Assembler::notEqual, slow_path_unlock);
 
     // slow path re-enters here
@@ -1729,20 +1783,20 @@
   // Unpack oop result
   if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
       Label L;
-      __ cmpl(rax, NULL_WORD);
+      __ cmpptr(rax, (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, L);
-      __ movl(rax, Address(rax, 0));
+      __ movptr(rax, Address(rax, 0));
       __ bind(L);
       __ verify_oop(rax);
   }
 
   // reset handle block
-  __ movl(rcx, Address(thread, JavaThread::active_handles_offset()));
-
-  __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), 0);
+  __ movptr(rcx, Address(thread, JavaThread::active_handles_offset()));
+
+  __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
 
   // Any exception pending?
-  __ cmpl(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
+  __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, exception_pending);
 
 
@@ -1782,15 +1836,15 @@
 
     // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
     // args are (oop obj, BasicLock* lock, JavaThread* thread)
-    __ pushl(thread);
-    __ pushl(lock_reg);
-    __ pushl(obj_reg);
+    __ push(thread);
+    __ push(lock_reg);
+    __ push(obj_reg);
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C)));
-    __ addl(rsp, 3*wordSize);
+    __ addptr(rsp, 3*wordSize);
 
 #ifdef ASSERT
     { Label L;
-    __ cmpl(Address(thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
+    __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
     __ jcc(Assembler::equal, L);
     __ stop("no pending exception allowed on exit from monitorenter");
     __ bind(L);
@@ -1810,29 +1864,29 @@
     }
     // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
 
-    __ pushl(Address(thread, in_bytes(Thread::pending_exception_offset())));
-    __ movl(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
+    __ pushptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
+    __ movptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
 
 
     // should be a peal
     // +wordSize because of the push above
-    __ leal(rax, Address(rbp, lock_slot_rbp_offset));
-    __ pushl(rax);
-
-    __ pushl(obj_reg);
+    __ lea(rax, Address(rbp, lock_slot_rbp_offset));
+    __ push(rax);
+
+    __ push(obj_reg);
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
 #ifdef ASSERT
     {
       Label L;
-      __ cmpl(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
+      __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, L);
       __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
       __ bind(L);
     }
 #endif /* ASSERT */
 
-    __ popl(Address(thread, in_bytes(Thread::pending_exception_offset())));
+    __ popptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
 
     if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
       restore_native_result(masm, ret_type, stack_slots);
@@ -2320,7 +2374,7 @@
 
   map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words);
   // Normal deoptimization
-  __ pushl(Deoptimization::Unpack_deopt);
+  __ push(Deoptimization::Unpack_deopt);
   __ jmp(cont);
 
   int reexecute_offset = __ pc() - start;
@@ -2331,7 +2385,7 @@
   // No need to update map as each call to save_live_registers will produce identical oopmap
   (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words);
 
-  __ pushl(Deoptimization::Unpack_reexecute);
+  __ push(Deoptimization::Unpack_reexecute);
   __ jmp(cont);
 
   int exception_offset = __ pc() - start;
@@ -2344,8 +2398,8 @@
   // unpack_with_exception_in_tls entry point.
 
   __ get_thread(rdi);
-  __ movl(Address(rdi, JavaThread::exception_pc_offset()), rdx);
-  __ movl(Address(rdi, JavaThread::exception_oop_offset()), rax);
+  __ movptr(Address(rdi, JavaThread::exception_pc_offset()), rdx);
+  __ movptr(Address(rdi, JavaThread::exception_oop_offset()), rax);
 
   int exception_in_tls_offset = __ pc() - start;
 
@@ -2360,7 +2414,7 @@
   // make room on stack for the return address
   // It will be patched later with the throwing pc. The correct value is not
   // available now because loading it from memory would destroy registers.
-  __ pushl(0);
+  __ push(0);
 
   // Save everything in sight.
 
@@ -2370,24 +2424,24 @@
   // Now it is safe to overwrite any register
 
   // store the correct deoptimization type
-  __ pushl(Deoptimization::Unpack_exception);
+  __ push(Deoptimization::Unpack_exception);
 
   // load throwing pc from JavaThread and patch it as the return address
   // of the current frame. Then clear the field in JavaThread
   __ get_thread(rdi);
-  __ movl(rdx, Address(rdi, JavaThread::exception_pc_offset()));
-  __ movl(Address(rbp, wordSize), rdx);
-  __ movl(Address(rdi, JavaThread::exception_pc_offset()), NULL_WORD);
+  __ movptr(rdx, Address(rdi, JavaThread::exception_pc_offset()));
+  __ movptr(Address(rbp, wordSize), rdx);
+  __ movptr(Address(rdi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
 
 #ifdef ASSERT
   // verify that there is really an exception oop in JavaThread
-  __ movl(rax, Address(rdi, JavaThread::exception_oop_offset()));
+  __ movptr(rax, Address(rdi, JavaThread::exception_oop_offset()));
   __ verify_oop(rax);
 
   // verify that there is no pending exception
   Label no_pending_exception;
-  __ movl(rax, Address(rdi, Thread::pending_exception_offset()));
-  __ testl(rax, rax);
+  __ movptr(rax, Address(rdi, Thread::pending_exception_offset()));
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, no_pending_exception);
   __ stop("must not have pending exception here");
   __ bind(no_pending_exception);
@@ -2402,7 +2456,7 @@
   // Call C code.  Need thread and this frame, but NOT official VM entry
   // crud.  We cannot block on this call, no GC can happen.
   __ get_thread(rcx);
-  __ pushl(rcx);
+  __ push(rcx);
   // fetch_unroll_info needs to call last_java_frame()
   __ set_last_Java_frame(rcx, noreg, noreg, NULL);
 
@@ -2414,35 +2468,35 @@
   oop_maps->add_gc_map( __ pc()-start, map);
 
   // Discard arg to fetch_unroll_info
-  __ popl(rcx);
+  __ pop(rcx);
 
   __ get_thread(rcx);
   __ reset_last_Java_frame(rcx, false, false);
 
   // Load UnrollBlock into EDI
-  __ movl(rdi, rax);
+  __ mov(rdi, rax);
 
   // Move the unpack kind to a safe place in the UnrollBlock because
   // we are very short of registers
 
   Address unpack_kind(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes());
   // retrieve the deopt kind from where we left it.
-  __ popl(rax);
+  __ pop(rax);
   __ movl(unpack_kind, rax);                      // save the unpack_kind value
 
    Label noException;
   __ cmpl(rax, Deoptimization::Unpack_exception);   // Was exception pending?
   __ jcc(Assembler::notEqual, noException);
-  __ movl(rax, Address(rcx, JavaThread::exception_oop_offset()));
-  __ movl(rdx, Address(rcx, JavaThread::exception_pc_offset()));
-  __ movl(Address(rcx, JavaThread::exception_oop_offset()), NULL_WORD);
-  __ movl(Address(rcx, JavaThread::exception_pc_offset()), NULL_WORD);
+  __ movptr(rax, Address(rcx, JavaThread::exception_oop_offset()));
+  __ movptr(rdx, Address(rcx, JavaThread::exception_pc_offset()));
+  __ movptr(Address(rcx, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
+  __ movptr(Address(rcx, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
 
   __ verify_oop(rax);
 
   // Overwrite the result registers with the exception results.
-  __ movl(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
-  __ movl(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
+  __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
+  __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
 
   __ bind(noException);
 
@@ -2467,7 +2521,7 @@
   // when we are done the return to frame 3 will still be on the stack.
 
   // Pop deoptimized frame
-  __ addl(rsp,Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
+  __ addptr(rsp, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
 
   // sp should be pointing at the return address to the caller (3)
 
@@ -2478,12 +2532,12 @@
   }
 
   // Load array of frame pcs into ECX
-  __ movl(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
-
-  __ popl(rsi); // trash the old pc
+  __ movptr(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
+
+  __ pop(rsi); // trash the old pc
 
   // Load array of frame sizes into ESI
-  __ movl(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
+  __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
 
   Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
 
@@ -2491,7 +2545,7 @@
   __ movl(counter, rbx);
 
   // Pick up the initial fp we should save
-  __ movl(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
+  __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
 
   // Now adjust the caller's stack to make up for the extra locals
   // but record the original sp so that we can save it in the skeletal interpreter
@@ -2499,43 +2553,44 @@
   // value and not the "real" sp value.
 
   Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
-  __ movl(sp_temp, rsp);
-  __ subl(rsp, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
+  __ movptr(sp_temp, rsp);
+  __ movl2ptr(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
+  __ subptr(rsp, rbx);
 
   // Push interpreter frames in a loop
   Label loop;
   __ bind(loop);
-  __ movl(rbx, Address(rsi, 0));        // Load frame size
+  __ movptr(rbx, Address(rsi, 0));      // Load frame size
 #ifdef CC_INTERP
-  __ subl(rbx, 4*wordSize);             // we'll push pc and ebp by hand and
+  __ subptr(rbx, 4*wordSize);           // we'll push pc and ebp by hand and
 #ifdef ASSERT
-  __ pushl(0xDEADDEAD);                 // Make a recognizable pattern
-  __ pushl(0xDEADDEAD);
+  __ push(0xDEADDEAD);                  // Make a recognizable pattern
+  __ push(0xDEADDEAD);
 #else /* ASSERT */
-  __ subl(rsp, 2*wordSize);             // skip the "static long no_param"
+  __ subptr(rsp, 2*wordSize);           // skip the "static long no_param"
 #endif /* ASSERT */
 #else /* CC_INTERP */
-  __ subl(rbx, 2*wordSize);             // we'll push pc and rbp, by hand
+  __ subptr(rbx, 2*wordSize);           // we'll push pc and rbp, by hand
 #endif /* CC_INTERP */
-  __ pushl(Address(rcx, 0));            // save return address
+  __ pushptr(Address(rcx, 0));          // save return address
   __ enter();                           // save old & set new rbp,
-  __ subl(rsp, rbx);                    // Prolog!
-  __ movl(rbx, sp_temp);                // sender's sp
+  __ subptr(rsp, rbx);                  // Prolog!
+  __ movptr(rbx, sp_temp);              // sender's sp
 #ifdef CC_INTERP
-  __ movl(Address(rbp,
+  __ movptr(Address(rbp,
                   -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
           rbx); // Make it walkable
 #else /* CC_INTERP */
   // This value is corrected by layout_activation_impl
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD );
-  __ movl(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
+  __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
 #endif /* CC_INTERP */
-  __ movl(sp_temp, rsp);                // pass to next frame
-  __ addl(rsi, 4);                      // Bump array pointer (sizes)
-  __ addl(rcx, 4);                      // Bump array pointer (pcs)
-  __ decrement(counter);                // decrement counter
+  __ movptr(sp_temp, rsp);              // pass to next frame
+  __ addptr(rsi, wordSize);             // Bump array pointer (sizes)
+  __ addptr(rcx, wordSize);             // Bump array pointer (pcs)
+  __ decrementl(counter);             // decrement counter
   __ jcc(Assembler::notZero, loop);
-  __ pushl(Address(rcx, 0));            // save final return address
+  __ pushptr(Address(rcx, 0));          // save final return address
 
   // Re-push self-frame
   __ enter();                           // save old & set new rbp,
@@ -2543,11 +2598,11 @@
   //  Return address and rbp, are in place
   // We'll push additional args later. Just allocate a full sized
   // register save area
-  __ subl(rsp, (frame_size_in_words-additional_words - 2) * wordSize);
+  __ subptr(rsp, (frame_size_in_words-additional_words - 2) * wordSize);
 
   // Restore frame locals after moving the frame
-  __ movl(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
-  __ movl(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
+  __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
+  __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
   __ fstp_d(Address(rsp, RegisterSaver::fpResultOffset()*wordSize));   // Pop float stack and store in local
   if( UseSSE>=2 ) __ movdbl(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
   if( UseSSE==1 ) __ movflt(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
@@ -2556,7 +2611,7 @@
 
   __ pushl(unpack_kind);                     // get the unpack_kind value
   __ get_thread(rcx);
-  __ pushl(rcx);
+  __ push(rcx);
 
   // set last_Java_sp, last_Java_fp
   __ set_last_Java_frame(rcx, noreg, rbp, NULL);
@@ -2569,14 +2624,14 @@
   oop_maps->add_gc_map( __ pc()-start, new OopMap( frame_size_in_words, 0 ));
 
   // rax, contains the return result type
-  __ pushl(rax);
+  __ push(rax);
 
   __ get_thread(rcx);
   __ reset_last_Java_frame(rcx, false, false);
 
   // Collect return values
-  __ movl(rax,Address(rsp, (RegisterSaver::raxOffset() + additional_words + 1)*wordSize));
-  __ movl(rdx,Address(rsp, (RegisterSaver::rdxOffset() + additional_words + 1)*wordSize));
+  __ movptr(rax,Address(rsp, (RegisterSaver::raxOffset() + additional_words + 1)*wordSize));
+  __ movptr(rdx,Address(rsp, (RegisterSaver::rdxOffset() + additional_words + 1)*wordSize));
 
   // Clear floating point stack before returning to interpreter
   __ empty_FPU_stack();
@@ -2637,12 +2692,12 @@
 
   address start = __ pc();
   // Push self-frame.
-  __ subl(rsp, return_off*wordSize);     // Epilog!
+  __ subptr(rsp, return_off*wordSize);     // Epilog!
 
   // rbp, is an implicitly saved callee saved register (i.e. the calling
   // convention will save restore it in prolog/epilog) Other than that
   // there are no callee save registers no that adapter frames are gone.
-  __ movl(Address(rsp, rbp_off*wordSize),rbp);
+  __ movptr(Address(rsp, rbp_off*wordSize), rbp);
 
   // Clear the floating point exception stack
   __ empty_FPU_stack();
@@ -2654,7 +2709,7 @@
   // Call C code.  Need thread but NOT official VM entry
   // crud.  We cannot block on this call, no GC can happen.  Call should
   // capture callee-saved registers as well as return values.
-  __ movl(Address(rsp, arg0_off*wordSize),rdx);
+  __ movptr(Address(rsp, arg0_off*wordSize), rdx);
   // argument already in ECX
   __ movl(Address(rsp, arg1_off*wordSize),rcx);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
@@ -2671,7 +2726,7 @@
   __ reset_last_Java_frame(rcx, false, false);
 
   // Load UnrollBlock into EDI
-  __ movl(rdi, rax);
+  __ movptr(rdi, rax);
 
   // Pop all the frames we must move/replace.
   //
@@ -2681,10 +2736,11 @@
   // 3: caller of deopting frame (could be compiled/interpreted).
 
   // Pop self-frame.  We have no frame, and must rely only on EAX and ESP.
-  __ addl(rsp,(framesize-1)*wordSize);     // Epilog!
+  __ addptr(rsp,(framesize-1)*wordSize);     // Epilog!
 
   // Pop deoptimized frame
-  __ addl(rsp,Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
+  __ movl2ptr(rcx, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
+  __ addptr(rsp, rcx);
 
   // sp should be pointing at the return address to the caller (3)
 
@@ -2698,10 +2754,10 @@
   // Load array of frame pcs into ECX
   __ movl(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
 
-  __ popl(rsi); // trash the pc
+  __ pop(rsi); // trash the pc
 
   // Load array of frame sizes into ESI
-  __ movl(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
+  __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
 
   Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
 
@@ -2709,7 +2765,7 @@
   __ movl(counter, rbx);
 
   // Pick up the initial fp we should save
-  __ movl(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
+  __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
 
   // Now adjust the caller's stack to make up for the extra locals
   // but record the original sp so that we can save it in the skeletal interpreter
@@ -2717,47 +2773,48 @@
   // value and not the "real" sp value.
 
   Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
-  __ movl(sp_temp, rsp);
-  __ subl(rsp, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
+  __ movptr(sp_temp, rsp);
+  __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
+  __ subptr(rsp, rbx);
 
   // Push interpreter frames in a loop
   Label loop;
   __ bind(loop);
-  __ movl(rbx, Address(rsi, 0));        // Load frame size
+  __ movptr(rbx, Address(rsi, 0));      // Load frame size
 #ifdef CC_INTERP
-  __ subl(rbx, 4*wordSize);             // we'll push pc and ebp by hand and
+  __ subptr(rbx, 4*wordSize);           // we'll push pc and ebp by hand and
 #ifdef ASSERT
-  __ pushl(0xDEADDEAD);                 // Make a recognizable pattern
-  __ pushl(0xDEADDEAD);                 // (parm to RecursiveInterpreter...)
+  __ push(0xDEADDEAD);                  // Make a recognizable pattern
+  __ push(0xDEADDEAD);                  // (parm to RecursiveInterpreter...)
 #else /* ASSERT */
-  __ subl(rsp, 2*wordSize);             // skip the "static long no_param"
+  __ subptr(rsp, 2*wordSize);           // skip the "static long no_param"
 #endif /* ASSERT */
 #else /* CC_INTERP */
-  __ subl(rbx, 2*wordSize);             // we'll push pc and rbp, by hand
+  __ subptr(rbx, 2*wordSize);           // we'll push pc and rbp, by hand
 #endif /* CC_INTERP */
-  __ pushl(Address(rcx, 0));            // save return address
+  __ pushptr(Address(rcx, 0));          // save return address
   __ enter();                           // save old & set new rbp,
-  __ subl(rsp, rbx);                    // Prolog!
-  __ movl(rbx, sp_temp);                // sender's sp
+  __ subptr(rsp, rbx);                  // Prolog!
+  __ movptr(rbx, sp_temp);              // sender's sp
 #ifdef CC_INTERP
-  __ movl(Address(rbp,
+  __ movptr(Address(rbp,
                   -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
           rbx); // Make it walkable
 #else /* CC_INTERP */
   // This value is corrected by layout_activation_impl
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD );
-  __ movl(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
+  __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
 #endif /* CC_INTERP */
-  __ movl(sp_temp, rsp);                // pass to next frame
-  __ addl(rsi, 4);                      // Bump array pointer (sizes)
-  __ addl(rcx, 4);                      // Bump array pointer (pcs)
-  __ decrement(counter);                // decrement counter
+  __ movptr(sp_temp, rsp);              // pass to next frame
+  __ addptr(rsi, wordSize);             // Bump array pointer (sizes)
+  __ addptr(rcx, wordSize);             // Bump array pointer (pcs)
+  __ decrementl(counter);             // decrement counter
   __ jcc(Assembler::notZero, loop);
-  __ pushl(Address(rcx, 0));            // save final return address
+  __ pushptr(Address(rcx, 0));            // save final return address
 
   // Re-push self-frame
   __ enter();                           // save old & set new rbp,
-  __ subl(rsp, (framesize-2) * wordSize);   // Prolog!
+  __ subptr(rsp, (framesize-2) * wordSize);   // Prolog!
 
 
   // set last_Java_sp, last_Java_fp
@@ -2767,7 +2824,7 @@
   // Call C code.  Need thread but NOT official VM entry
   // crud.  We cannot block on this call, no GC can happen.  Call should
   // restore return values to their stack-slots with the new SP.
-  __ movl(Address(rsp,arg0_off*wordSize),rdi);
+  __ movptr(Address(rsp,arg0_off*wordSize),rdi);
   __ movl(Address(rsp,arg1_off*wordSize), Deoptimization::Unpack_uncommon_trap);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
   // Set an oopmap for the call site
@@ -2824,7 +2881,7 @@
   // Otherwise we push space for a return address that the safepoint
   // handler will install later to make the stack walking sensible.
   if( !cause_return )
-    __ pushl(rbx);                // Make room for return address (or push it again)
+    __ push(rbx);                // Make room for return address (or push it again)
 
   map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
 
@@ -2834,13 +2891,13 @@
 
   // Push thread argument and setup last_Java_sp
   __ get_thread(java_thread);
-  __ pushl(java_thread);
+  __ push(java_thread);
   __ set_last_Java_frame(java_thread, noreg, noreg, NULL);
 
   // if this was not a poll_return then we need to correct the return address now.
   if( !cause_return ) {
-    __ movl(rax, Address(java_thread, JavaThread::saved_exception_pc_offset()));
-    __ movl(Address(rbp, wordSize), rax);
+    __ movptr(rax, Address(java_thread, JavaThread::saved_exception_pc_offset()));
+    __ movptr(Address(rbp, wordSize), rax);
   }
 
   // do the call
@@ -2854,7 +2911,7 @@
   oop_maps->add_gc_map( __ pc() - start, map);
 
   // Discard arg
-  __ popl(rcx);
+  __ pop(rcx);
 
   Label noException;
 
@@ -2862,7 +2919,7 @@
   __ get_thread(java_thread);
   __ reset_last_Java_frame(java_thread, false, false);
 
-  __ cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
+  __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
   __ jcc(Assembler::equal, noException);
 
   // Exception pending
@@ -2919,7 +2976,7 @@
   const Register thread = rdi;
   __ get_thread(rdi);
 
-  __ pushl(thread);
+  __ push(thread);
   __ set_last_Java_frame(thread, noreg, rbp, NULL);
 
   __ call(RuntimeAddress(destination));
@@ -2933,20 +2990,20 @@
 
   // rax, contains the address we are going to jump to assuming no exception got installed
 
-  __ addl(rsp, wordSize);
+  __ addptr(rsp, wordSize);
 
   // clear last_Java_sp
   __ reset_last_Java_frame(thread, true, false);
   // check for pending exceptions
   Label pending;
-  __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+  __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, pending);
 
   // get the returned methodOop
-  __ movl(rbx, Address(thread, JavaThread::vm_result_offset()));
-  __ movl(Address(rsp, RegisterSaver::rbx_offset() * wordSize), rbx);
-
-  __ movl(Address(rsp, RegisterSaver::rax_offset() * wordSize), rax);
+  __ movptr(rbx, Address(thread, JavaThread::vm_result_offset()));
+  __ movptr(Address(rsp, RegisterSaver::rbx_offset() * wordSize), rbx);
+
+  __ movptr(Address(rsp, RegisterSaver::rax_offset() * wordSize), rax);
 
   RegisterSaver::restore_live_registers(masm);
 
@@ -2963,8 +3020,8 @@
   // exception pending => remove activation and forward to exception handler
 
   __ get_thread(thread);
-  __ movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
-  __ movl(rax, Address(thread, Thread::pending_exception_offset()));
+  __ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+  __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
   __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
 
   // -------------
--- a/hotspot/src/cpu/x86/vm/sharedRuntime_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/sharedRuntime_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -120,6 +120,7 @@
   // values on its own
 
   static int rax_offset_in_bytes(void)    { return BytesPerInt * rax_off; }
+  static int rdx_offset_in_bytes(void)    { return BytesPerInt * rdx_off; }
   static int rbx_offset_in_bytes(void)    { return BytesPerInt * rbx_off; }
   static int xmm0_offset_in_bytes(void)   { return BytesPerInt * xmm0_off; }
   static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
@@ -152,7 +153,7 @@
   __ push_CPU_state(); // Push a multiple of 16 bytes
   if (frame::arg_reg_save_area_bytes != 0) {
     // Allocate argument register save area
-    __ subq(rsp, frame::arg_reg_save_area_bytes);
+    __ subptr(rsp, frame::arg_reg_save_area_bytes);
   }
 
   // Set an oopmap for the call site.  This oopmap will map all
@@ -266,12 +267,12 @@
 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
   if (frame::arg_reg_save_area_bytes != 0) {
     // Pop arg register save area
-    __ addq(rsp, frame::arg_reg_save_area_bytes);
+    __ addptr(rsp, frame::arg_reg_save_area_bytes);
   }
   // Recover CPU state
   __ pop_CPU_state();
   // Get the rbp described implicitly by the calling convention (no oopMap)
-  __ popq(rbp);
+  __ pop(rbp);
 }
 
 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
@@ -285,9 +286,11 @@
   // Restore fp result register
   __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
   // Restore integer result register
-  __ movq(rax, Address(rsp, rax_offset_in_bytes()));
+  __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
+  __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
+
   // Pop all of the register save are off the stack except the return address
-  __ addq(rsp, return_offset_in_bytes());
+  __ addptr(rsp, return_offset_in_bytes());
 }
 
 // The java_calling_convention describes stack locations as ideal slots on
@@ -407,18 +410,18 @@
 static void patch_callers_callsite(MacroAssembler *masm) {
   Label L;
   __ verify_oop(rbx);
-  __ cmpq(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int)NULL_WORD);
+  __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
   __ jcc(Assembler::equal, L);
 
   // Save the current stack pointer
-  __ movq(r13, rsp);
+  __ mov(r13, rsp);
   // Schedule the branch target address early.
   // Call into the VM to patch the caller, then jump to compiled callee
   // rax isn't live so capture return address while we easily can
-  __ movq(rax, Address(rsp, 0));
+  __ movptr(rax, Address(rsp, 0));
 
   // align stack so push_CPU_state doesn't fault
-  __ andq(rsp, -(StackAlignmentInBytes));
+  __ andptr(rsp, -(StackAlignmentInBytes));
   __ push_CPU_state();
 
 
@@ -430,20 +433,20 @@
 
   // Allocate argument register save area
   if (frame::arg_reg_save_area_bytes != 0) {
-    __ subq(rsp, frame::arg_reg_save_area_bytes);
+    __ subptr(rsp, frame::arg_reg_save_area_bytes);
   }
-  __ movq(c_rarg0, rbx);
-  __ movq(c_rarg1, rax);
+  __ mov(c_rarg0, rbx);
+  __ mov(c_rarg1, rax);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
 
   // De-allocate argument register save area
   if (frame::arg_reg_save_area_bytes != 0) {
-    __ addq(rsp, frame::arg_reg_save_area_bytes);
+    __ addptr(rsp, frame::arg_reg_save_area_bytes);
   }
 
   __ pop_CPU_state();
   // restore sp
-  __ movq(rsp, r13);
+  __ mov(rsp, r13);
   __ bind(L);
 }
 
@@ -452,13 +455,13 @@
   if (TaggedStackInterpreter) {
     int tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(0);
     if (sig == T_OBJECT || sig == T_ARRAY) {
-      __ mov64(Address(rsp, tag_offset), frame::TagReference);
+      __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagReference);
     } else if (sig == T_LONG || sig == T_DOUBLE) {
       int next_tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(1);
-      __ mov64(Address(rsp, next_tag_offset), frame::TagValue);
-      __ mov64(Address(rsp, tag_offset), frame::TagValue);
+      __ movptr(Address(rsp, next_tag_offset), (int32_t) frame::TagValue);
+      __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
     } else {
-      __ mov64(Address(rsp, tag_offset), frame::TagValue);
+      __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
     }
   }
 }
@@ -490,15 +493,15 @@
   extraspace = round_to(extraspace, 2*wordSize);
 
   // Get return address
-  __ popq(rax);
+  __ pop(rax);
 
   // set senderSP value
-  __ movq(r13, rsp);
-
-  __ subq(rsp, extraspace);
+  __ mov(r13, rsp);
+
+  __ subptr(rsp, extraspace);
 
   // Store the return address in the expected location
-  __ movq(Address(rsp, 0), rax);
+  __ movptr(Address(rsp, 0), rax);
 
   // Now write the args into the outgoing interpreter space
   for (int i = 0; i < total_args_passed; i++) {
@@ -537,7 +540,7 @@
       if (!r_2->is_valid()) {
         // sign extend??
         __ movl(rax, Address(rsp, ld_off));
-        __ movq(Address(rsp, st_off), rax);
+        __ movptr(Address(rsp, st_off), rax);
         tag_stack(masm, sig_bt[i], st_off);
 
       } else {
@@ -553,7 +556,7 @@
 #ifdef ASSERT
           // Overwrite the unused slot with known junk
           __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
-          __ movq(Address(rsp, st_off), rax);
+          __ movptr(Address(rsp, st_off), rax);
 #endif /* ASSERT */
           tag_stack(masm, sig_bt[i], next_off);
         } else {
@@ -576,12 +579,12 @@
 #ifdef ASSERT
           // Overwrite the unused slot with known junk
           __ mov64(rax, CONST64(0xdeadffffdeadaaab));
-          __ movq(Address(rsp, st_off), rax);
+          __ movptr(Address(rsp, st_off), rax);
 #endif /* ASSERT */
           __ movq(Address(rsp, next_off), r);
           tag_stack(masm, sig_bt[i], next_off);
         } else {
-          __ movq(Address(rsp, st_off), r);
+          __ movptr(Address(rsp, st_off), r);
           tag_stack(masm, sig_bt[i], st_off);
         }
       }
@@ -595,7 +598,7 @@
 #ifdef ASSERT
         // Overwrite the unused slot with known junk
         __ mov64(rax, CONST64(0xdeadffffdeadaaac));
-        __ movq(Address(rsp, st_off), rax);
+        __ movptr(Address(rsp, st_off), rax);
 #endif /* ASSERT */
         __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
         tag_stack(masm, sig_bt[i], next_off);
@@ -604,7 +607,7 @@
   }
 
   // Schedule the branch target address early.
-  __ movq(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
+  __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
   __ jmp(rcx);
 }
 
@@ -631,7 +634,7 @@
   // save code can segv when fxsave instructions find improperly
   // aligned stack pointer.
 
-  __ movq(rax, Address(rsp, 0));
+  __ movptr(rax, Address(rsp, 0));
 
   // Cut-out for having no stack args.  Since up to 2 int/oop args are passed
   // in registers, we will occasionally have no stack args.
@@ -645,20 +648,20 @@
     comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
     // Round up to miminum stack alignment, in wordSize
     comp_words_on_stack = round_to(comp_words_on_stack, 2);
-    __ subq(rsp, comp_words_on_stack * wordSize);
+    __ subptr(rsp, comp_words_on_stack * wordSize);
   }
 
 
   // Ensure compiled code always sees stack at proper alignment
-  __ andq(rsp, -16);
+  __ andptr(rsp, -16);
 
   // push the return address and misalign the stack that youngest frame always sees
   // as far as the placement of the call instruction
-  __ pushq(rax);
+  __ push(rax);
 
   // Will jump to the compiled code just as if compiled code was doing it.
   // Pre-load the register-jump target early, to schedule it better.
-  __ movq(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
+  __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
 
   // Now generate the shuffle code.  Pick up all register args and move the
   // rest through the floating point stack top.
@@ -697,7 +700,7 @@
       if (!r_2->is_valid()) {
         // sign extend???
         __ movl(rax, Address(r13, ld_off));
-        __ movq(Address(rsp, st_off), rax);
+        __ movptr(Address(rsp, st_off), rax);
       } else {
         //
         // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
@@ -751,12 +754,12 @@
   // is possible. So we stash the desired callee in the thread
   // and the vm will find there should this case occur.
 
-  __ movq(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
+  __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
 
   // put methodOop where a c2i would expect should we end up there
   // only needed becaus eof c2 resolve stubs return methodOop as a result in
   // rax
-  __ movq(rax, rbx);
+  __ mov(rax, rbx);
   __ jmp(r11);
 }
 
@@ -792,8 +795,8 @@
     __ load_klass(temp, receiver);
     __ verify_oop(temp);
 
-    __ cmpq(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
-    __ movq(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
+    __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
+    __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
     __ jcc(Assembler::equal, ok);
     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 
@@ -801,7 +804,7 @@
     // Method might have been compiled since the call site was patched to
     // interpreted if that is the case treat it as a miss so we can get
     // the call site corrected.
-    __ cmpq(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int)NULL_WORD);
+    __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, skip_fixup);
     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
   }
@@ -980,10 +983,10 @@
       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
     }
 
-    __ cmpq(Address(rbp, reg2offset_in(src.first())), (int)NULL_WORD);
-    __ leaq(rHandle, Address(rbp, reg2offset_in(src.first())));
+    __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
+    __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
     // conditionally move a NULL
-    __ cmovq(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
+    __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
   } else {
 
     // Oop is in an a register we must store it to the space we reserve
@@ -1011,20 +1014,20 @@
 
     map->set_oop(VMRegImpl::stack2reg(oop_slot));
     // Store oop in handle area, may be NULL
-    __ movq(Address(rsp, offset), rOop);
+    __ movptr(Address(rsp, offset), rOop);
     if (is_receiver) {
       *receiver_offset = offset;
     }
 
-    __ cmpq(rOop, (int)NULL);
-    __ leaq(rHandle, Address(rsp, offset));
+    __ cmpptr(rOop, (int32_t)NULL_WORD);
+    __ lea(rHandle, Address(rsp, offset));
     // conditionally move a NULL from the handle area where it was just stored
-    __ cmovq(Assembler::equal, rHandle, Address(rsp, offset));
+    __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
   }
 
   // If arg is on the stack then place it otherwise it is already in correct reg.
   if (dst.first()->is_stack()) {
-    __ movq(Address(rsp, reg2offset_out(dst.first())), rHandle);
+    __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
   }
 }
 
@@ -1039,7 +1042,7 @@
   if (src.first()->is_stack()) {
     if (dst.first()->is_stack()) {
       __ movl(rax, Address(rbp, reg2offset_in(src.first())));
-      __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
+      __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
     } else {
       // stack to reg
       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
@@ -1068,7 +1071,7 @@
   if (src.is_single_phys_reg() ) {
     if (dst.is_single_phys_reg()) {
       if (dst.first() != src.first()) {
-        __ movq(dst.first()->as_Register(), src.first()->as_Register());
+        __ mov(dst.first()->as_Register(), src.first()->as_Register());
       }
     } else {
       assert(dst.is_single_reg(), "not a stack pair");
@@ -1124,7 +1127,7 @@
     break;
   case T_VOID:  break;
   default: {
-    __ movq(Address(rbp, -wordSize), rax);
+    __ movptr(Address(rbp, -wordSize), rax);
     }
   }
 }
@@ -1141,7 +1144,7 @@
     break;
   case T_VOID:  break;
   default: {
-    __ movq(rax, Address(rbp, -wordSize));
+    __ movptr(rax, Address(rbp, -wordSize));
     }
   }
 }
@@ -1149,9 +1152,9 @@
 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
     for ( int i = first_arg ; i < arg_count ; i++ ) {
       if (args[i].first()->is_Register()) {
-        __ pushq(args[i].first()->as_Register());
+        __ push(args[i].first()->as_Register());
       } else if (args[i].first()->is_XMMRegister()) {
-        __ subq(rsp, 2*wordSize);
+        __ subptr(rsp, 2*wordSize);
         __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
       }
     }
@@ -1160,10 +1163,10 @@
 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
     for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
       if (args[i].first()->is_Register()) {
-        __ popq(args[i].first()->as_Register());
+        __ pop(args[i].first()->as_Register());
       } else if (args[i].first()->is_XMMRegister()) {
         __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
-        __ addq(rsp, 2*wordSize);
+        __ addptr(rsp, 2*wordSize);
       }
     }
 }
@@ -1303,16 +1306,16 @@
   Label exception_pending;
 
   __ verify_oop(receiver);
-  __ pushq(tmp); // spill (any other registers free here???)
+  __ push(tmp); // spill (any other registers free here???)
   __ load_klass(tmp, receiver);
   __ cmpq(ic_reg, tmp);
   __ jcc(Assembler::equal, ok);
 
-  __ popq(tmp);
+  __ pop(tmp);
   __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 
   __ bind(ok);
-  __ popq(tmp);
+  __ pop(tmp);
 
   // Verified entry point must be aligned
   __ align(8);
@@ -1335,7 +1338,7 @@
   // Generate a new frame for the wrapper.
   __ enter();
   // -2 because return address is already present and so is saved rbp
-  __ subq(rsp, stack_size - 2*wordSize);
+  __ subptr(rsp, stack_size - 2*wordSize);
 
     // Frame is now completed as far as size and linkage.
 
@@ -1344,9 +1347,9 @@
 #ifdef ASSERT
     {
       Label L;
-      __ movq(rax, rsp);
-      __ andq(rax, -16); // must be 16 byte boundry (see amd64 ABI)
-      __ cmpq(rax, rsp);
+      __ mov(rax, rsp);
+      __ andptr(rax, -16); // must be 16 byte boundry (see amd64 ABI)
+      __ cmpptr(rax, rsp);
       __ jcc(Assembler::equal, L);
       __ stop("improperly aligned stack");
       __ bind(L);
@@ -1467,13 +1470,13 @@
     __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
 
     // Now handlize the static class mirror it's known not-null.
-    __ movq(Address(rsp, klass_offset), oop_handle_reg);
+    __ movptr(Address(rsp, klass_offset), oop_handle_reg);
     map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
 
     // Now get the handle
-    __ leaq(oop_handle_reg, Address(rsp, klass_offset));
+    __ lea(oop_handle_reg, Address(rsp, klass_offset));
     // store the klass handle as second argument
-    __ movq(c_rarg1, oop_handle_reg);
+    __ movptr(c_rarg1, oop_handle_reg);
     // and protect the arg if we must spill
     c_arg--;
   }
@@ -1521,14 +1524,14 @@
     const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
 
     // Get the handle (the 2nd argument)
-    __ movq(oop_handle_reg, c_rarg1);
+    __ mov(oop_handle_reg, c_rarg1);
 
     // Get address of the box
 
-    __ leaq(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
+    __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
 
     // Load the oop from the handle
-    __ movq(obj_reg, Address(oop_handle_reg, 0));
+    __ movptr(obj_reg, Address(oop_handle_reg, 0));
 
     if (UseBiasedLocking) {
       __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
@@ -1538,17 +1541,17 @@
     __ movl(swap_reg, 1);
 
     // Load (object->mark() | 1) into swap_reg %rax
-    __ orq(swap_reg, Address(obj_reg, 0));
+    __ orptr(swap_reg, Address(obj_reg, 0));
 
     // Save (object->mark() | 1) into BasicLock's displaced header
-    __ movq(Address(lock_reg, mark_word_offset), swap_reg);
+    __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
 
     if (os::is_MP()) {
       __ lock();
     }
 
     // src -> dest iff dest == rax else rax <- dest
-    __ cmpxchgq(lock_reg, Address(obj_reg, 0));
+    __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
     __ jcc(Assembler::equal, lock_done);
 
     // Hmm should this move to the slow path code area???
@@ -1562,11 +1565,11 @@
     // least significant 2 bits clear.
     // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
 
-    __ subq(swap_reg, rsp);
-    __ andq(swap_reg, 3 - os::vm_page_size());
+    __ subptr(swap_reg, rsp);
+    __ andptr(swap_reg, 3 - os::vm_page_size());
 
     // Save the test result, for recursive case, the result is zero
-    __ movq(Address(lock_reg, mark_word_offset), swap_reg);
+    __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
     __ jcc(Assembler::notEqual, slow_path_lock);
 
     // Slow path will re-enter here
@@ -1580,21 +1583,21 @@
 
   // get JNIEnv* which is first argument to native
 
-  __ leaq(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
+  __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
 
   // Now set thread in native
-  __ mov64(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
+  __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
 
   __ call(RuntimeAddress(method->native_function()));
 
     // Either restore the MXCSR register after returning from the JNI Call
     // or verify that it wasn't changed.
     if (RestoreMXCSROnJNICalls) {
-      __ ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
+      __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
 
     }
     else if (CheckJNICalls ) {
-      __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::amd64::verify_mxcsr_entry())));
+      __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
     }
 
 
@@ -1624,7 +1627,7 @@
   //     VM thread changes sync state to synchronizing and suspends threads for GC.
   //     Thread A is resumed to finish this native method, but doesn't block here since it
   //     didn't see any synchronization is progress, and escapes.
-  __ mov64(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
+  __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
 
   if(os::is_MP()) {
     if (UseMembar) {
@@ -1662,12 +1665,12 @@
     // by hand.
     //
     save_native_result(masm, ret_type, stack_slots);
-    __ movq(c_rarg0, r15_thread);
-    __ movq(r12, rsp); // remember sp
-    __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-    __ andq(rsp, -16); // align stack as required by ABI
+    __ mov(c_rarg0, r15_thread);
+    __ mov(r12, rsp); // remember sp
+    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rsp, -16); // align stack as required by ABI
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
-    __ movq(rsp, r12); // restore sp
+    __ mov(rsp, r12); // restore sp
     __ reinit_heapbase();
     // Restore any method result value
     restore_native_result(masm, ret_type, stack_slots);
@@ -1691,7 +1694,7 @@
   if (method->is_synchronized()) {
 
     // Get locked oop from the handle we passed to jni
-    __ movq(obj_reg, Address(oop_handle_reg, 0));
+    __ movptr(obj_reg, Address(oop_handle_reg, 0));
 
     Label done;
 
@@ -1701,7 +1704,7 @@
 
     // Simple recursive lock?
 
-    __ cmpq(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int)NULL_WORD);
+    __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, done);
 
     // Must save rax if if it is live now because cmpxchg must use it
@@ -1711,15 +1714,15 @@
 
 
     // get address of the stack lock
-    __ leaq(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
+    __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
     //  get old displaced header
-    __ movq(old_hdr, Address(rax, 0));
+    __ movptr(old_hdr, Address(rax, 0));
 
     // Atomic swap old header if oop still contains the stack lock
     if (os::is_MP()) {
       __ lock();
     }
-    __ cmpxchgq(old_hdr, Address(obj_reg, 0));
+    __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
     __ jcc(Assembler::notEqual, slow_path_unlock);
 
     // slow path re-enters here
@@ -1746,23 +1749,23 @@
   // Unpack oop result
   if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
       Label L;
-      __ testq(rax, rax);
+      __ testptr(rax, rax);
       __ jcc(Assembler::zero, L);
-      __ movq(rax, Address(rax, 0));
+      __ movptr(rax, Address(rax, 0));
       __ bind(L);
       __ verify_oop(rax);
   }
 
   // reset handle block
-  __ movq(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
-  __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int)NULL_WORD);
+  __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
+  __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
 
   // pop our frame
 
   __ leave();
 
   // Any exception pending?
-  __ cmpq(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
+  __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, exception_pending);
 
   // Return
@@ -1790,9 +1793,9 @@
     // protect the args we've loaded
     save_args(masm, total_c_args, c_arg, out_regs);
 
-    __ movq(c_rarg0, obj_reg);
-    __ movq(c_rarg1, lock_reg);
-    __ movq(c_rarg2, r15_thread);
+    __ mov(c_rarg0, obj_reg);
+    __ mov(c_rarg1, lock_reg);
+    __ mov(c_rarg2, r15_thread);
 
     // Not a leaf but we have last_Java_frame setup as we want
     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
@@ -1800,7 +1803,7 @@
 
 #ifdef ASSERT
     { Label L;
-    __ cmpq(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
+    __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, L);
     __ stop("no pending exception allowed on exit from monitorenter");
     __ bind(L);
@@ -1820,32 +1823,32 @@
       save_native_result(masm, ret_type, stack_slots);
     }
 
-    __ leaq(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
-
-    __ movq(c_rarg0, obj_reg);
-    __ movq(r12, rsp); // remember sp
-    __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-    __ andq(rsp, -16); // align stack as required by ABI
+    __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
+
+    __ mov(c_rarg0, obj_reg);
+    __ mov(r12, rsp); // remember sp
+    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rsp, -16); // align stack as required by ABI
 
     // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
     // NOTE that obj_reg == rbx currently
-    __ movq(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
-    __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
+    __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
+    __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
 
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
-    __ movq(rsp, r12); // restore sp
+    __ mov(rsp, r12); // restore sp
     __ reinit_heapbase();
 #ifdef ASSERT
     {
       Label L;
-      __ cmpq(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
+      __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
       __ jcc(Assembler::equal, L);
       __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
       __ bind(L);
     }
 #endif /* ASSERT */
 
-    __ movq(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
+    __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
 
     if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
       restore_native_result(masm, ret_type, stack_slots);
@@ -1860,11 +1863,11 @@
 
   __ bind(reguard);
   save_native_result(masm, ret_type, stack_slots);
-  __ movq(r12, rsp); // remember sp
-  __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-  __ andq(rsp, -16); // align stack as required by ABI
+  __ mov(r12, rsp); // remember sp
+  __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+  __ andptr(rsp, -16); // align stack as required by ABI
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
-  __ movq(rsp, r12); // restore sp
+  __ mov(rsp, r12); // restore sp
   __ reinit_heapbase();
   restore_native_result(masm, ret_type, stack_slots);
   // and continue
@@ -2574,19 +2577,74 @@
   // Normal deoptimization.  Save exec mode for unpack_frames.
   __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
   __ jmp(cont);
+
+  int reexecute_offset = __ pc() - start;
+
+  // Reexecute case
+  // return address is the pc describes what bci to do re-execute at
+
+  // No need to update map as each call to save_live_registers will produce identical oopmap
+  (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
+
+  __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
+  __ jmp(cont);
+
   int exception_offset = __ pc() - start;
 
   // Prolog for exception case
 
-  // Push throwing pc as return address
-  __ pushq(rdx);
+  // all registers are dead at this entry point, except for rax, and
+  // rdx which contain the exception oop and exception pc
+  // respectively.  Set them in TLS and fall thru to the
+  // unpack_with_exception_in_tls entry point.
+
+  __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
+  __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
+
+  int exception_in_tls_offset = __ pc() - start;
+
+  // new implementation because exception oop is now passed in JavaThread
+
+  // Prolog for exception case
+  // All registers must be preserved because they might be used by LinearScan
+  // Exceptiop oop and throwing PC are passed in JavaThread
+  // tos: stack at point of call to method that threw the exception (i.e. only
+  // args are on the stack, no return address)
+
+  // make room on stack for the return address
+  // It will be patched later with the throwing pc. The correct value is not
+  // available now because loading it from memory would destroy registers.
+  __ push(0);
 
   // Save everything in sight.
   map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
 
+  // Now it is safe to overwrite any register
+
   // Deopt during an exception.  Save exec mode for unpack_frames.
   __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
 
+  // load throwing pc from JavaThread and patch it as the return address
+  // of the current frame. Then clear the field in JavaThread
+
+  __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
+  __ movptr(Address(rbp, wordSize), rdx);
+  __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
+
+#ifdef ASSERT
+  // verify that there is really an exception oop in JavaThread
+  __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
+  __ verify_oop(rax);
+
+  // verify that there is no pending exception
+  Label no_pending_exception;
+  __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
+  __ testptr(rax, rax);
+  __ jcc(Assembler::zero, no_pending_exception);
+  __ stop("must not have pending exception here");
+  __ bind(no_pending_exception);
+#endif
+
   __ bind(cont);
 
   // Call C code.  Need thread and this frame, but NOT official VM entry
@@ -2599,15 +2657,15 @@
   __ set_last_Java_frame(noreg, noreg, NULL);
 #ifdef ASSERT
   { Label L;
-    __ cmpq(Address(r15_thread,
+    __ cmpptr(Address(r15_thread,
                     JavaThread::last_Java_fp_offset()),
-            0);
+            (int32_t)0);
     __ jcc(Assembler::equal, L);
     __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
     __ bind(L);
   }
 #endif // ASSERT
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
 
   // Need to have an oopmap that tells fetch_unroll_info where to
@@ -2617,7 +2675,25 @@
   __ reset_last_Java_frame(false, false);
 
   // Load UnrollBlock* into rdi
-  __ movq(rdi, rax);
+  __ mov(rdi, rax);
+
+   Label noException;
+  __ cmpl(r12, Deoptimization::Unpack_exception);   // Was exception pending?
+  __ jcc(Assembler::notEqual, noException);
+  __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
+  // QQQ this is useless it was NULL above
+  __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
+  __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
+  __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
+
+  __ verify_oop(rax);
+
+  // Overwrite the result registers with the exception results.
+  __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
+  // I think this is useless
+  __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
+
+  __ bind(noException);
 
   // Only register save data is on the stack.
   // Now restore the result registers.  Everything else is either dead
@@ -2640,7 +2716,7 @@
 
   // Pop deoptimized frame
   __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
-  __ addq(rsp, rcx);
+  __ addptr(rsp, rcx);
 
   // rsp should be pointing at the return address to the caller (3)
 
@@ -2651,19 +2727,19 @@
   }
 
   // Load address of array of frame pcs into rcx
-  __ movq(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
+  __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
 
   // Trash the old pc
-  __ addq(rsp, wordSize);
+  __ addptr(rsp, wordSize);
 
   // Load address of array of frame sizes into rsi
-  __ movq(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
+  __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
 
   // Load counter into rdx
   __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
 
   // Pick up the initial fp we should save
-  __ movq(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
+  __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
 
   // Now adjust the caller's stack to make up for the extra locals
   // but record the original sp so that we can save it in the skeletal interpreter
@@ -2672,41 +2748,56 @@
 
   const Register sender_sp = r8;
 
-  __ movq(sender_sp, rsp);
+  __ mov(sender_sp, rsp);
   __ movl(rbx, Address(rdi,
                        Deoptimization::UnrollBlock::
                        caller_adjustment_offset_in_bytes()));
-  __ subq(rsp, rbx);
+  __ subptr(rsp, rbx);
 
   // Push interpreter frames in a loop
   Label loop;
   __ bind(loop);
-  __ movq(rbx, Address(rsi, 0));        // Load frame size
-  __ subq(rbx, 2*wordSize);             // We'll push pc and ebp by hand
-  __ pushq(Address(rcx, 0));            // Save return address
+  __ movptr(rbx, Address(rsi, 0));      // Load frame size
+#ifdef CC_INTERP
+  __ subptr(rbx, 4*wordSize);           // we'll push pc and ebp by hand and
+#ifdef ASSERT
+  __ push(0xDEADDEAD);                  // Make a recognizable pattern
+  __ push(0xDEADDEAD);
+#else /* ASSERT */
+  __ subptr(rsp, 2*wordSize);           // skip the "static long no_param"
+#endif /* ASSERT */
+#else
+  __ subptr(rbx, 2*wordSize);           // We'll push pc and ebp by hand
+#endif // CC_INTERP
+  __ pushptr(Address(rcx, 0));          // Save return address
   __ enter();                           // Save old & set new ebp
-  __ subq(rsp, rbx);                    // Prolog
-  __ movq(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
-          sender_sp);                   // Make it walkable
+  __ subptr(rsp, rbx);                  // Prolog
+#ifdef CC_INTERP
+  __ movptr(Address(rbp,
+                  -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
+            sender_sp); // Make it walkable
+#else /* CC_INTERP */
   // This value is corrected by layout_activation_impl
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int)NULL_WORD );
-  __ movq(sender_sp, rsp);              // Pass sender_sp to next frame
-  __ addq(rsi, wordSize);               // Bump array pointer (sizes)
-  __ addq(rcx, wordSize);               // Bump array pointer (pcs)
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
+  __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
+#endif /* CC_INTERP */
+  __ mov(sender_sp, rsp);               // Pass sender_sp to next frame
+  __ addptr(rsi, wordSize);             // Bump array pointer (sizes)
+  __ addptr(rcx, wordSize);             // Bump array pointer (pcs)
   __ decrementl(rdx);                   // Decrement counter
   __ jcc(Assembler::notZero, loop);
-  __ pushq(Address(rcx, 0));            // Save final return address
+  __ pushptr(Address(rcx, 0));          // Save final return address
 
   // Re-push self-frame
   __ enter();                           // Save old & set new ebp
 
   // Allocate a full sized register save area.
   // Return address and rbp are in place, so we allocate two less words.
-  __ subq(rsp, (frame_size_in_words - 2) * wordSize);
+  __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
 
   // Restore frame locals after moving the frame
   __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
-  __ movq(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
+  __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
 
   // Call C code.  Need thread but NOT official VM entry
   // crud.  We cannot block on this call, no GC can happen.  Call should
@@ -2717,7 +2808,7 @@
   // Use rbp because the frames look interpreted now
   __ set_last_Java_frame(noreg, rbp, NULL);
 
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ movl(c_rarg1, r14); // second arg: exec_mode
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
 
@@ -2729,7 +2820,9 @@
 
   // Collect return values
   __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
-  __ movq(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
+  __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
+  // I think this is useless (throwing pc?)
+  __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
 
   // Pop self-frame.
   __ leave();                           // Epilog
@@ -2740,7 +2833,8 @@
   // Make sure all code is generated
   masm->flush();
 
-  _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, 0, frame_size_in_words);
+  _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
+  _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
 }
 
 #ifdef COMPILER2
@@ -2758,10 +2852,10 @@
 
   // Push self-frame.  We get here with a return address on the
   // stack, so rsp is 8-byte aligned until we allocate our frame.
-  __ subq(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
+  __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
 
   // No callee saved registers. rbp is assumed implicitly saved
-  __ movq(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
+  __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
 
   // compiler left unloaded_class_index in j_rarg0 move to where the
   // runtime expects it.
@@ -2776,7 +2870,7 @@
   //
   // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
 
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
 
   // Set an oopmap for the call site
@@ -2790,7 +2884,7 @@
   __ reset_last_Java_frame(false, false);
 
   // Load UnrollBlock* into rdi
-  __ movq(rdi, rax);
+  __ mov(rdi, rax);
 
   // Pop all the frames we must move/replace.
   //
@@ -2800,13 +2894,13 @@
   // 3: caller of deopting frame (could be compiled/interpreted).
 
   // Pop self-frame.  We have no frame, and must rely only on rax and rsp.
-  __ addq(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
+  __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
 
   // Pop deoptimized frame (int)
   __ movl(rcx, Address(rdi,
                        Deoptimization::UnrollBlock::
                        size_of_deoptimized_frame_offset_in_bytes()));
-  __ addq(rsp, rcx);
+  __ addptr(rsp, rcx);
 
   // rsp should be pointing at the return address to the caller (3)
 
@@ -2817,17 +2911,17 @@
   }
 
   // Load address of array of frame pcs into rcx (address*)
-  __ movq(rcx,
-          Address(rdi,
-                  Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
+  __ movptr(rcx,
+            Address(rdi,
+                    Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
 
   // Trash the return pc
-  __ addq(rsp, wordSize);
+  __ addptr(rsp, wordSize);
 
   // Load address of array of frame sizes into rsi (intptr_t*)
-  __ movq(rsi, Address(rdi,
-                       Deoptimization::UnrollBlock::
-                       frame_sizes_offset_in_bytes()));
+  __ movptr(rsi, Address(rdi,
+                         Deoptimization::UnrollBlock::
+                         frame_sizes_offset_in_bytes()));
 
   // Counter
   __ movl(rdx, Address(rdi,
@@ -2835,9 +2929,9 @@
                        number_of_frames_offset_in_bytes())); // (int)
 
   // Pick up the initial fp we should save
-  __ movq(rbp,
-          Address(rdi,
-                  Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
+  __ movptr(rbp,
+            Address(rdi,
+                    Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
 
   // Now adjust the caller's stack to make up for the extra locals but
   // record the original sp so that we can save it in the skeletal
@@ -2846,34 +2940,34 @@
 
   const Register sender_sp = r8;
 
-  __ movq(sender_sp, rsp);
+  __ mov(sender_sp, rsp);
   __ movl(rbx, Address(rdi,
                        Deoptimization::UnrollBlock::
                        caller_adjustment_offset_in_bytes())); // (int)
-  __ subq(rsp, rbx);
+  __ subptr(rsp, rbx);
 
   // Push interpreter frames in a loop
   Label loop;
   __ bind(loop);
-  __ movq(rbx, Address(rsi, 0)); // Load frame size
-  __ subq(rbx, 2 * wordSize); // We'll push pc and rbp by hand
-  __ pushq(Address(rcx, 0));  // Save return address
-  __ enter();                 // Save old & set new rbp
-  __ subq(rsp, rbx);          // Prolog
-  __ movq(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
-          sender_sp);         // Make it walkable
+  __ movptr(rbx, Address(rsi, 0)); // Load frame size
+  __ subptr(rbx, 2 * wordSize);    // We'll push pc and rbp by hand
+  __ pushptr(Address(rcx, 0));     // Save return address
+  __ enter();                      // Save old & set new rbp
+  __ subptr(rsp, rbx);             // Prolog
+  __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
+            sender_sp);            // Make it walkable
   // This value is corrected by layout_activation_impl
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int)NULL_WORD );
-  __ movq(sender_sp, rsp);    // Pass sender_sp to next frame
-  __ addq(rsi, wordSize);     // Bump array pointer (sizes)
-  __ addq(rcx, wordSize);     // Bump array pointer (pcs)
-  __ decrementl(rdx);         // Decrement counter
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
+  __ mov(sender_sp, rsp);          // Pass sender_sp to next frame
+  __ addptr(rsi, wordSize);        // Bump array pointer (sizes)
+  __ addptr(rcx, wordSize);        // Bump array pointer (pcs)
+  __ decrementl(rdx);              // Decrement counter
   __ jcc(Assembler::notZero, loop);
-  __ pushq(Address(rcx, 0)); // Save final return address
+  __ pushptr(Address(rcx, 0));     // Save final return address
 
   // Re-push self-frame
   __ enter();                 // Save old & set new rbp
-  __ subq(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
+  __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
                               // Prolog
 
   // Use rbp because the frames look interpreted now
@@ -2886,7 +2980,7 @@
   //
   // BasicType unpack_frames(JavaThread* thread, int exec_mode);
 
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
 
@@ -2933,7 +3027,7 @@
 
   // Make room for return address (or push it again)
   if (!cause_return) {
-    __ pushq(rbx);
+    __ push(rbx);
   }
 
   // Save registers, fpu state, and flags
@@ -2950,12 +3044,12 @@
 
   if (!cause_return) {
     // overwrite the dummy value we pushed on entry
-    __ movq(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
-    __ movq(Address(rbp, wordSize), c_rarg0);
+    __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
+    __ movptr(Address(rbp, wordSize), c_rarg0);
   }
 
   // Do the call
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ call(RuntimeAddress(call_ptr));
 
   // Set an oopmap for the call site.  This oopmap will map all
@@ -2969,7 +3063,7 @@
 
   __ reset_last_Java_frame(false, false);
 
-  __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int)NULL_WORD);
+  __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
   __ jcc(Assembler::equal, noException);
 
   // Exception pending
@@ -3023,7 +3117,7 @@
 
   __ set_last_Java_frame(noreg, noreg, NULL);
 
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
 
   __ call(RuntimeAddress(destination));
 
@@ -3040,14 +3134,14 @@
   __ reset_last_Java_frame(false, false);
   // check for pending exceptions
   Label pending;
-  __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int)NULL_WORD);
+  __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, pending);
 
   // get the returned methodOop
-  __ movq(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
-  __ movq(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
-
-  __ movq(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
+  __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
+  __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
+
+  __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
 
   RegisterSaver::restore_live_registers(masm);
 
@@ -3065,7 +3159,7 @@
 
   __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
 
-  __ movq(rax, Address(r15_thread, Thread::pending_exception_offset()));
+  __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
   __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
 
   // -------------
@@ -3154,8 +3248,8 @@
   address start = __ pc();
 
   // Exception pc is 'return address' for stack walker
-  __ pushq(rdx);
-  __ subq(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
+  __ push(rdx);
+  __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
 
   // Save callee-saved registers.  See x86_64.ad.
 
@@ -3163,14 +3257,14 @@
   // convention will save restore it in prolog/epilog) Other than that
   // there are no callee save registers now that adapter frames are gone.
 
-  __ movq(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
+  __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
 
   // Store exception in Thread object. We cannot pass any arguments to the
   // handle_exception call, since we do not want to make any assumption
   // about the size of the frame where the exception happened in.
   // c_rarg0 is either rdi (Linux) or rcx (Windows).
-  __ movq(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
-  __ movq(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
+  __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
+  __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
 
   // This call does all the hard work.  It checks if an exception handler
   // exists in the method.
@@ -3181,7 +3275,7 @@
   // address OptoRuntime::handle_exception_C(JavaThread* thread)
 
   __ set_last_Java_frame(noreg, noreg, NULL);
-  __ movq(c_rarg0, r15_thread);
+  __ mov(c_rarg0, r15_thread);
   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
 
   // Set an oopmap for the call site.  This oopmap will only be used if we
@@ -3202,20 +3296,20 @@
   // convention will save restore it in prolog/epilog) Other than that
   // there are no callee save registers no that adapter frames are gone.
 
-  __ movq(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
-
-  __ addq(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
-  __ popq(rdx);                  // No need for exception pc anymore
+  __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
+
+  __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
+  __ pop(rdx);                  // No need for exception pc anymore
 
   // rax: exception handler
 
   // We have a handler in rax (could be deopt blob).
-  __ movq(r8, rax);
+  __ mov(r8, rax);
 
   // Get the exception oop
-  __ movq(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
+  __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
   // Get the exception pc in case we are deoptimized
-  __ movq(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
+  __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
 #ifdef ASSERT
   __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
   __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
--- a/hotspot/src/cpu/x86/vm/stubGenerator_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubGenerator_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -30,6 +30,7 @@
 // see the comment in stubRoutines.hpp
 
 #define __ _masm->
+#define a__ ((Assembler*)_masm)->
 
 #ifdef PRODUCT
 #define BLOCK_COMMENT(str) /* nothing */
@@ -67,7 +68,7 @@
 #define inc_counter_np(counter) (0)
 #else
   void inc_counter_np_(int& counter) {
-    __ increment(ExternalAddress((address)&counter));
+    __ incrementl(ExternalAddress((address)&counter));
   }
 #define inc_counter_np(counter) \
   BLOCK_COMMENT("inc_counter " #counter); \
@@ -137,16 +138,16 @@
 
     // stub code
     __ enter();
-    __ movl(rcx, parameter_size);              // parameter counter
-    __ shll(rcx, Interpreter::logStackElementSize()); // convert parameter count to bytes
-    __ addl(rcx, locals_count_in_bytes);       // reserve space for register saves
-    __ subl(rsp, rcx);
-    __ andl(rsp, -(StackAlignmentInBytes));    // Align stack
+    __ movptr(rcx, parameter_size);              // parameter counter
+    __ shlptr(rcx, Interpreter::logStackElementSize()); // convert parameter count to bytes
+    __ addptr(rcx, locals_count_in_bytes);       // reserve space for register saves
+    __ subptr(rsp, rcx);
+    __ andptr(rsp, -(StackAlignmentInBytes));    // Align stack
 
     // save rdi, rsi, & rbx, according to C calling conventions
-    __ movl(saved_rdi, rdi);
-    __ movl(saved_rsi, rsi);
-    __ movl(saved_rbx, rbx);
+    __ movptr(saved_rdi, rdi);
+    __ movptr(saved_rsi, rsi);
+    __ movptr(saved_rbx, rbx);
     // save and initialize %mxcsr
     if (sse_save) {
       Label skip_ldmx;
@@ -166,8 +167,8 @@
 #ifdef ASSERT
     // make sure we have no pending exceptions
     { Label L;
-      __ movl(rcx, thread);
-      __ cmpl(Address(rcx, Thread::pending_exception_offset()), NULL_WORD);
+      __ movptr(rcx, thread);
+      __ cmpptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, L);
       __ stop("StubRoutines::call_stub: entered with pending exception");
       __ bind(L);
@@ -189,20 +190,20 @@
     // source is rdx[rcx: N-1..0]
     // dest   is rsp[rbx: 0..N-1]
 
-    __ movl(rdx, parameters);          // parameter pointer
-    __ xorl(rbx, rbx);
+    __ movptr(rdx, parameters);          // parameter pointer
+    __ xorptr(rbx, rbx);
 
     __ BIND(loop);
     if (TaggedStackInterpreter) {
-      __ movl(rax, Address(rdx, rcx, Interpreter::stackElementScale(),
+      __ movptr(rax, Address(rdx, rcx, Interpreter::stackElementScale(),
                       -2*wordSize));                          // get tag
-      __ movl(Address(rsp, rbx, Interpreter::stackElementScale(),
+      __ movptr(Address(rsp, rbx, Interpreter::stackElementScale(),
                       Interpreter::expr_tag_offset_in_bytes(0)), rax);     // store tag
     }
 
     // get parameter
-    __ movl(rax, Address(rdx, rcx, Interpreter::stackElementScale(), -wordSize));
-    __ movl(Address(rsp, rbx, Interpreter::stackElementScale(),
+    __ movptr(rax, Address(rdx, rcx, Interpreter::stackElementScale(), -wordSize));
+    __ movptr(Address(rsp, rbx, Interpreter::stackElementScale(),
                     Interpreter::expr_offset_in_bytes(0)), rax);          // store parameter
     __ increment(rbx);
     __ decrement(rcx);
@@ -210,9 +211,9 @@
 
     // call Java function
     __ BIND(parameters_done);
-    __ movl(rbx, method);              // get methodOop
-    __ movl(rax, entry_point);         // get entry_point
-    __ movl(rsi, rsp);                 // set sender sp
+    __ movptr(rbx, method);           // get methodOop
+    __ movptr(rax, entry_point);      // get entry_point
+    __ mov(rsi, rsp);                 // set sender sp
     BLOCK_COMMENT("call Java function");
     __ call(rax);
 
@@ -225,7 +226,7 @@
 
     // store result depending on type
     // (everything that is not T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
-    __ movl(rdi, result);
+    __ movptr(rdi, result);
     Label is_long, is_float, is_double, exit;
     __ movl(rsi, result_type);
     __ cmpl(rsi, T_LONG);
@@ -243,7 +244,7 @@
     __ verify_FPU(0, "generate_call_stub");
 
     // pop parameters
-    __ leal(rsp, rsp_after_call);
+    __ lea(rsp, rsp_after_call);
 
     // restore %mxcsr
     if (sse_save) {
@@ -251,13 +252,13 @@
     }
 
     // restore rdi, rsi and rbx,
-    __ movl(rbx, saved_rbx);
-    __ movl(rsi, saved_rsi);
-    __ movl(rdi, saved_rdi);
-    __ addl(rsp, 4*wordSize);
+    __ movptr(rbx, saved_rbx);
+    __ movptr(rsi, saved_rsi);
+    __ movptr(rdi, saved_rdi);
+    __ addptr(rsp, 4*wordSize);
 
     // return
-    __ popl(rbp);
+    __ pop(rbp);
     __ ret(0);
 
     // handle return types different from T_INT
@@ -291,7 +292,7 @@
     // return above that handles interpreter returns.
 
     BLOCK_COMMENT("call_stub_compiled_return:");
-    StubRoutines::i486::set_call_stub_compiled_return( __ pc());
+    StubRoutines::x86::set_call_stub_compiled_return( __ pc());
 
 #ifdef COMPILER2
     if (UseSSE >= 2) {
@@ -337,12 +338,12 @@
     address start = __ pc();
 
     // get thread directly
-    __ movl(rcx, thread);
+    __ movptr(rcx, thread);
 #ifdef ASSERT
     // verify that threads correspond
     { Label L;
       __ get_thread(rbx);
-      __ cmpl(rbx, rcx);
+      __ cmpptr(rbx, rcx);
       __ jcc(Assembler::equal, L);
       __ stop("StubRoutines::catch_exception: threads must correspond");
       __ bind(L);
@@ -350,7 +351,7 @@
 #endif
     // set pending exception
     __ verify_oop(rax);
-    __ movl(Address(rcx, Thread::pending_exception_offset()), rax          );
+    __ movptr(Address(rcx, Thread::pending_exception_offset()), rax          );
     __ lea(Address(rcx, Thread::exception_file_offset   ()),
            ExternalAddress((address)__FILE__));
     __ movl(Address(rcx, Thread::exception_line_offset   ()), __LINE__ );
@@ -389,7 +390,7 @@
     // make sure this code is only executed if there is a pending exception
     { Label L;
       __ get_thread(rcx);
-      __ cmpl(Address(rcx, Thread::pending_exception_offset()), NULL_WORD);
+      __ cmpptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
       __ jcc(Assembler::notEqual, L);
       __ stop("StubRoutines::forward exception: no pending exception (1)");
       __ bind(L);
@@ -397,21 +398,21 @@
 #endif
 
     // compute exception handler into rbx,
-    __ movl(rax, Address(rsp, 0));
+    __ movptr(rax, Address(rsp, 0));
     BLOCK_COMMENT("call exception_handler_for_return_address");
     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), rax);
-    __ movl(rbx, rax);
+    __ mov(rbx, rax);
 
     // setup rax, & rdx, remove return address & clear pending exception
     __ get_thread(rcx);
-    __ popl(rdx);
-    __ movl(rax, Address(rcx, Thread::pending_exception_offset()));
-    __ movl(Address(rcx, Thread::pending_exception_offset()), NULL_WORD);
+    __ pop(rdx);
+    __ movptr(rax, Address(rcx, Thread::pending_exception_offset()));
+    __ movptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
 
 #ifdef ASSERT
     // make sure exception is set
     { Label L;
-      __ testl(rax, rax);
+      __ testptr(rax, rax);
       __ jcc(Assembler::notEqual, L);
       __ stop("StubRoutines::forward exception: no pending exception (2)");
       __ bind(L);
@@ -447,13 +448,13 @@
     StubCodeMark mark(this, "StubRoutines", "atomic_xchg");
     address start = __ pc();
 
-    __ pushl(rdx);
+    __ push(rdx);
     Address exchange(rsp, 2 * wordSize);
     Address dest_addr(rsp, 3 * wordSize);
     __ movl(rax, exchange);
-    __ movl(rdx, dest_addr);
-    __ xchg(rax, Address(rdx, 0));
-    __ popl(rdx);
+    __ movptr(rdx, dest_addr);
+    __ xchgl(rax, Address(rdx, 0));
+    __ pop(rdx);
     __ ret(0);
 
     return start;
@@ -476,8 +477,8 @@
     if (CheckJNICalls && UseSSE > 0 ) {
       Label ok_ret;
       ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
-      __ pushl(rax);
-      __ subl(rsp, wordSize);      // allocate a temp location
+      __ push(rax);
+      __ subptr(rsp, wordSize);      // allocate a temp location
       __ stmxcsr(mxcsr_save);
       __ movl(rax, mxcsr_save);
       __ andl(rax, MXCSR_MASK);
@@ -489,8 +490,8 @@
       __ ldmxcsr(mxcsr_std);
 
       __ bind(ok_ret);
-      __ addl(rsp, wordSize);
-      __ popl(rax);
+      __ addptr(rsp, wordSize);
+      __ pop(rax);
     }
 
     __ ret(0);
@@ -514,8 +515,8 @@
 
     if (CheckJNICalls) {
       Label ok_ret;
-      __ pushl(rax);
-      __ subl(rsp, wordSize);      // allocate a temp location
+      __ push(rax);
+      __ subptr(rsp, wordSize);      // allocate a temp location
       __ fnstcw(fpu_cntrl_wrd_save);
       __ movl(rax, fpu_cntrl_wrd_save);
       __ andl(rax, FPU_CNTRL_WRD_MASK);
@@ -528,8 +529,8 @@
       __ fldcw(fpu_std);
 
       __ bind(ok_ret);
-      __ addl(rsp, wordSize);
-      __ popl(rax);
+      __ addptr(rsp, wordSize);
+      __ pop(rax);
     }
 
     __ ret(0);
@@ -563,22 +564,22 @@
   assert(FPUStateSizeInWords == 27, "update stack layout");
 
     // Save outgoing argument to stack across push_FPU_state()
-    __ subl(rsp, wordSize * 2);
+    __ subptr(rsp, wordSize * 2);
     __ fstp_d(Address(rsp, 0));
 
     // Save CPU & FPU state
-    __ pushl(rbx);
-    __ pushl(rcx);
-    __ pushl(rsi);
-    __ pushl(rdi);
-    __ pushl(rbp);
+    __ push(rbx);
+    __ push(rcx);
+    __ push(rsi);
+    __ push(rdi);
+    __ push(rbp);
     __ push_FPU_state();
 
     // push_FPU_state() resets the FP top of stack
     // Load original double into FP top of stack
     __ fld_d(Address(rsp, saved_argument_off * wordSize));
     // Store double into stack as outgoing argument
-    __ subl(rsp, wordSize*2);
+    __ subptr(rsp, wordSize*2);
     __ fst_d(Address(rsp, 0));
 
     // Prepare FPU for doing math in C-land
@@ -592,12 +593,12 @@
 
     // Restore CPU & FPU state
     __ pop_FPU_state();
-    __ popl(rbp);
-    __ popl(rdi);
-    __ popl(rsi);
-    __ popl(rcx);
-    __ popl(rbx);
-    __ addl(rsp, wordSize * 2);
+    __ pop(rbp);
+    __ pop(rdi);
+    __ pop(rsi);
+    __ pop(rcx);
+    __ pop(rbx);
+    __ addptr(rsp, wordSize * 2);
 
     __ ret(0);
 
@@ -613,13 +614,13 @@
     StubCodeMark mark(this, "StubRoutines", "handler_for_unsafe_access");
     address start = __ pc();
 
-    __ pushl(0);                      // hole for return address-to-be
-    __ pushad();                      // push registers
+    __ push(0);                       // hole for return address-to-be
+    __ pusha();                       // push registers
     Address next_pc(rsp, RegisterImpl::number_of_registers * BytesPerWord);
     BLOCK_COMMENT("call handle_unsafe_access");
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, handle_unsafe_access)));
-    __ movl(next_pc, rax);            // stuff next address
-    __ popad();
+    __ movptr(next_pc, rax);          // stuff next address
+    __ popa();
     __ ret(0);                        // jump to next address
 
     return start;
@@ -643,62 +644,62 @@
     // [tos + 5]: saved rax, - saved by caller and bashed
 
     Label exit, error;
-    __ pushfd();
-    __ increment(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
-    __ pushl(rdx);                               // save rdx
+    __ pushf();
+    __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
+    __ push(rdx);                                // save rdx
     // make sure object is 'reasonable'
-    __ movl(rax, Address(rsp, 4 * wordSize));    // get object
-    __ testl(rax, rax);
+    __ movptr(rax, Address(rsp, 4 * wordSize));    // get object
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, exit);               // if obj is NULL it is ok
 
     // Check if the oop is in the right area of memory
     const int oop_mask = Universe::verify_oop_mask();
     const int oop_bits = Universe::verify_oop_bits();
-    __ movl(rdx, rax);
-    __ andl(rdx, oop_mask);
-    __ cmpl(rdx, oop_bits);
+    __ mov(rdx, rax);
+    __ andptr(rdx, oop_mask);
+    __ cmpptr(rdx, oop_bits);
     __ jcc(Assembler::notZero, error);
 
     // make sure klass is 'reasonable'
-    __ movl(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass
-    __ testl(rax, rax);
+    __ movptr(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, error);              // if klass is NULL it is broken
 
     // Check if the klass is in the right area of memory
     const int klass_mask = Universe::verify_klass_mask();
     const int klass_bits = Universe::verify_klass_bits();
-    __ movl(rdx, rax);
-    __ andl(rdx, klass_mask);
-    __ cmpl(rdx, klass_bits);
+    __ mov(rdx, rax);
+    __ andptr(rdx, klass_mask);
+    __ cmpptr(rdx, klass_bits);
     __ jcc(Assembler::notZero, error);
 
     // make sure klass' klass is 'reasonable'
-    __ movl(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass' klass
-    __ testl(rax, rax);
+    __ movptr(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass' klass
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, error);              // if klass' klass is NULL it is broken
 
-    __ movl(rdx, rax);
-    __ andl(rdx, klass_mask);
-    __ cmpl(rdx, klass_bits);
+    __ mov(rdx, rax);
+    __ andptr(rdx, klass_mask);
+    __ cmpptr(rdx, klass_bits);
     __ jcc(Assembler::notZero, error);           // if klass not in right area
                                                  // of memory it is broken too.
 
     // return if everything seems ok
     __ bind(exit);
-    __ movl(rax, Address(rsp, 5 * wordSize));    // get saved rax, back
-    __ popl(rdx);                                // restore rdx
-    __ popfd();                                  // restore EFLAGS
+    __ movptr(rax, Address(rsp, 5 * wordSize));  // get saved rax, back
+    __ pop(rdx);                                 // restore rdx
+    __ popf();                                   // restore EFLAGS
     __ ret(3 * wordSize);                        // pop arguments
 
     // handle errors
     __ bind(error);
-    __ movl(rax, Address(rsp, 5 * wordSize));    // get saved rax, back
-    __ popl(rdx);                                // get saved rdx back
-    __ popfd();                                  // get saved EFLAGS off stack -- will be ignored
-    __ pushad();                                 // push registers (eip = return address & msg are already pushed)
+    __ movptr(rax, Address(rsp, 5 * wordSize));  // get saved rax, back
+    __ pop(rdx);                                 // get saved rdx back
+    __ popf();                                   // get saved EFLAGS off stack -- will be ignored
+    __ pusha();                                  // push registers (eip = return address & msg are already pushed)
     BLOCK_COMMENT("call MacroAssembler::debug");
-    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
-    __ popad();
+    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
+    __ popa();
     __ ret(3 * wordSize);                        // pop arguments
     return start;
   }
@@ -717,12 +718,12 @@
       case BarrierSet::G1SATBCT:
       case BarrierSet::G1SATBCTLogging:
         {
-          __ pushad();                      // push registers
-          __ pushl(count);
-          __ pushl(start);
+          __ pusha();                      // push registers
+          __ push(count);
+          __ push(start);
           __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre));
           __ addl(esp, wordSize * 2);
-          __ popad();
+          __ popa();
         }
         break;
       case BarrierSet::CardTableModRef:
@@ -753,12 +754,12 @@
       case BarrierSet::G1SATBCT:
       case BarrierSet::G1SATBCTLogging:
         {
-          __ pushad();                      // push registers
-          __ pushl(count);
-          __ pushl(start);
+          __ pusha();                      // push registers
+          __ push(count);
+          __ push(start);
           __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post));
           __ addl(esp, wordSize * 2);
-          __ popad();
+          __ popa();
 
         }
         break;
@@ -774,10 +775,10 @@
           const Register end = count;  // elements count; end == start+count-1
           assert_different_registers(start, end);
 
-          __ leal(end,   Address(start, count, Address::times_4, -4));
-          __ shrl(start, CardTableModRefBS::card_shift);
-          __ shrl(end,   CardTableModRefBS::card_shift);
-          __ subl(end, start); // end --> count
+          __ lea(end,  Address(start, count, Address::times_ptr, -wordSize));
+          __ shrptr(start, CardTableModRefBS::card_shift);
+          __ shrptr(end,   CardTableModRefBS::card_shift);
+          __ subptr(end, start); // end --> count
         __ BIND(L_loop);
           intptr_t disp = (intptr_t) ct->byte_map_base;
           Address cardtable(start, count, Address::times_1, disp);
@@ -823,7 +824,7 @@
     __ movq(Address(from, to_from, Address::times_1, 40), mmx5);
     __ movq(Address(from, to_from, Address::times_1, 48), mmx6);
     __ movq(Address(from, to_from, Address::times_1, 56), mmx7);
-    __ addl(from, 64);
+    __ addptr(from, 64);
   __ BIND(L_copy_64_bytes);
     __ subl(qword_count, 8);
     __ jcc(Assembler::greaterEqual, L_copy_64_bytes_loop);
@@ -835,7 +836,7 @@
   __ BIND(L_copy_8_bytes);
     __ movq(mmx0, Address(from, 0));
     __ movq(Address(from, to_from, Address::times_1), mmx0);
-    __ addl(from, 8);
+    __ addptr(from, 8);
     __ decrement(qword_count);
     __ jcc(Assembler::greater, L_copy_8_bytes);
   __ BIND(L_exit);
@@ -852,7 +853,7 @@
     Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
     Label L_copy_2_bytes, L_copy_4_bytes, L_copy_64_bytes;
 
-    int shift = Address::times_4 - sf;
+    int shift = Address::times_ptr - sf;
 
     const Register from     = rsi;  // source array address
     const Register to       = rdi;  // destination array address
@@ -861,22 +862,22 @@
     const Register saved_to = rdx;  // saved destination array address
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ pushl(rsi);
-    __ pushl(rdi);
-    __ movl(from , Address(rsp, 12+ 4));
-    __ movl(to   , Address(rsp, 12+ 8));
+    __ push(rsi);
+    __ push(rdi);
+    __ movptr(from , Address(rsp, 12+ 4));
+    __ movptr(to   , Address(rsp, 12+ 8));
     __ movl(count, Address(rsp, 12+ 12));
     if (t == T_OBJECT) {
       __ testl(count, count);
       __ jcc(Assembler::zero, L_0_count);
       gen_write_ref_array_pre_barrier(to, count);
-      __ movl(saved_to, to);          // save 'to'
+      __ mov(saved_to, to);          // save 'to'
     }
 
     *entry = __ pc(); // Entry point from conjoint arraycopy stub.
     BLOCK_COMMENT("Entry:");
 
-    __ subl(to, from); // to --> to_from
+    __ subptr(to, from); // to --> to_from
     __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
     __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
     if (!aligned && (t == T_BYTE || t == T_SHORT)) {
@@ -896,28 +897,28 @@
       __ jccb(Assembler::zero, L_skip_align2);
       __ movw(rax, Address(from, 0));
       __ movw(Address(from, to_from, Address::times_1, 0), rax);
-      __ addl(from, 2);
+      __ addptr(from, 2);
       __ subl(count, 1<<(shift-1));
     __ BIND(L_skip_align2);
     }
     if (!VM_Version::supports_mmx()) {
-      __ movl(rax, count);     // save 'count'
-      __ shrl(count, shift);   // bytes count
-      __ addl(to_from, from);  // restore 'to'
-      __ rep_movl();
-      __ subl(to_from, from);  // restore 'to_from'
-      __ movl(count, rax);     // restore 'count'
+      __ mov(rax, count);      // save 'count'
+      __ shrl(count, shift); // bytes count
+      __ addptr(to_from, from);// restore 'to'
+      __ rep_mov();
+      __ subptr(to_from, from);// restore 'to_from'
+      __ mov(count, rax);      // restore 'count'
       __ jmpb(L_copy_2_bytes); // all dwords were copied
     } else {
       // align to 8 bytes, we know we are 4 byte aligned to start
-      __ testl(from, 4);
+      __ testptr(from, 4);
       __ jccb(Assembler::zero, L_copy_64_bytes);
       __ movl(rax, Address(from, 0));
       __ movl(Address(from, to_from, Address::times_1, 0), rax);
-      __ addl(from, 4);
+      __ addptr(from, 4);
       __ subl(count, 1<<shift);
     __ BIND(L_copy_64_bytes);
-      __ movl(rax, count);
+      __ mov(rax, count);
       __ shrl(rax, shift+1);  // 8 bytes chunk count
       //
       // Copy 8-byte chunks through MMX registers, 8 per iteration of the loop
@@ -931,7 +932,7 @@
     __ movl(rax, Address(from, 0));
     __ movl(Address(from, to_from, Address::times_1, 0), rax);
     if (t == T_BYTE || t == T_SHORT) {
-      __ addl(from, 4);
+      __ addptr(from, 4);
     __ BIND(L_copy_2_bytes);
       // copy tailing word
       __ testl(count, 1<<(shift-1));
@@ -939,7 +940,7 @@
       __ movw(rax, Address(from, 0));
       __ movw(Address(from, to_from, Address::times_1, 0), rax);
       if (t == T_BYTE) {
-        __ addl(from, 2);
+        __ addptr(from, 2);
       __ BIND(L_copy_byte);
         // copy tailing byte
         __ testl(count, 1);
@@ -956,15 +957,15 @@
 
     if (t == T_OBJECT) {
       __ movl(count, Address(rsp, 12+12)); // reread 'count'
-      __ movl(to, saved_to); // restore 'to'
+      __ mov(to, saved_to); // restore 'to'
       gen_write_ref_array_post_barrier(to, count);
     __ BIND(L_0_count);
     }
     inc_copy_counter_np(t);
-    __ popl(rdi);
-    __ popl(rsi);
+    __ pop(rdi);
+    __ pop(rsi);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
-    __ xorl(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ ret(0);
     return start;
   }
@@ -981,7 +982,7 @@
     Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
     Label L_copy_2_bytes, L_copy_4_bytes, L_copy_8_bytes, L_copy_8_bytes_loop;
 
-    int shift = Address::times_4 - sf;
+    int shift = Address::times_ptr - sf;
 
     const Register src   = rax;  // source array address
     const Register dst   = rdx;  // destination array address
@@ -991,11 +992,11 @@
     const Register end   = rax;  // array end address
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ pushl(rsi);
-    __ pushl(rdi);
-    __ movl(src  , Address(rsp, 12+ 4));  // from
-    __ movl(dst  , Address(rsp, 12+ 8));  // to
-    __ movl(count, Address(rsp, 12+12));  // count
+    __ push(rsi);
+    __ push(rdi);
+    __ movptr(src  , Address(rsp, 12+ 4));   // from
+    __ movptr(dst  , Address(rsp, 12+ 8));   // to
+    __ movl2ptr(count, Address(rsp, 12+12)); // count
     if (t == T_OBJECT) {
        gen_write_ref_array_pre_barrier(dst, count);
     }
@@ -1009,15 +1010,15 @@
       __ testl(count, count);
       __ jcc(Assembler::zero, L_0_count);
     }
-    __ movl(from, src);
-    __ movl(to  , dst);
+    __ mov(from, src);
+    __ mov(to  , dst);
 
     // arrays overlap test
     RuntimeAddress nooverlap(nooverlap_target);
-    __ cmpl(dst, src);
-    __ leal(end, Address(src, count, sf, 0)); // src + count * elem_size
+    __ cmpptr(dst, src);
+    __ lea(end, Address(src, count, sf, 0)); // src + count * elem_size
     __ jump_cc(Assembler::belowEqual, nooverlap);
-    __ cmpl(dst, end);
+    __ cmpptr(dst, end);
     __ jump_cc(Assembler::aboveEqual, nooverlap);
 
     // copy from high to low
@@ -1025,7 +1026,7 @@
     __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
     if (t == T_BYTE || t == T_SHORT) {
       // Align the end of destination array at 4 bytes address boundary
-      __ leal(end, Address(dst, count, sf, 0));
+      __ lea(end, Address(dst, count, sf, 0));
       if (t == T_BYTE) {
         // One byte misalignment happens only for byte arrays
         __ testl(end, 1);
@@ -1038,7 +1039,7 @@
       // Two bytes misalignment happens only for byte and short (char) arrays
       __ testl(end, 2);
       __ jccb(Assembler::zero, L_skip_align2);
-      __ subl(count, 1<<(shift-1));
+      __ subptr(count, 1<<(shift-1));
       __ movw(rdx, Address(from, count, sf, 0));
       __ movw(Address(to, count, sf, 0), rdx);
     __ BIND(L_skip_align2);
@@ -1048,21 +1049,21 @@
 
     if (!VM_Version::supports_mmx()) {
       __ std();
-      __ movl(rax, count); // Save 'count'
-      __ movl(rdx, to);    // Save 'to'
-      __ leal(rsi, Address(from, count, sf, -4));
-      __ leal(rdi, Address(to  , count, sf, -4));
-      __ shrl(count, shift); // bytes count
-      __ rep_movl();
+      __ mov(rax, count); // Save 'count'
+      __ mov(rdx, to);    // Save 'to'
+      __ lea(rsi, Address(from, count, sf, -4));
+      __ lea(rdi, Address(to  , count, sf, -4));
+      __ shrptr(count, shift); // bytes count
+      __ rep_mov();
       __ cld();
-      __ movl(count, rax); // restore 'count'
+      __ mov(count, rax); // restore 'count'
       __ andl(count, (1<<shift)-1);      // mask the number of rest elements
-      __ movl(from, Address(rsp, 12+4)); // reread 'from'
-      __ movl(to, rdx);   // restore 'to'
+      __ movptr(from, Address(rsp, 12+4)); // reread 'from'
+      __ mov(to, rdx);   // restore 'to'
       __ jmpb(L_copy_2_bytes); // all dword were copied
    } else {
       // Align to 8 bytes the end of array. It is aligned to 4 bytes already.
-      __ testl(end, 4);
+      __ testptr(end, 4);
       __ jccb(Assembler::zero, L_copy_8_bytes);
       __ subl(count, 1<<shift);
       __ movl(rdx, Address(from, count, sf, 0));
@@ -1111,15 +1112,15 @@
     __ BIND(L_copy_2_bytes);
     }
     if (t == T_OBJECT) {
-      __ movl(count, Address(rsp, 12+12)); // reread count
+      __ movl2ptr(count, Address(rsp, 12+12)); // reread count
       gen_write_ref_array_post_barrier(to, count);
     __ BIND(L_0_count);
     }
     inc_copy_counter_np(t);
-    __ popl(rdi);
-    __ popl(rsi);
+    __ pop(rdi);
+    __ pop(rsi);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
-    __ xorl(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ ret(0);
     return start;
   }
@@ -1137,14 +1138,14 @@
     const Register to_from    = rdx;  // (to - from)
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ movl(from , Address(rsp, 8+0));       // from
-    __ movl(to   , Address(rsp, 8+4));       // to
-    __ movl(count, Address(rsp, 8+8));       // count
+    __ movptr(from , Address(rsp, 8+0));       // from
+    __ movptr(to   , Address(rsp, 8+4));       // to
+    __ movl2ptr(count, Address(rsp, 8+8));     // count
 
     *entry = __ pc(); // Entry point from conjoint arraycopy stub.
     BLOCK_COMMENT("Entry:");
 
-    __ subl(to, from); // to --> to_from
+    __ subptr(to, from); // to --> to_from
     if (VM_Version::supports_mmx()) {
       mmx_copy_forward(from, to_from, count);
     } else {
@@ -1153,14 +1154,14 @@
     __ BIND(L_copy_8_bytes_loop);
       __ fild_d(Address(from, 0));
       __ fistp_d(Address(from, to_from, Address::times_1));
-      __ addl(from, 8);
+      __ addptr(from, 8);
     __ BIND(L_copy_8_bytes);
       __ decrement(count);
       __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
     }
     inc_copy_counter_np(T_LONG);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
-    __ xorl(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ ret(0);
     return start;
   }
@@ -1178,20 +1179,20 @@
     const Register end_from   = rax;  // source array end address
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ movl(from , Address(rsp, 8+0));       // from
-    __ movl(to   , Address(rsp, 8+4));       // to
-    __ movl(count, Address(rsp, 8+8));       // count
+    __ movptr(from , Address(rsp, 8+0));       // from
+    __ movptr(to   , Address(rsp, 8+4));       // to
+    __ movl2ptr(count, Address(rsp, 8+8));     // count
 
     *entry = __ pc(); // Entry point from generic arraycopy stub.
     BLOCK_COMMENT("Entry:");
 
     // arrays overlap test
-    __ cmpl(to, from);
+    __ cmpptr(to, from);
     RuntimeAddress nooverlap(nooverlap_target);
     __ jump_cc(Assembler::belowEqual, nooverlap);
-    __ leal(end_from, Address(from, count, Address::times_8, 0));
-    __ cmpl(to, end_from);
-    __ movl(from, Address(rsp, 8));  // from
+    __ lea(end_from, Address(from, count, Address::times_8, 0));
+    __ cmpptr(to, end_from);
+    __ movptr(from, Address(rsp, 8));  // from
     __ jump_cc(Assembler::aboveEqual, nooverlap);
 
     __ jmpb(L_copy_8_bytes);
@@ -1214,7 +1215,7 @@
     }
     inc_copy_counter_np(T_LONG);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
-    __ xorl(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ ret(0);
     return start;
   }
@@ -1251,14 +1252,14 @@
     Address super_cache_addr(     sub_klass, sc_offset);
 
     // if the pointers are equal, we are done (e.g., String[] elements)
-    __ cmpl(sub_klass, super_klass_addr);
+    __ cmpptr(sub_klass, super_klass_addr);
     __ jcc(Assembler::equal, L_success);
 
     // check the supertype display:
-    __ movl(temp, super_check_offset_addr);
+    __ movl2ptr(temp, super_check_offset_addr);
     Address super_check_addr(sub_klass, temp, Address::times_1, 0);
-    __ movl(temp, super_check_addr); // load displayed supertype
-    __ cmpl(temp, super_klass_addr); // test the super type
+    __ movptr(temp, super_check_addr); // load displayed supertype
+    __ cmpptr(temp, super_klass_addr); // test the super type
     __ jcc(Assembler::equal, L_success);
 
     // if it was a primary super, we can just fail immediately
@@ -1271,31 +1272,31 @@
     {
       // The repne_scan instruction uses fixed registers, which we must spill.
       // (We need a couple more temps in any case.)
-      __ pushl(rax);
-      __ pushl(rcx);
-      __ pushl(rdi);
+      __ push(rax);
+      __ push(rcx);
+      __ push(rdi);
       assert_different_registers(sub_klass, rax, rcx, rdi);
 
-      __ movl(rdi, secondary_supers_addr);
+      __ movptr(rdi, secondary_supers_addr);
       // Load the array length.
       __ movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
       // Skip to start of data.
-      __ addl(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+      __ addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
       // Scan rcx words at [edi] for occurance of rax,
       // Set NZ/Z based on last compare
-      __ movl(rax, super_klass_addr);
+      __ movptr(rax, super_klass_addr);
       __ repne_scan();
 
       // Unspill the temp. registers:
-      __ popl(rdi);
-      __ popl(rcx);
-      __ popl(rax);
+      __ pop(rdi);
+      __ pop(rcx);
+      __ pop(rax);
     }
     __ jcc(Assembler::notEqual, L_failure);
 
     // Success.  Cache the super we found and proceed in triumph.
-    __ movl(temp, super_klass_addr); // note: rax, is dead
-    __ movl(super_cache_addr, temp);
+    __ movptr(temp, super_klass_addr); // note: rax, is dead
+    __ movptr(super_cache_addr, temp);
 
     if (!fall_through_on_success)
       __ jmp(L_success);
@@ -1338,9 +1339,9 @@
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
 
-    __ pushl(rsi);
-    __ pushl(rdi);
-    __ pushl(rbx);
+    __ push(rsi);
+    __ push(rdi);
+    __ push(rbx);
 
     Address   from_arg(rsp, 16+ 4);     // from
     Address     to_arg(rsp, 16+ 8);     // to
@@ -1349,9 +1350,9 @@
     Address  ckval_arg(rsp, 16+20);     // super_klass
 
     // Load up:
-    __ movl(from,     from_arg);
-    __ movl(to,         to_arg);
-    __ movl(length, length_arg);
+    __ movptr(from,     from_arg);
+    __ movptr(to,         to_arg);
+    __ movl2ptr(length, length_arg);
 
     *entry = __ pc(); // Entry point from generic arraycopy stub.
     BLOCK_COMMENT("Entry:");
@@ -1364,28 +1365,28 @@
     // checked.
 
     // Loop-invariant addresses.  They are exclusive end pointers.
-    Address end_from_addr(from, length, Address::times_4, 0);
-    Address   end_to_addr(to,   length, Address::times_4, 0);
+    Address end_from_addr(from, length, Address::times_ptr, 0);
+    Address   end_to_addr(to,   length, Address::times_ptr, 0);
 
     Register end_from = from;           // re-use
     Register end_to   = to;             // re-use
     Register count    = length;         // re-use
 
     // Loop-variant addresses.  They assume post-incremented count < 0.
-    Address from_element_addr(end_from, count, Address::times_4, 0);
-    Address   to_element_addr(end_to,   count, Address::times_4, 0);
+    Address from_element_addr(end_from, count, Address::times_ptr, 0);
+    Address   to_element_addr(end_to,   count, Address::times_ptr, 0);
     Address elem_klass_addr(elem, oopDesc::klass_offset_in_bytes());
 
     // Copy from low to high addresses, indexed from the end of each array.
-    __ leal(end_from, end_from_addr);
-    __ leal(end_to,   end_to_addr);
+    __ lea(end_from, end_from_addr);
+    __ lea(end_to,   end_to_addr);
     gen_write_ref_array_pre_barrier(to, count);
     assert(length == count, "");        // else fix next line:
-    __ negl(count);                     // negate and test the length
+    __ negptr(count);                   // negate and test the length
     __ jccb(Assembler::notZero, L_load_element);
 
     // Empty array:  Nothing to do.
-    __ xorl(rax, rax);                  // return 0 on (trivial) success
+    __ xorptr(rax, rax);                  // return 0 on (trivial) success
     __ jmp(L_done);
 
     // ======== begin loop ========
@@ -1396,20 +1397,20 @@
     __ align(16);
 
     __ BIND(L_store_element);
-    __ movl(to_element_addr, elem);     // store the oop
+    __ movptr(to_element_addr, elem);     // store the oop
     __ increment(count);                // increment the count toward zero
     __ jccb(Assembler::zero, L_do_card_marks);
 
     // ======== loop entry is here ========
     __ BIND(L_load_element);
-    __ movl(elem, from_element_addr);   // load the oop
-    __ testl(elem, elem);
+    __ movptr(elem, from_element_addr);   // load the oop
+    __ testptr(elem, elem);
     __ jccb(Assembler::zero, L_store_element);
 
     // (Could do a trick here:  Remember last successful non-null
     // element stored and make a quick oop equality check on it.)
 
-    __ movl(elem_klass, elem_klass_addr); // query the object klass
+    __ movptr(elem_klass, elem_klass_addr); // query the object klass
     generate_type_check(elem_klass, ckoff_arg, ckval_arg, temp,
                         &L_store_element, NULL);
       // (On fall-through, we have failed the element type check.)
@@ -1420,25 +1421,25 @@
     // Emit GC store barriers for the oops we have copied (length_arg + count),
     // and report their number to the caller.
     __ addl(count, length_arg);         // transfers = (length - remaining)
-    __ movl(rax, count);                // save the value
-    __ notl(rax);                       // report (-1^K) to caller
-    __ movl(to, to_arg);                // reload
+    __ movl2ptr(rax, count);            // save the value
+    __ notptr(rax);                     // report (-1^K) to caller
+    __ movptr(to, to_arg);              // reload
     assert_different_registers(to, count, rax);
     gen_write_ref_array_post_barrier(to, count);
     __ jmpb(L_done);
 
     // Come here on success only.
     __ BIND(L_do_card_marks);
-    __ movl(count, length_arg);
-    __ movl(to, to_arg);                // reload
+    __ movl2ptr(count, length_arg);
+    __ movptr(to, to_arg);                // reload
     gen_write_ref_array_post_barrier(to, count);
-    __ xorl(rax, rax);                  // return 0 on success
+    __ xorptr(rax, rax);                  // return 0 on success
 
     // Common exit point (success or failure).
     __ BIND(L_done);
-    __ popl(rbx);
-    __ popl(rdi);
-    __ popl(rsi);
+    __ pop(rbx);
+    __ pop(rdi);
+    __ pop(rsi);
     inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
@@ -1480,24 +1481,24 @@
     const Register count      = rcx;  // elements count
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ pushl(rsi);
-    __ pushl(rdi);
+    __ push(rsi);
+    __ push(rdi);
     Address  from_arg(rsp, 12+ 4);      // from
     Address    to_arg(rsp, 12+ 8);      // to
     Address count_arg(rsp, 12+12);      // byte count
 
     // Load up:
-    __ movl(from ,  from_arg);
-    __ movl(to   ,    to_arg);
-    __ movl(count, count_arg);
+    __ movptr(from ,  from_arg);
+    __ movptr(to   ,    to_arg);
+    __ movl2ptr(count, count_arg);
 
     // bump this on entry, not on exit:
     inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
 
     const Register bits = rsi;
-    __ movl(bits, from);
-    __ orl(bits, to);
-    __ orl(bits, count);
+    __ mov(bits, from);
+    __ orptr(bits, to);
+    __ orptr(bits, count);
 
     __ testl(bits, BytesPerLong-1);
     __ jccb(Assembler::zero, L_long_aligned);
@@ -1509,20 +1510,20 @@
     __ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry));
 
     __ BIND(L_short_aligned);
-    __ shrl(count, LogBytesPerShort); // size => short_count
+    __ shrptr(count, LogBytesPerShort); // size => short_count
     __ movl(count_arg, count);          // update 'count'
     __ jump(RuntimeAddress(short_copy_entry));
 
     __ BIND(L_int_aligned);
-    __ shrl(count, LogBytesPerInt); // size => int_count
+    __ shrptr(count, LogBytesPerInt); // size => int_count
     __ movl(count_arg, count);          // update 'count'
     __ jump(RuntimeAddress(int_copy_entry));
 
     __ BIND(L_long_aligned);
-    __ shrl(count, LogBytesPerLong); // size => qword_count
+    __ shrptr(count, LogBytesPerLong); // size => qword_count
     __ movl(count_arg, count);          // update 'count'
-    __ popl(rdi); // Do pops here since jlong_arraycopy stub does not do it.
-    __ popl(rsi);
+    __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
+    __ pop(rsi);
     __ jump(RuntimeAddress(long_copy_entry));
 
     return start;
@@ -1595,8 +1596,8 @@
     address start = __ pc();
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
-    __ pushl(rsi);
-    __ pushl(rdi);
+    __ push(rsi);
+    __ push(rdi);
 
     // bump this on entry, not on exit:
     inc_counter_np(SharedRuntime::_generic_array_copy_ctr);
@@ -1629,27 +1630,27 @@
     const Register length  = rcx;       // transfer count
 
     //  if (src == NULL) return -1;
-    __ movl(src, SRC);      // src oop
-    __ testl(src, src);
+    __ movptr(src, SRC);      // src oop
+    __ testptr(src, src);
     __ jccb(Assembler::zero, L_failed_0);
 
     //  if (src_pos < 0) return -1;
-    __ movl(src_pos, SRC_POS);  // src_pos
+    __ movl2ptr(src_pos, SRC_POS);  // src_pos
     __ testl(src_pos, src_pos);
     __ jccb(Assembler::negative, L_failed_0);
 
     //  if (dst == NULL) return -1;
-    __ movl(dst, DST);      // dst oop
-    __ testl(dst, dst);
+    __ movptr(dst, DST);      // dst oop
+    __ testptr(dst, dst);
     __ jccb(Assembler::zero, L_failed_0);
 
     //  if (dst_pos < 0) return -1;
-    __ movl(dst_pos, DST_POS);  // dst_pos
+    __ movl2ptr(dst_pos, DST_POS);  // dst_pos
     __ testl(dst_pos, dst_pos);
     __ jccb(Assembler::negative, L_failed_0);
 
     //  if (length < 0) return -1;
-    __ movl(length, LENGTH);   // length
+    __ movl2ptr(length, LENGTH);   // length
     __ testl(length, length);
     __ jccb(Assembler::negative, L_failed_0);
 
@@ -1657,18 +1658,18 @@
     Address src_klass_addr(src, oopDesc::klass_offset_in_bytes());
     Address dst_klass_addr(dst, oopDesc::klass_offset_in_bytes());
     const Register rcx_src_klass = rcx;    // array klass
-    __ movl(rcx_src_klass, Address(src, oopDesc::klass_offset_in_bytes()));
+    __ movptr(rcx_src_klass, Address(src, oopDesc::klass_offset_in_bytes()));
 
 #ifdef ASSERT
     //  assert(src->klass() != NULL);
     BLOCK_COMMENT("assert klasses not null");
     { Label L1, L2;
-      __ testl(rcx_src_klass, rcx_src_klass);
+      __ testptr(rcx_src_klass, rcx_src_klass);
       __ jccb(Assembler::notZero, L2);   // it is broken if klass is NULL
       __ bind(L1);
       __ stop("broken null klass");
       __ bind(L2);
-      __ cmpl(dst_klass_addr, 0);
+      __ cmpptr(dst_klass_addr, (int32_t)NULL_WORD);
       __ jccb(Assembler::equal, L1);      // this would be broken also
       BLOCK_COMMENT("assert done");
     }
@@ -1692,7 +1693,7 @@
     __ jcc(Assembler::equal, L_objArray);
 
     //  if (src->klass() != dst->klass()) return -1;
-    __ cmpl(rcx_src_klass, dst_klass_addr);
+    __ cmpptr(rcx_src_klass, dst_klass_addr);
     __ jccb(Assembler::notEqual, L_failed_0);
 
     const Register rcx_lh = rcx;  // layout helper
@@ -1726,12 +1727,12 @@
     const Register dst_array  = dst; // dst array offset
     const Register rdi_elsize = rdi; // log2 element size
 
-    __ movl(rsi_offset, rcx_lh);
-    __ shrl(rsi_offset, Klass::_lh_header_size_shift);
-    __ andl(rsi_offset, Klass::_lh_header_size_mask);   // array_offset
-    __ addl(src_array, rsi_offset);  // src array offset
-    __ addl(dst_array, rsi_offset);  // dst array offset
-    __ andl(rcx_lh, Klass::_lh_log2_element_size_mask); // log2 elsize
+    __ mov(rsi_offset, rcx_lh);
+    __ shrptr(rsi_offset, Klass::_lh_header_size_shift);
+    __ andptr(rsi_offset, Klass::_lh_header_size_mask);   // array_offset
+    __ addptr(src_array, rsi_offset);  // src array offset
+    __ addptr(dst_array, rsi_offset);  // dst array offset
+    __ andptr(rcx_lh, Klass::_lh_log2_element_size_mask); // log2 elsize
 
     // next registers should be set before the jump to corresponding stub
     const Register from       = src; // source array address
@@ -1743,17 +1744,17 @@
 #define COUNT  Address(rsp, 12+12)   // Only for oop arraycopy
 
     BLOCK_COMMENT("scale indexes to element size");
-    __ movl(rsi, SRC_POS);  // src_pos
-    __ shll(rsi); // src_pos << rcx (log2 elsize)
+    __ movl2ptr(rsi, SRC_POS);  // src_pos
+    __ shlptr(rsi);             // src_pos << rcx (log2 elsize)
     assert(src_array == from, "");
-    __ addl(from, rsi);     // from = src_array + SRC_POS << log2 elsize
-    __ movl(rdi, DST_POS);  // dst_pos
-    __ shll(rdi); // dst_pos << rcx (log2 elsize)
+    __ addptr(from, rsi);       // from = src_array + SRC_POS << log2 elsize
+    __ movl2ptr(rdi, DST_POS);  // dst_pos
+    __ shlptr(rdi);             // dst_pos << rcx (log2 elsize)
     assert(dst_array == to, "");
-    __ addl(to,  rdi);      // to   = dst_array + DST_POS << log2 elsize
-    __ movl(FROM, from);    // src_addr
-    __ movl(rdi_elsize, rcx_lh); // log2 elsize
-    __ movl(count, LENGTH); // elements count
+    __ addptr(to,  rdi);        // to   = dst_array + DST_POS << log2 elsize
+    __ movptr(FROM, from);      // src_addr
+    __ mov(rdi_elsize, rcx_lh); // log2 elsize
+    __ movl2ptr(count, LENGTH); // elements count
 
     BLOCK_COMMENT("choose copy loop based on element size");
     __ cmpl(rdi_elsize, 0);
@@ -1767,15 +1768,15 @@
     __ cmpl(rdi_elsize, LogBytesPerLong);
     __ jccb(Assembler::notEqual, L_failed);
 #endif
-    __ popl(rdi); // Do pops here since jlong_arraycopy stub does not do it.
-    __ popl(rsi);
+    __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
+    __ pop(rsi);
     __ jump(RuntimeAddress(entry_jlong_arraycopy));
 
   __ BIND(L_failed);
-    __ xorl(rax, rax);
-    __ notl(rax); // return -1
-    __ popl(rdi);
-    __ popl(rsi);
+    __ xorptr(rax, rax);
+    __ notptr(rax); // return -1
+    __ pop(rdi);
+    __ pop(rsi);
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1785,7 +1786,7 @@
 
     Label L_plain_copy, L_checkcast_copy;
     //  test array classes for subtyping
-    __ cmpl(rcx_src_klass, dst_klass_addr); // usual case is exact equality
+    __ cmpptr(rcx_src_klass, dst_klass_addr); // usual case is exact equality
     __ jccb(Assembler::notEqual, L_checkcast_copy);
 
     // Identically typed arrays can be copied without element-wise checks.
@@ -1793,15 +1794,15 @@
     arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
 
   __ BIND(L_plain_copy);
-    __ movl(count, LENGTH); // elements count
-    __ movl(src_pos, SRC_POS);  // reload src_pos
-    __ leal(from, Address(src, src_pos, Address::times_4,
-                  arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
-    __ movl(dst_pos, DST_POS);  // reload dst_pos
-    __ leal(to,   Address(dst, dst_pos, Address::times_4,
-                  arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
-    __ movl(FROM,  from);   // src_addr
-    __ movl(TO,    to);     // dst_addr
+    __ movl2ptr(count, LENGTH); // elements count
+    __ movl2ptr(src_pos, SRC_POS);  // reload src_pos
+    __ lea(from, Address(src, src_pos, Address::times_ptr,
+                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
+    __ movl2ptr(dst_pos, DST_POS);  // reload dst_pos
+    __ lea(to,   Address(dst, dst_pos, Address::times_ptr,
+                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
+    __ movptr(FROM,  from);   // src_addr
+    __ movptr(TO,    to);     // dst_addr
     __ movl(COUNT, count);  // count
     __ jump(RuntimeAddress(entry_oop_arraycopy));
 
@@ -1821,37 +1822,37 @@
       Address dst_klass_lh_addr(rsi_dst_klass, lh_offset);
 
       // Before looking at dst.length, make sure dst is also an objArray.
-      __ movl(rsi_dst_klass, dst_klass_addr);
+      __ movptr(rsi_dst_klass, dst_klass_addr);
       __ cmpl(dst_klass_lh_addr, objArray_lh);
       __ jccb(Assembler::notEqual, L_failed);
 
       // It is safe to examine both src.length and dst.length.
-      __ movl(src_pos, SRC_POS);        // reload rsi
+      __ movl2ptr(src_pos, SRC_POS);        // reload rsi
       arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
       // (Now src_pos and dst_pos are killed, but not src and dst.)
 
       // We'll need this temp (don't forget to pop it after the type check).
-      __ pushl(rbx);
+      __ push(rbx);
       Register rbx_src_klass = rbx;
 
-      __ movl(rbx_src_klass, rcx_src_klass); // spill away from rcx
-      __ movl(rsi_dst_klass, dst_klass_addr);
+      __ mov(rbx_src_klass, rcx_src_klass); // spill away from rcx
+      __ movptr(rsi_dst_klass, dst_klass_addr);
       Address super_check_offset_addr(rsi_dst_klass, sco_offset);
       Label L_fail_array_check;
       generate_type_check(rbx_src_klass,
                           super_check_offset_addr, dst_klass_addr,
                           rdi_temp, NULL, &L_fail_array_check);
       // (On fall-through, we have passed the array type check.)
-      __ popl(rbx);
+      __ pop(rbx);
       __ jmp(L_plain_copy);
 
       __ BIND(L_fail_array_check);
       // Reshuffle arguments so we can call checkcast_arraycopy:
 
       // match initial saves for checkcast_arraycopy
-      // pushl(rsi);    // already done; see above
-      // pushl(rdi);    // already done; see above
-      // pushl(rbx);    // already done; see above
+      // push(rsi);    // already done; see above
+      // push(rdi);    // already done; see above
+      // push(rbx);    // already done; see above
 
       // Marshal outgoing arguments now, freeing registers.
       Address   from_arg(rsp, 16+ 4);   // from
@@ -1866,24 +1867,24 @@
       // push rbx, changed the incoming offsets (why not just use rbp,??)
       // assert(SRC_POS_arg.disp() == SRC_POS.disp() + 4, "");
 
-      __ movl(rbx, Address(rsi_dst_klass, ek_offset));
-      __ movl(length, LENGTH_arg);    // reload elements count
-      __ movl(src_pos, SRC_POS_arg);  // reload src_pos
-      __ movl(dst_pos, DST_POS_arg);  // reload dst_pos
+      __ movptr(rbx, Address(rsi_dst_klass, ek_offset));
+      __ movl2ptr(length, LENGTH_arg);    // reload elements count
+      __ movl2ptr(src_pos, SRC_POS_arg);  // reload src_pos
+      __ movl2ptr(dst_pos, DST_POS_arg);  // reload dst_pos
 
-      __ movl(ckval_arg, rbx);          // destination element type
+      __ movptr(ckval_arg, rbx);          // destination element type
       __ movl(rbx, Address(rbx, sco_offset));
       __ movl(ckoff_arg, rbx);          // corresponding class check offset
 
       __ movl(length_arg, length);      // outgoing length argument
 
-      __ leal(from, Address(src, src_pos, Address::times_4,
+      __ lea(from, Address(src, src_pos, Address::times_ptr,
                             arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
-      __ movl(from_arg, from);
+      __ movptr(from_arg, from);
 
-      __ leal(to, Address(dst, dst_pos, Address::times_4,
+      __ lea(to, Address(dst, dst_pos, Address::times_ptr,
                           arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
-      __ movl(to_arg, to);
+      __ movptr(to_arg, to);
       __ jump(RuntimeAddress(entry_checkcast_arraycopy));
     }
 
@@ -1934,10 +1935,10 @@
                                &entry_jint_arraycopy, "jint_arraycopy");
 
     StubRoutines::_oop_disjoint_arraycopy =
-        generate_disjoint_copy(T_OBJECT, true, Address::times_4, &entry,
+        generate_disjoint_copy(T_OBJECT, true, Address::times_ptr, &entry,
                                "oop_disjoint_arraycopy");
     StubRoutines::_oop_arraycopy =
-        generate_conjoint_copy(T_OBJECT, true, Address::times_4,  entry,
+        generate_conjoint_copy(T_OBJECT, true, Address::times_ptr,  entry,
                                &entry_oop_arraycopy, "oop_arraycopy");
 
     StubRoutines::_jlong_disjoint_arraycopy =
@@ -2037,21 +2038,21 @@
     Register java_thread = rbx;
     __ get_thread(java_thread);
     if (restore_saved_exception_pc) {
-      __ movl(rax, Address(java_thread, in_bytes(JavaThread::saved_exception_pc_offset())));
-      __ pushl(rax);
+      __ movptr(rax, Address(java_thread, in_bytes(JavaThread::saved_exception_pc_offset())));
+      __ push(rax);
     }
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
 
     // pc and rbp, already pushed
-    __ subl(rsp, (framesize-2) * wordSize); // prolog
+    __ subptr(rsp, (framesize-2) * wordSize); // prolog
 
     // Frame is now completed as far as size and linkage.
 
     int frame_complete = __ pc() - start;
 
     // push java thread (becomes first argument of C function)
-    __ movl(Address(rsp, thread_off * wordSize), java_thread);
+    __ movptr(Address(rsp, thread_off * wordSize), java_thread);
 
     // Set up last_Java_sp and last_Java_fp
     __ set_last_Java_frame(java_thread, rsp, rbp, NULL);
@@ -2075,7 +2076,7 @@
     // check for pending exceptions
 #ifdef ASSERT
     Label L;
-    __ cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::notEqual, L);
     __ should_not_reach_here();
     __ bind(L);
@@ -2137,8 +2138,8 @@
     // platform dependent
     create_control_words();
 
-    StubRoutines::i486::_verify_mxcsr_entry                 = generate_verify_mxcsr();
-    StubRoutines::i486::_verify_fpu_cntrl_wrd_entry         = generate_verify_fpu_cntrl_wrd();
+    StubRoutines::x86::_verify_mxcsr_entry                 = generate_verify_mxcsr();
+    StubRoutines::x86::_verify_fpu_cntrl_wrd_entry         = generate_verify_fpu_cntrl_wrd();
     StubRoutines::_d2i_wrapper                              = generate_d2i_wrapper(T_INT,
                                                                                    CAST_FROM_FN_PTR(address, SharedRuntime::d2i));
     StubRoutines::_d2l_wrapper                              = generate_d2i_wrapper(T_LONG,
--- a/hotspot/src/cpu/x86/vm/stubGenerator_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubGenerator_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -31,6 +31,7 @@
 
 #define __ _masm->
 #define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8)
+#define a__ ((Assembler*)_masm)->
 
 #ifdef PRODUCT
 #define BLOCK_COMMENT(str) /* nothing */
@@ -210,32 +211,32 @@
 
     // stub code
     __ enter();
-    __ subq(rsp, -rsp_after_call_off * wordSize);
+    __ subptr(rsp, -rsp_after_call_off * wordSize);
 
     // save register parameters
 #ifndef _WIN64
-    __ movq(parameters,   c_rarg5); // parameters
-    __ movq(entry_point,  c_rarg4); // entry_point
+    __ movptr(parameters,   c_rarg5); // parameters
+    __ movptr(entry_point,  c_rarg4); // entry_point
 #endif
 
-    __ movq(method,       c_rarg3); // method
-    __ movl(result_type,  c_rarg2); // result type
-    __ movq(result,       c_rarg1); // result
-    __ movq(call_wrapper, c_rarg0); // call wrapper
+    __ movptr(method,       c_rarg3); // method
+    __ movl(result_type,  c_rarg2);   // result type
+    __ movptr(result,       c_rarg1); // result
+    __ movptr(call_wrapper, c_rarg0); // call wrapper
 
     // save regs belonging to calling function
-    __ movq(rbx_save, rbx);
-    __ movq(r12_save, r12);
-    __ movq(r13_save, r13);
-    __ movq(r14_save, r14);
-    __ movq(r15_save, r15);
+    __ movptr(rbx_save, rbx);
+    __ movptr(r12_save, r12);
+    __ movptr(r13_save, r13);
+    __ movptr(r14_save, r14);
+    __ movptr(r15_save, r15);
 
 #ifdef _WIN64
     const Address rdi_save(rbp, rdi_off * wordSize);
     const Address rsi_save(rbp, rsi_off * wordSize);
 
-    __ movq(rsi_save, rsi);
-    __ movq(rdi_save, rdi);
+    __ movptr(rsi_save, rsi);
+    __ movptr(rdi_save, rdi);
 #else
     const Address mxcsr_save(rbp, mxcsr_off * wordSize);
     {
@@ -243,7 +244,7 @@
       __ stmxcsr(mxcsr_save);
       __ movl(rax, mxcsr_save);
       __ andl(rax, MXCSR_MASK);    // Only check control and mask bits
-      ExternalAddress mxcsr_std(StubRoutines::amd64::mxcsr_std());
+      ExternalAddress mxcsr_std(StubRoutines::x86::mxcsr_std());
       __ cmp32(rax, mxcsr_std);
       __ jcc(Assembler::equal, skip_ldmx);
       __ ldmxcsr(mxcsr_std);
@@ -252,14 +253,14 @@
 #endif
 
     // Load up thread register
-    __ movq(r15_thread, thread);
+    __ movptr(r15_thread, thread);
     __ reinit_heapbase();
 
 #ifdef ASSERT
     // make sure we have no pending exceptions
     {
       Label L;
-      __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int)NULL_WORD);
+      __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, L);
       __ stop("StubRoutines::call_stub: entered with pending exception");
       __ bind(L);
@@ -274,25 +275,25 @@
     __ jcc(Assembler::zero, parameters_done);
 
     Label loop;
-    __ movq(c_rarg2, parameters);     // parameter pointer
-    __ movl(c_rarg1, c_rarg3);        // parameter counter is in c_rarg1
+    __ movptr(c_rarg2, parameters);       // parameter pointer
+    __ movl(c_rarg1, c_rarg3);            // parameter counter is in c_rarg1
     __ BIND(loop);
     if (TaggedStackInterpreter) {
-      __ movq(rax, Address(c_rarg2, 0)); // get tag
-      __ addq(c_rarg2, wordSize);     // advance to next tag
-      __ pushq(rax);                  // pass tag
+      __ movl(rax, Address(c_rarg2, 0)); // get tag
+      __ addptr(c_rarg2, wordSize);      // advance to next tag
+      __ push(rax);                      // pass tag
     }
-    __ movq(rax, Address(c_rarg2, 0));  // get parameter
-    __ addq(c_rarg2, wordSize);       // advance to next parameter
-    __ decrementl(c_rarg1);           // decrement counter
-    __ pushq(rax);                    // pass parameter
+    __ movptr(rax, Address(c_rarg2, 0));// get parameter
+    __ addptr(c_rarg2, wordSize);       // advance to next parameter
+    __ decrementl(c_rarg1);             // decrement counter
+    __ push(rax);                       // pass parameter
     __ jcc(Assembler::notZero, loop);
 
     // call Java function
     __ BIND(parameters_done);
-    __ movq(rbx, method);             // get methodOop
-    __ movq(c_rarg1, entry_point);    // get entry_point
-    __ movq(r13, rsp);                // set sender sp
+    __ movptr(rbx, method);             // get methodOop
+    __ movptr(c_rarg1, entry_point);    // get entry_point
+    __ mov(r13, rsp);                   // set sender sp
     BLOCK_COMMENT("call Java function");
     __ call(c_rarg1);
 
@@ -301,7 +302,7 @@
 
     // store result depending on type (everything that is not
     // T_OBJECT, T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
-    __ movq(c_rarg0, result);
+    __ movptr(c_rarg0, result);
     Label is_long, is_float, is_double, exit;
     __ movl(c_rarg1, result_type);
     __ cmpl(c_rarg1, T_OBJECT);
@@ -319,16 +320,16 @@
     __ BIND(exit);
 
     // pop parameters
-    __ leaq(rsp, rsp_after_call);
+    __ lea(rsp, rsp_after_call);
 
 #ifdef ASSERT
     // verify that threads correspond
     {
       Label L, S;
-      __ cmpq(r15_thread, thread);
+      __ cmpptr(r15_thread, thread);
       __ jcc(Assembler::notEqual, S);
       __ get_thread(rbx);
-      __ cmpq(r15_thread, rbx);
+      __ cmpptr(r15_thread, rbx);
       __ jcc(Assembler::equal, L);
       __ bind(S);
       __ jcc(Assembler::equal, L);
@@ -338,24 +339,24 @@
 #endif
 
     // restore regs belonging to calling function
-    __ movq(r15, r15_save);
-    __ movq(r14, r14_save);
-    __ movq(r13, r13_save);
-    __ movq(r12, r12_save);
-    __ movq(rbx, rbx_save);
+    __ movptr(r15, r15_save);
+    __ movptr(r14, r14_save);
+    __ movptr(r13, r13_save);
+    __ movptr(r12, r12_save);
+    __ movptr(rbx, rbx_save);
 
 #ifdef _WIN64
-    __ movq(rdi, rdi_save);
-    __ movq(rsi, rsi_save);
+    __ movptr(rdi, rdi_save);
+    __ movptr(rsi, rsi_save);
 #else
     __ ldmxcsr(mxcsr_save);
 #endif
 
     // restore rsp
-    __ addq(rsp, -rsp_after_call_off * wordSize);
+    __ addptr(rsp, -rsp_after_call_off * wordSize);
 
     // return
-    __ popq(rbp);
+    __ pop(rbp);
     __ ret(0);
 
     // handle return types different from T_INT
@@ -398,10 +399,10 @@
     // verify that threads correspond
     {
       Label L, S;
-      __ cmpq(r15_thread, thread);
+      __ cmpptr(r15_thread, thread);
       __ jcc(Assembler::notEqual, S);
       __ get_thread(rbx);
-      __ cmpq(r15_thread, rbx);
+      __ cmpptr(r15_thread, rbx);
       __ jcc(Assembler::equal, L);
       __ bind(S);
       __ stop("StubRoutines::catch_exception: threads must correspond");
@@ -412,9 +413,9 @@
     // set pending exception
     __ verify_oop(rax);
 
-    __ movq(Address(r15_thread, Thread::pending_exception_offset()), rax);
+    __ movptr(Address(r15_thread, Thread::pending_exception_offset()), rax);
     __ lea(rscratch1, ExternalAddress((address)__FILE__));
-    __ movq(Address(r15_thread, Thread::exception_file_offset()), rscratch1);
+    __ movptr(Address(r15_thread, Thread::exception_file_offset()), rscratch1);
     __ movl(Address(r15_thread, Thread::exception_line_offset()), (int)  __LINE__);
 
     // complete return to VM
@@ -453,7 +454,7 @@
     // make sure this code is only executed if there is a pending exception
     {
       Label L;
-      __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int) NULL);
+      __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t) NULL);
       __ jcc(Assembler::notEqual, L);
       __ stop("StubRoutines::forward exception: no pending exception (1)");
       __ bind(L);
@@ -461,23 +462,23 @@
 #endif
 
     // compute exception handler into rbx
-    __ movq(c_rarg0, Address(rsp, 0));
+    __ movptr(c_rarg0, Address(rsp, 0));
     BLOCK_COMMENT("call exception_handler_for_return_address");
     __ call_VM_leaf(CAST_FROM_FN_PTR(address,
                          SharedRuntime::exception_handler_for_return_address),
                     c_rarg0);
-    __ movq(rbx, rax);
+    __ mov(rbx, rax);
 
     // setup rax & rdx, remove return address & clear pending exception
-    __ popq(rdx);
-    __ movq(rax, Address(r15_thread, Thread::pending_exception_offset()));
+    __ pop(rdx);
+    __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
     __ movptr(Address(r15_thread, Thread::pending_exception_offset()), (int)NULL_WORD);
 
 #ifdef ASSERT
     // make sure exception is set
     {
       Label L;
-      __ testq(rax, rax);
+      __ testptr(rax, rax);
       __ jcc(Assembler::notEqual, L);
       __ stop("StubRoutines::forward exception: no pending exception (2)");
       __ bind(L);
@@ -525,8 +526,8 @@
     StubCodeMark mark(this, "StubRoutines", "atomic_xchg_ptr");
     address start = __ pc();
 
-    __ movq(rax, c_rarg0); // Copy to eax we need a return value anyhow
-    __ xchgq(rax, Address(c_rarg1, 0)); // automatic LOCK
+    __ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow
+    __ xchgptr(rax, Address(c_rarg1, 0)); // automatic LOCK
     __ ret(0);
 
     return start;
@@ -619,10 +620,10 @@
     StubCodeMark mark(this, "StubRoutines", "atomic_add_ptr");
     address start = __ pc();
 
-    __ movq(rax, c_rarg0); // Copy to eax we need a return value anyhow
+    __ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow
    if ( os::is_MP() ) __ lock();
-    __ xaddl(Address(c_rarg1, 0), c_rarg0);
-    __ addl(rax, c_rarg0);
+    __ xaddptr(Address(c_rarg1, 0), c_rarg0);
+    __ addptr(rax, c_rarg0);
     __ ret(0);
 
     return start;
@@ -655,9 +656,9 @@
     address start = __ pc();
 
     __ enter();
-    __ movq(rax, old_fp); // callers fp
-    __ movq(rax, older_fp); // the frame for ps()
-    __ popq(rbp);
+    __ movptr(rax, old_fp); // callers fp
+    __ movptr(rax, older_fp); // the frame for ps()
+    __ pop(rbp);
     __ ret(0);
 
     return start;
@@ -678,21 +679,21 @@
 
     if (CheckJNICalls) {
       Label ok_ret;
-      __ pushq(rax);
-      __ subq(rsp, wordSize);      // allocate a temp location
+      __ push(rax);
+      __ subptr(rsp, wordSize);      // allocate a temp location
       __ stmxcsr(mxcsr_save);
       __ movl(rax, mxcsr_save);
       __ andl(rax, MXCSR_MASK);    // Only check control and mask bits
-      __ cmpl(rax, *(int *)(StubRoutines::amd64::mxcsr_std()));
+      __ cmpl(rax, *(int *)(StubRoutines::x86::mxcsr_std()));
       __ jcc(Assembler::equal, ok_ret);
 
       __ warn("MXCSR changed by native JNI code, use -XX:+RestoreMXCSROnJNICall");
 
-      __ ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
+      __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
 
       __ bind(ok_ret);
-      __ addq(rsp, wordSize);
-      __ popq(rax);
+      __ addptr(rsp, wordSize);
+      __ pop(rax);
     }
 
     __ ret(0);
@@ -708,10 +709,10 @@
 
     Label L;
 
-    __ pushq(rax);
-    __ pushq(c_rarg3);
-    __ pushq(c_rarg2);
-    __ pushq(c_rarg1);
+    __ push(rax);
+    __ push(c_rarg3);
+    __ push(c_rarg2);
+    __ push(c_rarg1);
 
     __ movl(rax, 0x7f800000);
     __ xorl(c_rarg3, c_rarg3);
@@ -726,12 +727,12 @@
     __ cmovl(Assembler::positive, c_rarg3, rax);
 
     __ bind(L);
-    __ movq(inout, c_rarg3);
-
-    __ popq(c_rarg1);
-    __ popq(c_rarg2);
-    __ popq(c_rarg3);
-    __ popq(rax);
+    __ movptr(inout, c_rarg3);
+
+    __ pop(c_rarg1);
+    __ pop(c_rarg2);
+    __ pop(c_rarg3);
+    __ pop(rax);
 
     __ ret(0);
 
@@ -745,10 +746,10 @@
 
     Label L;
 
-    __ pushq(rax);
-    __ pushq(c_rarg3);
-    __ pushq(c_rarg2);
-    __ pushq(c_rarg1);
+    __ push(rax);
+    __ push(c_rarg3);
+    __ push(c_rarg2);
+    __ push(c_rarg1);
 
     __ movl(rax, 0x7f800000);
     __ xorl(c_rarg3, c_rarg3);
@@ -760,15 +761,15 @@
     __ testl(c_rarg2, c_rarg2); // signed ? min_jlong : max_jlong
     __ mov64(c_rarg3, 0x8000000000000000);
     __ mov64(rax, 0x7fffffffffffffff);
-    __ cmovq(Assembler::positive, c_rarg3, rax);
+    __ cmov(Assembler::positive, c_rarg3, rax);
 
     __ bind(L);
-    __ movq(inout, c_rarg3);
-
-    __ popq(c_rarg1);
-    __ popq(c_rarg2);
-    __ popq(c_rarg3);
-    __ popq(rax);
+    __ movptr(inout, c_rarg3);
+
+    __ pop(c_rarg1);
+    __ pop(c_rarg2);
+    __ pop(c_rarg3);
+    __ pop(rax);
 
     __ ret(0);
 
@@ -783,19 +784,19 @@
 
     Label L;
 
-    __ pushq(rax);
-    __ pushq(c_rarg3);
-    __ pushq(c_rarg2);
-    __ pushq(c_rarg1);
-    __ pushq(c_rarg0);
+    __ push(rax);
+    __ push(c_rarg3);
+    __ push(c_rarg2);
+    __ push(c_rarg1);
+    __ push(c_rarg0);
 
     __ movl(rax, 0x7ff00000);
     __ movq(c_rarg2, inout);
     __ movl(c_rarg3, c_rarg2);
-    __ movq(c_rarg1, c_rarg2);
-    __ movq(c_rarg0, c_rarg2);
+    __ mov(c_rarg1, c_rarg2);
+    __ mov(c_rarg0, c_rarg2);
     __ negl(c_rarg3);
-    __ shrq(c_rarg1, 0x20);
+    __ shrptr(c_rarg1, 0x20);
     __ orl(c_rarg3, c_rarg2);
     __ andl(c_rarg1, 0x7fffffff);
     __ xorl(c_rarg2, c_rarg2);
@@ -803,19 +804,19 @@
     __ orl(c_rarg1, c_rarg3);
     __ cmpl(rax, c_rarg1);
     __ jcc(Assembler::negative, L); // NaN -> 0
-    __ testq(c_rarg0, c_rarg0); // signed ? min_jint : max_jint
+    __ testptr(c_rarg0, c_rarg0); // signed ? min_jint : max_jint
     __ movl(c_rarg2, 0x80000000);
     __ movl(rax, 0x7fffffff);
-    __ cmovl(Assembler::positive, c_rarg2, rax);
+    __ cmov(Assembler::positive, c_rarg2, rax);
 
     __ bind(L);
-    __ movq(inout, c_rarg2);
-
-    __ popq(c_rarg0);
-    __ popq(c_rarg1);
-    __ popq(c_rarg2);
-    __ popq(c_rarg3);
-    __ popq(rax);
+    __ movptr(inout, c_rarg2);
+
+    __ pop(c_rarg0);
+    __ pop(c_rarg1);
+    __ pop(c_rarg2);
+    __ pop(c_rarg3);
+    __ pop(rax);
 
     __ ret(0);
 
@@ -830,19 +831,19 @@
 
     Label L;
 
-    __ pushq(rax);
-    __ pushq(c_rarg3);
-    __ pushq(c_rarg2);
-    __ pushq(c_rarg1);
-    __ pushq(c_rarg0);
+    __ push(rax);
+    __ push(c_rarg3);
+    __ push(c_rarg2);
+    __ push(c_rarg1);
+    __ push(c_rarg0);
 
     __ movl(rax, 0x7ff00000);
     __ movq(c_rarg2, inout);
     __ movl(c_rarg3, c_rarg2);
-    __ movq(c_rarg1, c_rarg2);
-    __ movq(c_rarg0, c_rarg2);
+    __ mov(c_rarg1, c_rarg2);
+    __ mov(c_rarg0, c_rarg2);
     __ negl(c_rarg3);
-    __ shrq(c_rarg1, 0x20);
+    __ shrptr(c_rarg1, 0x20);
     __ orl(c_rarg3, c_rarg2);
     __ andl(c_rarg1, 0x7fffffff);
     __ xorl(c_rarg2, c_rarg2);
@@ -858,11 +859,11 @@
     __ bind(L);
     __ movq(inout, c_rarg2);
 
-    __ popq(c_rarg0);
-    __ popq(c_rarg1);
-    __ popq(c_rarg2);
-    __ popq(c_rarg3);
-    __ popq(rax);
+    __ pop(c_rarg0);
+    __ pop(c_rarg1);
+    __ pop(c_rarg2);
+    __ pop(c_rarg3);
+    __ pop(rax);
 
     __ ret(0);
 
@@ -889,17 +890,17 @@
     StubCodeMark mark(this, "StubRoutines", "handler_for_unsafe_access");
     address start = __ pc();
 
-    __ pushq(0);                      // hole for return address-to-be
-    __ pushaq();                      // push registers
+    __ push(0);                       // hole for return address-to-be
+    __ pusha();                       // push registers
     Address next_pc(rsp, RegisterImpl::number_of_registers * BytesPerWord);
 
-    __ subq(rsp, frame::arg_reg_save_area_bytes);
+    __ subptr(rsp, frame::arg_reg_save_area_bytes);
     BLOCK_COMMENT("call handle_unsafe_access");
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, handle_unsafe_access)));
-    __ addq(rsp, frame::arg_reg_save_area_bytes);
-
-    __ movq(next_pc, rax);            // stuff next address
-    __ popaq();
+    __ addptr(rsp, frame::arg_reg_save_area_bytes);
+
+    __ movptr(next_pc, rax);          // stuff next address
+    __ popa();
     __ ret(0);                        // jump to next address
 
     return start;
@@ -926,14 +927,14 @@
 
     Label exit, error;
 
-    __ pushfq();
+    __ pushf();
     __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
 
-    __ pushq(r12);
+    __ push(r12);
 
     // save c_rarg2 and c_rarg3
-    __ pushq(c_rarg2);
-    __ pushq(c_rarg3);
+    __ push(c_rarg2);
+    __ push(c_rarg3);
 
     enum {
            // After previous pushes.
@@ -946,17 +947,17 @@
     };
 
     // get object
-    __ movq(rax, Address(rsp, oop_to_verify));
+    __ movptr(rax, Address(rsp, oop_to_verify));
 
     // make sure object is 'reasonable'
-    __ testq(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, exit); // if obj is NULL it is OK
     // Check if the oop is in the right area of memory
-    __ movq(c_rarg2, rax);
+    __ movptr(c_rarg2, rax);
     __ movptr(c_rarg3, (int64_t) Universe::verify_oop_mask());
-    __ andq(c_rarg2, c_rarg3);
+    __ andptr(c_rarg2, c_rarg3);
     __ movptr(c_rarg3, (int64_t) Universe::verify_oop_bits());
-    __ cmpq(c_rarg2, c_rarg3);
+    __ cmpptr(c_rarg2, c_rarg3);
     __ jcc(Assembler::notZero, error);
 
     // set r12 to heapbase for load_klass()
@@ -964,46 +965,46 @@
 
     // make sure klass is 'reasonable'
     __ load_klass(rax, rax);  // get klass
-    __ testq(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, error); // if klass is NULL it is broken
     // Check if the klass is in the right area of memory
-    __ movq(c_rarg2, rax);
+    __ mov(c_rarg2, rax);
     __ movptr(c_rarg3, (int64_t) Universe::verify_klass_mask());
-    __ andq(c_rarg2, c_rarg3);
+    __ andptr(c_rarg2, c_rarg3);
     __ movptr(c_rarg3, (int64_t) Universe::verify_klass_bits());
-    __ cmpq(c_rarg2, c_rarg3);
+    __ cmpptr(c_rarg2, c_rarg3);
     __ jcc(Assembler::notZero, error);
 
     // make sure klass' klass is 'reasonable'
     __ load_klass(rax, rax);
-    __ testq(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, error); // if klass' klass is NULL it is broken
     // Check if the klass' klass is in the right area of memory
     __ movptr(c_rarg3, (int64_t) Universe::verify_klass_mask());
-    __ andq(rax, c_rarg3);
+    __ andptr(rax, c_rarg3);
     __ movptr(c_rarg3, (int64_t) Universe::verify_klass_bits());
-    __ cmpq(rax, c_rarg3);
+    __ cmpptr(rax, c_rarg3);
     __ jcc(Assembler::notZero, error);
 
     // return if everything seems ok
     __ bind(exit);
-    __ movq(rax, Address(rsp, saved_rax));       // get saved rax back
-    __ popq(c_rarg3);                            // restore c_rarg3
-    __ popq(c_rarg2);                            // restore c_rarg2
-    __ popq(r12);                                // restore r12
-    __ popfq();                                  // restore flags
+    __ movptr(rax, Address(rsp, saved_rax));     // get saved rax back
+    __ pop(c_rarg3);                             // restore c_rarg3
+    __ pop(c_rarg2);                             // restore c_rarg2
+    __ pop(r12);                                 // restore r12
+    __ popf();                                   // restore flags
     __ ret(3 * wordSize);                        // pop caller saved stuff
 
     // handle errors
     __ bind(error);
-    __ movq(rax, Address(rsp, saved_rax));       // get saved rax back
-    __ popq(c_rarg3);                            // get saved c_rarg3 back
-    __ popq(c_rarg2);                            // get saved c_rarg2 back
-    __ popq(r12);                                // get saved r12 back
-    __ popfq();                                  // get saved flags off stack --
+    __ movptr(rax, Address(rsp, saved_rax));     // get saved rax back
+    __ pop(c_rarg3);                             // get saved c_rarg3 back
+    __ pop(c_rarg2);                             // get saved c_rarg2 back
+    __ pop(r12);                                 // get saved r12 back
+    __ popf();                                   // get saved flags off stack --
                                                  // will be ignored
 
-    __ pushaq();                                 // push registers
+    __ pusha();                                  // push registers
                                                  // (rip is already
                                                  // already pushed)
     // debug(char* msg, int64_t pc, int64_t regs[])
@@ -1016,17 +1017,17 @@
     //   * [tos + 19] saved rax - saved by caller and bashed
     //   * = popped on exit
 
-    __ movq(c_rarg0, Address(rsp, error_msg));   // pass address of error message
-    __ movq(c_rarg1, Address(rsp, return_addr)); // pass return address
-    __ movq(c_rarg2, rsp);                       // pass address of regs on stack
-    __ movq(r12, rsp);                           // remember rsp
-    __ subq(rsp, frame::arg_reg_save_area_bytes);// windows
-    __ andq(rsp, -16);                           // align stack as required by ABI
+    __ movptr(c_rarg0, Address(rsp, error_msg));    // pass address of error message
+    __ movptr(c_rarg1, Address(rsp, return_addr));  // pass return address
+    __ movq(c_rarg2, rsp);                          // pass address of regs on stack
+    __ mov(r12, rsp);                               // remember rsp
+    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rsp, -16);                            // align stack as required by ABI
     BLOCK_COMMENT("call MacroAssembler::debug");
-    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
-    __ movq(rsp, r12);                           // restore rsp
-    __ popaq();                                  // pop registers (includes r12)
-    __ ret(3 * wordSize);                        // pop caller saved stuff
+    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
+    __ mov(rsp, r12);                               // restore rsp
+    __ popa();                                      // pop registers (includes r12)
+    __ ret(3 * wordSize);                           // pop caller saved stuff
 
     return start;
   }
@@ -1088,16 +1089,16 @@
     const Register count    = c_rarg2;
     const Register end_from = rax;
 
-    __ cmpq(to, from);
-    __ leaq(end_from, Address(from, count, sf, 0));
+    __ cmpptr(to, from);
+    __ lea(end_from, Address(from, count, sf, 0));
     if (NOLp == NULL) {
       ExternalAddress no_overlap(no_overlap_target);
       __ jump_cc(Assembler::belowEqual, no_overlap);
-      __ cmpq(to, end_from);
+      __ cmpptr(to, end_from);
       __ jump_cc(Assembler::aboveEqual, no_overlap);
     } else {
       __ jcc(Assembler::belowEqual, (*NOLp));
-      __ cmpq(to, end_from);
+      __ cmpptr(to, end_from);
       __ jcc(Assembler::aboveEqual, (*NOLp));
     }
   }
@@ -1121,14 +1122,14 @@
     assert(c_rarg0 == rcx && c_rarg1 == rdx && c_rarg2 == r8 && c_rarg3 == r9,
            "unexpected argument registers");
     if (nargs >= 4)
-      __ movq(rax, r9);  // r9 is also saved_rdi
-    __ movq(saved_rdi, rdi);
-    __ movq(saved_rsi, rsi);
-    __ movq(rdi, rcx); // c_rarg0
-    __ movq(rsi, rdx); // c_rarg1
-    __ movq(rdx, r8);  // c_rarg2
+      __ mov(rax, r9);  // r9 is also saved_rdi
+    __ movptr(saved_rdi, rdi);
+    __ movptr(saved_rsi, rsi);
+    __ mov(rdi, rcx); // c_rarg0
+    __ mov(rsi, rdx); // c_rarg1
+    __ mov(rdx, r8);  // c_rarg2
     if (nargs >= 4)
-      __ movq(rcx, rax); // c_rarg3 (via rax)
+      __ mov(rcx, rax); // c_rarg3 (via rax)
 #else
     assert(c_rarg0 == rdi && c_rarg1 == rsi && c_rarg2 == rdx && c_rarg3 == rcx,
            "unexpected argument registers");
@@ -1139,8 +1140,8 @@
     const Register saved_rdi = r9;
     const Register saved_rsi = r10;
 #ifdef _WIN64
-    __ movq(rdi, saved_rdi);
-    __ movq(rsi, saved_rsi);
+    __ movptr(rdi, saved_rdi);
+    __ movptr(rsi, saved_rsi);
 #endif
   }
 
@@ -1160,11 +1161,11 @@
       case BarrierSet::G1SATBCT:
       case BarrierSet::G1SATBCTLogging:
         {
-          __ pushaq();                      // push registers
-          __ movq(c_rarg0, addr);
-          __ movq(c_rarg1, count);
+          __ pusha();                      // push registers
+          __ movptr(c_rarg0, addr);
+          __ movptr(c_rarg1, count);
           __ call(RuntimeAddress(BarrierSet::static_write_ref_array_pre));
-          __ popaq();
+          __ popa();
         }
         break;
       case BarrierSet::CardTableModRef:
@@ -1197,16 +1198,16 @@
       case BarrierSet::G1SATBCTLogging:
 
         {
-          __ pushaq();                      // push registers (overkill)
+          __ pusha();                      // push registers (overkill)
           // must compute element count unless barrier set interface is changed (other platforms supply count)
           assert_different_registers(start, end, scratch);
-          __ leaq(scratch, Address(end, wordSize));
-          __ subq(scratch, start);
-          __ shrq(scratch, LogBytesPerWord);
-          __ movq(c_rarg0, start);
-          __ movq(c_rarg1, scratch);
+          __ lea(scratch, Address(end, wordSize));
+          __ subptr(scratch, start);
+          __ shrptr(scratch, LogBytesPerWord);
+          __ mov(c_rarg0, start);
+          __ mov(c_rarg1, scratch);
           __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post));
-          __ popaq();
+          __ popa();
         }
         break;
 #endif // 0 G1 - only
@@ -1218,9 +1219,9 @@
 
           Label L_loop;
 
-           __ shrq(start, CardTableModRefBS::card_shift);
-           __ shrq(end, CardTableModRefBS::card_shift);
-           __ subq(end, start); // number of bytes to copy
+           __ shrptr(start, CardTableModRefBS::card_shift);
+           __ shrptr(end, CardTableModRefBS::card_shift);
+           __ subptr(end, start); // number of bytes to copy
 
           intptr_t disp = (intptr_t) ct->byte_map_base;
           if (__ is_simm32(disp)) {
@@ -1232,10 +1233,10 @@
           }
 
           const Register count = end; // 'end' register contains bytes count now
-          __ addq(start, scratch);
+          __ addptr(start, scratch);
         __ BIND(L_loop);
           __ movb(Address(start, count, Address::times_1), 0);
-          __ decrementq(count);
+          __ decrement(count);
           __ jcc(Assembler::greaterEqual, L_loop);
         }
       }
@@ -1267,9 +1268,9 @@
     __ movq(to, Address(end_from, qword_count, Address::times_8, - 0));
     __ movq(Address(end_to, qword_count, Address::times_8, - 0), to);
   __ BIND(L_copy_32_bytes);
-    __ addq(qword_count, 4);
+    __ addptr(qword_count, 4);
     __ jcc(Assembler::lessEqual, L_loop);
-    __ subq(qword_count, 4);
+    __ subptr(qword_count, 4);
     __ jcc(Assembler::less, L_copy_8_bytes); // Copy trailing qwords
   }
 
@@ -1300,9 +1301,9 @@
     __ movq(to, Address(from, qword_count, Address::times_8,  0));
     __ movq(Address(dest, qword_count, Address::times_8,  0), to);
   __ BIND(L_copy_32_bytes);
-    __ subq(qword_count, 4);
+    __ subptr(qword_count, 4);
     __ jcc(Assembler::greaterEqual, L_loop);
-    __ addq(qword_count, 4);
+    __ addptr(qword_count, 4);
     __ jcc(Assembler::greater, L_copy_8_bytes); // Copy trailing qwords
   }
 
@@ -1354,45 +1355,45 @@
                       // r9 and r10 may be used to save non-volatile registers
 
     // 'from', 'to' and 'count' are now valid
-    __ movq(byte_count, count);
-    __ shrq(count, 3); // count => qword_count
+    __ movptr(byte_count, count);
+    __ shrptr(count, 3); // count => qword_count
 
     // Copy from low to high addresses.  Use 'to' as scratch.
-    __ leaq(end_from, Address(from, qword_count, Address::times_8, -8));
-    __ leaq(end_to,   Address(to,   qword_count, Address::times_8, -8));
-    __ negq(qword_count); // make the count negative
+    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
+    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
+    __ negptr(qword_count); // make the count negative
     __ jmp(L_copy_32_bytes);
 
     // Copy trailing qwords
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
     __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
-    __ incrementq(qword_count);
+    __ increment(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     // Check for and copy trailing dword
   __ BIND(L_copy_4_bytes);
-    __ testq(byte_count, 4);
+    __ testl(byte_count, 4);
     __ jccb(Assembler::zero, L_copy_2_bytes);
     __ movl(rax, Address(end_from, 8));
     __ movl(Address(end_to, 8), rax);
 
-    __ addq(end_from, 4);
-    __ addq(end_to, 4);
+    __ addptr(end_from, 4);
+    __ addptr(end_to, 4);
 
     // Check for and copy trailing word
   __ BIND(L_copy_2_bytes);
-    __ testq(byte_count, 2);
+    __ testl(byte_count, 2);
     __ jccb(Assembler::zero, L_copy_byte);
     __ movw(rax, Address(end_from, 8));
     __ movw(Address(end_to, 8), rax);
 
-    __ addq(end_from, 2);
-    __ addq(end_to, 2);
+    __ addptr(end_from, 2);
+    __ addptr(end_to, 2);
 
     // Check for and copy trailing byte
   __ BIND(L_copy_byte);
-    __ testq(byte_count, 1);
+    __ testl(byte_count, 1);
     __ jccb(Assembler::zero, L_exit);
     __ movb(rax, Address(end_from, 8));
     __ movb(Address(end_to, 8), rax);
@@ -1400,7 +1401,7 @@
   __ BIND(L_exit);
     inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1450,28 +1451,28 @@
                       // r9 and r10 may be used to save non-volatile registers
 
     // 'from', 'to' and 'count' are now valid
-    __ movq(byte_count, count);
-    __ shrq(count, 3);   // count => qword_count
+    __ movptr(byte_count, count);
+    __ shrptr(count, 3);   // count => qword_count
 
     // Copy from high to low addresses.
 
     // Check for and copy trailing byte
-    __ testq(byte_count, 1);
+    __ testl(byte_count, 1);
     __ jcc(Assembler::zero, L_copy_2_bytes);
     __ movb(rax, Address(from, byte_count, Address::times_1, -1));
     __ movb(Address(to, byte_count, Address::times_1, -1), rax);
-    __ decrementq(byte_count); // Adjust for possible trailing word
+    __ decrement(byte_count); // Adjust for possible trailing word
 
     // Check for and copy trailing word
   __ BIND(L_copy_2_bytes);
-    __ testq(byte_count, 2);
+    __ testl(byte_count, 2);
     __ jcc(Assembler::zero, L_copy_4_bytes);
     __ movw(rax, Address(from, byte_count, Address::times_1, -2));
     __ movw(Address(to, byte_count, Address::times_1, -2), rax);
 
     // Check for and copy trailing dword
   __ BIND(L_copy_4_bytes);
-    __ testq(byte_count, 4);
+    __ testl(byte_count, 4);
     __ jcc(Assembler::zero, L_copy_32_bytes);
     __ movl(rax, Address(from, qword_count, Address::times_8));
     __ movl(Address(to, qword_count, Address::times_8), rax);
@@ -1481,12 +1482,12 @@
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(from, qword_count, Address::times_8, -8));
     __ movq(Address(to, qword_count, Address::times_8, -8), rax);
-    __ decrementq(qword_count);
+    __ decrement(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1495,7 +1496,7 @@
 
     inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1548,20 +1549,20 @@
                       // r9 and r10 may be used to save non-volatile registers
 
     // 'from', 'to' and 'count' are now valid
-    __ movq(word_count, count);
-    __ shrq(count, 2); // count => qword_count
+    __ movptr(word_count, count);
+    __ shrptr(count, 2); // count => qword_count
 
     // Copy from low to high addresses.  Use 'to' as scratch.
-    __ leaq(end_from, Address(from, qword_count, Address::times_8, -8));
-    __ leaq(end_to,   Address(to,   qword_count, Address::times_8, -8));
-    __ negq(qword_count);
+    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
+    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
+    __ negptr(qword_count);
     __ jmp(L_copy_32_bytes);
 
     // Copy trailing qwords
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
     __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
-    __ incrementq(qword_count);
+    __ increment(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     // Original 'dest' is trashed, so we can't use it as a
@@ -1569,17 +1570,17 @@
 
     // Check for and copy trailing dword
   __ BIND(L_copy_4_bytes);
-    __ testq(word_count, 2);
+    __ testl(word_count, 2);
     __ jccb(Assembler::zero, L_copy_2_bytes);
     __ movl(rax, Address(end_from, 8));
     __ movl(Address(end_to, 8), rax);
 
-    __ addq(end_from, 4);
-    __ addq(end_to, 4);
+    __ addptr(end_from, 4);
+    __ addptr(end_to, 4);
 
     // Check for and copy trailing word
   __ BIND(L_copy_2_bytes);
-    __ testq(word_count, 1);
+    __ testl(word_count, 1);
     __ jccb(Assembler::zero, L_exit);
     __ movw(rax, Address(end_from, 8));
     __ movw(Address(end_to, 8), rax);
@@ -1587,7 +1588,7 @@
   __ BIND(L_exit);
     inc_counter_np(SharedRuntime::_jshort_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1637,20 +1638,20 @@
                       // r9 and r10 may be used to save non-volatile registers
 
     // 'from', 'to' and 'count' are now valid
-    __ movq(word_count, count);
-    __ shrq(count, 2); // count => qword_count
+    __ movptr(word_count, count);
+    __ shrptr(count, 2); // count => qword_count
 
     // Copy from high to low addresses.  Use 'to' as scratch.
 
     // Check for and copy trailing word
-    __ testq(word_count, 1);
+    __ testl(word_count, 1);
     __ jccb(Assembler::zero, L_copy_4_bytes);
     __ movw(rax, Address(from, word_count, Address::times_2, -2));
     __ movw(Address(to, word_count, Address::times_2, -2), rax);
 
     // Check for and copy trailing dword
   __ BIND(L_copy_4_bytes);
-    __ testq(word_count, 2);
+    __ testl(word_count, 2);
     __ jcc(Assembler::zero, L_copy_32_bytes);
     __ movl(rax, Address(from, qword_count, Address::times_8));
     __ movl(Address(to, qword_count, Address::times_8), rax);
@@ -1660,12 +1661,12 @@
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(from, qword_count, Address::times_8, -8));
     __ movq(Address(to, qword_count, Address::times_8, -8), rax);
-    __ decrementq(qword_count);
+    __ decrement(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     inc_counter_np(SharedRuntime::_jshort_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1674,7 +1675,7 @@
 
     inc_counter_np(SharedRuntime::_jshort_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1738,25 +1739,25 @@
     }
 
     // 'from', 'to' and 'count' are now valid
-    __ movq(dword_count, count);
-    __ shrq(count, 1); // count => qword_count
+    __ movptr(dword_count, count);
+    __ shrptr(count, 1); // count => qword_count
 
     // Copy from low to high addresses.  Use 'to' as scratch.
-    __ leaq(end_from, Address(from, qword_count, Address::times_8, -8));
-    __ leaq(end_to,   Address(to,   qword_count, Address::times_8, -8));
-    __ negq(qword_count);
+    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
+    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
+    __ negptr(qword_count);
     __ jmp(L_copy_32_bytes);
 
     // Copy trailing qwords
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
     __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
-    __ incrementq(qword_count);
+    __ increment(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     // Check for and copy trailing dword
   __ BIND(L_copy_4_bytes);
-    __ testq(dword_count, 1); // Only byte test since the value is 0 or 1
+    __ testl(dword_count, 1); // Only byte test since the value is 0 or 1
     __ jccb(Assembler::zero, L_exit);
     __ movl(rax, Address(end_from, 8));
     __ movl(Address(end_to, 8), rax);
@@ -1768,7 +1769,7 @@
     }
     inc_counter_np(SharedRuntime::_jint_array_copy_ctr);
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1825,13 +1826,13 @@
 
     assert_clean_int(count, rax); // Make sure 'count' is clean int.
     // 'from', 'to' and 'count' are now valid
-    __ movq(dword_count, count);
-    __ shrq(count, 1); // count => qword_count
+    __ movptr(dword_count, count);
+    __ shrptr(count, 1); // count => qword_count
 
     // Copy from high to low addresses.  Use 'to' as scratch.
 
     // Check for and copy trailing dword
-    __ testq(dword_count, 1);
+    __ testl(dword_count, 1);
     __ jcc(Assembler::zero, L_copy_32_bytes);
     __ movl(rax, Address(from, dword_count, Address::times_4, -4));
     __ movl(Address(to, dword_count, Address::times_4, -4), rax);
@@ -1841,7 +1842,7 @@
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(from, qword_count, Address::times_8, -8));
     __ movq(Address(to, qword_count, Address::times_8, -8), rax);
-    __ decrementq(qword_count);
+    __ decrement(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     inc_counter_np(SharedRuntime::_jint_array_copy_ctr);
@@ -1849,7 +1850,7 @@
       __ jmp(L_exit);
     }
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1864,7 +1865,7 @@
        gen_write_ref_array_post_barrier(to, end_to, rax);
      }
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -1921,16 +1922,16 @@
     // 'from', 'to' and 'qword_count' are now valid
 
     // Copy from low to high addresses.  Use 'to' as scratch.
-    __ leaq(end_from, Address(from, qword_count, Address::times_8, -8));
-    __ leaq(end_to,   Address(to,   qword_count, Address::times_8, -8));
-    __ negq(qword_count);
+    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
+    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
+    __ negptr(qword_count);
     __ jmp(L_copy_32_bytes);
 
     // Copy trailing qwords
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
     __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
-    __ incrementq(qword_count);
+    __ increment(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     if (is_oop) {
@@ -1938,7 +1939,7 @@
     } else {
       inc_counter_np(SharedRuntime::_jlong_array_copy_ctr);
       restore_arg_regs();
-      __ xorq(rax, rax); // return 0
+      __ xorptr(rax, rax); // return 0
       __ leave(); // required for proper stackwalking of RuntimeStub frame
       __ ret(0);
     }
@@ -1954,7 +1955,7 @@
       inc_counter_np(SharedRuntime::_jlong_array_copy_ctr);
     }
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -2008,7 +2009,7 @@
 
     if (is_oop) {
       // Save to and count for store barrier
-      __ movq(saved_count, qword_count);
+      __ movptr(saved_count, qword_count);
       // No registers are destroyed by this call
       gen_write_ref_array_pre_barrier(to, saved_count);
     }
@@ -2019,7 +2020,7 @@
   __ BIND(L_copy_8_bytes);
     __ movq(rax, Address(from, qword_count, Address::times_8, -8));
     __ movq(Address(to, qword_count, Address::times_8, -8), rax);
-    __ decrementq(qword_count);
+    __ decrement(qword_count);
     __ jcc(Assembler::notZero, L_copy_8_bytes);
 
     if (is_oop) {
@@ -2027,7 +2028,7 @@
     } else {
       inc_counter_np(SharedRuntime::_jlong_array_copy_ctr);
       restore_arg_regs();
-      __ xorq(rax, rax); // return 0
+      __ xorptr(rax, rax); // return 0
       __ leave(); // required for proper stackwalking of RuntimeStub frame
       __ ret(0);
     }
@@ -2037,14 +2038,14 @@
 
     if (is_oop) {
     __ BIND(L_exit);
-      __ leaq(rcx, Address(to, saved_count, Address::times_8, -8));
+      __ lea(rcx, Address(to, saved_count, Address::times_8, -8));
       gen_write_ref_array_post_barrier(to, rcx, rax);
       inc_counter_np(SharedRuntime::_oop_array_copy_ctr);
     } else {
       inc_counter_np(SharedRuntime::_jlong_array_copy_ctr);
     }
     restore_arg_regs();
-    __ xorq(rax, rax); // return 0
+    __ xorptr(rax, rax); // return 0
     __ leave(); // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -2073,12 +2074,12 @@
     Address super_cache_addr(     sub_klass, sc_offset);
 
     // if the pointers are equal, we are done (e.g., String[] elements)
-    __ cmpq(super_klass, sub_klass);
+    __ cmpptr(super_klass, sub_klass);
     __ jcc(Assembler::equal, L_success);
 
     // check the supertype display:
     Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
-    __ cmpq(super_klass, super_check_addr); // test the super type
+    __ cmpptr(super_klass, super_check_addr); // test the super type
     __ jcc(Assembler::equal, L_success);
 
     // if it was a primary super, we can just fail immediately
@@ -2091,38 +2092,38 @@
     // This code is rarely used, so simplicity is a virtue here.
     inc_counter_np(SharedRuntime::_partial_subtype_ctr);
     {
-      __ pushq(rax);
-      __ pushq(rcx);
-      __ pushq(rdi);
+      __ push(rax);
+      __ push(rcx);
+      __ push(rdi);
       assert_different_registers(sub_klass, super_klass, rax, rcx, rdi);
 
-      __ movq(rdi, secondary_supers_addr);
+      __ movptr(rdi, secondary_supers_addr);
       // Load the array length.
       __ movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
       // Skip to start of data.
-      __ addq(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+      __ addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
       // Scan rcx words at [rdi] for occurance of rax
       // Set NZ/Z based on last compare
-      __ movq(rax, super_klass);
+      __ movptr(rax, super_klass);
       if (UseCompressedOops) {
         // Compare against compressed form.  Don't need to uncompress because
         // looks like orig rax is restored in popq below.
         __ encode_heap_oop(rax);
         __ repne_scanl();
       } else {
-         __ repne_scanq();
+        __ repne_scan();
       }
 
       // Unspill the temp. registers:
-      __ popq(rdi);
-      __ popq(rcx);
-      __ popq(rax);
+      __ pop(rdi);
+      __ pop(rcx);
+      __ pop(rax);
 
       __ jcc(Assembler::notEqual, L_miss);
     }
 
     // Success.  Cache the super we found and proceed in triumph.
-    __ movq(super_cache_addr, super_klass); // note: rax is dead
+    __ movptr(super_cache_addr, super_klass); // note: rax is dead
     __ jmp(L_success);
 
     // Fall through on failure!
@@ -2202,16 +2203,16 @@
       saved_rip_offset,
       saved_rarg0_offset
     };
-    __ subq(rsp, saved_rbp_offset * wordSize);
-    __ movq(Address(rsp, saved_r13_offset * wordSize), r13);
-    __ movq(Address(rsp, saved_r14_offset * wordSize), r14);
+    __ subptr(rsp, saved_rbp_offset * wordSize);
+    __ movptr(Address(rsp, saved_r13_offset * wordSize), r13);
+    __ movptr(Address(rsp, saved_r14_offset * wordSize), r14);
     setup_arg_regs(4); // from => rdi, to => rsi, length => rdx
                        // ckoff => rcx, ckval => r8
                        // r9 and r10 may be used to save non-volatile registers
 #ifdef _WIN64
     // last argument (#4) is on stack on Win64
     const int ckval_offset = saved_rarg0_offset + 4;
-    __ movq(ckval, Address(rsp, ckval_offset * wordSize));
+    __ movptr(ckval, Address(rsp, ckval_offset * wordSize));
 #endif
 
     // check that int operands are properly extended to size_t
@@ -2242,15 +2243,15 @@
     gen_write_ref_array_pre_barrier(to, count);
 
     // Copy from low to high addresses, indexed from the end of each array.
-    __ leaq(end_from, end_from_addr);
-    __ leaq(end_to,   end_to_addr);
-    __ movq(r14_length, length);        // save a copy of the length
-    assert(length == count, "");        // else fix next line:
-    __ negq(count);                     // negate and test the length
+    __ lea(end_from, end_from_addr);
+    __ lea(end_to,   end_to_addr);
+    __ movptr(r14_length, length);        // save a copy of the length
+    assert(length == count, "");          // else fix next line:
+    __ negptr(count);                     // negate and test the length
     __ jcc(Assembler::notZero, L_load_element);
 
     // Empty array:  Nothing to do.
-    __ xorq(rax, rax);                  // return 0 on (trivial) success
+    __ xorptr(rax, rax);                  // return 0 on (trivial) success
     __ jmp(L_done);
 
     // ======== begin loop ========
@@ -2262,13 +2263,13 @@
 
     __ BIND(L_store_element);
     __ store_heap_oop(to_element_addr, rax_oop);  // store the oop
-    __ incrementq(count);               // increment the count toward zero
+    __ increment(count);               // increment the count toward zero
     __ jcc(Assembler::zero, L_do_card_marks);
 
     // ======== loop entry is here ========
     __ BIND(L_load_element);
     __ load_heap_oop(rax_oop, from_element_addr); // load the oop
-    __ testq(rax_oop, rax_oop);
+    __ testptr(rax_oop, rax_oop);
     __ jcc(Assembler::zero, L_store_element);
 
     __ load_klass(r11_klass, rax_oop);// query the object klass
@@ -2280,23 +2281,23 @@
     // Emit GC store barriers for the oops we have copied (r14 + rdx),
     // and report their number to the caller.
     assert_different_registers(rax, r14_length, count, to, end_to, rcx);
-    __ leaq(end_to, to_element_addr);
+    __ lea(end_to, to_element_addr);
     gen_write_ref_array_post_barrier(to, end_to, rcx);
-    __ movq(rax, r14_length);           // original oops
-    __ addq(rax, count);                // K = (original - remaining) oops
-    __ notq(rax);                       // report (-1^K) to caller
+    __ movptr(rax, r14_length);           // original oops
+    __ addptr(rax, count);                // K = (original - remaining) oops
+    __ notptr(rax);                       // report (-1^K) to caller
     __ jmp(L_done);
 
     // Come here on success only.
     __ BIND(L_do_card_marks);
-    __ addq(end_to, -wordSize);         // make an inclusive end pointer
+    __ addptr(end_to, -wordSize);         // make an inclusive end pointer
     gen_write_ref_array_post_barrier(to, end_to, rcx);
-    __ xorq(rax, rax);                  // return 0 on success
+    __ xorptr(rax, rax);                  // return 0 on success
 
     // Common exit point (success or failure).
     __ BIND(L_done);
-    __ movq(r13, Address(rsp, saved_r13_offset * wordSize));
-    __ movq(r14, Address(rsp, saved_r14_offset * wordSize));
+    __ movptr(r13, Address(rsp, saved_r13_offset * wordSize));
+    __ movptr(r14, Address(rsp, saved_r14_offset * wordSize));
     inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
     restore_arg_regs();
     __ leave(); // required for proper stackwalking of RuntimeStub frame
@@ -2339,9 +2340,9 @@
     // bump this on entry, not on exit:
     inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
 
-    __ movq(bits, from);
-    __ orq(bits, to);
-    __ orq(bits, size);
+    __ mov(bits, from);
+    __ orptr(bits, to);
+    __ orptr(bits, size);
 
     __ testb(bits, BytesPerLong-1);
     __ jccb(Assembler::zero, L_long_aligned);
@@ -2353,15 +2354,15 @@
     __ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry));
 
     __ BIND(L_short_aligned);
-    __ shrq(size, LogBytesPerShort); // size => short_count
+    __ shrptr(size, LogBytesPerShort); // size => short_count
     __ jump(RuntimeAddress(short_copy_entry));
 
     __ BIND(L_int_aligned);
-    __ shrq(size, LogBytesPerInt); // size => int_count
+    __ shrptr(size, LogBytesPerInt); // size => int_count
     __ jump(RuntimeAddress(int_copy_entry));
 
     __ BIND(L_long_aligned);
-    __ shrq(size, LogBytesPerLong); // size => qword_count
+    __ shrptr(size, LogBytesPerLong); // size => qword_count
     __ jump(RuntimeAddress(long_copy_entry));
 
     return start;
@@ -2469,7 +2470,7 @@
     //
 
     //  if (src == NULL) return -1;
-    __ testq(src, src);         // src oop
+    __ testptr(src, src);         // src oop
     size_t j1off = __ offset();
     __ jccb(Assembler::zero, L_failed_0);
 
@@ -2478,7 +2479,7 @@
     __ jccb(Assembler::negative, L_failed_0);
 
     //  if (dst == NULL) return -1;
-    __ testq(dst, dst);         // dst oop
+    __ testptr(dst, dst);         // dst oop
     __ jccb(Assembler::zero, L_failed_0);
 
     //  if (dst_pos < 0) return -1;
@@ -2509,7 +2510,7 @@
     //  assert(src->klass() != NULL);
     BLOCK_COMMENT("assert klasses not null");
     { Label L1, L2;
-      __ testq(r10_src_klass, r10_src_klass);
+      __ testptr(r10_src_klass, r10_src_klass);
       __ jcc(Assembler::notZero, L2);   // it is broken if klass is NULL
       __ bind(L1);
       __ stop("broken null klass");
@@ -2574,9 +2575,9 @@
 
     __ movl(r10_offset, rax_lh);
     __ shrl(r10_offset, Klass::_lh_header_size_shift);
-    __ andq(r10_offset, Klass::_lh_header_size_mask);   // array_offset
-    __ addq(src, r10_offset);           // src array offset
-    __ addq(dst, r10_offset);           // dst array offset
+    __ andptr(r10_offset, Klass::_lh_header_size_mask);   // array_offset
+    __ addptr(src, r10_offset);           // src array offset
+    __ addptr(dst, r10_offset);           // dst array offset
     BLOCK_COMMENT("choose copy loop based on element size");
     __ andl(rax_lh, Klass::_lh_log2_element_size_mask); // rax_lh -> rax_elsize
 
@@ -2591,25 +2592,25 @@
   __ BIND(L_copy_bytes);
     __ cmpl(rax_elsize, 0);
     __ jccb(Assembler::notEqual, L_copy_shorts);
-    __ leaq(from, Address(src, src_pos, Address::times_1, 0));// src_addr
-    __ leaq(to,   Address(dst, dst_pos, Address::times_1, 0));// dst_addr
-    __ movslq(count, r11_length); // length
+    __ lea(from, Address(src, src_pos, Address::times_1, 0));// src_addr
+    __ lea(to,   Address(dst, dst_pos, Address::times_1, 0));// dst_addr
+    __ movl2ptr(count, r11_length); // length
     __ jump(RuntimeAddress(byte_copy_entry));
 
   __ BIND(L_copy_shorts);
     __ cmpl(rax_elsize, LogBytesPerShort);
     __ jccb(Assembler::notEqual, L_copy_ints);
-    __ leaq(from, Address(src, src_pos, Address::times_2, 0));// src_addr
-    __ leaq(to,   Address(dst, dst_pos, Address::times_2, 0));// dst_addr
-    __ movslq(count, r11_length); // length
+    __ lea(from, Address(src, src_pos, Address::times_2, 0));// src_addr
+    __ lea(to,   Address(dst, dst_pos, Address::times_2, 0));// dst_addr
+    __ movl2ptr(count, r11_length); // length
     __ jump(RuntimeAddress(short_copy_entry));
 
   __ BIND(L_copy_ints);
     __ cmpl(rax_elsize, LogBytesPerInt);
     __ jccb(Assembler::notEqual, L_copy_longs);
-    __ leaq(from, Address(src, src_pos, Address::times_4, 0));// src_addr
-    __ leaq(to,   Address(dst, dst_pos, Address::times_4, 0));// dst_addr
-    __ movslq(count, r11_length); // length
+    __ lea(from, Address(src, src_pos, Address::times_4, 0));// src_addr
+    __ lea(to,   Address(dst, dst_pos, Address::times_4, 0));// dst_addr
+    __ movl2ptr(count, r11_length); // length
     __ jump(RuntimeAddress(int_copy_entry));
 
   __ BIND(L_copy_longs);
@@ -2621,9 +2622,9 @@
       __ bind(L);
     }
 #endif
-    __ leaq(from, Address(src, src_pos, Address::times_8, 0));// src_addr
-    __ leaq(to,   Address(dst, dst_pos, Address::times_8, 0));// dst_addr
-    __ movslq(count, r11_length); // length
+    __ lea(from, Address(src, src_pos, Address::times_8, 0));// src_addr
+    __ lea(to,   Address(dst, dst_pos, Address::times_8, 0));// dst_addr
+    __ movl2ptr(count, r11_length); // length
     __ jump(RuntimeAddress(long_copy_entry));
 
     // objArrayKlass
@@ -2640,11 +2641,11 @@
     arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length,
                            r10, L_failed);
 
-    __ leaq(from, Address(src, src_pos, TIMES_OOP,
+    __ lea(from, Address(src, src_pos, TIMES_OOP,
                  arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
-    __ leaq(to,   Address(dst, dst_pos, TIMES_OOP,
-                  arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
-    __ movslq(count, r11_length); // length
+    __ lea(to,   Address(dst, dst_pos, TIMES_OOP,
+                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
+    __ movl2ptr(count, r11_length); // length
   __ BIND(L_plain_copy);
     __ jump(RuntimeAddress(oop_copy_entry));
 
@@ -2671,9 +2672,9 @@
 #endif
 
       // Marshal the base address arguments now, freeing registers.
-      __ leaq(from, Address(src, src_pos, TIMES_OOP,
+      __ lea(from, Address(src, src_pos, TIMES_OOP,
                    arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
-      __ leaq(to,   Address(dst, dst_pos, TIMES_OOP,
+      __ lea(to,   Address(dst, dst_pos, TIMES_OOP,
                    arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
       __ movl(count, C_RARG4);          // length (reloaded)
       Register sco_temp = c_rarg3;      // this register is free now
@@ -2691,19 +2692,19 @@
       // Fetch destination element klass from the objArrayKlass header.
       int ek_offset = (klassOopDesc::header_size() * HeapWordSize +
                        objArrayKlass::element_klass_offset_in_bytes());
-      __ movq(r11_dst_klass, Address(r11_dst_klass, ek_offset));
+      __ movptr(r11_dst_klass, Address(r11_dst_klass, ek_offset));
       __ movl(sco_temp,      Address(r11_dst_klass, sco_offset));
       assert_clean_int(sco_temp, rax);
 
       // the checkcast_copy loop needs two extra arguments:
       assert(c_rarg3 == sco_temp, "#3 already in place");
-      __ movq(C_RARG4, r11_dst_klass);  // dst.klass.element_klass
+      __ movptr(C_RARG4, r11_dst_klass);  // dst.klass.element_klass
       __ jump(RuntimeAddress(checkcast_copy_entry));
     }
 
   __ BIND(L_failed);
-    __ xorq(rax, rax);
-    __ notq(rax); // return -1
+    __ xorptr(rax, rax);
+    __ notptr(rax); // return -1
     __ leave();   // required for proper stackwalking of RuntimeStub frame
     __ ret(0);
 
@@ -2806,10 +2807,10 @@
     // thread-local storage and also sets up last_Java_sp slightly
     // differently than the real call_VM
     if (restore_saved_exception_pc) {
-      __ movq(rax,
-              Address(r15_thread,
-                      in_bytes(JavaThread::saved_exception_pc_offset())));
-      __ pushq(rax);
+      __ movptr(rax,
+                Address(r15_thread,
+                        in_bytes(JavaThread::saved_exception_pc_offset())));
+      __ push(rax);
     }
 
     __ enter(); // required for proper stackwalking of RuntimeStub frame
@@ -2817,7 +2818,7 @@
     assert(is_even(framesize/2), "sp not 16-byte aligned");
 
     // return address and rbp are already in place
-    __ subq(rsp, (framesize-4) << LogBytesPerInt); // prolog
+    __ subptr(rsp, (framesize-4) << LogBytesPerInt); // prolog
 
     int frame_complete = __ pc() - start;
 
@@ -2825,7 +2826,7 @@
     __ set_last_Java_frame(rsp, rbp, NULL);
 
     // Call runtime
-    __ movq(c_rarg0, r15_thread);
+    __ movptr(c_rarg0, r15_thread);
     BLOCK_COMMENT("call runtime_entry");
     __ call(RuntimeAddress(runtime_entry));
 
@@ -2841,8 +2842,8 @@
     // check for pending exceptions
 #ifdef ASSERT
     Label L;
-    __ cmpq(Address(r15_thread, Thread::pending_exception_offset()),
-            (int) NULL);
+    __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()),
+            (int32_t) NULL_WORD);
     __ jcc(Assembler::notEqual, L);
     __ should_not_reach_here();
     __ bind(L);
@@ -2865,7 +2866,7 @@
     // Generates all stubs and initializes the entry points
 
     // This platform-specific stub is needed by generate_call_stub()
-    StubRoutines::amd64::_mxcsr_std        = generate_fp_mask("mxcsr_std",        0x0000000000001F80);
+    StubRoutines::x86::_mxcsr_std        = generate_fp_mask("mxcsr_std",        0x0000000000001F80);
 
     // entry points that exist in all platforms Note: This is code
     // that could be shared among different platforms - however the
@@ -2894,9 +2895,9 @@
       generate_handler_for_unsafe_access();
 
     // platform dependent
-    StubRoutines::amd64::_get_previous_fp_entry = generate_get_previous_fp();
-
-    StubRoutines::amd64::_verify_mxcsr_entry    = generate_verify_mxcsr();
+    StubRoutines::x86::_get_previous_fp_entry = generate_get_previous_fp();
+
+    StubRoutines::x86::_verify_mxcsr_entry    = generate_verify_mxcsr();
   }
 
   void generate_all() {
@@ -2948,15 +2949,15 @@
                                false);
 
     // entry points that are platform specific
-    StubRoutines::amd64::_f2i_fixup = generate_f2i_fixup();
-    StubRoutines::amd64::_f2l_fixup = generate_f2l_fixup();
-    StubRoutines::amd64::_d2i_fixup = generate_d2i_fixup();
-    StubRoutines::amd64::_d2l_fixup = generate_d2l_fixup();
-
-    StubRoutines::amd64::_float_sign_mask  = generate_fp_mask("float_sign_mask",  0x7FFFFFFF7FFFFFFF);
-    StubRoutines::amd64::_float_sign_flip  = generate_fp_mask("float_sign_flip",  0x8000000080000000);
-    StubRoutines::amd64::_double_sign_mask = generate_fp_mask("double_sign_mask", 0x7FFFFFFFFFFFFFFF);
-    StubRoutines::amd64::_double_sign_flip = generate_fp_mask("double_sign_flip", 0x8000000000000000);
+    StubRoutines::x86::_f2i_fixup = generate_f2i_fixup();
+    StubRoutines::x86::_f2l_fixup = generate_f2l_fixup();
+    StubRoutines::x86::_d2i_fixup = generate_d2i_fixup();
+    StubRoutines::x86::_d2l_fixup = generate_d2l_fixup();
+
+    StubRoutines::x86::_float_sign_mask  = generate_fp_mask("float_sign_mask",  0x7FFFFFFF7FFFFFFF);
+    StubRoutines::x86::_float_sign_flip  = generate_fp_mask("float_sign_flip",  0x8000000080000000);
+    StubRoutines::x86::_double_sign_mask = generate_fp_mask("double_sign_mask", 0x7FFFFFFFFFFFFFFF);
+    StubRoutines::x86::_double_sign_flip = generate_fp_mask("double_sign_flip", 0x8000000000000000);
 
     // support for verify_oop (must happen after universe_init)
     StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop();
--- a/hotspot/src/cpu/x86/vm/stubRoutines_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubRoutines_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -28,6 +28,6 @@
 // Implementation of the platform-specific part of StubRoutines - for
 // a description of how to extend it, see the stubRoutines.hpp file.
 
-address StubRoutines::i486::_verify_mxcsr_entry        = NULL;
-address StubRoutines::i486::_verify_fpu_cntrl_wrd_entry= NULL;
-address StubRoutines::i486::_call_stub_compiled_return = NULL;
+address StubRoutines::x86::_verify_mxcsr_entry        = NULL;
+address StubRoutines::x86::_verify_fpu_cntrl_wrd_entry= NULL;
+address StubRoutines::x86::_call_stub_compiled_return = NULL;
--- a/hotspot/src/cpu/x86/vm/stubRoutines_x86_32.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubRoutines_x86_32.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -31,7 +31,7 @@
   code_size2 = 22000            // simply increase if too small (assembler will crash if too small)
 };
 
-class i486 {
+class x86 {
  friend class StubGenerator;
  friend class VMStructs;
 
@@ -54,4 +54,4 @@
 };
 
   static bool    returns_to_call_stub(address return_pc)     { return (return_pc == _call_stub_return_address) ||
-                                                                       return_pc == i486::get_call_stub_compiled_return(); }
+                                                                       return_pc == x86::get_call_stub_compiled_return(); }
--- a/hotspot/src/cpu/x86/vm/stubRoutines_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubRoutines_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -28,16 +28,16 @@
 // Implementation of the platform-specific part of StubRoutines - for
 // a description of how to extend it, see the stubRoutines.hpp file.
 
-address StubRoutines::amd64::_get_previous_fp_entry = NULL;
+address StubRoutines::x86::_get_previous_fp_entry = NULL;
 
-address StubRoutines::amd64::_verify_mxcsr_entry = NULL;
+address StubRoutines::x86::_verify_mxcsr_entry = NULL;
 
-address StubRoutines::amd64::_f2i_fixup = NULL;
-address StubRoutines::amd64::_f2l_fixup = NULL;
-address StubRoutines::amd64::_d2i_fixup = NULL;
-address StubRoutines::amd64::_d2l_fixup = NULL;
-address StubRoutines::amd64::_float_sign_mask = NULL;
-address StubRoutines::amd64::_float_sign_flip = NULL;
-address StubRoutines::amd64::_double_sign_mask = NULL;
-address StubRoutines::amd64::_double_sign_flip = NULL;
-address StubRoutines::amd64::_mxcsr_std = NULL;
+address StubRoutines::x86::_f2i_fixup = NULL;
+address StubRoutines::x86::_f2l_fixup = NULL;
+address StubRoutines::x86::_d2i_fixup = NULL;
+address StubRoutines::x86::_d2l_fixup = NULL;
+address StubRoutines::x86::_float_sign_mask = NULL;
+address StubRoutines::x86::_float_sign_flip = NULL;
+address StubRoutines::x86::_double_sign_mask = NULL;
+address StubRoutines::x86::_double_sign_flip = NULL;
+address StubRoutines::x86::_mxcsr_std = NULL;
--- a/hotspot/src/cpu/x86/vm/stubRoutines_x86_64.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/stubRoutines_x86_64.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -30,13 +30,13 @@
 
 enum platform_dependent_constants
 {
-  code_size1 =  9000, // simply increase if too small (assembler will
+  code_size1 =  19000, // simply increase if too small (assembler will
                       // crash if too small)
   code_size2 = 22000  // simply increase if too small (assembler will
                       // crash if too small)
 };
 
-class amd64 {
+class x86 {
  friend class StubGenerator;
 
  private:
--- a/hotspot/src/cpu/x86/vm/templateInterpreter_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/templateInterpreter_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -43,9 +43,9 @@
   //
 #ifdef ASSERT
   { Label L;
-    __ leal(rax, Address(rbp,
+    __ lea(rax, Address(rbp,
                 frame::interpreter_frame_monitor_block_top_offset * wordSize));
-    __ cmpl(rax, rsp);  // rax, = maximal rsp for current rbp,
+    __ cmpptr(rax, rsp);  // rax, = maximal rsp for current rbp,
                         //  (stack grows negative)
     __ jcc(Assembler::aboveEqual, L); // check if frame is complete
     __ stop ("interpreter frame not set up");
@@ -80,7 +80,7 @@
 address TemplateInterpreterGenerator::generate_ClassCastException_handler() {
   address entry = __ pc();
   // object is at TOS
-  __ popl(rax);
+  __ pop(rax);
   // expression stack must be empty before entering the VM if an exception
   // happened
   __ empty_expression_stack();
@@ -97,7 +97,7 @@
   address entry = __ pc();
   if (pass_oop) {
     // object is at TOS
-    __ popl(rbx);
+    __ pop(rbx);
   }
   // expression stack must be empty before entering the VM if an exception happened
   __ empty_expression_stack();
@@ -110,7 +110,7 @@
     if (message != NULL) {
       __ lea(rbx, ExternalAddress((address)message));
     } else {
-      __ movl(rbx, NULL_WORD);
+      __ movptr(rbx, (int32_t)NULL_WORD);
     }
     __ call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::create_exception), rax, rbx);
   }
@@ -123,7 +123,7 @@
 address TemplateInterpreterGenerator::generate_continuation_for(TosState state) {
   address entry = __ pc();
   // NULL last_sp until next java call
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   __ dispatch_next(state);
   return entry;
 }
@@ -160,32 +160,32 @@
   // In SSE mode, interpreter returns FP results in xmm0 but they need
   // to end up back on the FPU so it can operate on them.
   if (state == ftos && UseSSE >= 1) {
-    __ subl(rsp, wordSize);
+    __ subptr(rsp, wordSize);
     __ movflt(Address(rsp, 0), xmm0);
     __ fld_s(Address(rsp, 0));
-    __ addl(rsp, wordSize);
+    __ addptr(rsp, wordSize);
   } else if (state == dtos && UseSSE >= 2) {
-    __ subl(rsp, 2*wordSize);
+    __ subptr(rsp, 2*wordSize);
     __ movdbl(Address(rsp, 0), xmm0);
     __ fld_d(Address(rsp, 0));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
   }
 
   __ MacroAssembler::verify_FPU(state == ftos || state == dtos ? 1 : 0, "generate_return_entry_for in interpreter");
 
   // Restore stack bottom in case i2c adjusted stack
-  __ movl(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ movptr(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
   // and NULL it as marker that rsp is now tos until next java call
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
 
   __ restore_bcp();
   __ restore_locals();
   __ get_cache_and_index_at_bcp(rbx, rcx, 1);
   __ movl(rbx, Address(rbx, rcx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() +
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() +
                     ConstantPoolCacheEntry::flags_offset()));
-  __ andl(rbx, 0xFF);
-  __ leal(rsp, Address(rsp, rbx, Interpreter::stackElementScale()));
+  __ andptr(rbx, 0xFF);
+  __ lea(rsp, Address(rsp, rbx, Interpreter::stackElementScale()));
   __ dispatch_next(state, step);
   return entry;
 }
@@ -196,29 +196,29 @@
 
   // In SSE mode, FP results are in xmm0
   if (state == ftos && UseSSE > 0) {
-    __ subl(rsp, wordSize);
+    __ subptr(rsp, wordSize);
     __ movflt(Address(rsp, 0), xmm0);
     __ fld_s(Address(rsp, 0));
-    __ addl(rsp, wordSize);
+    __ addptr(rsp, wordSize);
   } else if (state == dtos && UseSSE >= 2) {
-    __ subl(rsp, 2*wordSize);
+    __ subptr(rsp, 2*wordSize);
     __ movdbl(Address(rsp, 0), xmm0);
     __ fld_d(Address(rsp, 0));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
   }
 
   __ MacroAssembler::verify_FPU(state == ftos || state == dtos ? 1 : 0, "generate_deopt_entry_for in interpreter");
 
   // The stack is not extended by deopt but we must NULL last_sp as this
   // entry is like a "return".
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   __ restore_bcp();
   __ restore_locals();
   // handle exceptions
   { Label L;
     const Register thread = rcx;
     __ get_thread(thread);
-    __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::zero, L);
     __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_pending_exception));
     __ should_not_reach_here();
@@ -254,14 +254,14 @@
   address entry = __ pc();
   switch (type) {
     case T_BOOLEAN: __ c2bool(rax);            break;
-    case T_CHAR   : __ andl(rax, 0xFFFF);      break;
+    case T_CHAR   : __ andptr(rax, 0xFFFF);    break;
     case T_BYTE   : __ sign_extend_byte (rax); break;
     case T_SHORT  : __ sign_extend_short(rax); break;
     case T_INT    : /* nothing to do */        break;
     case T_DOUBLE :
     case T_FLOAT  :
       { const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
-        __ popl(t);                            // remove return address first
+        __ pop(t);                            // remove return address first
         __ pop_dtos_to_rsp();
         // Must return a result for interpreter or compiler. In SSE
         // mode, results are returned in xmm0 and the FPU stack must
@@ -280,13 +280,13 @@
           __ fld_d(Address(rsp, 0));
         }
         // and pop the temp
-        __ addl(rsp, 2 * wordSize);
-        __ pushl(t);                           // restore return address
+        __ addptr(rsp, 2 * wordSize);
+        __ push(t);                           // restore return address
       }
       break;
     case T_OBJECT :
       // retrieve result from frame
-      __ movl(rax, Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize));
+      __ movptr(rax, Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize));
       // and verify it
       __ verify_oop(rax);
       break;
@@ -322,12 +322,12 @@
   const Address backedge_counter  (rbx, methodOopDesc::backedge_counter_offset() + InvocationCounter::counter_offset());
 
   if (ProfileInterpreter) { // %%% Merge this into methodDataOop
-    __ increment(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
+    __ incrementl(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
   }
   // Update standard invocation counters
   __ movl(rax, backedge_counter);               // load backedge counter
 
-  __ increment(rcx, InvocationCounter::count_increment);
+  __ incrementl(rcx, InvocationCounter::count_increment);
   __ andl(rax, InvocationCounter::count_mask_value);  // mask out the status bits
 
   __ movl(invocation_counter, rcx);             // save invocation count
@@ -382,10 +382,10 @@
   // indicating if the counter overflow occurs at a backwards branch (non-NULL bcp).
   // The call returns the address of the verified entry point for the method or NULL
   // if the compilation did not complete (either went background or bailed out).
-  __ movl(rax, (int)false);
+  __ movptr(rax, (int32_t)false);
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), rax);
 
-  __ movl(rbx, Address(rbp, method_offset));   // restore methodOop
+  __ movptr(rbx, Address(rbp, method_offset));   // restore methodOop
 
   // Preserve invariant that rsi/rdi contain bcp/locals of sender frame
   // and jump to the interpreted entry.
@@ -433,7 +433,7 @@
 
   Label after_frame_check_pop;
 
-  __ pushl(rsi);
+  __ push(rsi);
 
   const Register thread = rsi;
 
@@ -443,43 +443,43 @@
   const Address stack_size(thread, Thread::stack_size_offset());
 
   // locals + overhead, in bytes
-  __ leal(rax, Address(noreg, rdx, Interpreter::stackElementScale(), overhead_size));
+  __ lea(rax, Address(noreg, rdx, Interpreter::stackElementScale(), overhead_size));
 
 #ifdef ASSERT
   Label stack_base_okay, stack_size_okay;
   // verify that thread stack base is non-zero
-  __ cmpl(stack_base, 0);
+  __ cmpptr(stack_base, (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, stack_base_okay);
   __ stop("stack base is zero");
   __ bind(stack_base_okay);
   // verify that thread stack size is non-zero
-  __ cmpl(stack_size, 0);
+  __ cmpptr(stack_size, 0);
   __ jcc(Assembler::notEqual, stack_size_okay);
   __ stop("stack size is zero");
   __ bind(stack_size_okay);
 #endif
 
   // Add stack base to locals and subtract stack size
-  __ addl(rax, stack_base);
-  __ subl(rax, stack_size);
+  __ addptr(rax, stack_base);
+  __ subptr(rax, stack_size);
 
   // Use the maximum number of pages we might bang.
   const int max_pages = StackShadowPages > (StackRedPages+StackYellowPages) ? StackShadowPages :
                                                                               (StackRedPages+StackYellowPages);
-  __ addl(rax, max_pages * page_size);
+  __ addptr(rax, max_pages * page_size);
 
   // check against the current stack bottom
-  __ cmpl(rsp, rax);
+  __ cmpptr(rsp, rax);
   __ jcc(Assembler::above, after_frame_check_pop);
 
-  __ popl(rsi);  // get saved bcp / (c++ prev state ).
+  __ pop(rsi);  // get saved bcp / (c++ prev state ).
 
-  __ popl(rax);  // get return address
+  __ pop(rax);  // get return address
   __ jump(ExternalAddress(Interpreter::throw_StackOverflowError_entry()));
 
   // all done with frame size check
   __ bind(after_frame_check_pop);
-  __ popl(rsi);
+  __ pop(rsi);
 
   __ bind(after_frame_check);
 }
@@ -507,18 +507,18 @@
     const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
     __ movl(rax, access_flags);
     __ testl(rax, JVM_ACC_STATIC);
-    __ movl(rax, Address(rdi, Interpreter::local_offset_in_bytes(0)));                                         // get receiver (assume this is frequent case)
+    __ movptr(rax, Address(rdi, Interpreter::local_offset_in_bytes(0)));  // get receiver (assume this is frequent case)
     __ jcc(Assembler::zero, done);
-    __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
-    __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movl(rax, Address(rax, mirror_offset));
+    __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(rax, Address(rax, mirror_offset));
     __ bind(done);
   }
   // add space for monitor & lock
-  __ subl(rsp, entry_size);                                             // add space for a monitor entry
-  __ movl(monitor_block_top, rsp);                                      // set new monitor block top
-  __ movl(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax);   // store object
-  __ movl(rdx, rsp);                                                    // object address
+  __ subptr(rsp, entry_size);                                           // add space for a monitor entry
+  __ movptr(monitor_block_top, rsp);                                    // set new monitor block top
+  __ movptr(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
+  __ mov(rdx, rsp);                                                    // object address
   __ lock_object(rdx);
 }
 
@@ -528,38 +528,38 @@
 
 void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call) {
   // initialize fixed part of activation frame
-  __ pushl(rax);                                      // save return address
+  __ push(rax);                                       // save return address
   __ enter();                                         // save old & set new rbp,
 
 
-  __ pushl(rsi);                                      // set sender sp
-  __ pushl(NULL_WORD);                                // leave last_sp as null
-  __ movl(rsi, Address(rbx,methodOopDesc::const_offset())); // get constMethodOop
-  __ leal(rsi, Address(rsi,constMethodOopDesc::codes_offset())); // get codebase
-  __ pushl(rbx);                                      // save methodOop
+  __ push(rsi);                                       // set sender sp
+  __ push((int32_t)NULL_WORD);                        // leave last_sp as null
+  __ movptr(rsi, Address(rbx,methodOopDesc::const_offset())); // get constMethodOop
+  __ lea(rsi, Address(rsi,constMethodOopDesc::codes_offset())); // get codebase
+  __ push(rbx);                                      // save methodOop
   if (ProfileInterpreter) {
     Label method_data_continue;
-    __ movl(rdx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-    __ testl(rdx, rdx);
+    __ movptr(rdx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+    __ testptr(rdx, rdx);
     __ jcc(Assembler::zero, method_data_continue);
-    __ addl(rdx, in_bytes(methodDataOopDesc::data_offset()));
+    __ addptr(rdx, in_bytes(methodDataOopDesc::data_offset()));
     __ bind(method_data_continue);
-    __ pushl(rdx);                                      // set the mdp (method data pointer)
+    __ push(rdx);                                       // set the mdp (method data pointer)
   } else {
-    __ pushl(0);
+    __ push(0);
   }
 
-  __ movl(rdx, Address(rbx, methodOopDesc::constants_offset()));
-  __ movl(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
-  __ pushl(rdx);                                      // set constant pool cache
-  __ pushl(rdi);                                      // set locals pointer
+  __ movptr(rdx, Address(rbx, methodOopDesc::constants_offset()));
+  __ movptr(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
+  __ push(rdx);                                       // set constant pool cache
+  __ push(rdi);                                       // set locals pointer
   if (native_call) {
-    __ pushl(0);                                      // no bcp
+    __ push(0);                                       // no bcp
   } else {
-    __ pushl(rsi);                                    // set bcp
+    __ push(rsi);                                     // set bcp
     }
-  __ pushl(0);                                        // reserve word for pointer to expression stack bottom
-  __ movl(Address(rsp, 0), rsp);                      // set expression stack bottom
+  __ push(0);                                         // reserve word for pointer to expression stack bottom
+  __ movptr(Address(rsp, 0), rsp);                    // set expression stack bottom
 }
 
 // End of helpers
@@ -598,21 +598,21 @@
     //       these conditions first and use slow path if necessary.
     // rbx,: method
     // rcx: receiver
-    __ movl(rax, Address(rsp, wordSize));
+    __ movptr(rax, Address(rsp, wordSize));
 
     // check if local 0 != NULL and read field
-    __ testl(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, slow_path);
 
-    __ movl(rdi, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rdi, Address(rbx, methodOopDesc::constants_offset()));
     // read first instruction word and extract bytecode @ 1 and index @ 2
-    __ movl(rdx, Address(rbx, methodOopDesc::const_offset()));
+    __ movptr(rdx, Address(rbx, methodOopDesc::const_offset()));
     __ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
     // Shift codes right to get the index on the right.
     // The bytecode fetched looks like <index><0xb4><0x2a>
     __ shrl(rdx, 2*BitsPerByte);
     __ shll(rdx, exact_log2(in_words(ConstantPoolCacheEntry::size())));
-    __ movl(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
+    __ movptr(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
 
     // rax,: local 0
     // rbx,: method
@@ -629,21 +629,21 @@
     __ movl(rcx,
             Address(rdi,
                     rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
     __ shrl(rcx, 2*BitsPerByte);
     __ andl(rcx, 0xFF);
     __ cmpl(rcx, Bytecodes::_getfield);
     __ jcc(Assembler::notEqual, slow_path);
 
     // Note: constant pool entry is not valid before bytecode is resolved
-    __ movl(rcx,
-            Address(rdi,
-                    rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
+    __ movptr(rcx,
+              Address(rdi,
+                      rdx,
+                      Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
     __ movl(rdx,
             Address(rdi,
                     rdx,
-                    Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
+                    Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
 
     Label notByte, notShort, notChar;
     const Address field_address (rax, rcx, Address::times_1);
@@ -682,13 +682,14 @@
     __ bind(okay);
 #endif // ASSERT
     // All the rest are a 32 bit wordsize
-    __ movl(rax, field_address);
+    // This is ok for now. Since fast accessors should be going away
+    __ movptr(rax, field_address);
 
     __ bind(xreturn_path);
 
     // _ireturn/_areturn
-    __ popl(rdi);                              // get return address
-    __ movl(rsp, rsi);                         // set sp to sender sp
+    __ pop(rdi);                               // get return address
+    __ mov(rsp, rsi);                          // set sp to sender sp
     __ jmp(rdi);
 
     // generate a vanilla interpreter entry as the slow path
@@ -732,18 +733,18 @@
   // rcx: size of parameters
   // rsi: sender sp
 
-  __ popl(rax);                                       // get return address
+  __ pop(rax);                                       // get return address
   // for natives the size of locals is zero
 
   // compute beginning of parameters (rdi)
-  __ leal(rdi, Address(rsp, rcx, Interpreter::stackElementScale(), -wordSize));
+  __ lea(rdi, Address(rsp, rcx, Interpreter::stackElementScale(), -wordSize));
 
 
   // add 2 zero-initialized slots for native calls
   // NULL result handler
-  __ pushl(NULL_WORD);
+  __ push((int32_t)NULL_WORD);
   // NULL oop temp (mirror or jni oop result)
-  __ pushl(NULL_WORD);
+  __ push((int32_t)NULL_WORD);
 
   if (inc_counter) __ movl(rcx, invocation_counter);  // (pre-)fetch invocation count
   // initialize fixed part of activation frame
@@ -818,8 +819,8 @@
   { Label L;
     const Address monitor_block_top (rbp,
                  frame::interpreter_frame_monitor_block_top_offset * wordSize);
-    __ movl(rax, monitor_block_top);
-    __ cmpl(rax, rsp);
+    __ movptr(rax, monitor_block_top);
+    __ cmpptr(rax, rsp);
     __ jcc(Assembler::equal, L);
     __ stop("broken stack frame setup in interpreter");
     __ bind(L);
@@ -838,19 +839,19 @@
   __ get_method(method);
   __ verify_oop(method);
   __ load_unsigned_word(t, Address(method, methodOopDesc::size_of_parameters_offset()));
-  __ shll(t, Interpreter::logStackElementSize());
-  __ addl(t, 2*wordSize);     // allocate two more slots for JNIEnv and possible mirror
-  __ subl(rsp, t);
-  __ andl(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
+  __ shlptr(t, Interpreter::logStackElementSize());
+  __ addptr(t, 2*wordSize);     // allocate two more slots for JNIEnv and possible mirror
+  __ subptr(rsp, t);
+  __ andptr(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
 
   // get signature handler
   { Label L;
-    __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
-    __ testl(t, t);
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ testptr(t, t);
     __ jcc(Assembler::notZero, L);
     __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
     __ get_method(method);
-    __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
     __ bind(L);
   }
 
@@ -867,7 +868,7 @@
 
   // result handler is in rax,
   // set result handler
-  __ movl(Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize), rax);
+  __ movptr(Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize), rax);
 
   // pass mirror handle if static call
   { Label L;
@@ -876,34 +877,34 @@
     __ testl(t, JVM_ACC_STATIC);
     __ jcc(Assembler::zero, L);
     // get mirror
-    __ movl(t, Address(method, methodOopDesc:: constants_offset()));
-    __ movl(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movl(t, Address(t, mirror_offset));
+    __ movptr(t, Address(method, methodOopDesc:: constants_offset()));
+    __ movptr(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(t, Address(t, mirror_offset));
     // copy mirror into activation frame
-    __ movl(Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize), t);
+    __ movptr(Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize), t);
     // pass handle to mirror
-    __ leal(t, Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize));
-    __ movl(Address(rsp, wordSize), t);
+    __ lea(t, Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize));
+    __ movptr(Address(rsp, wordSize), t);
     __ bind(L);
   }
 
   // get native function entry point
   { Label L;
-    __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
     ExternalAddress unsatisfied(SharedRuntime::native_method_throw_unsatisfied_link_error_entry());
-    __ cmp32(rax, unsatisfied.addr());
+    __ cmpptr(rax, unsatisfied.addr());
     __ jcc(Assembler::notEqual, L);
     __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
     __ get_method(method);
     __ verify_oop(method);
-    __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
     __ bind(L);
   }
 
   // pass JNIEnv
   __ get_thread(thread);
-  __ leal(t, Address(thread, JavaThread::jni_environment_offset()));
-  __ movl(Address(rsp, 0), t);
+  __ lea(t, Address(thread, JavaThread::jni_environment_offset()));
+  __ movptr(Address(rsp, 0), t);
 
   // set_last_Java_frame_before_call
   // It is enough that the pc()
@@ -934,14 +935,14 @@
       __ ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
     }
     else if (CheckJNICalls ) {
-      __ call(RuntimeAddress(StubRoutines::i486::verify_mxcsr_entry()));
+      __ call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
     }
   }
 
   // Either restore the x87 floating pointer control word after returning
   // from the JNI call or verify that it wasn't changed.
   if (CheckJNICalls) {
-    __ call(RuntimeAddress(StubRoutines::i486::verify_fpu_cntrl_wrd_entry()));
+    __ call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
   }
 
   // save potential result in ST(0) & rdx:rax
@@ -975,7 +976,10 @@
   __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
   if(os::is_MP()) {
     if (UseMembar) {
-      __ membar(); // Force this write out before the read below
+      // Force this write out before the read below
+      __ membar(Assembler::Membar_mask_bits(
+           Assembler::LoadLoad | Assembler::LoadStore |
+           Assembler::StoreLoad | Assembler::StoreStore));
     } else {
       // Write serialization page so VM thread can do a pseudo remote membar.
       // We use the current thread pointer to calculate a thread specific
@@ -1008,7 +1012,7 @@
     // preserved and correspond to the bcp/locals pointers. So we do a runtime call
     // by hand.
     //
-    __ pushl(thread);
+    __ push(thread);
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
                                             JavaThread::check_special_condition_for_native_trans)));
     __ increment(rsp, wordSize);
@@ -1023,8 +1027,8 @@
   __ reset_last_Java_frame(thread, true, true);
 
   // reset handle block
-  __ movl(t, Address(thread, JavaThread::active_handles_offset()));
-  __ movl(Address(t, JNIHandleBlock::top_offset_in_bytes()), 0);
+  __ movptr(t, Address(thread, JavaThread::active_handles_offset()));
+  __ movptr(Address(t, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
 
   // If result was an oop then unbox and save it in the frame
   { Label L;
@@ -1033,14 +1037,14 @@
     __ cmpptr(Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize),
               handler.addr());
     __ jcc(Assembler::notEqual, no_oop);
-    __ cmpl(Address(rsp, 0), NULL_WORD);
+    __ cmpptr(Address(rsp, 0), (int32_t)NULL_WORD);
     __ pop(ltos);
-    __ testl(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, store_result);
     // unbox
-    __ movl(rax, Address(rax, 0));
+    __ movptr(rax, Address(rax, 0));
     __ bind(store_result);
-    __ movl(Address(rbp, (frame::interpreter_frame_oop_temp_offset)*wordSize), rax);
+    __ movptr(Address(rbp, (frame::interpreter_frame_oop_temp_offset)*wordSize), rax);
     // keep stack depth as expected by pushing oop which will eventually be discarded
     __ push(ltos);
     __ bind(no_oop);
@@ -1051,9 +1055,9 @@
      __ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
      __ jcc(Assembler::notEqual, no_reguard);
 
-     __ pushad();
+     __ pusha();
      __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
-     __ popad();
+     __ popa();
 
      __ bind(no_reguard);
    }
@@ -1063,12 +1067,12 @@
   // Can't call_VM until bcp is within reasonable.
   __ get_method(method);      // method is junk from thread_in_native to now.
   __ verify_oop(method);
-  __ movl(rsi, Address(method,methodOopDesc::const_offset())); // get constMethodOop
-  __ leal(rsi, Address(rsi,constMethodOopDesc::codes_offset()));    // get codebase
+  __ movptr(rsi, Address(method,methodOopDesc::const_offset()));   // get constMethodOop
+  __ lea(rsi, Address(rsi,constMethodOopDesc::codes_offset()));    // get codebase
 
   // handle exceptions (exception handling will handle unlocking!)
   { Label L;
-    __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+    __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::zero, L);
     // Note: At some point we may want to unify this with the code used in call_VM_base();
     //       i.e., we should use the StubRoutines::forward_exception code. For now this
@@ -1089,10 +1093,10 @@
       // to check that the object has not been unlocked by an explicit monitorexit bytecode.
       const Address monitor(rbp, frame::interpreter_frame_initial_sp_offset * wordSize - (int)sizeof(BasicObjectLock));
 
-      __ leal(rdx, monitor);                   // address of first monitor
+      __ lea(rdx, monitor);                   // address of first monitor
 
-      __ movl(t, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
-      __ testl(t, t);
+      __ movptr(t, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
+      __ testptr(t, t);
       __ jcc(Assembler::notZero, unlock);
 
       // Entry already unlocked, need to throw exception
@@ -1114,14 +1118,14 @@
 
   // restore potential result in rdx:rax, call result handler to restore potential result in ST0 & handle result
   __ pop(ltos);
-  __ movl(t, Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize));
+  __ movptr(t, Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize));
   __ call(t);
 
   // remove activation
-  __ movl(t, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
+  __ movptr(t, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
   __ leave();                                // remove frame anchor
-  __ popl(rdi);                              // get return address
-  __ movl(rsp, t);                           // set sp to sender sp
+  __ pop(rdi);                               // get return address
+  __ mov(rsp, t);                            // set sp to sender sp
   __ jmp(rdi);
 
   if (inc_counter) {
@@ -1165,10 +1169,10 @@
   generate_stack_overflow_check();
 
   // get return address
-  __ popl(rax);
+  __ pop(rax);
 
   // compute beginning of parameters (rdi)
-  __ leal(rdi, Address(rsp, rcx, Interpreter::stackElementScale(), -wordSize));
+  __ lea(rdi, Address(rsp, rcx, Interpreter::stackElementScale(), -wordSize));
 
   // rdx - # of additional locals
   // allocate space for locals
@@ -1178,8 +1182,10 @@
     __ testl(rdx, rdx);
     __ jcc(Assembler::lessEqual, exit);               // do nothing if rdx <= 0
     __ bind(loop);
-    if (TaggedStackInterpreter) __ pushl(NULL_WORD);  // push tag
-    __ pushl(NULL_WORD);                              // initialize local variables
+    if (TaggedStackInterpreter) {
+      __ push((int32_t)NULL_WORD);                    // push tag
+    }
+    __ push((int32_t)NULL_WORD);                      // initialize local variables
     __ decrement(rdx);                                // until everything initialized
     __ jcc(Assembler::greater, loop);
     __ bind(exit);
@@ -1262,8 +1268,8 @@
   { Label L;
      const Address monitor_block_top (rbp,
                  frame::interpreter_frame_monitor_block_top_offset * wordSize);
-    __ movl(rax, monitor_block_top);
-    __ cmpl(rax, rsp);
+    __ movptr(rax, monitor_block_top);
+    __ cmpptr(rax, rsp);
     __ jcc(Assembler::equal, L);
     __ stop("broken stack frame setup in interpreter");
     __ bind(L);
@@ -1283,12 +1289,12 @@
 
       __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method), rsi, true);
 
-      __ movl(rbx, Address(rbp, method_offset));   // restore methodOop
-      __ movl(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-      __ movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rax);
+      __ movptr(rbx, Address(rbp, method_offset));   // restore methodOop
+      __ movptr(rax, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rax);
       __ test_method_data_pointer(rax, profile_method_continue);
-      __ addl(rax, in_bytes(methodDataOopDesc::data_offset()));
-      __ movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rax);
+      __ addptr(rax, in_bytes(methodDataOopDesc::data_offset()));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rax);
       __ jmp(profile_method_continue);
     }
     // Handle overflow of counter and compile method
@@ -1482,7 +1488,7 @@
 
   // Restore sp to interpreter_frame_last_sp even though we are going
   // to empty the expression stack for the exception processing.
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   // rax,: exception
   // rdx: return address/pc that threw exception
   __ restore_bcp();                              // rsi points to call/send
@@ -1544,7 +1550,7 @@
     // deoptimization blob's unpack entry because of the presence of
     // adapter frames in C2.
     Label caller_not_deoptimized;
-    __ movl(rdx, Address(rbp, frame::return_addr_offset * wordSize));
+    __ movptr(rdx, Address(rbp, frame::return_addr_offset * wordSize));
     __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::interpreter_contains), rdx);
     __ testl(rax, rax);
     __ jcc(Assembler::notZero, caller_not_deoptimized);
@@ -1553,10 +1559,10 @@
     __ get_method(rax);
     __ verify_oop(rax);
     __ load_unsigned_word(rax, Address(rax, in_bytes(methodOopDesc::size_of_parameters_offset())));
-    __ shll(rax, Interpreter::logStackElementSize());
+    __ shlptr(rax, Interpreter::logStackElementSize());
     __ restore_locals();
-    __ subl(rdi, rax);
-    __ addl(rdi, wordSize);
+    __ subptr(rdi, rax);
+    __ addptr(rdi, wordSize);
     // Save these arguments
     __ get_thread(rcx);
     __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::popframe_preserve_args), rcx, rax, rdi);
@@ -1592,8 +1598,8 @@
   // maintain this kind of invariant all the time we call a small
   // fixup routine to move the mutated arguments onto the top of our
   // expression stack if necessary.
-  __ movl(rax, rsp);
-  __ movl(rbx, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ mov(rax, rsp);
+  __ movptr(rbx, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
   __ get_thread(rcx);
   // PC must point into interpreter here
   __ set_last_Java_frame(rcx, noreg, rbp, __ pc());
@@ -1601,8 +1607,8 @@
   __ get_thread(rcx);
   __ reset_last_Java_frame(rcx, true, true);
   // Restore the last_sp and null it out
-  __ movl(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
-  __ movl(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
 
   __ restore_bcp();
   __ restore_locals();
@@ -1624,13 +1630,13 @@
   // preserve exception over this code sequence
   __ pop_ptr(rax);
   __ get_thread(rcx);
-  __ movl(Address(rcx, JavaThread::vm_result_offset()), rax);
+  __ movptr(Address(rcx, JavaThread::vm_result_offset()), rax);
   // remove the activation (without doing throws on illegalMonitorExceptions)
   __ remove_activation(vtos, rdx, false, true, false);
   // restore exception
   __ get_thread(rcx);
-  __ movl(rax, Address(rcx, JavaThread::vm_result_offset()));
-  __ movl(Address(rcx, JavaThread::vm_result_offset()), NULL_WORD);
+  __ movptr(rax, Address(rcx, JavaThread::vm_result_offset()));
+  __ movptr(Address(rcx, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
   __ verify_oop(rax);
 
   // Inbetween activations - previous activation type unknown yet
@@ -1641,12 +1647,12 @@
   // rdx: return address/pc that threw exception
   // rsp: expression stack of caller
   // rbp,: rbp, of caller
-  __ pushl(rax);                                 // save exception
-  __ pushl(rdx);                                 // save return address
+  __ push(rax);                                  // save exception
+  __ push(rdx);                                  // save return address
   __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), rdx);
-  __ movl(rbx, rax);                             // save exception handler
-  __ popl(rdx);                                  // restore return address
-  __ popl(rax);                                  // restore exception
+  __ mov(rbx, rax);                              // save exception handler
+  __ pop(rdx);                                   // restore return address
+  __ pop(rax);                                   // restore exception
   // Note that an "issuing PC" is actually the next PC after the call
   __ jmp(rbx);                                   // jump to exception handler of caller
 }
@@ -1665,7 +1671,7 @@
   __ load_earlyret_value(state);
 
   __ get_thread(rcx);
-  __ movl(rcx, Address(rcx, JavaThread::jvmti_thread_state_offset()));
+  __ movptr(rcx, Address(rcx, JavaThread::jvmti_thread_state_offset()));
   const Address cond_addr(rcx, JvmtiThreadState::earlyret_state_offset());
 
   // Clear the earlyret state
@@ -1716,12 +1722,12 @@
   address entry = __ pc();
 
   // prepare expression stack
-  __ popl(rcx);         // pop return address so expression stack is 'pure'
+  __ pop(rcx);          // pop return address so expression stack is 'pure'
   __ push(state);       // save tosca
 
   // pass tosca registers as arguments & call tracer
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::trace_bytecode), rcx, rax, rdx);
-  __ movl(rcx, rax);    // make sure return address is not destroyed by pop(state)
+  __ mov(rcx, rax);     // make sure return address is not destroyed by pop(state)
   __ pop(state);        // restore tosca
 
   // return
@@ -1732,12 +1738,12 @@
 
 
 void TemplateInterpreterGenerator::count_bytecode() {
-  __ increment(ExternalAddress((address) &BytecodeCounter::_counter_value));
+  __ incrementl(ExternalAddress((address) &BytecodeCounter::_counter_value));
 }
 
 
 void TemplateInterpreterGenerator::histogram_bytecode(Template* t) {
-  __ increment(ExternalAddress((address) &BytecodeHistogram::_counters[t->bytecode()]));
+  __ incrementl(ExternalAddress((address) &BytecodeHistogram::_counters[t->bytecode()]));
 }
 
 
@@ -1747,7 +1753,7 @@
   __ orl(rbx, ((int)t->bytecode()) << BytecodePairHistogram::log2_number_of_codes);
   ExternalAddress table((address) BytecodePairHistogram::_counters);
   Address index(noreg, rbx, Address::times_4);
-  __ increment(ArrayAddress(table, index));
+  __ incrementl(ArrayAddress(table, index));
 }
 
 
--- a/hotspot/src/cpu/x86/vm/templateInterpreter_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/templateInterpreter_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -27,6 +27,8 @@
 
 #define __ _masm->
 
+#ifndef CC_INTERP
+
 const int method_offset = frame::interpreter_frame_method_offset * wordSize;
 const int bci_offset    = frame::interpreter_frame_bcx_offset    * wordSize;
 const int locals_offset = frame::interpreter_frame_locals_offset * wordSize;
@@ -39,11 +41,11 @@
 #ifdef ASSERT
   {
     Label L;
-    __ leaq(rax, Address(rbp,
-                         frame::interpreter_frame_monitor_block_top_offset *
-                         wordSize));
-    __ cmpq(rax, rsp); // rax = maximal rsp for current rbp (stack
-                       // grows negative)
+    __ lea(rax, Address(rbp,
+                        frame::interpreter_frame_monitor_block_top_offset *
+                        wordSize));
+    __ cmpptr(rax, rsp); // rax = maximal rsp for current rbp (stack
+                         // grows negative)
     __ jcc(Assembler::aboveEqual, L); // check if frame is complete
     __ stop ("interpreter frame not set up");
     __ bind(L);
@@ -84,7 +86,7 @@
   address entry = __ pc();
 
   // object is at TOS
-  __ popq(c_rarg1);
+  __ pop(c_rarg1);
 
   // expression stack must be empty before entering the VM if an
   // exception happened
@@ -104,7 +106,7 @@
   address entry = __ pc();
   if (pass_oop) {
     // object is at TOS
-    __ popq(c_rarg2);
+    __ pop(c_rarg2);
   }
   // expression stack must be empty before entering the VM if an
   // exception happened
@@ -137,7 +139,7 @@
 address TemplateInterpreterGenerator::generate_continuation_for(TosState state) {
   address entry = __ pc();
   // NULL last_sp until next java call
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   __ dispatch_next(state);
   return entry;
 }
@@ -153,12 +155,13 @@
   address entry = __ pc();
 
   // Restore stack bottom in case i2c adjusted stack
-  __ movq(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ movptr(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
   // and NULL it as marker that esp is now tos until next java call
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
 
   __ restore_bcp();
   __ restore_locals();
+
   __ get_cache_and_index_at_bcp(rbx, rcx, 1);
   __ movl(rbx, Address(rbx, rcx,
                        Address::times_8,
@@ -166,7 +169,7 @@
                        3 * wordSize));
   __ andl(rbx, 0xFF);
   if (TaggedStackInterpreter) __ shll(rbx, 1); // 2 slots per parameter.
-  __ leaq(rsp, Address(rsp, rbx, Address::times_8));
+  __ lea(rsp, Address(rsp, rbx, Address::times_8));
   __ dispatch_next(state, step);
   return entry;
 }
@@ -176,13 +179,13 @@
                                                                int step) {
   address entry = __ pc();
   // NULL last_sp until next java call
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   __ restore_bcp();
   __ restore_locals();
   // handle exceptions
   {
     Label L;
-    __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int) NULL);
+    __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
     __ jcc(Assembler::zero, L);
     __ call_VM(noreg,
                CAST_FROM_FN_PTR(address,
@@ -231,7 +234,7 @@
   case T_DOUBLE : /* nothing to do */        break;
   case T_OBJECT :
     // retrieve result from frame
-    __ movq(rax, Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize));
+    __ movptr(rax, Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize));
     // and verify it
     __ verify_oop(rax);
     break;
@@ -336,7 +339,7 @@
                               InterpreterRuntime::frequency_counter_overflow),
              c_rarg1);
 
-  __ movq(rbx, Address(rbp, method_offset));   // restore methodOop
+  __ movptr(rbx, Address(rbp, method_offset));   // restore methodOop
   // Preserve invariant that r13/r14 contain bcp/locals of sender frame
   // and jump to the interpreted entry.
   __ jmp(*do_continue, relocInfo::none);
@@ -385,36 +388,36 @@
   const Address stack_size(r15_thread, Thread::stack_size_offset());
 
   // locals + overhead, in bytes
-  __ movq(rax, rdx);
-  __ shll(rax, Interpreter::logStackElementSize()); // 2 slots per parameter.
-  __ addq(rax, overhead_size);
+  __ mov(rax, rdx);
+  __ shlptr(rax, Interpreter::logStackElementSize()); // 2 slots per parameter.
+  __ addptr(rax, overhead_size);
 
 #ifdef ASSERT
   Label stack_base_okay, stack_size_okay;
   // verify that thread stack base is non-zero
-  __ cmpq(stack_base, 0);
+  __ cmpptr(stack_base, (int32_t)NULL_WORD);
   __ jcc(Assembler::notEqual, stack_base_okay);
   __ stop("stack base is zero");
   __ bind(stack_base_okay);
   // verify that thread stack size is non-zero
-  __ cmpq(stack_size, 0);
+  __ cmpptr(stack_size, 0);
   __ jcc(Assembler::notEqual, stack_size_okay);
   __ stop("stack size is zero");
   __ bind(stack_size_okay);
 #endif
 
   // Add stack base to locals and subtract stack size
-  __ addq(rax, stack_base);
-  __ subq(rax, stack_size);
+  __ addptr(rax, stack_base);
+  __ subptr(rax, stack_size);
 
   // add in the red and yellow zone sizes
-  __ addq(rax, (StackRedPages + StackYellowPages) * page_size);
+  __ addptr(rax, (StackRedPages + StackYellowPages) * page_size);
 
   // check against the current stack bottom
-  __ cmpq(rsp, rax);
+  __ cmpptr(rsp, rax);
   __ jcc(Assembler::above, after_frame_check);
 
-  __ popq(rax); // get return address
+  __ pop(rax); // get return address
   __ jump(ExternalAddress(Interpreter::throw_StackOverflowError_entry()));
 
   // all done with frame size check
@@ -458,17 +461,17 @@
     __ movl(rax, access_flags);
     __ testl(rax, JVM_ACC_STATIC);
     // get receiver (assume this is frequent case)
-    __ movq(rax, Address(r14, Interpreter::local_offset_in_bytes(0)));
+    __ movptr(rax, Address(r14, Interpreter::local_offset_in_bytes(0)));
     __ jcc(Assembler::zero, done);
-    __ movq(rax, Address(rbx, methodOopDesc::constants_offset()));
-    __ movq(rax, Address(rax,
-                         constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movq(rax, Address(rax, mirror_offset));
+    __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+    __ movptr(rax, Address(rax,
+                           constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(rax, Address(rax, mirror_offset));
 
 #ifdef ASSERT
     {
       Label L;
-      __ testq(rax, rax);
+      __ testptr(rax, rax);
       __ jcc(Assembler::notZero, L);
       __ stop("synchronization object is NULL");
       __ bind(L);
@@ -479,11 +482,11 @@
   }
 
   // add space for monitor & lock
-  __ subq(rsp, entry_size); // add space for a monitor entry
-  __ movq(monitor_block_top, rsp);  // set new monitor block top
+  __ subptr(rsp, entry_size); // add space for a monitor entry
+  __ movptr(monitor_block_top, rsp);  // set new monitor block top
   // store object
-  __ movq(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax);
-  __ movq(c_rarg1, rsp); // object address
+  __ movptr(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax);
+  __ movptr(c_rarg1, rsp); // object address
   __ lock_object(c_rarg1);
 }
 
@@ -498,40 +501,187 @@
 //      rdx: cp cache
 void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call) {
   // initialize fixed part of activation frame
-  __ pushq(rax);       // save return address
+  __ push(rax);        // save return address
   __ enter();          // save old & set new rbp
-  __ pushq(r13);       // set sender sp
-  __ pushq((int)NULL_WORD); // leave last_sp as null
-  __ movq(r13, Address(rbx, methodOopDesc::const_offset()));      // get constMethodOop
-  __ leaq(r13, Address(r13, constMethodOopDesc::codes_offset())); // get codebase
-  __ pushq(rbx);       // save methodOop
+  __ push(r13);        // set sender sp
+  __ push((int)NULL_WORD); // leave last_sp as null
+  __ movptr(r13, Address(rbx, methodOopDesc::const_offset()));      // get constMethodOop
+  __ lea(r13, Address(r13, constMethodOopDesc::codes_offset())); // get codebase
+  __ push(rbx);        // save methodOop
   if (ProfileInterpreter) {
     Label method_data_continue;
-    __ movq(rdx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
-    __ testq(rdx, rdx);
+    __ movptr(rdx, Address(rbx, in_bytes(methodOopDesc::method_data_offset())));
+    __ testptr(rdx, rdx);
     __ jcc(Assembler::zero, method_data_continue);
-    __ addq(rdx, in_bytes(methodDataOopDesc::data_offset()));
+    __ addptr(rdx, in_bytes(methodDataOopDesc::data_offset()));
     __ bind(method_data_continue);
-    __ pushq(rdx);     // set the mdp (method data pointer)
+    __ push(rdx);      // set the mdp (method data pointer)
   } else {
-    __ pushq(0);
+    __ push(0);
   }
 
-  __ movq(rdx, Address(rbx, methodOopDesc::constants_offset()));
-  __ movq(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
-  __ pushq(rdx); // set constant pool cache
-  __ pushq(r14); // set locals pointer
+  __ movptr(rdx, Address(rbx, methodOopDesc::constants_offset()));
+  __ movptr(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
+  __ push(rdx); // set constant pool cache
+  __ push(r14); // set locals pointer
   if (native_call) {
-    __ pushq(0); // no bcp
+    __ push(0); // no bcp
   } else {
-    __ pushq(r13); // set bcp
+    __ push(r13); // set bcp
   }
-  __ pushq(0); // reserve word for pointer to expression stack bottom
-  __ movq(Address(rsp, 0), rsp); // set expression stack bottom
+  __ push(0); // reserve word for pointer to expression stack bottom
+  __ movptr(Address(rsp, 0), rsp); // set expression stack bottom
 }
 
 // End of helpers
 
+// Various method entries
+//------------------------------------------------------------------------------------------------------------------------
+//
+//
+
+// Call an accessor method (assuming it is resolved, otherwise drop
+// into vanilla (slow path) entry
+address InterpreterGenerator::generate_accessor_entry(void) {
+  // rbx: methodOop
+
+  // r13: senderSP must preserver for slow path, set SP to it on fast path
+
+  address entry_point = __ pc();
+  Label xreturn_path;
+
+  // do fastpath for resolved accessor methods
+  if (UseFastAccessorMethods) {
+    // Code: _aload_0, _(i|a)getfield, _(i|a)return or any rewrites
+    //       thereof; parameter size = 1
+    // Note: We can only use this code if the getfield has been resolved
+    //       and if we don't have a null-pointer exception => check for
+    //       these conditions first and use slow path if necessary.
+    Label slow_path;
+    // If we need a safepoint check, generate full interpreter entry.
+    __ cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
+             SafepointSynchronize::_not_synchronized);
+
+    __ jcc(Assembler::notEqual, slow_path);
+    // rbx: method
+    __ movptr(rax, Address(rsp, wordSize));
+
+    // check if local 0 != NULL and read field
+    __ testptr(rax, rax);
+    __ jcc(Assembler::zero, slow_path);
+
+    __ movptr(rdi, Address(rbx, methodOopDesc::constants_offset()));
+    // read first instruction word and extract bytecode @ 1 and index @ 2
+    __ movptr(rdx, Address(rbx, methodOopDesc::const_offset()));
+    __ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
+    // Shift codes right to get the index on the right.
+    // The bytecode fetched looks like <index><0xb4><0x2a>
+    __ shrl(rdx, 2 * BitsPerByte);
+    __ shll(rdx, exact_log2(in_words(ConstantPoolCacheEntry::size())));
+    __ movptr(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
+
+    // rax: local 0
+    // rbx: method
+    // rdx: constant pool cache index
+    // rdi: constant pool cache
+
+    // check if getfield has been resolved and read constant pool cache entry
+    // check the validity of the cache entry by testing whether _indices field
+    // contains Bytecode::_getfield in b1 byte.
+    assert(in_words(ConstantPoolCacheEntry::size()) == 4,
+           "adjust shift below");
+    __ movl(rcx,
+            Address(rdi,
+                    rdx,
+                    Address::times_8,
+                    constantPoolCacheOopDesc::base_offset() +
+                    ConstantPoolCacheEntry::indices_offset()));
+    __ shrl(rcx, 2 * BitsPerByte);
+    __ andl(rcx, 0xFF);
+    __ cmpl(rcx, Bytecodes::_getfield);
+    __ jcc(Assembler::notEqual, slow_path);
+
+    // Note: constant pool entry is not valid before bytecode is resolved
+    __ movptr(rcx,
+              Address(rdi,
+                      rdx,
+                      Address::times_8,
+                      constantPoolCacheOopDesc::base_offset() +
+                      ConstantPoolCacheEntry::f2_offset()));
+    // edx: flags
+    __ movl(rdx,
+            Address(rdi,
+                    rdx,
+                    Address::times_8,
+                    constantPoolCacheOopDesc::base_offset() +
+                    ConstantPoolCacheEntry::flags_offset()));
+
+    Label notObj, notInt, notByte, notShort;
+    const Address field_address(rax, rcx, Address::times_1);
+
+    // Need to differentiate between igetfield, agetfield, bgetfield etc.
+    // because they are different sizes.
+    // Use the type from the constant pool cache
+    __ shrl(rdx, ConstantPoolCacheEntry::tosBits);
+    // Make sure we don't need to mask edx for tosBits after the above shift
+    ConstantPoolCacheEntry::verify_tosBits();
+
+    __ cmpl(rdx, atos);
+    __ jcc(Assembler::notEqual, notObj);
+    // atos
+    __ load_heap_oop(rax, field_address);
+    __ jmp(xreturn_path);
+
+    __ bind(notObj);
+    __ cmpl(rdx, itos);
+    __ jcc(Assembler::notEqual, notInt);
+    // itos
+    __ movl(rax, field_address);
+    __ jmp(xreturn_path);
+
+    __ bind(notInt);
+    __ cmpl(rdx, btos);
+    __ jcc(Assembler::notEqual, notByte);
+    // btos
+    __ load_signed_byte(rax, field_address);
+    __ jmp(xreturn_path);
+
+    __ bind(notByte);
+    __ cmpl(rdx, stos);
+    __ jcc(Assembler::notEqual, notShort);
+    // stos
+    __ load_signed_word(rax, field_address);
+    __ jmp(xreturn_path);
+
+    __ bind(notShort);
+#ifdef ASSERT
+    Label okay;
+    __ cmpl(rdx, ctos);
+    __ jcc(Assembler::equal, okay);
+    __ stop("what type is this?");
+    __ bind(okay);
+#endif
+    // ctos
+    __ load_unsigned_word(rax, field_address);
+
+    __ bind(xreturn_path);
+
+    // _ireturn/_areturn
+    __ pop(rdi);
+    __ mov(rsp, r13);
+    __ jmp(rdi);
+    __ ret(0);
+
+    // generate a vanilla interpreter entry as the slow path
+    __ bind(slow_path);
+    (void) generate_normal_entry(false);
+  } else {
+    (void) generate_normal_entry(false);
+  }
+
+  return entry_point;
+}
+
 // Interpreter stub for calling a native method. (asm interpreter)
 // This sets up a somewhat different looking stack for calling the
 // native method than the typical interpreter frame setup.
@@ -561,20 +711,20 @@
   // rbx: methodOop
   // rcx: size of parameters
   // r13: sender sp
-  __ popq(rax);                                       // get return address
+  __ pop(rax);                                       // get return address
 
   // for natives the size of locals is zero
 
   // compute beginning of parameters (r14)
   if (TaggedStackInterpreter) __ shll(rcx, 1); // 2 slots per parameter.
-  __ leaq(r14, Address(rsp, rcx, Address::times_8, -wordSize));
+  __ lea(r14, Address(rsp, rcx, Address::times_8, -wordSize));
 
   // add 2 zero-initialized slots for native calls
   // initialize result_handler slot
-  __ pushq((int) NULL);
+  __ push((int) NULL_WORD);
   // slot for oop temp
   // (static native method holder mirror/jni oop result)
-  __ pushq((int) NULL);
+  __ push((int) NULL_WORD);
 
   if (inc_counter) {
     __ movl(rcx, invocation_counter);  // (pre-)fetch invocation count
@@ -651,8 +801,8 @@
     Label L;
     const Address monitor_block_top(rbp,
                  frame::interpreter_frame_monitor_block_top_offset * wordSize);
-    __ movq(rax, monitor_block_top);
-    __ cmpq(rax, rsp);
+    __ movptr(rax, monitor_block_top);
+    __ cmpptr(rax, rsp);
     __ jcc(Assembler::equal, L);
     __ stop("broken stack frame setup in interpreter");
     __ bind(L);
@@ -674,22 +824,22 @@
                                 methodOopDesc::size_of_parameters_offset()));
   __ shll(t, Interpreter::logStackElementSize());
 
-  __ subq(rsp, t);
-  __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-  __ andq(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+  __ subptr(rsp, t);
+  __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+  __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
 
   // get signature handler
   {
     Label L;
-    __ movq(t, Address(method, methodOopDesc::signature_handler_offset()));
-    __ testq(t, t);
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ testptr(t, t);
     __ jcc(Assembler::notZero, L);
     __ call_VM(noreg,
                CAST_FROM_FN_PTR(address,
                                 InterpreterRuntime::prepare_native_call),
                method);
     __ get_method(method);
-    __ movq(t, Address(method, methodOopDesc::signature_handler_offset()));
+    __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
     __ bind(L);
   }
 
@@ -711,9 +861,9 @@
 
   // result handler is in rax
   // set result handler
-  __ movq(Address(rbp,
-                  (frame::interpreter_frame_result_handler_offset) * wordSize),
-          rax);
+  __ movptr(Address(rbp,
+                    (frame::interpreter_frame_result_handler_offset) * wordSize),
+            rax);
 
   // pass mirror handle if static call
   {
@@ -724,25 +874,25 @@
     __ testl(t, JVM_ACC_STATIC);
     __ jcc(Assembler::zero, L);
     // get mirror
-    __ movq(t, Address(method, methodOopDesc::constants_offset()));
-    __ movq(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
-    __ movq(t, Address(t, mirror_offset));
+    __ movptr(t, Address(method, methodOopDesc::constants_offset()));
+    __ movptr(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+    __ movptr(t, Address(t, mirror_offset));
     // copy mirror into activation frame
-    __ movq(Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize),
+    __ movptr(Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize),
             t);
     // pass handle to mirror
-    __ leaq(c_rarg1,
-            Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize));
+    __ lea(c_rarg1,
+           Address(rbp, frame::interpreter_frame_oop_temp_offset * wordSize));
     __ bind(L);
   }
 
   // get native function entry point
   {
     Label L;
-    __ movq(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
     ExternalAddress unsatisfied(SharedRuntime::native_method_throw_unsatisfied_link_error_entry());
     __ movptr(rscratch2, unsatisfied.addr());
-    __ cmpq(rax, rscratch2);
+    __ cmpptr(rax, rscratch2);
     __ jcc(Assembler::notEqual, L);
     __ call_VM(noreg,
                CAST_FROM_FN_PTR(address,
@@ -750,12 +900,12 @@
                method);
     __ get_method(method);
     __ verify_oop(method);
-    __ movq(rax, Address(method, methodOopDesc::native_function_offset()));
+    __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
     __ bind(L);
   }
 
   // pass JNIEnv
-  __ leaq(c_rarg0, Address(r15_thread, JavaThread::jni_environment_offset()));
+  __ lea(c_rarg0, Address(r15_thread, JavaThread::jni_environment_offset()));
 
   // It is enough that the pc() points into the right code
   // segment. It does not have to be the correct return pc.
@@ -786,10 +936,10 @@
   // register after returning from the JNI Call or verify that
   // it wasn't changed during -Xcheck:jni.
   if (RestoreMXCSROnJNICalls) {
-    __ ldmxcsr(ExternalAddress(StubRoutines::amd64::mxcsr_std()));
+    __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
   }
   else if (CheckJNICalls) {
-    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::amd64::verify_mxcsr_entry())));
+    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
   }
 
   // NOTE: The order of these pushes is known to frame::interpreter_frame_result
@@ -838,12 +988,12 @@
     // preserved and correspond to the bcp/locals pointers. So we do a
     // runtime call by hand.
     //
-    __ movq(c_rarg0, r15_thread);
-    __ movq(r12, rsp); // remember sp
-    __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-    __ andq(rsp, -16); // align stack as required by ABI
+    __ mov(c_rarg0, r15_thread);
+    __ mov(r12, rsp); // remember sp
+    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rsp, -16); // align stack as required by ABI
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
-    __ movq(rsp, r12); // restore sp
+    __ mov(rsp, r12); // restore sp
     __ reinit_heapbase();
     __ bind(Continue);
   }
@@ -855,8 +1005,8 @@
   __ reset_last_Java_frame(true, true);
 
   // reset handle block
-  __ movq(t, Address(r15_thread, JavaThread::active_handles_offset()));
-  __ movptr(Address(t, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
+  __ movptr(t, Address(r15_thread, JavaThread::active_handles_offset()));
+  __ movptr(Address(t, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
 
   // If result is an oop unbox and store it in frame where gc will see it
   // and result handler will pick it up
@@ -864,15 +1014,15 @@
   {
     Label no_oop, store_result;
     __ lea(t, ExternalAddress(AbstractInterpreter::result_handler(T_OBJECT)));
-    __ cmpq(t, Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize));
+    __ cmpptr(t, Address(rbp, frame::interpreter_frame_result_handler_offset*wordSize));
     __ jcc(Assembler::notEqual, no_oop);
     // retrieve result
     __ pop(ltos);
-    __ testq(rax, rax);
+    __ testptr(rax, rax);
     __ jcc(Assembler::zero, store_result);
-    __ movq(rax, Address(rax, 0));
+    __ movptr(rax, Address(rax, 0));
     __ bind(store_result);
-    __ movq(Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize), rax);
+    __ movptr(Address(rbp, frame::interpreter_frame_oop_temp_offset*wordSize), rax);
     // keep stack depth as expected by pushing oop which will eventually be discarde
     __ push(ltos);
     __ bind(no_oop);
@@ -885,13 +1035,13 @@
             JavaThread::stack_guard_yellow_disabled);
     __ jcc(Assembler::notEqual, no_reguard);
 
-    __ pushaq(); // XXX only save smashed registers
-    __ movq(r12, rsp); // remember sp
-    __ subq(rsp, frame::arg_reg_save_area_bytes); // windows
-    __ andq(rsp, -16); // align stack as required by ABI
+    __ pusha(); // XXX only save smashed registers
+    __ mov(r12, rsp); // remember sp
+    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+    __ andptr(rsp, -16); // align stack as required by ABI
     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
-    __ movq(rsp, r12); // restore sp
-    __ popaq(); // XXX only restore smashed registers
+    __ mov(rsp, r12); // restore sp
+    __ popa(); // XXX only restore smashed registers
     __ reinit_heapbase();
 
     __ bind(no_reguard);
@@ -906,12 +1056,12 @@
 
   // restore r13 to have legal interpreter frame, i.e., bci == 0 <=>
   // r13 == code_base()
-  __ movq(r13, Address(method, methodOopDesc::const_offset()));   // get constMethodOop
-  __ leaq(r13, Address(r13, constMethodOopDesc::codes_offset())); // get codebase
+  __ movptr(r13, Address(method, methodOopDesc::const_offset()));   // get constMethodOop
+  __ lea(r13, Address(r13, constMethodOopDesc::codes_offset()));    // get codebase
   // handle exceptions (exception handling will handle unlocking!)
   {
     Label L;
-    __ cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int) NULL);
+    __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
     __ jcc(Assembler::zero, L);
     // Note: At some point we may want to unify this with the code
     // used in call_VM_base(); i.e., we should use the
@@ -942,10 +1092,10 @@
                                        wordSize - sizeof(BasicObjectLock)));
 
       // monitor expect in c_rarg1 for slow unlock path
-      __ leaq(c_rarg1, monitor); // address of first monitor
+      __ lea(c_rarg1, monitor); // address of first monitor
 
-      __ movq(t, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
-      __ testq(t, t);
+      __ movptr(t, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
+      __ testptr(t, t);
       __ jcc(Assembler::notZero, unlock);
 
       // Entry already unlocked, need to throw exception
@@ -973,17 +1123,17 @@
   __ pop(ltos);
   __ pop(dtos);
 
-  __ movq(t, Address(rbp,
-                     (frame::interpreter_frame_result_handler_offset) * wordSize));
+  __ movptr(t, Address(rbp,
+                       (frame::interpreter_frame_result_handler_offset) * wordSize));
   __ call(t);
 
   // remove activation
-  __ movq(t, Address(rbp,
-                     frame::interpreter_frame_sender_sp_offset *
-                     wordSize)); // get sender sp
+  __ movptr(t, Address(rbp,
+                       frame::interpreter_frame_sender_sp_offset *
+                       wordSize)); // get sender sp
   __ leave();                                // remove frame anchor
-  __ popq(rdi);                              // get return address
-  __ movq(rsp, t);                           // set sp to sender sp
+  __ pop(rdi);                               // get return address
+  __ mov(rsp, t);                            // set sp to sender sp
   __ jmp(rdi);
 
   if (inc_counter) {
@@ -1032,11 +1182,11 @@
   generate_stack_overflow_check();
 
   // get return address
-  __ popq(rax);
+  __ pop(rax);
 
   // compute beginning of parameters (r14)
   if (TaggedStackInterpreter) __ shll(rcx, 1); // 2 slots per parameter.
-  __ leaq(r14, Address(rsp, rcx, Address::times_8, -wordSize));
+  __ lea(r14, Address(rsp, rcx, Address::times_8, -wordSize));
 
   // rdx - # of additional locals
   // allocate space for locals
@@ -1046,8 +1196,8 @@
     __ testl(rdx, rdx);
     __ jcc(Assembler::lessEqual, exit); // do nothing if rdx <= 0
     __ bind(loop);
-    if (TaggedStackInterpreter) __ pushq((int) NULL);  // push tag
-    __ pushq((int) NULL); // initialize local variables
+    if (TaggedStackInterpreter) __ push((int) NULL_WORD);  // push tag
+    __ push((int) NULL_WORD); // initialize local variables
     __ decrementl(rdx); // until everything initialized
     __ jcc(Assembler::greater, loop);
     __ bind(exit);
@@ -1137,8 +1287,8 @@
     Label L;
      const Address monitor_block_top (rbp,
                  frame::interpreter_frame_monitor_block_top_offset * wordSize);
-    __ movq(rax, monitor_block_top);
-    __ cmpq(rax, rsp);
+    __ movptr(rax, monitor_block_top);
+    __ cmpptr(rax, rsp);
     __ jcc(Assembler::equal, L);
     __ stop("broken stack frame setup in interpreter");
     __ bind(L);
@@ -1160,14 +1310,14 @@
                  CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method),
                  r13, true);
 
-      __ movq(rbx, Address(rbp, method_offset)); // restore methodOop
-      __ movq(rax, Address(rbx,
-                           in_bytes(methodOopDesc::method_data_offset())));
-      __ movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
-              rax);
+      __ movptr(rbx, Address(rbp, method_offset)); // restore methodOop
+      __ movptr(rax, Address(rbx,
+                             in_bytes(methodOopDesc::method_data_offset())));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
+                rax);
       __ test_method_data_pointer(rax, profile_method_continue);
-      __ addq(rax, in_bytes(methodDataOopDesc::data_offset()));
-      __ movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
+      __ addptr(rax, in_bytes(methodDataOopDesc::data_offset()));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
               rax);
       __ jmp(profile_method_continue);
     }
@@ -1357,7 +1507,7 @@
   Interpreter::_rethrow_exception_entry = __ pc();
   // Restore sp to interpreter_frame_last_sp even though we are going
   // to empty the expression stack for the exception processing.
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
   // rax: exception
   // rdx: return address/pc that threw exception
   __ restore_bcp();    // r13 points to call/send
@@ -1369,7 +1519,7 @@
   // rax: exception
   // r13: exception bcp
   __ verify_oop(rax);
-  __ movq(c_rarg1, rax);
+  __ mov(c_rarg1, rax);
 
   // expression stack must be empty before entering the VM in case of
   // an exception
@@ -1424,7 +1574,7 @@
     // deoptimization blob's unpack entry because of the presence of
     // adapter frames in C2.
     Label caller_not_deoptimized;
-    __ movq(c_rarg1, Address(rbp, frame::return_addr_offset * wordSize));
+    __ movptr(c_rarg1, Address(rbp, frame::return_addr_offset * wordSize));
     __ super_call_VM_leaf(CAST_FROM_FN_PTR(address,
                                InterpreterRuntime::interpreter_contains), c_rarg1);
     __ testl(rax, rax);
@@ -1437,8 +1587,8 @@
                                                 size_of_parameters_offset())));
     __ shll(rax, Interpreter::logStackElementSize());
     __ restore_locals(); // XXX do we need this?
-    __ subq(r14, rax);
-    __ addq(r14, wordSize);
+    __ subptr(r14, rax);
+    __ addptr(r14, wordSize);
     // Save these arguments
     __ super_call_VM_leaf(CAST_FROM_FN_PTR(address,
                                            Deoptimization::
@@ -1477,15 +1627,15 @@
   // maintain this kind of invariant all the time we call a small
   // fixup routine to move the mutated arguments onto the top of our
   // expression stack if necessary.
-  __ movq(c_rarg1, rsp);
-  __ movq(c_rarg2, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ mov(c_rarg1, rsp);
+  __ movptr(c_rarg2, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
   // PC must point into interpreter here
   __ set_last_Java_frame(noreg, rbp, __ pc());
   __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::popframe_move_outgoing_args), r15_thread, c_rarg1, c_rarg2);
   __ reset_last_Java_frame(true, true);
   // Restore the last_sp and null it out
-  __ movq(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
-  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
+  __ movptr(rsp, Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize));
+  __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);
 
   __ restore_bcp();  // XXX do we need this?
   __ restore_locals(); // XXX do we need this?
@@ -1506,12 +1656,12 @@
 
   // preserve exception over this code sequence
   __ pop_ptr(rax);
-  __ movq(Address(r15_thread, JavaThread::vm_result_offset()), rax);
+  __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), rax);
   // remove the activation (without doing throws on illegalMonitorExceptions)
   __ remove_activation(vtos, rdx, false, true, false);
   // restore exception
-  __ movq(rax, Address(r15_thread, JavaThread::vm_result_offset()));
-  __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), NULL_WORD);
+  __ movptr(rax, Address(r15_thread, JavaThread::vm_result_offset()));
+  __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
   __ verify_oop(rax);
 
   // In between activations - previous activation type unknown yet
@@ -1522,14 +1672,14 @@
   // rdx: return address/pc that threw exception
   // rsp: expression stack of caller
   // rbp: ebp of caller
-  __ pushq(rax);                                 // save exception
-  __ pushq(rdx);                                 // save return address
+  __ push(rax);                                  // save exception
+  __ push(rdx);                                  // save return address
   __ super_call_VM_leaf(CAST_FROM_FN_PTR(address,
                           SharedRuntime::exception_handler_for_return_address),
                         rdx);
-  __ movq(rbx, rax);                             // save exception handler
-  __ popq(rdx);                                  // restore return address
-  __ popq(rax);                                  // restore exception
+  __ mov(rbx, rax);                              // save exception handler
+  __ pop(rdx);                                   // restore return address
+  __ pop(rax);                                   // restore exception
   // Note that an "issuing PC" is actually the next PC after the call
   __ jmp(rbx);                                   // jump to exception
                                                  // handler of caller
@@ -1547,7 +1697,7 @@
   __ empty_expression_stack();
   __ load_earlyret_value(state);
 
-  __ movq(rdx, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
+  __ movptr(rdx, Address(r15_thread, JavaThread::jvmti_thread_state_offset()));
   Address cond_addr(rdx, JvmtiThreadState::earlyret_state_offset());
 
   // Clear the earlyret state
@@ -1609,21 +1759,21 @@
   address entry = __ pc();
 
   __ push(state);
-  __ pushq(c_rarg0);
-  __ pushq(c_rarg1);
-  __ pushq(c_rarg2);
-  __ pushq(c_rarg3);
-  __ movq(c_rarg2, rax);  // Pass itos
+  __ push(c_rarg0);
+  __ push(c_rarg1);
+  __ push(c_rarg2);
+  __ push(c_rarg3);
+  __ mov(c_rarg2, rax);  // Pass itos
 #ifdef _WIN64
   __ movflt(xmm3, xmm0); // Pass ftos
 #endif
   __ call_VM(noreg,
              CAST_FROM_FN_PTR(address, SharedRuntime::trace_bytecode),
              c_rarg1, c_rarg2, c_rarg3);
-  __ popq(c_rarg3);
-  __ popq(c_rarg2);
-  __ popq(c_rarg1);
-  __ popq(c_rarg0);
+  __ pop(c_rarg3);
+  __ pop(c_rarg2);
+  __ pop(c_rarg1);
+  __ pop(c_rarg0);
   __ pop(state);
   __ ret(0);                                   // return from result handler
 
@@ -1657,10 +1807,10 @@
 
   assert(Interpreter::trace_code(t->tos_in()) != NULL,
          "entry must have been generated");
-  __ movq(r12, rsp); // remember sp
-  __ andq(rsp, -16); // align stack as required by ABI
+  __ mov(r12, rsp); // remember sp
+  __ andptr(rsp, -16); // align stack as required by ABI
   __ call(RuntimeAddress(Interpreter::trace_code(t->tos_in())));
-  __ movq(rsp, r12); // restore sp
+  __ mov(rsp, r12); // restore sp
   __ reinit_heapbase();
 }
 
@@ -1674,3 +1824,4 @@
   __ bind(L);
 }
 #endif // !PRODUCT
+#endif // ! CC_INTERP
--- a/hotspot/src/cpu/x86/vm/templateTable_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/templateTable_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -119,12 +119,14 @@
 
   if (!RewriteBytecodes) return;
   // the pair bytecodes have already done the load.
-  if (load_bc_into_scratch) __ movl(bc, bytecode);
+  if (load_bc_into_scratch) {
+    __ movl(bc, bytecode);
+  }
   Label patch_done;
   if (JvmtiExport::can_post_breakpoint()) {
     Label fast_patch;
     // if a breakpoint is present we can't rewrite the stream directly
-    __ movzxb(scratch, at_bcp(0));
+    __ movzbl(scratch, at_bcp(0));
     __ cmpl(scratch, Bytecodes::_breakpoint);
     __ jcc(Assembler::notEqual, fast_patch);
     __ get_method(scratch);
@@ -169,16 +171,16 @@
 
 void TemplateTable::aconst_null() {
   transition(vtos, atos);
-  __ xorl(rax, rax);
+  __ xorptr(rax, rax);
 }
 
 
 void TemplateTable::iconst(int value) {
   transition(vtos, itos);
   if (value == 0) {
-    __ xorl(rax, rax);
+    __ xorptr(rax, rax);
   } else {
-    __ movl(rax, value);
+    __ movptr(rax, value);
   }
 }
 
@@ -186,12 +188,12 @@
 void TemplateTable::lconst(int value) {
   transition(vtos, ltos);
   if (value == 0) {
-    __ xorl(rax, rax);
+    __ xorptr(rax, rax);
   } else {
-    __ movl(rax, value);
+    __ movptr(rax, value);
   }
   assert(value >= 0, "check this code");
-  __ xorl(rdx, rdx);
+  __ xorptr(rdx, rdx);
 }
 
 
@@ -223,7 +225,7 @@
 void TemplateTable::sipush() {
   transition(vtos, itos);
   __ load_unsigned_word(rax, at_bcp(1));
-  __ bswap(rax);
+  __ bswapl(rax);
   __ sarl(rax, 16);
 }
 
@@ -241,7 +243,7 @@
   const int tags_offset = typeArrayOopDesc::header_size(T_BYTE) * wordSize;
 
   // get type
-  __ xorl(rdx, rdx);
+  __ xorptr(rdx, rdx);
   __ movb(rdx, Address(rax, rbx, Address::times_1, tags_offset));
 
   // unresolved string - get the resolved string
@@ -271,7 +273,7 @@
   __ cmpl(rdx, JVM_CONSTANT_Float);
   __ jccb(Assembler::notEqual, notFloat);
   // ftos
-  __ fld_s(    Address(rcx, rbx, Address::times_4, base_offset));
+  __ fld_s(    Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(ftos);
   __ jmp(Done);
 
@@ -288,13 +290,14 @@
 #endif
   Label isOop;
   // atos and itos
-  __ movl(rax, Address(rcx, rbx, Address::times_4, base_offset));
   // String is only oop type we will see here
   __ cmpl(rdx, JVM_CONSTANT_String);
   __ jccb(Assembler::equal, isOop);
+  __ movl(rax, Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(itos);
   __ jmp(Done);
   __ bind(isOop);
+  __ movptr(rax, Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(atos);
 
   if (VerifyOops) {
@@ -316,14 +319,14 @@
   __ cmpb(Address(rax, rbx, Address::times_1, tags_offset), JVM_CONSTANT_Double);
   __ jccb(Assembler::notEqual, Long);
   // dtos
-  __ fld_d(    Address(rcx, rbx, Address::times_4, base_offset));
+  __ fld_d(    Address(rcx, rbx, Address::times_ptr, base_offset));
   __ push(dtos);
   __ jmpb(Done);
 
   __ bind(Long);
   // ltos
-  __ movl(rax, Address(rcx, rbx, Address::times_4, base_offset + 0 * wordSize));
-  __ movl(rdx, Address(rcx, rbx, Address::times_4, base_offset + 1 * wordSize));
+  __ movptr(rax, Address(rcx, rbx, Address::times_ptr, base_offset + 0 * wordSize));
+  NOT_LP64(__ movptr(rdx, Address(rcx, rbx, Address::times_ptr, base_offset + 1 * wordSize)));
 
   __ push(ltos);
 
@@ -333,7 +336,7 @@
 
 void TemplateTable::locals_index(Register reg, int offset) {
   __ load_unsigned_byte(reg, at_bcp(offset));
-  __ negl(reg);
+  __ negptr(reg);
 }
 
 
@@ -399,8 +402,8 @@
 void TemplateTable::lload() {
   transition(vtos, ltos);
   locals_index(rbx);
-  __ movl(rax, laddress(rbx));
-  __ movl(rdx, haddress(rbx));
+  __ movptr(rax, laddress(rbx));
+  NOT_LP64(__ movl(rdx, haddress(rbx)));
   debug_only(__ verify_local_tag(frame::TagCategory2, rbx));
 }
 
@@ -421,10 +424,10 @@
     // float instruction into ST0
     __ movl(rax, laddress(rbx));
     __ movl(rdx, haddress(rbx));
-    __ pushl(rdx);  // push hi first
-    __ pushl(rax);
+    __ push(rdx);  // push hi first
+    __ push(rax);
     __ fld_d(Address(rsp, 0));
-    __ addl(rsp, 2*wordSize);
+    __ addptr(rsp, 2*wordSize);
     debug_only(__ verify_local_tag(frame::TagCategory2, rbx));
   } else {
     __ fld_d(daddress(rbx));
@@ -435,16 +438,16 @@
 void TemplateTable::aload() {
   transition(vtos, atos);
   locals_index(rbx);
-  __ movl(rax, iaddress(rbx));
+  __ movptr(rax, aaddress(rbx));
   debug_only(__ verify_local_tag(frame::TagReference, rbx));
 }
 
 
 void TemplateTable::locals_index_wide(Register reg) {
   __ movl(reg, at_bcp(2));
-  __ bswap(reg);
+  __ bswapl(reg);
   __ shrl(reg, 16);
-  __ negl(reg);
+  __ negptr(reg);
 }
 
 
@@ -459,8 +462,8 @@
 void TemplateTable::wide_lload() {
   transition(vtos, ltos);
   locals_index_wide(rbx);
-  __ movl(rax, laddress(rbx));
-  __ movl(rdx, haddress(rbx));
+  __ movptr(rax, laddress(rbx));
+  NOT_LP64(__ movl(rdx, haddress(rbx)));
   debug_only(__ verify_local_tag(frame::TagCategory2, rbx));
 }
 
@@ -481,8 +484,8 @@
     // float instruction into ST0
     __ movl(rax, laddress(rbx));
     __ movl(rdx, haddress(rbx));
-    __ pushl(rdx);  // push hi first
-    __ pushl(rax);
+    __ push(rdx);  // push hi first
+    __ push(rax);
     __ fld_d(Address(rsp, 0));
     __ addl(rsp, 2*wordSize);
     debug_only(__ verify_local_tag(frame::TagCategory2, rbx));
@@ -495,7 +498,7 @@
 void TemplateTable::wide_aload() {
   transition(vtos, atos);
   locals_index_wide(rbx);
-  __ movl(rax, iaddress(rbx));
+  __ movptr(rax, aaddress(rbx));
   debug_only(__ verify_local_tag(frame::TagReference, rbx));
 }
 
@@ -509,12 +512,13 @@
   // destroys rbx,
   // check array
   __ null_check(array, arrayOopDesc::length_offset_in_bytes());
+  LP64_ONLY(__ movslq(index, index));
   // check index
   __ cmpl(index, Address(array, arrayOopDesc::length_offset_in_bytes()));
   if (index != rbx) {
     // ??? convention: move aberrant index into rbx, for exception message
     assert(rbx != array, "different registers");
-    __ movl(rbx, index);
+    __ mov(rbx, index);
   }
   __ jump_cc(Assembler::aboveEqual,
              ExternalAddress(Interpreter::_throw_ArrayIndexOutOfBoundsException_entry));
@@ -535,10 +539,10 @@
   // rax,: index
   // rdx: array
   index_check(rdx, rax);
-  __ movl(rbx, rax);
+  __ mov(rbx, rax);
   // rbx,: index
-  __ movl(rax, Address(rdx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 0 * wordSize));
-  __ movl(rdx, Address(rdx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize));
+  __ movptr(rax, Address(rdx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 0 * wordSize));
+  NOT_LP64(__ movl(rdx, Address(rdx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize)));
 }
 
 
@@ -565,7 +569,7 @@
   // rdx: array
   index_check(rdx, rax);  // kills rbx,
   // rax,: index
-  __ movl(rax, Address(rdx, rax, Address::times_4, arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
+  __ movptr(rax, Address(rdx, rax, Address::times_ptr, arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
 }
 
 
@@ -576,7 +580,7 @@
   // rax,: index
   // can do better code for P5 - fix this at some point
   __ load_signed_byte(rbx, Address(rdx, rax, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_BYTE)));
-  __ movl(rax, rbx);
+  __ mov(rax, rbx);
 }
 
 
@@ -587,7 +591,7 @@
   // rax,: index
   // can do better code for P5 - may want to improve this at some point
   __ load_unsigned_word(rbx, Address(rdx, rax, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
-  __ movl(rax, rbx);
+  __ mov(rax, rbx);
 }
 
 // iload followed by caload frequent pair
@@ -602,7 +606,7 @@
   index_check(rdx, rax);
   // rax,: index
   __ load_unsigned_word(rbx, Address(rdx, rax, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
-  __ movl(rax, rbx);
+  __ mov(rax, rbx);
 }
 
 void TemplateTable::saload() {
@@ -612,7 +616,7 @@
   // rax,: index
   // can do better code for P5 - may want to improve this at some point
   __ load_signed_word(rbx, Address(rdx, rax, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_SHORT)));
-  __ movl(rax, rbx);
+  __ mov(rax, rbx);
 }
 
 
@@ -625,8 +629,8 @@
 
 void TemplateTable::lload(int n) {
   transition(vtos, ltos);
-  __ movl(rax, laddress(n));
-  __ movl(rdx, haddress(n));
+  __ movptr(rax, laddress(n));
+  NOT_LP64(__ movptr(rdx, haddress(n)));
   debug_only(__ verify_local_tag(frame::TagCategory2, n));
 }
 
@@ -645,10 +649,10 @@
     // float instruction into ST0
     __ movl(rax, laddress(n));
     __ movl(rdx, haddress(n));
-    __ pushl(rdx);  // push hi first
-    __ pushl(rax);
+    __ push(rdx);  // push hi first
+    __ push(rax);
     __ fld_d(Address(rsp, 0));
-    __ addl(rsp, 2*wordSize);  // reset rsp
+    __ addptr(rsp, 2*wordSize);  // reset rsp
     debug_only(__ verify_local_tag(frame::TagCategory2, n));
   } else {
     __ fld_d(daddress(n));
@@ -658,7 +662,7 @@
 
 void TemplateTable::aload(int n) {
   transition(vtos, atos);
-  __ movl(rax, aaddress(n));
+  __ movptr(rax, aaddress(n));
   debug_only(__ verify_local_tag(frame::TagReference, n));
 }
 
@@ -740,8 +744,8 @@
 void TemplateTable::lstore() {
   transition(ltos, vtos);
   locals_index(rbx);
-  __ movl(laddress(rbx), rax);
-  __ movl(haddress(rbx), rdx);
+  __ movptr(laddress(rbx), rax);
+  NOT_LP64(__ movptr(haddress(rbx), rdx));
   __ tag_local(frame::TagCategory2, rbx);
 }
 
@@ -759,12 +763,12 @@
   locals_index(rbx);
   if (TaggedStackInterpreter) {
     // Store double on stack and reload into locals nonadjacently
-    __ subl(rsp, 2 * wordSize);
+    __ subptr(rsp, 2 * wordSize);
     __ fstp_d(Address(rsp, 0));
-    __ popl(rax);
-    __ popl(rdx);
-    __ movl(laddress(rbx), rax);
-    __ movl(haddress(rbx), rdx);
+    __ pop(rax);
+    __ pop(rdx);
+    __ movptr(laddress(rbx), rax);
+    __ movptr(haddress(rbx), rdx);
     __ tag_local(frame::TagCategory2, rbx);
   } else {
     __ fstp_d(daddress(rbx));
@@ -776,7 +780,7 @@
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);   // will need to pop tag too
   locals_index(rbx);
-  __ movl(aaddress(rbx), rax);
+  __ movptr(aaddress(rbx), rax);
   __ tag_local(rdx, rbx);    // need to store same tag in local may be returnAddr
 }
 
@@ -794,8 +798,8 @@
   transition(vtos, vtos);
   __ pop_l(rax, rdx);
   locals_index_wide(rbx);
-  __ movl(laddress(rbx), rax);
-  __ movl(haddress(rbx), rdx);
+  __ movptr(laddress(rbx), rax);
+  NOT_LP64(__ movl(haddress(rbx), rdx));
   __ tag_local(frame::TagCategory2, rbx);
 }
 
@@ -814,7 +818,7 @@
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);
   locals_index_wide(rbx);
-  __ movl(aaddress(rbx), rax);
+  __ movptr(aaddress(rbx), rax);
   __ tag_local(rdx, rbx);
 }
 
@@ -838,8 +842,8 @@
   // rdx: high(value)
   index_check(rcx, rbx);  // prefer index in rbx,
   // rbx,: index
-  __ movl(Address(rcx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 0 * wordSize), rax);
-  __ movl(Address(rcx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize), rdx);
+  __ movptr(Address(rcx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 0 * wordSize), rax);
+  NOT_LP64(__ movl(Address(rcx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize), rdx));
 }
 
 
@@ -869,21 +873,21 @@
   Label is_null, ok_is_subtype, done;
   transition(vtos, vtos);
   // stack: ..., array, index, value
-  __ movl(rax, at_tos());     // Value
+  __ movptr(rax, at_tos());     // Value
   __ movl(rcx, at_tos_p1());  // Index
-  __ movl(rdx, at_tos_p2());  // Array
+  __ movptr(rdx, at_tos_p2());  // Array
   index_check_without_pop(rdx, rcx);      // kills rbx,
   // do array store check - check for NULL value first
-  __ testl(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, is_null);
 
   // Move subklass into EBX
-  __ movl(rbx, Address(rax, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rbx, Address(rax, oopDesc::klass_offset_in_bytes()));
   // Move superklass into EAX
-  __ movl(rax, Address(rdx, oopDesc::klass_offset_in_bytes()));
-  __ movl(rax, Address(rax, sizeof(oopDesc) + objArrayKlass::element_klass_offset_in_bytes()));
-  // Compress array+index*4+12 into a single register.  Frees ECX.
-  __ leal(rdx, Address(rdx, rcx, Address::times_4, arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
+  __ movptr(rax, Address(rdx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rax, Address(rax, sizeof(oopDesc) + objArrayKlass::element_klass_offset_in_bytes()));
+  // Compress array+index*wordSize+12 into a single register.  Frees ECX.
+  __ lea(rdx, Address(rdx, rcx, Address::times_ptr, arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
 
   // Generate subtype check.  Blows ECX.  Resets EDI to locals.
   // Superklass in EAX.  Subklass in EBX.
@@ -895,19 +899,19 @@
 
   // Come here on success
   __ bind(ok_is_subtype);
-  __ movl(rax, at_rsp());     // Value
-  __ movl(Address(rdx, 0), rax);
+  __ movptr(rax, at_rsp());     // Value
+  __ movptr(Address(rdx, 0), rax);
   __ store_check(rdx);
   __ jmpb(done);
 
   // Have a NULL in EAX, EDX=array, ECX=index.  Store NULL at ary[idx]
   __ bind(is_null);
   __ profile_null_seen(rbx);
-  __ movl(Address(rdx, rcx, Address::times_4, arrayOopDesc::base_offset_in_bytes(T_OBJECT)), rax);
+  __ movptr(Address(rdx, rcx, Address::times_ptr, arrayOopDesc::base_offset_in_bytes(T_OBJECT)), rax);
 
   // Pop stack arguments
   __ bind(done);
-  __ addl(rsp, 3 * Interpreter::stackElementSize());
+  __ addptr(rsp, 3 * Interpreter::stackElementSize());
 }
 
 
@@ -947,8 +951,8 @@
 
 void TemplateTable::lstore(int n) {
   transition(ltos, vtos);
-  __ movl(laddress(n), rax);
-  __ movl(haddress(n), rdx);
+  __ movptr(laddress(n), rax);
+  NOT_LP64(__ movptr(haddress(n), rdx));
   __ tag_local(frame::TagCategory2, n);
 }
 
@@ -963,10 +967,10 @@
 void TemplateTable::dstore(int n) {
   transition(dtos, vtos);
   if (TaggedStackInterpreter) {
-    __ subl(rsp, 2 * wordSize);
+    __ subptr(rsp, 2 * wordSize);
     __ fstp_d(Address(rsp, 0));
-    __ popl(rax);
-    __ popl(rdx);
+    __ pop(rax);
+    __ pop(rdx);
     __ movl(laddress(n), rax);
     __ movl(haddress(n), rdx);
     __ tag_local(frame::TagCategory2, n);
@@ -979,20 +983,20 @@
 void TemplateTable::astore(int n) {
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);
-  __ movl(aaddress(n), rax);
+  __ movptr(aaddress(n), rax);
   __ tag_local(rdx, n);
 }
 
 
 void TemplateTable::pop() {
   transition(vtos, vtos);
-  __ addl(rsp, Interpreter::stackElementSize());
+  __ addptr(rsp, Interpreter::stackElementSize());
 }
 
 
 void TemplateTable::pop2() {
   transition(vtos, vtos);
-  __ addl(rsp, 2*Interpreter::stackElementSize());
+  __ addptr(rsp, 2*Interpreter::stackElementSize());
 }
 
 
@@ -1099,14 +1103,14 @@
   transition(itos, itos);
   switch (op) {
     case add  :                    __ pop_i(rdx); __ addl (rax, rdx); break;
-    case sub  : __ movl(rdx, rax); __ pop_i(rax); __ subl (rax, rdx); break;
+    case sub  : __ mov(rdx, rax); __ pop_i(rax); __ subl (rax, rdx); break;
     case mul  :                    __ pop_i(rdx); __ imull(rax, rdx); break;
     case _and :                    __ pop_i(rdx); __ andl (rax, rdx); break;
     case _or  :                    __ pop_i(rdx); __ orl  (rax, rdx); break;
     case _xor :                    __ pop_i(rdx); __ xorl (rax, rdx); break;
-    case shl  : __ movl(rcx, rax); __ pop_i(rax); __ shll (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
-    case shr  : __ movl(rcx, rax); __ pop_i(rax); __ sarl (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
-    case ushr : __ movl(rcx, rax); __ pop_i(rax); __ shrl (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
+    case shl  : __ mov(rcx, rax); __ pop_i(rax); __ shll (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
+    case shr  : __ mov(rcx, rax); __ pop_i(rax); __ sarl (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
+    case ushr : __ mov(rcx, rax); __ pop_i(rax); __ shrl (rax);      break; // implicit masking of lower 5 bits by Intel shift instr.
     default   : ShouldNotReachHere();
   }
 }
@@ -1118,7 +1122,7 @@
   switch (op) {
     case add : __ addl(rax, rbx); __ adcl(rdx, rcx); break;
     case sub : __ subl(rbx, rax); __ sbbl(rcx, rdx);
-               __ movl(rax, rbx); __ movl(rdx, rcx); break;
+               __ mov(rax, rbx); __ mov(rdx, rcx); break;
     case _and: __ andl(rax, rbx); __ andl(rdx, rcx); break;
     case _or : __ orl (rax, rbx); __ orl (rdx, rcx); break;
     case _xor: __ xorl(rax, rbx); __ xorl(rdx, rcx); break;
@@ -1129,7 +1133,7 @@
 
 void TemplateTable::idiv() {
   transition(itos, itos);
-  __ movl(rcx, rax);
+  __ mov(rcx, rax);
   __ pop_i(rax);
   // Note: could xor rax, and rcx and compare with (-1 ^ min_int). If
   //       they are not equal, one could do a normal division (no correction
@@ -1141,52 +1145,52 @@
 
 void TemplateTable::irem() {
   transition(itos, itos);
-  __ movl(rcx, rax);
+  __ mov(rcx, rax);
   __ pop_i(rax);
   // Note: could xor rax, and rcx and compare with (-1 ^ min_int). If
   //       they are not equal, one could do a normal division (no correction
   //       needed), which may speed up this implementation for the common case.
   //       (see also JVM spec., p.243 & p.271)
   __ corrected_idivl(rcx);
-  __ movl(rax, rdx);
+  __ mov(rax, rdx);
 }
 
 
 void TemplateTable::lmul() {
   transition(ltos, ltos);
   __ pop_l(rbx, rcx);
-  __ pushl(rcx); __ pushl(rbx);
-  __ pushl(rdx); __ pushl(rax);
+  __ push(rcx); __ push(rbx);
+  __ push(rdx); __ push(rax);
   __ lmul(2 * wordSize, 0);
-  __ addl(rsp, 4 * wordSize);  // take off temporaries
+  __ addptr(rsp, 4 * wordSize);  // take off temporaries
 }
 
 
 void TemplateTable::ldiv() {
   transition(ltos, ltos);
   __ pop_l(rbx, rcx);
-  __ pushl(rcx); __ pushl(rbx);
-  __ pushl(rdx); __ pushl(rax);
+  __ push(rcx); __ push(rbx);
+  __ push(rdx); __ push(rax);
   // check if y = 0
   __ orl(rax, rdx);
   __ jump_cc(Assembler::zero,
              ExternalAddress(Interpreter::_throw_ArithmeticException_entry));
   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::ldiv));
-  __ addl(rsp, 4 * wordSize);  // take off temporaries
+  __ addptr(rsp, 4 * wordSize);  // take off temporaries
 }
 
 
 void TemplateTable::lrem() {
   transition(ltos, ltos);
   __ pop_l(rbx, rcx);
-  __ pushl(rcx); __ pushl(rbx);
-  __ pushl(rdx); __ pushl(rax);
+  __ push(rcx); __ push(rbx);
+  __ push(rdx); __ push(rax);
   // check if y = 0
   __ orl(rax, rdx);
   __ jump_cc(Assembler::zero,
              ExternalAddress(Interpreter::_throw_ArithmeticException_entry));
   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::lrem));
-  __ addl(rsp, 4 * wordSize);
+  __ addptr(rsp, 4 * wordSize);
 }
 
 
@@ -1200,7 +1204,7 @@
 
 void TemplateTable::lshr() {
   transition(itos, ltos);
-  __ movl(rcx, rax);                             // get shift count
+  __ mov(rcx, rax);                              // get shift count
   __ pop_l(rax, rdx);                            // get shift value
   __ lshr(rdx, rax, true);
 }
@@ -1208,7 +1212,7 @@
 
 void TemplateTable::lushr() {
   transition(itos, ltos);
-  __ movl(rcx, rax);                             // get shift count
+  __ mov(rcx, rax);                              // get shift count
   __ pop_l(rax, rdx);                            // get shift value
   __ lshr(rdx, rax);
 }
@@ -1226,7 +1230,7 @@
     default : ShouldNotReachHere();
   }
   __ f2ieee();
-  __ popl(rax);  // pop float thing off
+  __ pop(rax);  // pop float thing off
 }
 
 
@@ -1280,8 +1284,8 @@
   }
   __ d2ieee();
   // Pop double precision number from rsp.
-  __ popl(rax);
-  __ popl(rdx);
+  __ pop(rax);
+  __ pop(rdx);
 }
 
 
@@ -1321,7 +1325,7 @@
   transition(vtos, vtos);
   __ movl(rdx, at_bcp(4));                       // get constant
   locals_index_wide(rbx);
-  __ bswap(rdx);                                 // swap bytes & sign-extend constant
+  __ bswapl(rdx);                                 // swap bytes & sign-extend constant
   __ sarl(rdx, 16);
   __ addl(iaddress(rbx), rdx);
   // Note: should probably use only one movl to get both
@@ -1375,62 +1379,65 @@
 #endif // ASSERT
 
   // Conversion
-  // (Note: use pushl(rcx)/popl(rcx) for 1/2-word stack-ptr manipulation)
+  // (Note: use push(rcx)/pop(rcx) for 1/2-word stack-ptr manipulation)
   switch (bytecode()) {
     case Bytecodes::_i2l:
       __ extend_sign(rdx, rax);
       break;
     case Bytecodes::_i2f:
-      __ pushl(rax);         // store int on tos
+      __ push(rax);          // store int on tos
       __ fild_s(at_rsp());   // load int to ST0
       __ f2ieee();           // truncate to float size
-      __ popl(rcx);          // adjust rsp
+      __ pop(rcx);           // adjust rsp
       break;
     case Bytecodes::_i2d:
-      __ pushl(rax);         // add one slot for d2ieee()
-      __ pushl(rax);         // store int on tos
+      __ push(rax);          // add one slot for d2ieee()
+      __ push(rax);          // store int on tos
       __ fild_s(at_rsp());   // load int to ST0
       __ d2ieee();           // truncate to double size
-      __ popl(rcx);          // adjust rsp
-      __ popl(rcx);
+      __ pop(rcx);           // adjust rsp
+      __ pop(rcx);
       break;
     case Bytecodes::_i2b:
       __ shll(rax, 24);      // truncate upper 24 bits
       __ sarl(rax, 24);      // and sign-extend byte
+      LP64_ONLY(__ movsbl(rax, rax));
       break;
     case Bytecodes::_i2c:
       __ andl(rax, 0xFFFF);  // truncate upper 16 bits
+      LP64_ONLY(__ movzwl(rax, rax));
       break;
     case Bytecodes::_i2s:
       __ shll(rax, 16);      // truncate upper 16 bits
       __ sarl(rax, 16);      // and sign-extend short
+      LP64_ONLY(__ movswl(rax, rax));
       break;
     case Bytecodes::_l2i:
       /* nothing to do */
       break;
     case Bytecodes::_l2f:
-      __ pushl(rdx);         // store long on tos
-      __ pushl(rax);
+      __ push(rdx);          // store long on tos
+      __ push(rax);
       __ fild_d(at_rsp());   // load long to ST0
       __ f2ieee();           // truncate to float size
-      __ popl(rcx);          // adjust rsp
-      __ popl(rcx);
+      __ pop(rcx);           // adjust rsp
+      __ pop(rcx);
       break;
     case Bytecodes::_l2d:
-      __ pushl(rdx);         // store long on tos
-      __ pushl(rax);
+      __ push(rdx);          // store long on tos
+      __ push(rax);
       __ fild_d(at_rsp());   // load long to ST0
       __ d2ieee();           // truncate to double size
-      __ popl(rcx);          // adjust rsp
-      __ popl(rcx);
+      __ pop(rcx);           // adjust rsp
+      __ pop(rcx);
       break;
     case Bytecodes::_f2i:
-      __ pushl(rcx);         // reserve space for argument
+      __ push(rcx);          // reserve space for argument
       __ fstp_s(at_rsp());   // pass float argument on stack
       __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
       break;
     case Bytecodes::_f2l:
-      __ pushl(rcx);         // reserve space for argument
+      __ push(rcx);          // reserve space for argument
       __ fstp_s(at_rsp());   // pass float argument on stack
       __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
       break;
@@ -1438,21 +1445,21 @@
       /* nothing to do */
       break;
     case Bytecodes::_d2i:
-      __ pushl(rcx);         // reserve space for argument
-      __ pushl(rcx);
+      __ push(rcx);          // reserve space for argument
+      __ push(rcx);
       __ fstp_d(at_rsp());   // pass double argument on stack
       __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 2);
       break;
     case Bytecodes::_d2l:
-      __ pushl(rcx);         // reserve space for argument
-      __ pushl(rcx);
+      __ push(rcx);          // reserve space for argument
+      __ push(rcx);
       __ fstp_d(at_rsp());   // pass double argument on stack
       __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 2);
       break;
     case Bytecodes::_d2f:
-      __ pushl(rcx);         // reserve space for f2ieee()
+      __ push(rcx);          // reserve space for f2ieee()
       __ f2ieee();           // truncate to float size
-      __ popl(rcx);          // adjust rsp
+      __ pop(rcx);           // adjust rsp
       break;
     default             :
       ShouldNotReachHere();
@@ -1465,7 +1472,7 @@
   // y = rdx:rax
   __ pop_l(rbx, rcx);             // get x = rcx:rbx
   __ lcmp2int(rcx, rbx, rdx, rax);// rcx := cmp(x, y)
-  __ movl(rax, rcx);
+  __ mov(rax, rcx);
 }
 
 
@@ -1476,9 +1483,9 @@
   } else {
     __ pop_dtos_to_rsp();
     __ fld_d(at_rsp());
-    __ popl(rdx);
+    __ pop(rdx);
   }
-  __ popl(rcx);
+  __ pop(rcx);
   __ fcmp2int(rax, unordered_result < 0);
 }
 
@@ -1493,8 +1500,10 @@
 
   // Load up EDX with the branch displacement
   __ movl(rdx, at_bcp(1));
-  __ bswap(rdx);
+  __ bswapl(rdx);
   if (!is_wide) __ sarl(rdx, 16);
+  LP64_ONLY(__ movslq(rdx, rdx));
+
 
   // Handle all the JSR stuff here, then exit.
   // It's much shorter and cleaner than intermingling with the
@@ -1504,10 +1513,10 @@
     __ load_unsigned_byte(rbx, Address(rsi, rdx, Address::times_1, 0));
 
     // compute return address as bci in rax,
-    __ leal(rax, at_bcp((is_wide ? 5 : 3) - in_bytes(constMethodOopDesc::codes_offset())));
-    __ subl(rax, Address(rcx, methodOopDesc::const_offset()));
+    __ lea(rax, at_bcp((is_wide ? 5 : 3) - in_bytes(constMethodOopDesc::codes_offset())));
+    __ subptr(rax, Address(rcx, methodOopDesc::const_offset()));
     // Adjust the bcp in ESI by the displacement in EDX
-    __ addl(rsi, rdx);
+    __ addptr(rsi, rdx);
     // Push return address
     __ push_i(rax);
     // jsr returns vtos
@@ -1518,7 +1527,7 @@
   // Normal (non-jsr) branch handling
 
   // Adjust the bcp in ESI by the displacement in EDX
-  __ addl(rsi, rdx);
+  __ addptr(rsi, rdx);
 
   assert(UseLoopCounter || !UseOnStackReplacement, "on-stack-replacement requires loop counters");
   Label backedge_counter_overflow;
@@ -1537,7 +1546,7 @@
 
     // increment counter
     __ movl(rax, Address(rcx, be_offset));        // load backedge counter
-    __ increment(rax, InvocationCounter::count_increment); // increment counter
+    __ incrementl(rax, InvocationCounter::count_increment); // increment counter
     __ movl(Address(rcx, be_offset), rax);        // store counter
 
     __ movl(rax, Address(rcx, inv_offset));    // load invocation counter
@@ -1565,7 +1574,7 @@
         // routine while the method is being compiled, add a second test to make
         // sure the overflow function is called only once every overflow_frequency.
         const int overflow_frequency = 1024;
-        __ andl(rbx, overflow_frequency-1);
+        __ andptr(rbx, overflow_frequency-1);
         __ jcc(Assembler::zero, backedge_counter_overflow);
 
       }
@@ -1596,14 +1605,14 @@
       __ bind(profile_method);
       __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method), rsi);
       __ load_unsigned_byte(rbx, Address(rsi, 0));  // restore target bytecode
-      __ movl(rcx, Address(rbp, method_offset));
-      __ movl(rcx, Address(rcx, in_bytes(methodOopDesc::method_data_offset())));
-      __ movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rcx);
+      __ movptr(rcx, Address(rbp, method_offset));
+      __ movptr(rcx, Address(rcx, in_bytes(methodOopDesc::method_data_offset())));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rcx);
       __ test_method_data_pointer(rcx, dispatch);
       // offset non-null mdp by MDO::data_offset() + IR::profile_method()
-      __ addl(rcx, in_bytes(methodDataOopDesc::data_offset()));
-      __ addl(rcx, rax);
-      __ movl(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rcx);
+      __ addptr(rcx, in_bytes(methodDataOopDesc::data_offset()));
+      __ addptr(rcx, rax);
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize), rcx);
       __ jmp(dispatch);
     }
 
@@ -1611,8 +1620,8 @@
 
       // invocation counter overflow
       __ bind(backedge_counter_overflow);
-      __ negl(rdx);
-      __ addl(rdx, rsi);        // branch bcp
+      __ negptr(rdx);
+      __ addptr(rdx, rsi);        // branch bcp
       call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), rdx);
       __ load_unsigned_byte(rbx, Address(rsi, 0));  // restore target bytecode
 
@@ -1621,7 +1630,7 @@
       // rdx: scratch
       // rdi: locals pointer
       // rsi: bcp
-      __ testl(rax, rax);                        // test result
+      __ testptr(rax, rax);                      // test result
       __ jcc(Assembler::zero, dispatch);         // no osr if null
       // nmethod may have been invalidated (VM may block upon call_VM return)
       __ movl(rcx, Address(rax, nmethod::entry_bci_offset()));
@@ -1632,19 +1641,19 @@
       // We need to prepare to execute the OSR method. First we must
       // migrate the locals and monitors off of the stack.
 
-      __ movl(rbx, rax);                             // save the nmethod
+      __ mov(rbx, rax);                             // save the nmethod
 
       const Register thread = rcx;
       __ get_thread(thread);
       call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::OSR_migration_begin));
       // rax, is OSR buffer, move it to expected parameter location
-      __ movl(rcx, rax);
+      __ mov(rcx, rax);
 
       // pop the interpreter frame
-      __ movl(rdx, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
+      __ movptr(rdx, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
       __ leave();                                // remove frame anchor
-      __ popl(rdi);                              // get return address
-      __ movl(rsp, rdx);                         // set sp to sender sp
+      __ pop(rdi);                               // get return address
+      __ mov(rsp, rdx);                          // set sp to sender sp
 
 
       Label skip;
@@ -1663,29 +1672,29 @@
       __ jcc(Assembler::notEqual, chkint);
 
       // yes adjust to the specialized call stub  return.
-      assert(StubRoutines::i486::get_call_stub_compiled_return() != NULL, "must be set");
-      __ lea(rdi, ExternalAddress(StubRoutines::i486::get_call_stub_compiled_return()));
+      assert(StubRoutines::x86::get_call_stub_compiled_return() != NULL, "must be set");
+      __ lea(rdi, ExternalAddress(StubRoutines::x86::get_call_stub_compiled_return()));
       __ jmp(skip);
 
       __ bind(chkint);
 
       // Are we returning to the interpreter? Look for sentinel
 
-      __ cmpl(Address(rdi, -8), Interpreter::return_sentinel);
+      __ cmpl(Address(rdi, -2*wordSize), Interpreter::return_sentinel);
       __ jcc(Assembler::notEqual, skip);
 
       // Adjust to compiled return back to interpreter
 
-      __ movl(rdi, Address(rdi, -4));
+      __ movptr(rdi, Address(rdi, -wordSize));
       __ bind(skip);
 
       // Align stack pointer for compiled code (note that caller is
       // responsible for undoing this fixup by remembering the old SP
       // in an rbp,-relative location)
-      __ andl(rsp, -(StackAlignmentInBytes));
+      __ andptr(rsp, -(StackAlignmentInBytes));
 
       // push the (possibly adjusted) return address
-      __ pushl(rdi);
+      __ push(rdi);
 
       // and begin the OSR nmethod
       __ jmp(Address(rbx, nmethod::osr_entry_point_offset()));
@@ -1723,7 +1732,7 @@
   transition(atos, vtos);
   // assume branch is more often taken than not (loops use backward branches)
   Label not_taken;
-  __ testl(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(j_not(cc), not_taken);
   branch(false, false);
   __ bind(not_taken);
@@ -1736,7 +1745,7 @@
   // assume branch is more often taken than not (loops use backward branches)
   Label not_taken;
   __ pop_ptr(rdx);
-  __ cmpl(rdx, rax);
+  __ cmpptr(rdx, rax);
   __ jcc(j_not(cc), not_taken);
   branch(false, false);
   __ bind(not_taken);
@@ -1747,12 +1756,12 @@
 void TemplateTable::ret() {
   transition(vtos, vtos);
   locals_index(rbx);
-  __ movl(rbx, iaddress(rbx));                   // get return bci, compute return bcp
+  __ movptr(rbx, iaddress(rbx));                   // get return bci, compute return bcp
   __ profile_ret(rbx, rcx);
   __ get_method(rax);
-  __ movl(rsi, Address(rax, methodOopDesc::const_offset()));
-  __ leal(rsi, Address(rsi, rbx, Address::times_1,
-                       constMethodOopDesc::codes_offset()));
+  __ movptr(rsi, Address(rax, methodOopDesc::const_offset()));
+  __ lea(rsi, Address(rsi, rbx, Address::times_1,
+                      constMethodOopDesc::codes_offset()));
   __ dispatch_next(vtos);
 }
 
@@ -1760,11 +1769,11 @@
 void TemplateTable::wide_ret() {
   transition(vtos, vtos);
   locals_index_wide(rbx);
-  __ movl(rbx, iaddress(rbx));                   // get return bci, compute return bcp
+  __ movptr(rbx, iaddress(rbx));                   // get return bci, compute return bcp
   __ profile_ret(rbx, rcx);
   __ get_method(rax);
-  __ movl(rsi, Address(rax, methodOopDesc::const_offset()));
-  __ leal(rsi, Address(rsi, rbx, Address::times_1, constMethodOopDesc::codes_offset()));
+  __ movptr(rsi, Address(rax, methodOopDesc::const_offset()));
+  __ lea(rsi, Address(rsi, rbx, Address::times_1, constMethodOopDesc::codes_offset()));
   __ dispatch_next(vtos);
 }
 
@@ -1773,13 +1782,13 @@
   Label default_case, continue_execution;
   transition(itos, vtos);
   // align rsi
-  __ leal(rbx, at_bcp(wordSize));
-  __ andl(rbx, -wordSize);
+  __ lea(rbx, at_bcp(wordSize));
+  __ andptr(rbx, -wordSize);
   // load lo & hi
   __ movl(rcx, Address(rbx, 1 * wordSize));
   __ movl(rdx, Address(rbx, 2 * wordSize));
-  __ bswap(rcx);
-  __ bswap(rdx);
+  __ bswapl(rcx);
+  __ bswapl(rdx);
   // check against lo & hi
   __ cmpl(rax, rcx);
   __ jccb(Assembler::less, default_case);
@@ -1787,13 +1796,13 @@
   __ jccb(Assembler::greater, default_case);
   // lookup dispatch offset
   __ subl(rax, rcx);
-  __ movl(rdx, Address(rbx, rax, Address::times_4, 3 * wordSize));
+  __ movl(rdx, Address(rbx, rax, Address::times_4, 3 * BytesPerInt));
   __ profile_switch_case(rax, rbx, rcx);
   // continue execution
   __ bind(continue_execution);
-  __ bswap(rdx);
+  __ bswapl(rdx);
   __ load_unsigned_byte(rbx, Address(rsi, rdx, Address::times_1));
-  __ addl(rsi, rdx);
+  __ addptr(rsi, rdx);
   __ dispatch_only(vtos);
   // handle default
   __ bind(default_case);
@@ -1812,21 +1821,21 @@
 void TemplateTable::fast_linearswitch() {
   transition(itos, vtos);
   Label loop_entry, loop, found, continue_execution;
-  // bswap rax, so we can avoid bswapping the table entries
-  __ bswap(rax);
+  // bswapl rax, so we can avoid bswapping the table entries
+  __ bswapl(rax);
   // align rsi
-  __ leal(rbx, at_bcp(wordSize));                // btw: should be able to get rid of this instruction (change offsets below)
-  __ andl(rbx, -wordSize);
+  __ lea(rbx, at_bcp(wordSize));                // btw: should be able to get rid of this instruction (change offsets below)
+  __ andptr(rbx, -wordSize);
   // set counter
   __ movl(rcx, Address(rbx, wordSize));
-  __ bswap(rcx);
+  __ bswapl(rcx);
   __ jmpb(loop_entry);
   // table search
   __ bind(loop);
   __ cmpl(rax, Address(rbx, rcx, Address::times_8, 2 * wordSize));
   __ jccb(Assembler::equal, found);
   __ bind(loop_entry);
-  __ decrement(rcx);
+  __ decrementl(rcx);
   __ jcc(Assembler::greaterEqual, loop);
   // default case
   __ profile_switch_default(rax);
@@ -1838,9 +1847,9 @@
   __ profile_switch_case(rcx, rax, rbx);
   // continue execution
   __ bind(continue_execution);
-  __ bswap(rdx);
+  __ bswapl(rdx);
   __ load_unsigned_byte(rbx, Address(rsi, rdx, Address::times_1));
-  __ addl(rsi, rdx);
+  __ addptr(rsi, rdx);
   __ dispatch_only(vtos);
 }
 
@@ -1882,13 +1891,13 @@
   // setup array
   __ save_bcp();
 
-  __ leal(array, at_bcp(3*wordSize));            // btw: should be able to get rid of this instruction (change offsets below)
-  __ andl(array, -wordSize);
+  __ lea(array, at_bcp(3*wordSize));             // btw: should be able to get rid of this instruction (change offsets below)
+  __ andptr(array, -wordSize);
   // initialize i & j
   __ xorl(i, i);                                 // i = 0;
   __ movl(j, Address(array, -wordSize));         // j = length(array);
   // Convert j into native byteordering
-  __ bswap(j);
+  __ bswapl(j);
   // and start
   Label entry;
   __ jmp(entry);
@@ -1906,19 +1915,19 @@
     // }
     // Convert array[h].match to native byte-ordering before compare
     __ movl(temp, Address(array, h, Address::times_8, 0*wordSize));
-    __ bswap(temp);
+    __ bswapl(temp);
     __ cmpl(key, temp);
     if (VM_Version::supports_cmov()) {
       __ cmovl(Assembler::less        , j, h);   // j = h if (key <  array[h].fast_match())
       __ cmovl(Assembler::greaterEqual, i, h);   // i = h if (key >= array[h].fast_match())
     } else {
       Label set_i, end_of_if;
-      __ jccb(Assembler::greaterEqual, set_i);    // {
-      __ movl(j, h);                             //   j = h;
-      __ jmp(end_of_if);                         // }
-      __ bind(set_i);                            // else {
-      __ movl(i, h);                             //   i = h;
-      __ bind(end_of_if);                        // }
+      __ jccb(Assembler::greaterEqual, set_i);     // {
+      __ mov(j, h);                                //   j = h;
+      __ jmp(end_of_if);                           // }
+      __ bind(set_i);                              // else {
+      __ mov(i, h);                                //   i = h;
+      __ bind(end_of_if);                          // }
     }
     // while (i+1 < j)
     __ bind(entry);
@@ -1931,30 +1940,32 @@
   Label default_case;
   // Convert array[i].match to native byte-ordering before compare
   __ movl(temp, Address(array, i, Address::times_8, 0*wordSize));
-  __ bswap(temp);
+  __ bswapl(temp);
   __ cmpl(key, temp);
   __ jcc(Assembler::notEqual, default_case);
 
   // entry found -> j = offset
   __ movl(j , Address(array, i, Address::times_8, 1*wordSize));
   __ profile_switch_case(i, key, array);
-  __ bswap(j);
+  __ bswapl(j);
+  LP64_ONLY(__ movslq(j, j));
   __ restore_bcp();
   __ restore_locals();                           // restore rdi
   __ load_unsigned_byte(rbx, Address(rsi, j, Address::times_1));
 
-  __ addl(rsi, j);
+  __ addptr(rsi, j);
   __ dispatch_only(vtos);
 
   // default case -> j = default offset
   __ bind(default_case);
   __ profile_switch_default(i);
   __ movl(j, Address(array, -2*wordSize));
-  __ bswap(j);
+  __ bswapl(j);
+  LP64_ONLY(__ movslq(j, j));
   __ restore_bcp();
   __ restore_locals();                           // restore rdi
   __ load_unsigned_byte(rbx, Address(rsi, j, Address::times_1));
-  __ addl(rsi, j);
+  __ addptr(rsi, j);
   __ dispatch_only(vtos);
 }
 
@@ -1965,8 +1976,8 @@
 
   if (_desc->bytecode() == Bytecodes::_return_register_finalizer) {
     assert(state == vtos, "only valid state");
-    __ movl(rax, aaddress(0));
-    __ movl(rdi, Address(rax, oopDesc::klass_offset_in_bytes()));
+    __ movptr(rax, aaddress(0));
+    __ movptr(rdi, Address(rax, oopDesc::klass_offset_in_bytes()));
     __ movl(rdi, Address(rdi, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc)));
     __ testl(rdi, JVM_ACC_HAS_FINALIZER);
     Label skip_register_finalizer;
@@ -2007,10 +2018,10 @@
 // requirement (1) but miss the volatile-store-volatile-load case.  This final
 // case is placed after volatile-stores although it could just as well go
 // before volatile-loads.
-void TemplateTable::volatile_barrier( ) {
+void TemplateTable::volatile_barrier(Assembler::Membar_mask_bits order_constraint ) {
   // Helper function to insert a is-volatile test and memory barrier
   if( !os::is_MP() ) return;    // Not needed on single CPU
-  __ membar();
+  __ membar(order_constraint);
 }
 
 void TemplateTable::resolve_cache_and_index(int byte_no, Register Rcache, Register index) {
@@ -2023,10 +2034,13 @@
   const int shift_count = (1 + byte_no)*BitsPerByte;
   Label resolved;
   __ get_cache_and_index_at_bcp(Rcache, index, 1);
-  __ movl(temp, Address(Rcache, index, Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
+  __ movl(temp, Address(Rcache,
+                          index,
+                          Address::times_ptr,
+                          constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
   __ shrl(temp, shift_count);
   // have we resolved this bytecode?
-  __ andl(temp, 0xFF);
+  __ andptr(temp, 0xFF);
   __ cmpl(temp, (int)bytecode());
   __ jcc(Assembler::equal, resolved);
 
@@ -2062,16 +2076,16 @@
 
   ByteSize cp_base_offset = constantPoolCacheOopDesc::base_offset();
   // Field offset
-  __ movl(off, Address(cache, index, Address::times_4,
-           in_bytes(cp_base_offset + ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(off, Address(cache, index, Address::times_ptr,
+                         in_bytes(cp_base_offset + ConstantPoolCacheEntry::f2_offset())));
   // Flags
-  __ movl(flags, Address(cache, index, Address::times_4,
+  __ movl(flags, Address(cache, index, Address::times_ptr,
            in_bytes(cp_base_offset + ConstantPoolCacheEntry::flags_offset())));
 
   // klass     overwrite register
   if (is_static) {
-    __ movl(obj, Address(cache, index, Address::times_4,
-             in_bytes(cp_base_offset + ConstantPoolCacheEntry::f1_offset())));
+    __ movptr(obj, Address(cache, index, Address::times_ptr,
+                           in_bytes(cp_base_offset + ConstantPoolCacheEntry::f1_offset())));
   }
 }
 
@@ -2104,12 +2118,11 @@
 
   resolve_cache_and_index(byte_no, cache, index);
 
-  assert(wordSize == 4, "adjust code below");
-  __ movl(method, Address(cache, index, Address::times_4, method_offset));
+  __ movptr(method, Address(cache, index, Address::times_ptr, method_offset));
   if (itable_index != noreg) {
-    __ movl(itable_index, Address(cache, index, Address::times_4, index_offset));
+    __ movptr(itable_index, Address(cache, index, Address::times_ptr, index_offset));
   }
-  __ movl(flags , Address(cache, index, Address::times_4, flags_offset ));
+  __ movl(flags , Address(cache, index, Address::times_ptr, flags_offset ));
 }
 
 
@@ -2129,11 +2142,11 @@
     __ jcc(Assembler::zero, L1);
 
     // cache entry pointer
-    __ addl(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
+    __ addptr(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));
     __ shll(index, LogBytesPerWord);
-    __ addl(cache, index);
+    __ addptr(cache, index);
     if (is_static) {
-      __ movl(rax, 0);      // NULL object reference
+      __ xorptr(rax, rax);      // NULL object reference
     } else {
       __ pop(atos);         // Get the object
       __ verify_oop(rax);
@@ -2177,7 +2190,7 @@
   __ shrl(flags, ConstantPoolCacheEntry::tosBits);
   assert(btos == 0, "change code, btos != 0");
   // btos
-  __ andl(flags, 0x0f);
+  __ andptr(flags, 0x0f);
   __ jcc(Assembler::notZero, notByte);
 
   __ load_signed_byte(rax, lo );
@@ -2245,10 +2258,10 @@
   // Generate code as if volatile.  There just aren't enough registers to
   // save that information and this code is faster than the test.
   __ fild_d(lo);                // Must load atomically
-  __ subl(rsp,2*wordSize);      // Make space for store
+  __ subptr(rsp,2*wordSize);    // Make space for store
   __ fistp_d(Address(rsp,0));
-  __ popl(rax);
-  __ popl(rdx);
+  __ pop(rax);
+  __ pop(rdx);
 
   __ push(ltos);
   // Don't rewrite to _fast_lgetfield for potential volatile case.
@@ -2319,16 +2332,16 @@
 
     if (is_static) {
       // Life is simple.  Null out the object pointer.
-      __ xorl(rbx, rbx);
+      __ xorptr(rbx, rbx);
     } else {
       // Life is harder. The stack holds the value on top, followed by the object.
       // We don't know the size of the value, though; it could be one or two words
       // depending on its type. As a result, we must find the type to determine where
       // the object is.
       Label two_word, valsize_known;
-      __ movl(rcx, Address(rax, rdx, Address::times_4, in_bytes(cp_base_offset +
+      __ movl(rcx, Address(rax, rdx, Address::times_ptr, in_bytes(cp_base_offset +
                                    ConstantPoolCacheEntry::flags_offset())));
-      __ movl(rbx, rsp);
+      __ mov(rbx, rsp);
       __ shrl(rcx, ConstantPoolCacheEntry::tosBits);
       // Make sure we don't need to mask rcx for tosBits after the above shift
       ConstantPoolCacheEntry::verify_tosBits();
@@ -2336,22 +2349,22 @@
       __ jccb(Assembler::equal, two_word);
       __ cmpl(rcx, dtos);
       __ jccb(Assembler::equal, two_word);
-      __ addl(rbx, Interpreter::expr_offset_in_bytes(1)); // one word jvalue (not ltos, dtos)
+      __ addptr(rbx, Interpreter::expr_offset_in_bytes(1)); // one word jvalue (not ltos, dtos)
       __ jmpb(valsize_known);
 
       __ bind(two_word);
-      __ addl(rbx, Interpreter::expr_offset_in_bytes(2)); // two words jvalue
+      __ addptr(rbx, Interpreter::expr_offset_in_bytes(2)); // two words jvalue
 
       __ bind(valsize_known);
       // setup object pointer
-      __ movl(rbx, Address(rbx, 0));
+      __ movptr(rbx, Address(rbx, 0));
     }
     // cache entry pointer
-    __ addl(rax, in_bytes(cp_base_offset));
+    __ addptr(rax, in_bytes(cp_base_offset));
     __ shll(rdx, LogBytesPerWord);
-    __ addl(rax, rdx);
+    __ addptr(rax, rdx);
     // object (tos)
-    __ movl(rcx, rsp);
+    __ mov(rcx, rsp);
     // rbx,: object pointer set up above (NULL if static)
     // rax,: cache entry pointer
     // rcx: jvalue object on the stack
@@ -2426,7 +2439,7 @@
   __ pop(atos);
   if (!is_static) pop_and_check_object(obj);
 
-  __ movl(lo, rax );
+  __ movptr(lo, rax );
   __ store_check(obj, lo);  // Need to mark card
   if (!is_static) {
     patch_bytecode(Bytecodes::_fast_aputfield, rcx, rbx);
@@ -2472,12 +2485,14 @@
   if (!is_static) pop_and_check_object(obj);
 
   // Replace with real volatile test
-  __ pushl(rdx);
-  __ pushl(rax);                // Must update atomically with FIST
+  __ push(rdx);
+  __ push(rax);                 // Must update atomically with FIST
   __ fild_d(Address(rsp,0));    // So load into FPU register
   __ fistp_d(lo);               // and put into memory atomically
-  __ addl(rsp,2*wordSize);
-  volatile_barrier();
+  __ addptr(rsp, 2*wordSize);
+  // volatile_barrier();
+  volatile_barrier(Assembler::Membar_mask_bits(Assembler::StoreLoad |
+                                               Assembler::StoreStore));
   // Don't rewrite volatile version
   __ jmp(notVolatile);
 
@@ -2485,8 +2500,8 @@
 
   __ pop(ltos);  // overwrites rdx
   if (!is_static) pop_and_check_object(obj);
-  __ movl(hi, rdx);
-  __ movl(lo, rax);
+  NOT_LP64(__ movptr(hi, rdx));
+  __ movptr(lo, rax);
   if (!is_static) {
     patch_bytecode(Bytecodes::_fast_lputfield, rcx, rbx);
   }
@@ -2527,7 +2542,8 @@
   // Check for volatile store
   __ testl(rdx, rdx);
   __ jcc(Assembler::zero, notVolatile);
-  volatile_barrier( );
+  volatile_barrier(Assembler::Membar_mask_bits(Assembler::StoreLoad |
+                                               Assembler::StoreStore));
   __ bind(notVolatile);
 }
 
@@ -2552,10 +2568,10 @@
     __ pop_ptr(rbx);               // copy the object pointer from tos
     __ verify_oop(rbx);
     __ push_ptr(rbx);              // put the object pointer back on tos
-    __ subl(rsp, sizeof(jvalue));  // add space for a jvalue object
-    __ movl(rcx, rsp);
+    __ subptr(rsp, sizeof(jvalue));  // add space for a jvalue object
+    __ mov(rcx, rsp);
     __ push_ptr(rbx);                 // save object pointer so we can steal rbx,
-    __ movl(rbx, 0);
+    __ xorptr(rbx, rbx);
     const Address lo_value(rcx, rbx, Address::times_1, 0*wordSize);
     const Address hi_value(rcx, rbx, Address::times_1, 1*wordSize);
     switch (bytecode()) {          // load values into the jvalue object
@@ -2563,21 +2579,28 @@
     case Bytecodes::_fast_sputfield: __ movw(lo_value, rax); break;
     case Bytecodes::_fast_cputfield: __ movw(lo_value, rax); break;
     case Bytecodes::_fast_iputfield: __ movl(lo_value, rax);                         break;
-    case Bytecodes::_fast_lputfield: __ movl(hi_value, rdx); __ movl(lo_value, rax); break;
+    case Bytecodes::_fast_lputfield:
+      NOT_LP64(__ movptr(hi_value, rdx));
+      __ movptr(lo_value, rax);
+      break;
+
     // need to call fld_s() after fstp_s() to restore the value for below
     case Bytecodes::_fast_fputfield: __ fstp_s(lo_value); __ fld_s(lo_value);        break;
+
     // need to call fld_d() after fstp_d() to restore the value for below
     case Bytecodes::_fast_dputfield: __ fstp_d(lo_value); __ fld_d(lo_value);        break;
+
     // since rcx is not an object we don't call store_check() here
-    case Bytecodes::_fast_aputfield: __ movl(lo_value, rax);                         break;
+    case Bytecodes::_fast_aputfield: __ movptr(lo_value, rax);                       break;
+
     default:  ShouldNotReachHere();
     }
     __ pop_ptr(rbx);  // restore copy of object pointer
 
     // Save rax, and sometimes rdx because call_VM() will clobber them,
     // then use them for JVM/DI purposes
-    __ pushl(rax);
-    if (bytecode() == Bytecodes::_fast_lputfield) __ pushl(rdx);
+    __ push(rax);
+    if (bytecode() == Bytecodes::_fast_lputfield) __ push(rdx);
     // access constant pool cache entry
     __ get_cache_entry_pointer_at_bcp(rax, rdx, 1);
     __ verify_oop(rbx);
@@ -2585,9 +2608,9 @@
     // rax,: cache entry pointer
     // rcx: jvalue object on the stack
     __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::post_field_modification), rbx, rax, rcx);
-    if (bytecode() == Bytecodes::_fast_lputfield) __ popl(rdx);  // restore high value
-    __ popl(rax);     // restore lower value
-    __ addl(rsp, sizeof(jvalue));  // release jvalue object space
+    if (bytecode() == Bytecodes::_fast_lputfield) __ pop(rdx);  // restore high value
+    __ pop(rax);     // restore lower value
+    __ addptr(rsp, sizeof(jvalue));  // release jvalue object space
     __ bind(L2);
   }
 }
@@ -2603,12 +2626,12 @@
   __ get_cache_and_index_at_bcp(rcx, rbx, 1);
 
   // test for volatile with rdx but rdx is tos register for lputfield.
-  if (bytecode() == Bytecodes::_fast_lputfield) __ pushl(rdx);
-  __ movl(rdx, Address(rcx, rbx, Address::times_4, in_bytes(base +
+  if (bytecode() == Bytecodes::_fast_lputfield) __ push(rdx);
+  __ movl(rdx, Address(rcx, rbx, Address::times_ptr, in_bytes(base +
                        ConstantPoolCacheEntry::flags_offset())));
 
   // replace index with field offset from cache entry
-  __ movl(rbx, Address(rcx, rbx, Address::times_4, in_bytes(base + ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx, Address(rcx, rbx, Address::times_ptr, in_bytes(base + ConstantPoolCacheEntry::f2_offset())));
 
   // Doug Lea believes this is not needed with current Sparcs (TSO) and Intel (PSO).
   // volatile_barrier( );
@@ -2620,7 +2643,7 @@
   __ testl(rdx, rdx);
   __ jcc(Assembler::zero, notVolatile);
 
-  if (bytecode() == Bytecodes::_fast_lputfield) __ popl(rdx);
+  if (bytecode() == Bytecodes::_fast_lputfield) __ pop(rdx);
 
   // Get object from stack
   pop_and_check_object(rcx);
@@ -2635,22 +2658,26 @@
     case Bytecodes::_fast_sputfield: // fall through
     case Bytecodes::_fast_cputfield: __ movw(lo, rax); break;
     case Bytecodes::_fast_iputfield: __ movl(lo, rax); break;
-    case Bytecodes::_fast_lputfield: __ movl(hi, rdx); __ movl(lo, rax);        break;
+    case Bytecodes::_fast_lputfield:
+      NOT_LP64(__ movptr(hi, rdx));
+      __ movptr(lo, rax);
+      break;
     case Bytecodes::_fast_fputfield: __ fstp_s(lo); break;
     case Bytecodes::_fast_dputfield: __ fstp_d(lo); break;
-    case Bytecodes::_fast_aputfield: __ movl(lo, rax); __ store_check(rcx, lo); break;
+    case Bytecodes::_fast_aputfield: __ movptr(lo, rax); __ store_check(rcx, lo); break;
     default:
       ShouldNotReachHere();
   }
 
   Label done;
-  volatile_barrier( );
+  volatile_barrier(Assembler::Membar_mask_bits(Assembler::StoreLoad |
+                                               Assembler::StoreStore));
   __ jmpb(done);
 
   // Same code as above, but don't need rdx to test for volatile.
   __ bind(notVolatile);
 
-  if (bytecode() == Bytecodes::_fast_lputfield) __ popl(rdx);
+  if (bytecode() == Bytecodes::_fast_lputfield) __ pop(rdx);
 
   // Get object from stack
   pop_and_check_object(rcx);
@@ -2661,10 +2688,13 @@
     case Bytecodes::_fast_sputfield: // fall through
     case Bytecodes::_fast_cputfield: __ movw(lo, rax); break;
     case Bytecodes::_fast_iputfield: __ movl(lo, rax); break;
-    case Bytecodes::_fast_lputfield: __ movl(hi, rdx); __ movl(lo, rax);        break;
+    case Bytecodes::_fast_lputfield:
+      NOT_LP64(__ movptr(hi, rdx));
+      __ movptr(lo, rax);
+      break;
     case Bytecodes::_fast_fputfield: __ fstp_s(lo); break;
     case Bytecodes::_fast_dputfield: __ fstp_d(lo); break;
-    case Bytecodes::_fast_aputfield: __ movl(lo, rax); __ store_check(rcx, lo); break;
+    case Bytecodes::_fast_aputfield: __ movptr(lo, rax); __ store_check(rcx, lo); break;
     default:
       ShouldNotReachHere();
   }
@@ -2697,7 +2727,10 @@
   // access constant pool cache
   __ get_cache_and_index_at_bcp(rcx, rbx, 1);
   // replace index with field offset from cache entry
-  __ movl(rbx, Address(rcx, rbx, Address::times_4, in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx, Address(rcx,
+                         rbx,
+                         Address::times_ptr,
+                         in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset())));
 
 
   // rax,: object
@@ -2709,14 +2742,14 @@
 
   // access field
   switch (bytecode()) {
-    case Bytecodes::_fast_bgetfield: __ movsxb(rax, lo );                 break;
+    case Bytecodes::_fast_bgetfield: __ movsbl(rax, lo );                 break;
     case Bytecodes::_fast_sgetfield: __ load_signed_word(rax, lo );       break;
     case Bytecodes::_fast_cgetfield: __ load_unsigned_word(rax, lo );     break;
     case Bytecodes::_fast_igetfield: __ movl(rax, lo);                    break;
     case Bytecodes::_fast_lgetfield: __ stop("should not be rewritten");  break;
     case Bytecodes::_fast_fgetfield: __ fld_s(lo);                        break;
     case Bytecodes::_fast_dgetfield: __ fld_d(lo);                        break;
-    case Bytecodes::_fast_agetfield: __ movl(rax, lo); __ verify_oop(rax); break;
+    case Bytecodes::_fast_agetfield: __ movptr(rax, lo); __ verify_oop(rax); break;
     default:
       ShouldNotReachHere();
   }
@@ -2728,11 +2761,14 @@
 void TemplateTable::fast_xaccess(TosState state) {
   transition(vtos, state);
   // get receiver
-  __ movl(rax, aaddress(0));
+  __ movptr(rax, aaddress(0));
   debug_only(__ verify_local_tag(frame::TagReference, 0));
   // access constant pool cache
   __ get_cache_and_index_at_bcp(rcx, rdx, 2);
-  __ movl(rbx, Address(rcx, rdx, Address::times_4, in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx, Address(rcx,
+                         rdx,
+                         Address::times_ptr,
+                         in_bytes(constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset())));
   // make sure exception is reported in correct bcp range (getfield is next instruction)
   __ increment(rsi);
   __ null_check(rax);
@@ -2740,7 +2776,7 @@
   if (state == itos) {
     __ movl(rax, lo);
   } else if (state == atos) {
-    __ movl(rax, lo);
+    __ movptr(rax, lo);
     __ verify_oop(rax);
   } else if (state == ftos) {
     __ fld_s(lo);
@@ -2784,7 +2820,7 @@
     __ movl(recv, flags);
     __ andl(recv, 0xFF);
     // recv count is 0 based?
-    __ movl(recv, Address(rsp, recv, Interpreter::stackElementScale(), -Interpreter::expr_offset_in_bytes(1)));
+    __ movptr(recv, Address(rsp, recv, Interpreter::stackElementScale(), -Interpreter::expr_offset_in_bytes(1)));
     __ verify_oop(recv);
   }
 
@@ -2794,7 +2830,7 @@
   }
 
   if (save_flags) {
-    __ movl(rsi, flags);
+    __ mov(rsi, flags);
   }
 
   // compute return type
@@ -2802,20 +2838,19 @@
   // Make sure we don't need to mask flags for tosBits after the above shift
   ConstantPoolCacheEntry::verify_tosBits();
   // load return address
-  { const int table =
-      is_invokeinterface
-      ? (int)Interpreter::return_5_addrs_by_index_table()
-      : (int)Interpreter::return_3_addrs_by_index_table();
-    __ movl(flags, Address(noreg, flags, Address::times_4, table));
+  {
+    ExternalAddress table(is_invokeinterface ? (address)Interpreter::return_5_addrs_by_index_table() :
+                                               (address)Interpreter::return_3_addrs_by_index_table());
+    __ movptr(flags, ArrayAddress(table, Address(noreg, flags, Address::times_ptr)));
   }
 
   // push return address
-  __ pushl(flags);
+  __ push(flags);
 
   // Restore flag value from the constant pool cache, and restore rsi
   // for later null checks.  rsi is the bytecode pointer
   if (save_flags) {
-    __ movl(flags, rsi);
+    __ mov(flags, rsi);
     __ restore_bcp();
   }
 }
@@ -2852,7 +2887,7 @@
   // get receiver klass
   __ null_check(recv, oopDesc::klass_offset_in_bytes());
   // Keep recv in rcx for callee expects it there
-  __ movl(rax, Address(recv, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rax, Address(recv, oopDesc::klass_offset_in_bytes()));
   __ verify_oop(rax);
 
   // profile this call
@@ -2861,7 +2896,7 @@
   // get target methodOop & entry point
   const int base = instanceKlass::vtable_start_offset() * wordSize;
   assert(vtableEntry::size() * wordSize == 4, "adjust the scaling in the code below");
-  __ movl(method, Address(rax, index, Address::times_4, base + vtableEntry::method_offset_in_bytes()));
+  __ movptr(method, Address(rax, index, Address::times_ptr, base + vtableEntry::method_offset_in_bytes()));
   __ jump_from_interpreted(method, rdx);
 }
 
@@ -2927,19 +2962,19 @@
 
   // Get receiver klass into rdx - also a null check
   __ restore_locals();  // restore rdi
-  __ movl(rdx, Address(rcx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rdx, Address(rcx, oopDesc::klass_offset_in_bytes()));
   __ verify_oop(rdx);
 
   // profile this call
   __ profile_virtual_call(rdx, rsi, rdi);
 
-  __ movl(rdi, rdx); // Save klassOop in rdi
+  __ mov(rdi, rdx); // Save klassOop in rdi
 
   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
   const int base = instanceKlass::vtable_start_offset() * wordSize;
-  assert(vtableEntry::size() * wordSize == 4, "adjust the scaling in the code below");
+  assert(vtableEntry::size() * wordSize == (1 << (int)Address::times_ptr), "adjust the scaling in the code below");
   __ movl(rsi, Address(rdx, instanceKlass::vtable_length_offset() * wordSize)); // Get length of vtable
-  __ leal(rdx, Address(rdx, rsi, Address::times_4, base));
+  __ lea(rdx, Address(rdx, rsi, Address::times_4, base));
   if (HeapWordsPerLong > 1) {
     // Round up to align_object_offset boundary
     __ round_to(rdx, BytesPerLong);
@@ -2949,20 +2984,20 @@
 
   __ jmpb(entry);
   __ bind(search);
-  __ addl(rdx, itableOffsetEntry::size() * wordSize);
+  __ addptr(rdx, itableOffsetEntry::size() * wordSize);
 
   __ bind(entry);
 
   // Check that the entry is non-null.  A null entry means that the receiver
   // class doesn't implement the interface, and wasn't the same as the
   // receiver class checked when the interface was resolved.
-  __ pushl(rdx);
-  __ movl(rdx, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
-  __ testl(rdx, rdx);
+  __ push(rdx);
+  __ movptr(rdx, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
+  __ testptr(rdx, rdx);
   __ jcc(Assembler::notZero, interface_ok);
   // throw exception
-  __ popl(rdx);          // pop saved register first.
-  __ popl(rbx);          // pop return address (pushed by prepare_invoke)
+  __ pop(rdx);           // pop saved register first.
+  __ pop(rbx);           // pop return address (pushed by prepare_invoke)
   __ restore_bcp();      // rsi must be correct for exception handler   (was destroyed)
   __ restore_locals();   // make sure locals pointer is correct as well (was destroyed)
   __ call_VM(noreg, CAST_FROM_FN_PTR(address,
@@ -2971,15 +3006,15 @@
   __ should_not_reach_here();
   __ bind(interface_ok);
 
-    __ popl(rdx);
-
-    __ cmpl(rax, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
+    __ pop(rdx);
+
+    __ cmpptr(rax, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
     __ jcc(Assembler::notEqual, search);
 
     __ movl(rdx, Address(rdx, itableOffsetEntry::offset_offset_in_bytes()));
-    __ addl(rdx, rdi); // Add offset to klassOop
-    assert(itableMethodEntry::size() * wordSize == 4, "adjust the scaling in the code below");
-    __ movl(rbx, Address(rdx, rbx, Address::times_4));
+    __ addptr(rdx, rdi); // Add offset to klassOop
+    assert(itableMethodEntry::size() * wordSize == (1 << (int)Address::times_ptr), "adjust the scaling in the code below");
+    __ movptr(rbx, Address(rdx, rbx, Address::times_ptr));
     // rbx,: methodOop to call
     // rcx: receiver
     // Check for abstract method error
@@ -2987,12 +3022,12 @@
     //       interpreter entry point and a conditional jump to it in case of a null
     //       method.
     { Label L;
-      __ testl(rbx, rbx);
+      __ testptr(rbx, rbx);
       __ jcc(Assembler::notZero, L);
       // throw exception
           // note: must restore interpreter registers to canonical
           //       state for exception handling to work correctly!
-          __ popl(rbx);          // pop return address (pushed by prepare_invoke)
+          __ pop(rbx);           // pop return address (pushed by prepare_invoke)
           __ restore_bcp();      // rsi must be correct for exception handler   (was destroyed)
           __ restore_locals();   // make sure locals pointer is correct as well (was destroyed)
       __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_AbstractMethodError));
@@ -3023,8 +3058,8 @@
 
   __ get_cpool_and_tags(rcx, rax);
   // get instanceKlass
-  __ movl(rcx, Address(rcx, rdx, Address::times_4, sizeof(constantPoolOopDesc)));
-  __ pushl(rcx);  // save the contexts of klass for initializing the header
+  __ movptr(rcx, Address(rcx, rdx, Address::times_ptr, sizeof(constantPoolOopDesc)));
+  __ push(rcx);  // save the contexts of klass for initializing the header
 
   // make sure the class we're about to instantiate has been resolved.
   // Note: slow_case does a pop of stack, which is why we loaded class/pushed above
@@ -3057,11 +3092,11 @@
     const Register thread = rcx;
 
     __ get_thread(thread);
-    __ movl(rax, Address(thread, in_bytes(JavaThread::tlab_top_offset())));
-    __ leal(rbx, Address(rax, rdx, Address::times_1));
-    __ cmpl(rbx, Address(thread, in_bytes(JavaThread::tlab_end_offset())));
+    __ movptr(rax, Address(thread, in_bytes(JavaThread::tlab_top_offset())));
+    __ lea(rbx, Address(rax, rdx, Address::times_1));
+    __ cmpptr(rbx, Address(thread, in_bytes(JavaThread::tlab_end_offset())));
     __ jcc(Assembler::above, allow_shared_alloc ? allocate_shared : slow_case);
-    __ movl(Address(thread, in_bytes(JavaThread::tlab_top_offset())), rbx);
+    __ movptr(Address(thread, in_bytes(JavaThread::tlab_top_offset())), rbx);
     if (ZeroTLAB) {
       // the fields have been already cleared
       __ jmp(initialize_header);
@@ -3079,9 +3114,9 @@
 
     Label retry;
     __ bind(retry);
-    __ mov32(rax, heap_top);
-    __ leal(rbx, Address(rax, rdx, Address::times_1));
-    __ cmp32(rbx, ExternalAddress((address)Universe::heap()->end_addr()));
+    __ movptr(rax, heap_top);
+    __ lea(rbx, Address(rax, rdx, Address::times_1));
+    __ cmpptr(rbx, ExternalAddress((address)Universe::heap()->end_addr()));
     __ jcc(Assembler::above, slow_case);
 
     // Compare rax, with the top addr, and if still equal, store the new
@@ -3091,8 +3126,7 @@
     // rax,: object begin
     // rbx,: object end
     // rdx: instance size in bytes
-    if (os::is_MP()) __ lock();
-    __ cmpxchgptr(rbx, heap_top);
+    __ locked_cmpxchgptr(rbx, heap_top);
 
     // if someone beat us on the allocation, try again, otherwise continue
     __ jcc(Assembler::notEqual, retry);
@@ -3124,8 +3158,8 @@
     // initialize remaining object fields: rdx was a multiple of 8
     { Label loop;
     __ bind(loop);
-    __ movl(Address(rax, rdx, Address::times_8, sizeof(oopDesc) - 1*oopSize), rcx);
-    __ movl(Address(rax, rdx, Address::times_8, sizeof(oopDesc) - 2*oopSize), rcx);
+    __ movptr(Address(rax, rdx, Address::times_8, sizeof(oopDesc) - 1*oopSize), rcx);
+    NOT_LP64(__ movptr(Address(rax, rdx, Address::times_8, sizeof(oopDesc) - 2*oopSize), rcx));
     __ decrement(rdx);
     __ jcc(Assembler::notZero, loop);
     }
@@ -3133,15 +3167,15 @@
     // initialize object header only.
     __ bind(initialize_header);
     if (UseBiasedLocking) {
-      __ popl(rcx);   // get saved klass back in the register.
-      __ movl(rbx, Address(rcx, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-      __ movl(Address(rax, oopDesc::mark_offset_in_bytes ()), rbx);
+      __ pop(rcx);   // get saved klass back in the register.
+      __ movptr(rbx, Address(rcx, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+      __ movptr(Address(rax, oopDesc::mark_offset_in_bytes ()), rbx);
     } else {
-      __ movl(Address(rax, oopDesc::mark_offset_in_bytes ()),
-              (int)markOopDesc::prototype()); // header
-      __ popl(rcx);   // get saved klass back in the register.
+      __ movptr(Address(rax, oopDesc::mark_offset_in_bytes ()),
+                (int32_t)markOopDesc::prototype()); // header
+      __ pop(rcx);   // get saved klass back in the register.
     }
-    __ movl(Address(rax, oopDesc::klass_offset_in_bytes()), rcx);  // klass
+    __ movptr(Address(rax, oopDesc::klass_offset_in_bytes()), rcx);  // klass
 
     {
       SkipIfEqual skip_if(_masm, &DTraceAllocProbes, 0);
@@ -3157,7 +3191,7 @@
 
   // slow case
   __ bind(slow_case);
-  __ popl(rcx);   // restore stack pointer to what it was when we came in.
+  __ pop(rcx);   // restore stack pointer to what it was when we came in.
   __ get_constant_pool(rax);
   __ get_unsigned_2_byte_index_at_bcp(rdx, 1);
   call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::_new), rax, rdx);
@@ -3194,7 +3228,7 @@
 void TemplateTable::checkcast() {
   transition(atos, atos);
   Label done, is_null, ok_is_subtype, quicked, resolved;
-  __ testl(rax, rax);   // Object is in EAX
+  __ testptr(rax, rax);   // Object is in EAX
   __ jcc(Assembler::zero, is_null);
 
   // Get cpool & tags index
@@ -3211,24 +3245,24 @@
 
   // Get superklass in EAX and subklass in EBX
   __ bind(quicked);
-  __ movl(rdx, rax);          // Save object in EDX; EAX needed for subtype check
-  __ movl(rax, Address(rcx, rbx, Address::times_4, sizeof(constantPoolOopDesc)));
+  __ mov(rdx, rax);          // Save object in EDX; EAX needed for subtype check
+  __ movptr(rax, Address(rcx, rbx, Address::times_ptr, sizeof(constantPoolOopDesc)));
 
   __ bind(resolved);
-  __ movl(rbx, Address(rdx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rbx, Address(rdx, oopDesc::klass_offset_in_bytes()));
 
   // Generate subtype check.  Blows ECX.  Resets EDI.  Object in EDX.
   // Superklass in EAX.  Subklass in EBX.
   __ gen_subtype_check( rbx, ok_is_subtype );
 
   // Come here on failure
-  __ pushl(rdx);
+  __ push(rdx);
   // object is at TOS
   __ jump(ExternalAddress(Interpreter::_throw_ClassCastException_entry));
 
   // Come here on success
   __ bind(ok_is_subtype);
-  __ movl(rax,rdx);           // Restore object in EDX
+  __ mov(rax,rdx);           // Restore object in EDX
 
   // Collect counts on whether this check-cast sees NULLs a lot or not.
   if (ProfileInterpreter) {
@@ -3245,7 +3279,7 @@
 void TemplateTable::instanceof() {
   transition(atos, itos);
   Label done, is_null, ok_is_subtype, quicked, resolved;
-  __ testl(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, is_null);
 
   // Get cpool & tags index
@@ -3258,13 +3292,13 @@
   __ push(atos);
   call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::quicken_io_cc) );
   __ pop_ptr(rdx);
-  __ movl(rdx, Address(rdx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rdx, Address(rdx, oopDesc::klass_offset_in_bytes()));
   __ jmp(resolved);
 
   // Get superklass in EAX and subklass in EDX
   __ bind(quicked);
-  __ movl(rdx, Address(rax, oopDesc::klass_offset_in_bytes()));
-  __ movl(rax, Address(rcx, rbx, Address::times_4, sizeof(constantPoolOopDesc)));
+  __ movptr(rdx, Address(rax, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rax, Address(rcx, rbx, Address::times_ptr, sizeof(constantPoolOopDesc)));
 
   __ bind(resolved);
 
@@ -3306,7 +3340,7 @@
   // get the unpatched byte code
   __ get_method(rcx);
   __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::get_original_bytecode_at), rcx, rsi);
-  __ movl(rbx, rax);
+  __ mov(rbx, rax);
 
   // post the breakpoint event
   __ get_method(rcx);
@@ -3362,50 +3396,50 @@
 
   // find a free slot in the monitor block (result in rdx)
   { Label entry, loop, exit;
-    __ movl(rcx, monitor_block_top);             // points to current entry, starting with top-most entry
-    __ leal(rbx, monitor_block_bot);             // points to word before bottom of monitor block
+    __ movptr(rcx, monitor_block_top);            // points to current entry, starting with top-most entry
+    __ lea(rbx, monitor_block_bot);               // points to word before bottom of monitor block
     __ jmpb(entry);
 
     __ bind(loop);
-    __ cmpl(Address(rcx, BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);  // check if current entry is used
+    __ cmpptr(Address(rcx, BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);  // check if current entry is used
 
 // TODO - need new func here - kbt
     if (VM_Version::supports_cmov()) {
-      __ cmovl(Assembler::equal, rdx, rcx);      // if not used then remember entry in rdx
+      __ cmov(Assembler::equal, rdx, rcx);       // if not used then remember entry in rdx
     } else {
       Label L;
       __ jccb(Assembler::notEqual, L);
-      __ movl(rdx, rcx);                         // if not used then remember entry in rdx
+      __ mov(rdx, rcx);                          // if not used then remember entry in rdx
       __ bind(L);
     }
-    __ cmpl(rax, Address(rcx, BasicObjectLock::obj_offset_in_bytes()));   // check if current entry is for same object
-    __ jccb(Assembler::equal, exit);              // if same object then stop searching
-    __ addl(rcx, entry_size);                    // otherwise advance to next entry
+    __ cmpptr(rax, Address(rcx, BasicObjectLock::obj_offset_in_bytes()));   // check if current entry is for same object
+    __ jccb(Assembler::equal, exit);             // if same object then stop searching
+    __ addptr(rcx, entry_size);                  // otherwise advance to next entry
     __ bind(entry);
-    __ cmpl(rcx, rbx);                           // check if bottom reached
+    __ cmpptr(rcx, rbx);                         // check if bottom reached
     __ jcc(Assembler::notEqual, loop);           // if not at bottom then check this entry
     __ bind(exit);
   }
 
-  __ testl(rdx, rdx);                            // check if a slot has been found
-  __ jccb(Assembler::notZero, allocated);         // if found, continue with that one
+  __ testptr(rdx, rdx);                          // check if a slot has been found
+  __ jccb(Assembler::notZero, allocated);        // if found, continue with that one
 
   // allocate one if there's no free slot
   { Label entry, loop;
     // 1. compute new pointers                   // rsp: old expression stack top
-    __ movl(rdx, monitor_block_bot);             // rdx: old expression stack bottom
-    __ subl(rsp, entry_size);                    // move expression stack top
-    __ subl(rdx, entry_size);                    // move expression stack bottom
-    __ movl(rcx, rsp);                           // set start value for copy loop
-    __ movl(monitor_block_bot, rdx);             // set new monitor block top
+    __ movptr(rdx, monitor_block_bot);           // rdx: old expression stack bottom
+    __ subptr(rsp, entry_size);                  // move expression stack top
+    __ subptr(rdx, entry_size);                  // move expression stack bottom
+    __ mov(rcx, rsp);                            // set start value for copy loop
+    __ movptr(monitor_block_bot, rdx);           // set new monitor block top
     __ jmp(entry);
     // 2. move expression stack contents
     __ bind(loop);
-    __ movl(rbx, Address(rcx, entry_size));      // load expression stack word from old location
-    __ movl(Address(rcx, 0), rbx);               // and store it at new location
-    __ addl(rcx, wordSize);                      // advance to next word
+    __ movptr(rbx, Address(rcx, entry_size));    // load expression stack word from old location
+    __ movptr(Address(rcx, 0), rbx);             // and store it at new location
+    __ addptr(rcx, wordSize);                    // advance to next word
     __ bind(entry);
-    __ cmpl(rcx, rdx);                           // check if bottom reached
+    __ cmpptr(rcx, rdx);                         // check if bottom reached
     __ jcc(Assembler::notEqual, loop);           // if not at bottom then copy next word
   }
 
@@ -3417,7 +3451,7 @@
   // The object has already been poped from the stack, so the expression stack looks correct.
   __ increment(rsi);
 
-  __ movl(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), rax);     // store object
+  __ movptr(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), rax);     // store object
   __ lock_object(rdx);
 
   // check to make sure this monitor doesn't cause stack overflow after locking
@@ -3442,16 +3476,16 @@
 
   // find matching slot
   { Label entry, loop;
-    __ movl(rdx, monitor_block_top);             // points to current entry, starting with top-most entry
-    __ leal(rbx, monitor_block_bot);             // points to word before bottom of monitor block
+    __ movptr(rdx, monitor_block_top);           // points to current entry, starting with top-most entry
+    __ lea(rbx, monitor_block_bot);             // points to word before bottom of monitor block
     __ jmpb(entry);
 
     __ bind(loop);
-    __ cmpl(rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));   // check if current entry is for same object
+    __ cmpptr(rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));   // check if current entry is for same object
     __ jcc(Assembler::equal, found);             // if same object then stop searching
-    __ addl(rdx, entry_size);                    // otherwise advance to next entry
+    __ addptr(rdx, entry_size);                  // otherwise advance to next entry
     __ bind(entry);
-    __ cmpl(rdx, rbx);                           // check if bottom reached
+    __ cmpptr(rdx, rbx);                         // check if bottom reached
     __ jcc(Assembler::notEqual, loop);           // if not at bottom then check this entry
   }
 
@@ -3476,7 +3510,8 @@
 void TemplateTable::wide() {
   transition(vtos, vtos);
   __ load_unsigned_byte(rbx, at_bcp(1));
-  __ jmp(Address(noreg, rbx, Address::times_4, int(Interpreter::_wentry_point)));
+  ExternalAddress wtable((address)Interpreter::_wentry_point);
+  __ jump(ArrayAddress(wtable, Address(noreg, rbx, Address::times_ptr)));
   // Note: the rsi increment step is part of the individual wide bytecode implementations
 }
 
@@ -3490,10 +3525,10 @@
   // last dim is on top of stack; we want address of first one:
   // first_addr = last_addr + (ndims - 1) * stackElementSize - 1*wordsize
   // the latter wordSize to point to the beginning of the array.
-  __ leal(  rax, Address(rsp, rax, Interpreter::stackElementScale(), -wordSize));
+  __ lea(  rax, Address(rsp, rax, Interpreter::stackElementScale(), -wordSize));
   call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::multianewarray), rax);     // pass in rax,
   __ load_unsigned_byte(rbx, at_bcp(3));
-  __ leal(rsp, Address(rsp, rbx, Interpreter::stackElementScale()));  // get rid of counts
+  __ lea(rsp, Address(rsp, rbx, Interpreter::stackElementScale()));  // get rid of counts
 }
 
 #endif /* !CC_INTERP */
--- a/hotspot/src/cpu/x86/vm/templateTable_x86_32.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/templateTable_x86_32.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -26,7 +26,7 @@
                              Bytecodes::Code code);
   static void invokevirtual_helper(Register index, Register recv,
                                    Register flags);
-  static void volatile_barrier( );
+  static void volatile_barrier(Assembler::Membar_mask_bits order_constraint );
 
   // Helpers
   static void index_check(Register array, Register index);
--- a/hotspot/src/cpu/x86/vm/templateTable_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/templateTable_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -25,6 +25,8 @@
 #include "incls/_precompiled.incl"
 #include "incls/_templateTable_x86_64.cpp.incl"
 
+#ifndef CC_INTERP
+
 #define __ _masm->
 
 // Platform-dependent initialization
@@ -317,7 +319,7 @@
   __ jmp(Done);
 
   __ bind(isOop);
-  __ movq(rax, Address(rcx, rbx, Address::times_8, base_offset));
+  __ movptr(rax, Address(rcx, rbx, Address::times_8, base_offset));
   __ push_ptr(rax);
 
   if (VerifyOops) {
@@ -355,8 +357,8 @@
 
 void TemplateTable::locals_index(Register reg, int offset) {
   __ load_unsigned_byte(reg, at_bcp(offset));
-  __ negq(reg);
-  if (TaggedStackInterpreter) __ shlq(reg, 1);  // index = index*2
+  __ negptr(reg);
+  if (TaggedStackInterpreter) __ shlptr(reg, 1);  // index = index*2
 }
 
 void TemplateTable::iload() {
@@ -443,7 +445,7 @@
 void TemplateTable::aload() {
   transition(vtos, atos);
   locals_index(rbx);
-  __ movq(rax, aaddress(rbx));
+  __ movptr(rax, aaddress(rbx));
   debug_only(__ verify_local_tag(frame::TagReference, rbx));
 }
 
@@ -451,8 +453,8 @@
   __ movl(reg, at_bcp(2));
   __ bswapl(reg);
   __ shrl(reg, 16);
-  __ negq(reg);
-  if (TaggedStackInterpreter) __ shlq(reg, 1);  // index = index*2
+  __ negptr(reg);
+  if (TaggedStackInterpreter) __ shlptr(reg, 1);  // index = index*2
 }
 
 void TemplateTable::wide_iload() {
@@ -486,7 +488,7 @@
 void TemplateTable::wide_aload() {
   transition(vtos, atos);
   locals_index_wide(rbx);
-  __ movq(rax, aaddress(rbx));
+  __ movptr(rax, aaddress(rbx));
   debug_only(__ verify_local_tag(frame::TagReference, rbx));
 }
 
@@ -495,7 +497,7 @@
   // check array
   __ null_check(array, arrayOopDesc::length_offset_in_bytes());
   // sign extend index for use by indexed load
-  __ movslq(index, index);
+  __ movl2ptr(index, index);
   // check index
   __ cmpl(index, Address(array, arrayOopDesc::length_offset_in_bytes()));
   if (index != rbx) {
@@ -642,7 +644,7 @@
 
 void TemplateTable::aload(int n) {
   transition(vtos, atos);
-  __ movq(rax, aaddress(n));
+  __ movptr(rax, aaddress(n));
   debug_only(__ verify_local_tag(frame::TagReference, n));
 }
 
@@ -757,7 +759,7 @@
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);    // will need to pop tag too
   locals_index(rbx);
-  __ movq(aaddress(rbx), rax);
+  __ movptr(aaddress(rbx), rax);
   __ tag_local(rdx, rbx);  // store tag from stack, might be returnAddr
 }
 
@@ -797,7 +799,7 @@
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);    // will need to pop tag too
   locals_index_wide(rbx);
-  __ movq(aaddress(rbx), rax);
+  __ movptr(aaddress(rbx), rax);
   __ tag_local(rdx, rbx);  // store tag from stack, might be returnAddr
 }
 
@@ -861,25 +863,25 @@
   Label is_null, ok_is_subtype, done;
   transition(vtos, vtos);
   // stack: ..., array, index, value
-  __ movq(rax, at_tos());    // value
+  __ movptr(rax, at_tos());    // value
   __ movl(rcx, at_tos_p1()); // index
-  __ movq(rdx, at_tos_p2()); // array
+  __ movptr(rdx, at_tos_p2()); // array
   index_check(rdx, rcx);     // kills rbx
   // do array store check - check for NULL value first
-  __ testq(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, is_null);
 
   // Move subklass into rbx
   __ load_klass(rbx, rax);
   // Move superklass into rax
   __ load_klass(rax, rdx);
-  __ movq(rax, Address(rax,
-                       sizeof(oopDesc) +
-                       objArrayKlass::element_klass_offset_in_bytes()));
+  __ movptr(rax, Address(rax,
+                         sizeof(oopDesc) +
+                         objArrayKlass::element_klass_offset_in_bytes()));
   // Compress array + index*oopSize + 12 into a single register.  Frees rcx.
-  __ leaq(rdx, Address(rdx, rcx,
-                       UseCompressedOops ? Address::times_4 : Address::times_8,
-                       arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
+  __ lea(rdx, Address(rdx, rcx,
+                      UseCompressedOops ? Address::times_4 : Address::times_8,
+                      arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
 
   // Generate subtype check.  Blows rcx, rdi
   // Superklass in rax.  Subklass in rbx.
@@ -891,7 +893,7 @@
 
   // Come here on success
   __ bind(ok_is_subtype);
-  __ movq(rax, at_tos()); // Value
+  __ movptr(rax, at_tos()); // Value
   __ store_heap_oop(Address(rdx, 0), rax);
   __ store_check(rdx);
   __ jmp(done);
@@ -906,7 +908,7 @@
 
   // Pop stack arguments
   __ bind(done);
-  __ addq(rsp, 3 * Interpreter::stackElementSize());
+  __ addptr(rsp, 3 * Interpreter::stackElementSize());
 }
 
 void TemplateTable::bastore() {
@@ -968,18 +970,18 @@
 void TemplateTable::astore(int n) {
   transition(vtos, vtos);
   __ pop_ptr(rax, rdx);
-  __ movq(aaddress(n), rax);
+  __ movptr(aaddress(n), rax);
   __ tag_local(rdx, n);
 }
 
 void TemplateTable::pop() {
   transition(vtos, vtos);
-  __ addq(rsp, Interpreter::stackElementSize());
+  __ addptr(rsp, Interpreter::stackElementSize());
 }
 
 void TemplateTable::pop2() {
   transition(vtos, vtos);
-  __ addq(rsp, 2 * Interpreter::stackElementSize());
+  __ addptr(rsp, 2 * Interpreter::stackElementSize());
 }
 
 void TemplateTable::dup() {
@@ -1090,11 +1092,11 @@
 void TemplateTable::lop2(Operation op) {
   transition(ltos, ltos);
   switch (op) {
-  case add  :                    __ pop_l(rdx); __ addq (rax, rdx); break;
-  case sub  : __ movq(rdx, rax); __ pop_l(rax); __ subq (rax, rdx); break;
-  case _and :                    __ pop_l(rdx); __ andq (rax, rdx); break;
-  case _or  :                    __ pop_l(rdx); __ orq  (rax, rdx); break;
-  case _xor :                    __ pop_l(rdx); __ xorq (rax, rdx); break;
+  case add  :                    __ pop_l(rdx); __ addptr (rax, rdx); break;
+  case sub  : __ mov(rdx, rax);  __ pop_l(rax); __ subptr (rax, rdx); break;
+  case _and :                    __ pop_l(rdx); __ andptr (rax, rdx); break;
+  case _or  :                    __ pop_l(rdx); __ orptr  (rax, rdx); break;
+  case _xor :                    __ pop_l(rdx); __ xorptr (rax, rdx); break;
   default : ShouldNotReachHere();
   }
 }
@@ -1130,7 +1132,7 @@
 
 void TemplateTable::ldiv() {
   transition(ltos, ltos);
-  __ movq(rcx, rax);
+  __ mov(rcx, rax);
   __ pop_l(rax);
   // generate explicit div0 check
   __ testq(rcx, rcx);
@@ -1145,7 +1147,7 @@
 
 void TemplateTable::lrem() {
   transition(ltos, ltos);
-  __ movq(rcx, rax);
+  __ mov(rcx, rax);
   __ pop_l(rax);
   __ testq(rcx, rcx);
   __ jump_cc(Assembler::zero,
@@ -1155,7 +1157,7 @@
   //       needed), which may speed up this implementation for the common case.
   //       (see also JVM spec., p.243 & p.271)
   __ corrected_idivq(rcx); // kills rbx
-  __ movq(rax, rdx);
+  __ mov(rax, rdx);
 }
 
 void TemplateTable::lshl() {
@@ -1184,7 +1186,7 @@
   switch (op) {
   case add:
     __ addss(xmm0, at_rsp());
-    __ addq(rsp, Interpreter::stackElementSize());
+    __ addptr(rsp, Interpreter::stackElementSize());
     break;
   case sub:
     __ movflt(xmm1, xmm0);
@@ -1193,7 +1195,7 @@
     break;
   case mul:
     __ mulss(xmm0, at_rsp());
-    __ addq(rsp, Interpreter::stackElementSize());
+    __ addptr(rsp, Interpreter::stackElementSize());
     break;
   case div:
     __ movflt(xmm1, xmm0);
@@ -1216,7 +1218,7 @@
   switch (op) {
   case add:
     __ addsd(xmm0, at_rsp());
-    __ addq(rsp, 2 * Interpreter::stackElementSize());
+    __ addptr(rsp, 2 * Interpreter::stackElementSize());
     break;
   case sub:
     __ movdbl(xmm1, xmm0);
@@ -1225,7 +1227,7 @@
     break;
   case mul:
     __ mulsd(xmm0, at_rsp());
-    __ addq(rsp, 2 * Interpreter::stackElementSize());
+    __ addptr(rsp, 2 * Interpreter::stackElementSize());
     break;
   case div:
     __ movdbl(xmm1, xmm0);
@@ -1486,7 +1488,7 @@
   if (!is_wide) {
     __ sarl(rdx, 16);
   }
-  __ movslq(rdx, rdx);
+  __ movl2ptr(rdx, rdx);
 
   // Handle all the JSR stuff here, then exit.
   // It's much shorter and cleaner than intermingling with the non-JSR
@@ -1496,11 +1498,11 @@
     __ load_unsigned_byte(rbx, Address(r13, rdx, Address::times_1, 0));
 
     // compute return address as bci in rax
-    __ leaq(rax, at_bcp((is_wide ? 5 : 3) -
+    __ lea(rax, at_bcp((is_wide ? 5 : 3) -
                         in_bytes(constMethodOopDesc::codes_offset())));
-    __ subq(rax, Address(rcx, methodOopDesc::const_offset()));
+    __ subptr(rax, Address(rcx, methodOopDesc::const_offset()));
     // Adjust the bcp in r13 by the displacement in rdx
-    __ addq(r13, rdx);
+    __ addptr(r13, rdx);
     // jsr returns atos that is not an oop
     __ push_i(rax);
     __ dispatch_only(vtos);
@@ -1510,7 +1512,7 @@
   // Normal (non-jsr) branch handling
 
   // Adjust the bcp in r13 by the displacement in rdx
-  __ addq(r13, rdx);
+  __ addptr(r13, rdx);
 
   assert(UseLoopCounter || !UseOnStackReplacement,
          "on-stack-replacement requires loop counters");
@@ -1594,25 +1596,25 @@
                  CAST_FROM_FN_PTR(address,
                                   InterpreterRuntime::profile_method), r13);
       __ load_unsigned_byte(rbx, Address(r13, 0));  // restore target bytecode
-      __ movq(rcx, Address(rbp, method_offset));
-      __ movq(rcx, Address(rcx,
-                           in_bytes(methodOopDesc::method_data_offset())));
-      __ movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
-              rcx);
+      __ movptr(rcx, Address(rbp, method_offset));
+      __ movptr(rcx, Address(rcx,
+                             in_bytes(methodOopDesc::method_data_offset())));
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
+                rcx);
       __ test_method_data_pointer(rcx, dispatch);
       // offset non-null mdp by MDO::data_offset() + IR::profile_method()
-      __ addq(rcx, in_bytes(methodDataOopDesc::data_offset()));
-      __ addq(rcx, rax);
-      __ movq(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
-              rcx);
+      __ addptr(rcx, in_bytes(methodDataOopDesc::data_offset()));
+      __ addptr(rcx, rax);
+      __ movptr(Address(rbp, frame::interpreter_frame_mdx_offset * wordSize),
+                rcx);
       __ jmp(dispatch);
     }
 
     if (UseOnStackReplacement) {
       // invocation counter overflow
       __ bind(backedge_counter_overflow);
-      __ negq(rdx);
-      __ addq(rdx, r13); // branch bcp
+      __ negptr(rdx);
+      __ addptr(rdx, r13); // branch bcp
       // IcoResult frequency_counter_overflow([JavaThread*], address branch_bcp)
       __ call_VM(noreg,
                  CAST_FROM_FN_PTR(address,
@@ -1625,7 +1627,7 @@
       // rdx: scratch
       // r14: locals pointer
       // r13: bcp
-      __ testq(rax, rax);                        // test result
+      __ testptr(rax, rax);                        // test result
       __ jcc(Assembler::zero, dispatch);         // no osr if null
       // nmethod may have been invalidated (VM may block upon call_VM return)
       __ movl(rcx, Address(rax, nmethod::entry_bci_offset()));
@@ -1636,12 +1638,12 @@
       // We need to prepare to execute the OSR method. First we must
       // migrate the locals and monitors off of the stack.
 
-      __ movq(r13, rax);                             // save the nmethod
+      __ mov(r13, rax);                             // save the nmethod
 
       call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::OSR_migration_begin));
 
       // eax is OSR buffer, move it to expected parameter location
-      __ movq(j_rarg0, rax);
+      __ mov(j_rarg0, rax);
 
       // We use j_rarg definitions here so that registers don't conflict as parameter
       // registers change across platforms as we are in the midst of a calling
@@ -1651,18 +1653,18 @@
       const Register sender_sp = j_rarg1;
 
       // pop the interpreter frame
-      __ movq(sender_sp, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
+      __ movptr(sender_sp, Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize)); // get sender sp
       __ leave();                                // remove frame anchor
-      __ popq(retaddr);                            // get return address
-      __ movq(rsp, sender_sp);                   // set sp to sender sp
+      __ pop(retaddr);                           // get return address
+      __ mov(rsp, sender_sp);                   // set sp to sender sp
       // Ensure compiled code always sees stack at proper alignment
-      __ andq(rsp, -(StackAlignmentInBytes));
+      __ andptr(rsp, -(StackAlignmentInBytes));
 
       // unlike x86 we need no specialized return from compiled code
       // to the interpreter or the call stub.
 
       // push the return address
-      __ pushq(retaddr);
+      __ push(retaddr);
 
       // and begin the OSR nmethod
       __ jmp(Address(r13, nmethod::osr_entry_point_offset()));
@@ -1698,7 +1700,7 @@
   transition(atos, vtos);
   // assume branch is more often taken than not (loops use backward branches)
   Label not_taken;
-  __ testq(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(j_not(cc), not_taken);
   branch(false, false);
   __ bind(not_taken);
@@ -1710,7 +1712,7 @@
   // assume branch is more often taken than not (loops use backward branches)
   Label not_taken;
   __ pop_ptr(rdx);
-  __ cmpq(rdx, rax);
+  __ cmpptr(rdx, rax);
   __ jcc(j_not(cc), not_taken);
   branch(false, false);
   __ bind(not_taken);
@@ -1720,23 +1722,23 @@
 void TemplateTable::ret() {
   transition(vtos, vtos);
   locals_index(rbx);
-  __ movq(rbx, aaddress(rbx)); // get return bci, compute return bcp
+  __ movslq(rbx, iaddress(rbx)); // get return bci, compute return bcp
   __ profile_ret(rbx, rcx);
   __ get_method(rax);
-  __ movq(r13, Address(rax, methodOopDesc::const_offset()));
-  __ leaq(r13, Address(r13, rbx, Address::times_1,
-                       constMethodOopDesc::codes_offset()));
+  __ movptr(r13, Address(rax, methodOopDesc::const_offset()));
+  __ lea(r13, Address(r13, rbx, Address::times_1,
+                      constMethodOopDesc::codes_offset()));
   __ dispatch_next(vtos);
 }
 
 void TemplateTable::wide_ret() {
   transition(vtos, vtos);
   locals_index_wide(rbx);
-  __ movq(rbx, aaddress(rbx)); // get return bci, compute return bcp
+  __ movptr(rbx, aaddress(rbx)); // get return bci, compute return bcp
   __ profile_ret(rbx, rcx);
   __ get_method(rax);
-  __ movq(r13, Address(rax, methodOopDesc::const_offset()));
-  __ leaq(r13, Address(r13, rbx, Address::times_1, constMethodOopDesc::codes_offset()));
+  __ movptr(r13, Address(rax, methodOopDesc::const_offset()));
+  __ lea(r13, Address(r13, rbx, Address::times_1, constMethodOopDesc::codes_offset()));
   __ dispatch_next(vtos);
 }
 
@@ -1744,8 +1746,8 @@
   Label default_case, continue_execution;
   transition(itos, vtos);
   // align r13
-  __ leaq(rbx, at_bcp(BytesPerInt));
-  __ andq(rbx, -BytesPerInt);
+  __ lea(rbx, at_bcp(BytesPerInt));
+  __ andptr(rbx, -BytesPerInt);
   // load lo & hi
   __ movl(rcx, Address(rbx, BytesPerInt));
   __ movl(rdx, Address(rbx, 2 * BytesPerInt));
@@ -1763,9 +1765,9 @@
   // continue execution
   __ bind(continue_execution);
   __ bswapl(rdx);
-  __ movslq(rdx, rdx);
+  __ movl2ptr(rdx, rdx);
   __ load_unsigned_byte(rbx, Address(r13, rdx, Address::times_1));
-  __ addq(r13, rdx);
+  __ addptr(r13, rdx);
   __ dispatch_only(vtos);
   // handle default
   __ bind(default_case);
@@ -1785,10 +1787,10 @@
   // bswap rax so we can avoid bswapping the table entries
   __ bswapl(rax);
   // align r13
-  __ leaq(rbx, at_bcp(BytesPerInt)); // btw: should be able to get rid of
-                                     // this instruction (change offsets
-                                     // below)
-  __ andq(rbx, -BytesPerInt);
+  __ lea(rbx, at_bcp(BytesPerInt)); // btw: should be able to get rid of
+                                    // this instruction (change offsets
+                                    // below)
+  __ andptr(rbx, -BytesPerInt);
   // set counter
   __ movl(rcx, Address(rbx, BytesPerInt));
   __ bswapl(rcx);
@@ -1811,9 +1813,9 @@
   // continue execution
   __ bind(continue_execution);
   __ bswapl(rdx);
-  __ movslq(rdx, rdx);
+  __ movl2ptr(rdx, rdx);
   __ load_unsigned_byte(rbx, Address(r13, rdx, Address::times_1));
-  __ addq(r13, rdx);
+  __ addptr(r13, rdx);
   __ dispatch_only(vtos);
 }
 
@@ -1853,11 +1855,11 @@
   const Register temp  = rsi;
 
   // Find array start
-  __ leaq(array, at_bcp(3 * BytesPerInt)); // btw: should be able to
-                                           // get rid of this
-                                           // instruction (change
-                                           // offsets below)
-  __ andq(array, -BytesPerInt);
+  __ lea(array, at_bcp(3 * BytesPerInt)); // btw: should be able to
+                                          // get rid of this
+                                          // instruction (change
+                                          // offsets below)
+  __ andptr(array, -BytesPerInt);
 
   // Initialize i & j
   __ xorl(i, i);                            // i = 0;
@@ -1909,9 +1911,9 @@
   __ movl(j , Address(array, i, Address::times_8, BytesPerInt));
   __ profile_switch_case(i, key, array);
   __ bswapl(j);
-  __ movslq(j, j);
+  __ movl2ptr(j, j);
   __ load_unsigned_byte(rbx, Address(r13, j, Address::times_1));
-  __ addq(r13, j);
+  __ addptr(r13, j);
   __ dispatch_only(vtos);
 
   // default case -> j = default offset
@@ -1919,9 +1921,9 @@
   __ profile_switch_default(i);
   __ movl(j, Address(array, -2 * BytesPerInt));
   __ bswapl(j);
-  __ movslq(j, j);
+  __ movl2ptr(j, j);
   __ load_unsigned_byte(rbx, Address(r13, j, Address::times_1));
-  __ addq(r13, j);
+  __ addptr(r13, j);
   __ dispatch_only(vtos);
 }
 
@@ -1933,7 +1935,7 @@
 
   if (_desc->bytecode() == Bytecodes::_return_register_finalizer) {
     assert(state == vtos, "only valid state");
-    __ movq(c_rarg1, aaddress(0));
+    __ movptr(c_rarg1, aaddress(0));
     __ load_klass(rdi, c_rarg1);
     __ movl(rdi, Address(rdi, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc)));
     __ testl(rdi, JVM_ACC_HAS_FINALIZER);
@@ -2044,9 +2046,9 @@
 
   ByteSize cp_base_offset = constantPoolCacheOopDesc::base_offset();
   // Field offset
-  __ movq(off, Address(cache, index, Address::times_8,
-                       in_bytes(cp_base_offset +
-                                ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(off, Address(cache, index, Address::times_8,
+                         in_bytes(cp_base_offset +
+                                  ConstantPoolCacheEntry::f2_offset())));
   // Flags
   __ movl(flags, Address(cache, index, Address::times_8,
                          in_bytes(cp_base_offset +
@@ -2054,9 +2056,9 @@
 
   // klass overwrite register
   if (is_static) {
-    __ movq(obj, Address(cache, index, Address::times_8,
-                         in_bytes(cp_base_offset +
-                                  ConstantPoolCacheEntry::f1_offset())));
+    __ movptr(obj, Address(cache, index, Address::times_8,
+                           in_bytes(cp_base_offset +
+                                    ConstantPoolCacheEntry::f1_offset())));
   }
 }
 
@@ -2088,9 +2090,9 @@
   resolve_cache_and_index(byte_no, cache, index);
 
   assert(wordSize == 8, "adjust code below");
-  __ movq(method, Address(cache, index, Address::times_8, method_offset));
+  __ movptr(method, Address(cache, index, Address::times_8, method_offset));
   if (itable_index != noreg) {
-    __ movq(itable_index,
+    __ movptr(itable_index,
             Address(cache, index, Address::times_8, index_offset));
   }
   __ movl(flags , Address(cache, index, Address::times_8, flags_offset));
@@ -2116,13 +2118,13 @@
     __ get_cache_and_index_at_bcp(c_rarg2, c_rarg3, 1);
 
     // cache entry pointer
-    __ addq(c_rarg2, in_bytes(constantPoolCacheOopDesc::base_offset()));
+    __ addptr(c_rarg2, in_bytes(constantPoolCacheOopDesc::base_offset()));
     __ shll(c_rarg3, LogBytesPerWord);
-    __ addq(c_rarg2, c_rarg3);
+    __ addptr(c_rarg2, c_rarg3);
     if (is_static) {
       __ xorl(c_rarg1, c_rarg1); // NULL object reference
     } else {
-      __ movq(c_rarg1, at_tos()); // get object pointer without popping it
+      __ movptr(c_rarg1, at_tos()); // get object pointer without popping it
       __ verify_oop(c_rarg1);
     }
     // c_rarg1: object pointer or NULL
@@ -2319,20 +2321,20 @@
       // Make sure we don't need to mask rcx for tosBits after the
       // above shift
       ConstantPoolCacheEntry::verify_tosBits();
-      __ movq(c_rarg1, at_tos_p1());  // initially assume a one word jvalue
+      __ movptr(c_rarg1, at_tos_p1());  // initially assume a one word jvalue
       __ cmpl(c_rarg3, ltos);
-      __ cmovq(Assembler::equal,
-               c_rarg1, at_tos_p2()); // ltos (two word jvalue)
+      __ cmovptr(Assembler::equal,
+                 c_rarg1, at_tos_p2()); // ltos (two word jvalue)
       __ cmpl(c_rarg3, dtos);
-      __ cmovq(Assembler::equal,
-               c_rarg1, at_tos_p2()); // dtos (two word jvalue)
+      __ cmovptr(Assembler::equal,
+                 c_rarg1, at_tos_p2()); // dtos (two word jvalue)
     }
     // cache entry pointer
-    __ addq(c_rarg2, in_bytes(cp_base_offset));
+    __ addptr(c_rarg2, in_bytes(cp_base_offset));
     __ shll(rscratch1, LogBytesPerWord);
-    __ addq(c_rarg2, rscratch1);
+    __ addptr(c_rarg2, rscratch1);
     // object (tos)
-    __ movq(c_rarg3, rsp);
+    __ mov(c_rarg3, rsp);
     // c_rarg1: object pointer set up above (NULL if static)
     // c_rarg2: cache entry pointer
     // c_rarg3: jvalue object on the stack
@@ -2510,8 +2512,8 @@
     __ pop_ptr(rbx);                  // copy the object pointer from tos
     __ verify_oop(rbx);
     __ push_ptr(rbx);                 // put the object pointer back on tos
-    __ subq(rsp, sizeof(jvalue));  // add space for a jvalue object
-    __ movq(c_rarg3, rsp);
+    __ subptr(rsp, sizeof(jvalue));  // add space for a jvalue object
+    __ mov(c_rarg3, rsp);
     const Address field(c_rarg3, 0);
 
     switch (bytecode()) {          // load values into the jvalue object
@@ -2529,7 +2531,7 @@
 
     // Save rax because call_VM() will clobber it, then use it for
     // JVMTI purposes
-    __ pushq(rax);
+    __ push(rax);
     // access constant pool cache entry
     __ get_cache_entry_pointer_at_bcp(c_rarg2, rax, 1);
     __ verify_oop(rbx);
@@ -2540,8 +2542,8 @@
                CAST_FROM_FN_PTR(address,
                                 InterpreterRuntime::post_field_modification),
                rbx, c_rarg2, c_rarg3);
-    __ popq(rax);     // restore lower value
-    __ addq(rsp, sizeof(jvalue));  // release jvalue object space
+    __ pop(rax);     // restore lower value
+    __ addptr(rsp, sizeof(jvalue));  // release jvalue object space
     __ bind(L2);
   }
 }
@@ -2562,8 +2564,8 @@
                                 ConstantPoolCacheEntry::flags_offset())));
 
   // replace index with field offset from cache entry
-  __ movq(rbx, Address(rcx, rbx, Address::times_8,
-                       in_bytes(base + ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx, Address(rcx, rbx, Address::times_8,
+                         in_bytes(base + ConstantPoolCacheEntry::f2_offset())));
 
   // [jk] not needed currently
   // volatile_barrier(Assembler::Membar_mask_bits(Assembler::LoadStore |
@@ -2632,15 +2634,15 @@
     // access constant pool cache entry
     __ get_cache_entry_pointer_at_bcp(c_rarg2, rcx, 1);
     __ verify_oop(rax);
-    __ movq(r12, rax);  // save object pointer before call_VM() clobbers it
-    __ movq(c_rarg1, rax);
+    __ mov(r12, rax);  // save object pointer before call_VM() clobbers it
+    __ mov(c_rarg1, rax);
     // c_rarg1: object pointer copied above
     // c_rarg2: cache entry pointer
     __ call_VM(noreg,
                CAST_FROM_FN_PTR(address,
                                 InterpreterRuntime::post_field_access),
                c_rarg1, c_rarg2);
-    __ movq(rax, r12); // restore object pointer
+    __ mov(rax, r12); // restore object pointer
     __ reinit_heapbase();
     __ bind(L1);
   }
@@ -2656,9 +2658,9 @@
   //   __ shrl(rdx, ConstantPoolCacheEntry::volatileField);
   //   __ andl(rdx, 0x1);
   // }
-  __ movq(rbx, Address(rcx, rbx, Address::times_8,
-                       in_bytes(constantPoolCacheOopDesc::base_offset() +
-                                ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx, Address(rcx, rbx, Address::times_8,
+                         in_bytes(constantPoolCacheOopDesc::base_offset() +
+                                  ConstantPoolCacheEntry::f2_offset())));
 
   // rax: object
   __ verify_oop(rax);
@@ -2709,17 +2711,17 @@
   transition(vtos, state);
 
   // get receiver
-  __ movq(rax, aaddress(0));
+  __ movptr(rax, aaddress(0));
   debug_only(__ verify_local_tag(frame::TagReference, 0));
   // access constant pool cache
   __ get_cache_and_index_at_bcp(rcx, rdx, 2);
-  __ movq(rbx,
-          Address(rcx, rdx, Address::times_8,
-                  in_bytes(constantPoolCacheOopDesc::base_offset() +
-                           ConstantPoolCacheEntry::f2_offset())));
+  __ movptr(rbx,
+            Address(rcx, rdx, Address::times_8,
+                    in_bytes(constantPoolCacheOopDesc::base_offset() +
+                             ConstantPoolCacheEntry::f2_offset())));
   // make sure exception is reported in correct bcp range (getfield is
   // next instruction)
-  __ incrementq(r13);
+  __ increment(r13);
   __ null_check(rax);
   switch (state) {
   case itos:
@@ -2749,7 +2751,7 @@
   //   __ bind(notVolatile);
   // }
 
-  __ decrementq(r13);
+  __ decrement(r13);
 }
 
 
@@ -2788,7 +2790,7 @@
     __ movl(recv, flags);
     __ andl(recv, 0xFF);
     if (TaggedStackInterpreter) __ shll(recv, 1);  // index*2
-    __ movq(recv, Address(rsp, recv, Address::times_8,
+    __ movptr(recv, Address(rsp, recv, Address::times_8,
                                  -Interpreter::expr_offset_in_bytes(1)));
     __ verify_oop(recv);
   }
@@ -2811,11 +2813,11 @@
     ExternalAddress return_5((address)Interpreter::return_5_addrs_by_index_table());
     ExternalAddress return_3((address)Interpreter::return_3_addrs_by_index_table());
     __ lea(rscratch1, (is_invokeinterface ? return_5 : return_3));
-    __ movq(flags, Address(rscratch1, flags, Address::times_8));
+    __ movptr(flags, Address(rscratch1, flags, Address::times_8));
   }
 
   // push return address
-  __ pushq(flags);
+  __ push(flags);
 
   // Restore flag field from the constant pool cache, and restore esi
   // for later null checks.  r13 is the bytecode pointer
@@ -2867,10 +2869,10 @@
   const int base = instanceKlass::vtable_start_offset() * wordSize;
   assert(vtableEntry::size() * wordSize == 8,
          "adjust the scaling in the code below");
-  __ movq(method, Address(rax, index,
+  __ movptr(method, Address(rax, index,
                                  Address::times_8,
                                  base + vtableEntry::method_offset_in_bytes()));
-  __ movq(rdx, Address(method, methodOopDesc::interpreter_entry_offset()));
+  __ movptr(rdx, Address(method, methodOopDesc::interpreter_entry_offset()));
   __ jump_from_interpreted(method, rdx);
 }
 
@@ -2940,7 +2942,7 @@
   // profile this call
   __ profile_virtual_call(rdx, r13, r14);
 
-  __ movq(r14, rdx); // Save klassOop in r14
+  __ mov(r14, rdx); // Save klassOop in r14
 
   // Compute start of first itableOffsetEntry (which is at the end of
   // the vtable)
@@ -2950,18 +2952,18 @@
          "adjust the scaling in the code below");
   __ movl(r13, Address(rdx,
                        instanceKlass::vtable_length_offset() * wordSize));
-  __ leaq(rdx, Address(rdx, r13, Address::times_8, base));
+  __ lea(rdx, Address(rdx, r13, Address::times_8, base));
 
   if (HeapWordsPerLong > 1) {
     // Round up to align_object_offset boundary
-    __ round_to_q(rdx, BytesPerLong);
+    __ round_to(rdx, BytesPerLong);
   }
 
   Label entry, search, interface_ok;
 
   __ jmpb(entry);
   __ bind(search);
-  __ addq(rdx, itableOffsetEntry::size() * wordSize);
+  __ addptr(rdx, itableOffsetEntry::size() * wordSize);
 
   __ bind(entry);
 
@@ -2969,13 +2971,13 @@
   // receiver class doesn't implement the interface, and wasn't the
   // same as the receiver class checked when the interface was
   // resolved.
-  __ pushq(rdx);
-  __ movq(rdx, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
-  __ testq(rdx, rdx);
+  __ push(rdx);
+  __ movptr(rdx, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
+  __ testptr(rdx, rdx);
   __ jcc(Assembler::notZero, interface_ok);
   // throw exception
-  __ popq(rdx); // pop saved register first.
-  __ popq(rbx); // pop return address (pushed by prepare_invoke)
+  __ pop(rdx); // pop saved register first.
+  __ pop(rbx); // pop return address (pushed by prepare_invoke)
   __ restore_bcp(); // r13 must be correct for exception handler (was
                     // destroyed)
   __ restore_locals(); // make sure locals pointer is correct as well
@@ -2986,17 +2988,17 @@
   __ should_not_reach_here();
   __ bind(interface_ok);
 
-  __ popq(rdx);
-
-  __ cmpq(rax, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
+  __ pop(rdx);
+
+  __ cmpptr(rax, Address(rdx, itableOffsetEntry::interface_offset_in_bytes()));
   __ jcc(Assembler::notEqual, search);
 
   __ movl(rdx, Address(rdx, itableOffsetEntry::offset_offset_in_bytes()));
 
-  __ addq(rdx, r14); // Add offset to klassOop
+  __ addptr(rdx, r14); // Add offset to klassOop
   assert(itableMethodEntry::size() * wordSize == 8,
          "adjust the scaling in the code below");
-  __ movq(rbx, Address(rdx, rbx, Address::times_8));
+  __ movptr(rbx, Address(rdx, rbx, Address::times_8));
   // rbx: methodOop to call
   // rcx: receiver
   // Check for abstract method error
@@ -3005,12 +3007,12 @@
   // conditional jump to it in case of a null method.
   {
     Label L;
-    __ testq(rbx, rbx);
+    __ testptr(rbx, rbx);
     __ jcc(Assembler::notZero, L);
     // throw exception
     // note: must restore interpreter registers to canonical
     //       state for exception handling to work correctly!
-    __ popq(rbx);  // pop return address (pushed by prepare_invoke)
+    __ pop(rbx);  // pop return address (pushed by prepare_invoke)
     __ restore_bcp(); // r13 must be correct for exception handler
                       // (was destroyed)
     __ restore_locals(); // make sure locals pointer is correct as
@@ -3023,7 +3025,7 @@
     __ bind(L);
   }
 
-  __ movq(rcx, Address(rbx, methodOopDesc::interpreter_entry_offset()));
+  __ movptr(rcx, Address(rbx, methodOopDesc::interpreter_entry_offset()));
 
   // do the call
   // rcx: receiver
@@ -3047,8 +3049,8 @@
 
   __ get_cpool_and_tags(rsi, rax);
   // get instanceKlass
-  __ movq(rsi, Address(rsi, rdx,
-                       Address::times_8, sizeof(constantPoolOopDesc)));
+  __ movptr(rsi, Address(rsi, rdx,
+                         Address::times_8, sizeof(constantPoolOopDesc)));
 
   // make sure the class we're about to instantiate has been
   // resolved. Note: slow_case does a pop of stack, which is why we
@@ -3084,11 +3086,11 @@
     Universe::heap()->supports_inline_contig_alloc() && !CMSIncrementalMode;
 
   if (UseTLAB) {
-    __ movq(rax, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
-    __ leaq(rbx, Address(rax, rdx, Address::times_1));
-    __ cmpq(rbx, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
+    __ movptr(rax, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
+    __ lea(rbx, Address(rax, rdx, Address::times_1));
+    __ cmpptr(rbx, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
     __ jcc(Assembler::above, allow_shared_alloc ? allocate_shared : slow_case);
-    __ movq(Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())), rbx);
+    __ movptr(Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())), rbx);
     if (ZeroTLAB) {
       // the fields have been already cleared
       __ jmp(initialize_header);
@@ -3109,13 +3111,13 @@
 
     __ lea(RtopAddr, top);
     __ lea(RendAddr, end);
-    __ movq(rax, Address(RtopAddr, 0));
+    __ movptr(rax, Address(RtopAddr, 0));
 
     // For retries rax gets set by cmpxchgq
     Label retry;
     __ bind(retry);
-    __ leaq(rbx, Address(rax, rdx, Address::times_1));
-    __ cmpq(rbx, Address(RendAddr, 0));
+    __ lea(rbx, Address(rax, rdx, Address::times_1));
+    __ cmpptr(rbx, Address(RendAddr, 0));
     __ jcc(Assembler::above, slow_case);
 
     // Compare rax with the top addr, and if still equal, store the new
@@ -3128,7 +3130,7 @@
     if (os::is_MP()) {
       __ lock();
     }
-    __ cmpxchgq(rbx, Address(RtopAddr, 0));
+    __ cmpxchgptr(rbx, Address(RtopAddr, 0));
 
     // if someone beat us on the allocation, try again, otherwise continue
     __ jcc(Assembler::notEqual, retry);
@@ -3157,8 +3159,8 @@
     // initialize object header only.
     __ bind(initialize_header);
     if (UseBiasedLocking) {
-      __ movq(rscratch1, Address(rsi, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
-      __ movq(Address(rax, oopDesc::mark_offset_in_bytes()), rscratch1);
+      __ movptr(rscratch1, Address(rsi, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+      __ movptr(Address(rax, oopDesc::mark_offset_in_bytes()), rscratch1);
     } else {
       __ movptr(Address(rax, oopDesc::mark_offset_in_bytes()),
                (intptr_t) markOopDesc::prototype()); // header (address 0x1)
@@ -3215,7 +3217,7 @@
 void TemplateTable::checkcast() {
   transition(atos, atos);
   Label done, is_null, ok_is_subtype, quicked, resolved;
-  __ testq(rax, rax); // object is in rax
+  __ testptr(rax, rax); // object is in rax
   __ jcc(Assembler::zero, is_null);
 
   // Get cpool & tags index
@@ -3228,7 +3230,7 @@
           JVM_CONSTANT_Class);
   __ jcc(Assembler::equal, quicked);
   __ push(atos); // save receiver for result, and for GC
-  __ movq(r12, rcx); // save rcx XXX
+  __ mov(r12, rcx); // save rcx XXX
   call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::quicken_io_cc));
   __ movq(rcx, r12); // restore rcx XXX
   __ reinit_heapbase();
@@ -3237,8 +3239,8 @@
 
   // Get superklass in rax and subklass in rbx
   __ bind(quicked);
-  __ movq(rdx, rax); // Save object in rdx; rax needed for subtype check
-  __ movq(rax, Address(rcx, rbx,
+  __ mov(rdx, rax); // Save object in rdx; rax needed for subtype check
+  __ movptr(rax, Address(rcx, rbx,
                        Address::times_8, sizeof(constantPoolOopDesc)));
 
   __ bind(resolved);
@@ -3255,7 +3257,7 @@
 
   // Come here on success
   __ bind(ok_is_subtype);
-  __ movq(rax, rdx); // Restore object in rdx
+  __ mov(rax, rdx); // Restore object in rdx
 
   // Collect counts on whether this check-cast sees NULLs a lot or not.
   if (ProfileInterpreter) {
@@ -3271,7 +3273,7 @@
 void TemplateTable::instanceof() {
   transition(atos, itos);
   Label done, is_null, ok_is_subtype, quicked, resolved;
-  __ testq(rax, rax);
+  __ testptr(rax, rax);
   __ jcc(Assembler::zero, is_null);
 
   // Get cpool & tags index
@@ -3285,7 +3287,7 @@
   __ jcc(Assembler::equal, quicked);
 
   __ push(atos); // save receiver for result, and for GC
-  __ movq(r12, rcx); // save rcx
+  __ mov(r12, rcx); // save rcx
   call_VM(rax, CAST_FROM_FN_PTR(address, InterpreterRuntime::quicken_io_cc));
   __ movq(rcx, r12); // restore rcx
   __ reinit_heapbase();
@@ -3296,8 +3298,8 @@
   // Get superklass in rax and subklass in rdx
   __ bind(quicked);
   __ load_klass(rdx, rax);
-  __ movq(rax, Address(rcx, rbx,
-                              Address::times_8, sizeof(constantPoolOopDesc)));
+  __ movptr(rax, Address(rcx, rbx,
+                         Address::times_8, sizeof(constantPoolOopDesc)));
 
   __ bind(resolved);
 
@@ -3340,7 +3342,7 @@
              CAST_FROM_FN_PTR(address,
                               InterpreterRuntime::get_original_bytecode_at),
              c_rarg1, r13);
-  __ movq(rbx, rax);
+  __ mov(rbx, rax);
 
   // post the breakpoint event
   __ get_method(c_rarg1);
@@ -3398,52 +3400,52 @@
   // find a free slot in the monitor block (result in c_rarg1)
   {
     Label entry, loop, exit;
-    __ movq(c_rarg3, monitor_block_top); // points to current entry,
+    __ movptr(c_rarg3, monitor_block_top); // points to current entry,
                                      // starting with top-most entry
-    __ leaq(c_rarg2, monitor_block_bot); // points to word before bottom
+    __ lea(c_rarg2, monitor_block_bot); // points to word before bottom
                                      // of monitor block
     __ jmpb(entry);
 
     __ bind(loop);
     // check if current entry is used
-    __ cmpq(Address(c_rarg3, BasicObjectLock::obj_offset_in_bytes()), (int) NULL);
+    __ cmpptr(Address(c_rarg3, BasicObjectLock::obj_offset_in_bytes()), (int32_t) NULL_WORD);
     // if not used then remember entry in c_rarg1
-    __ cmovq(Assembler::equal, c_rarg1, c_rarg3);
+    __ cmov(Assembler::equal, c_rarg1, c_rarg3);
     // check if current entry is for same object
-    __ cmpq(rax, Address(c_rarg3, BasicObjectLock::obj_offset_in_bytes()));
+    __ cmpptr(rax, Address(c_rarg3, BasicObjectLock::obj_offset_in_bytes()));
     // if same object then stop searching
     __ jccb(Assembler::equal, exit);
     // otherwise advance to next entry
-    __ addq(c_rarg3, entry_size);
+    __ addptr(c_rarg3, entry_size);
     __ bind(entry);
     // check if bottom reached
-    __ cmpq(c_rarg3, c_rarg2);
+    __ cmpptr(c_rarg3, c_rarg2);
     // if not at bottom then check this entry
     __ jcc(Assembler::notEqual, loop);
     __ bind(exit);
   }
 
-  __ testq(c_rarg1, c_rarg1); // check if a slot has been found
+  __ testptr(c_rarg1, c_rarg1); // check if a slot has been found
   __ jcc(Assembler::notZero, allocated); // if found, continue with that one
 
   // allocate one if there's no free slot
   {
     Label entry, loop;
-    // 1. compute new pointers       // rsp: old expression stack top
-    __ movq(c_rarg1, monitor_block_bot); // c_rarg1: old expression stack bottom
-    __ subq(rsp, entry_size);        // move expression stack top
-    __ subq(c_rarg1, entry_size);        // move expression stack bottom
-    __ movq(c_rarg3, rsp);               // set start value for copy loop
-    __ movq(monitor_block_bot, c_rarg1); // set new monitor block bottom
+    // 1. compute new pointers             // rsp: old expression stack top
+    __ movptr(c_rarg1, monitor_block_bot); // c_rarg1: old expression stack bottom
+    __ subptr(rsp, entry_size);            // move expression stack top
+    __ subptr(c_rarg1, entry_size);        // move expression stack bottom
+    __ mov(c_rarg3, rsp);                  // set start value for copy loop
+    __ movptr(monitor_block_bot, c_rarg1); // set new monitor block bottom
     __ jmp(entry);
     // 2. move expression stack contents
     __ bind(loop);
-    __ movq(c_rarg2, Address(c_rarg3, entry_size)); // load expression stack
-                                            // word from old location
-    __ movq(Address(c_rarg3, 0), c_rarg2);  // and store it at new location
-    __ addq(c_rarg3, wordSize);             // advance to next word
+    __ movptr(c_rarg2, Address(c_rarg3, entry_size)); // load expression stack
+                                                      // word from old location
+    __ movptr(Address(c_rarg3, 0), c_rarg2);          // and store it at new location
+    __ addptr(c_rarg3, wordSize);                     // advance to next word
     __ bind(entry);
-    __ cmpq(c_rarg3, c_rarg1);              // check if bottom reached
+    __ cmpptr(c_rarg3, c_rarg1);            // check if bottom reached
     __ jcc(Assembler::notEqual, loop);      // if not at bottom then
                                             // copy next word
   }
@@ -3456,10 +3458,10 @@
   // handling for async. exceptions work correctly.
   // The object has already been poped from the stack, so the
   // expression stack looks correct.
-  __ incrementq(r13);
+  __ increment(r13);
 
   // store object
-  __ movq(Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()), rax);
+  __ movptr(Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()), rax);
   __ lock_object(c_rarg1);
 
   // check to make sure this monitor doesn't cause stack overflow after locking
@@ -3489,22 +3491,22 @@
   // find matching slot
   {
     Label entry, loop;
-    __ movq(c_rarg1, monitor_block_top); // points to current entry,
+    __ movptr(c_rarg1, monitor_block_top); // points to current entry,
                                      // starting with top-most entry
-    __ leaq(c_rarg2, monitor_block_bot); // points to word before bottom
+    __ lea(c_rarg2, monitor_block_bot); // points to word before bottom
                                      // of monitor block
     __ jmpb(entry);
 
     __ bind(loop);
     // check if current entry is for same object
-    __ cmpq(rax, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
+    __ cmpptr(rax, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes()));
     // if same object then stop searching
     __ jcc(Assembler::equal, found);
     // otherwise advance to next entry
-    __ addq(c_rarg1, entry_size);
+    __ addptr(c_rarg1, entry_size);
     __ bind(entry);
     // check if bottom reached
-    __ cmpq(c_rarg1, c_rarg2);
+    __ cmpptr(c_rarg1, c_rarg2);
     // if not at bottom then check this entry
     __ jcc(Assembler::notEqual, loop);
   }
@@ -3541,11 +3543,12 @@
   // last dim is on top of stack; we want address of first one:
   // first_addr = last_addr + (ndims - 1) * wordSize
   if (TaggedStackInterpreter) __ shll(rax, 1);  // index*2
-  __ leaq(c_rarg1, Address(rsp, rax, Address::times_8, -wordSize));
+  __ lea(c_rarg1, Address(rsp, rax, Address::times_8, -wordSize));
   call_VM(rax,
           CAST_FROM_FN_PTR(address, InterpreterRuntime::multianewarray),
           c_rarg1);
   __ load_unsigned_byte(rbx, at_bcp(3));
   if (TaggedStackInterpreter) __ shll(rbx, 1);  // index*2
-  __ leaq(rsp, Address(rsp, rbx, Address::times_8));
+  __ lea(rsp, Address(rsp, rbx, Address::times_8));
 }
+#endif // !CC_INTERP
--- a/hotspot/src/cpu/x86/vm/vm_version_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/vm_version_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -67,23 +67,23 @@
     //
     // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
     //
-    __ pushl(rbp);
-    __ movl(rbp, Address(rsp, 8)); // cpuid_info address
-    __ pushl(rbx);
-    __ pushl(rsi);
-    __ pushfd();                // preserve rbx, and flags
-    __ popl(rax);
-    __ pushl(rax);
-    __ movl(rcx, rax);
+    __ push(rbp);
+    __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
+    __ push(rbx);
+    __ push(rsi);
+    __ pushf();          // preserve rbx, and flags
+    __ pop(rax);
+    __ push(rax);
+    __ mov(rcx, rax);
     //
     // if we are unable to change the AC flag, we have a 386
     //
     __ xorl(rax, EFL_AC);
-    __ pushl(rax);
-    __ popfd();
-    __ pushfd();
-    __ popl(rax);
-    __ cmpl(rax, rcx);
+    __ push(rax);
+    __ popf();
+    __ pushf();
+    __ pop(rax);
+    __ cmpptr(rax, rcx);
     __ jccb(Assembler::notEqual, detect_486);
 
     __ movl(rax, CPU_FAMILY_386);
@@ -95,13 +95,13 @@
     // not support the "cpuid" instruction.
     //
     __ bind(detect_486);
-    __ movl(rax, rcx);
+    __ mov(rax, rcx);
     __ xorl(rax, EFL_ID);
-    __ pushl(rax);
-    __ popfd();
-    __ pushfd();
-    __ popl(rax);
-    __ cmpl(rcx, rax);
+    __ push(rax);
+    __ popf();
+    __ pushf();
+    __ pop(rax);
+    __ cmpptr(rcx, rax);
     __ jccb(Assembler::notEqual, detect_586);
 
     __ bind(cpu486);
@@ -113,13 +113,13 @@
     // at this point, we have a chip which supports the "cpuid" instruction
     //
     __ bind(detect_586);
-    __ xorl(rax, rax);
+    __ xorptr(rax, rax);
     __ cpuid();
-    __ orl(rax, rax);
+    __ orptr(rax, rax);
     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
                                         // value of at least 1, we give up and
                                         // assume a 486
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -134,13 +134,13 @@
     __ movl(rax, 4);     // and rcx already set to 0x0
     __ xorl(rcx, rcx);
     __ cpuid();
-    __ pushl(rax);
+    __ push(rax);
     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
     __ orl(rax, rax);    // rax,[4:0] == 0 indicates invalid cache
-    __ popl(rax);
+    __ pop(rax);
     __ jccb(Assembler::equal, std_cpuid1);
 
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -152,7 +152,7 @@
     __ bind(std_cpuid1);
     __ movl(rax, 1);
     __ cpuid();
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -171,7 +171,7 @@
     //
     __ movl(rax, 0x80000008);
     __ cpuid();
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -183,7 +183,7 @@
     __ bind(ext_cpuid5);
     __ movl(rax, 0x80000005);
     __ cpuid();
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -195,7 +195,7 @@
     __ bind(ext_cpuid1);
     __ movl(rax, 0x80000001);
     __ cpuid();
-    __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -205,10 +205,10 @@
     // return
     //
     __ bind(done);
-    __ popfd();
-    __ popl(rsi);
-    __ popl(rbx);
-    __ popl(rbp);
+    __ popf();
+    __ pop(rsi);
+    __ pop(rbx);
+    __ pop(rbp);
     __ ret(0);
 
 #   undef __
--- a/hotspot/src/cpu/x86/vm/vm_version_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/vm_version_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -60,17 +60,17 @@
     //
     // rcx and rdx are first and second argument registers on windows
 
-    __ pushq(rbp);
-    __ movq(rbp, c_rarg0); // cpuid_info address
-    __ pushq(rbx);
-    __ pushq(rsi);
+    __ push(rbp);
+    __ mov(rbp, c_rarg0); // cpuid_info address
+    __ push(rbx);
+    __ push(rsi);
 
     //
     // we have a chip which supports the "cpuid" instruction
     //
     __ xorl(rax, rax);
     __ cpuid();
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -85,13 +85,13 @@
     __ movl(rax, 4);
     __ xorl(rcx, rcx);   // L1 cache
     __ cpuid();
-    __ pushq(rax);
+    __ push(rax);
     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
-    __ popq(rax);
+    __ pop(rax);
     __ jccb(Assembler::equal, std_cpuid1);
 
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -103,7 +103,7 @@
     __ bind(std_cpuid1);
     __ movl(rax, 1);
     __ cpuid();
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -122,7 +122,7 @@
     //
     __ movl(rax, 0x80000008);
     __ cpuid();
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -134,7 +134,7 @@
     __ bind(ext_cpuid5);
     __ movl(rax, 0x80000005);
     __ cpuid();
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -146,7 +146,7 @@
     __ bind(ext_cpuid1);
     __ movl(rax, 0x80000001);
     __ cpuid();
-    __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
+    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
     __ movl(Address(rsi, 0), rax);
     __ movl(Address(rsi, 4), rbx);
     __ movl(Address(rsi, 8), rcx);
@@ -156,9 +156,9 @@
     // return
     //
     __ bind(done);
-    __ popq(rsi);
-    __ popq(rbx);
-    __ popq(rbp);
+    __ pop(rsi);
+    __ pop(rbx);
+    __ pop(rbp);
     __ ret(0);
 
 #   undef __
--- a/hotspot/src/cpu/x86/vm/vtableStubs_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/vtableStubs_x86_32.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -49,7 +49,7 @@
 #ifndef PRODUCT
 
   if (CountCompiledCalls) {
-    __ increment(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
+    __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
   }
 #endif /* PRODUCT */
 
@@ -58,7 +58,7 @@
 
   // get receiver klass
   address npe_addr = __ pc();
-  __ movl(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
   // compute entry offset (in words)
   int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
 #ifndef PRODUCT
@@ -76,12 +76,12 @@
   const Register method = rbx;
 
   // load methodOop and target address
-  __ movl(method, Address(rax, entry_offset*wordSize + vtableEntry::method_offset_in_bytes()));
+  __ movptr(method, Address(rax, entry_offset*wordSize + vtableEntry::method_offset_in_bytes()));
   if (DebugVtables) {
     Label L;
-    __ cmpl(method, NULL_WORD);
+    __ cmpptr(method, (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, L);
-    __ cmpl(Address(method, methodOopDesc::from_compiled_offset()), NULL_WORD);
+    __ cmpptr(Address(method, methodOopDesc::from_compiled_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::notZero, L);
     __ stop("Vtable entry is NULL");
     __ bind(L);
@@ -114,7 +114,7 @@
 
 #ifndef PRODUCT
   if (CountCompiledCalls) {
-    __ increment(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
+    __ incrementl(ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr()));
   }
 #endif /* PRODUCT */
   // get receiver (need to skip return address on top of stack)
@@ -123,16 +123,16 @@
 
   // get receiver klass (also an implicit null-check)
   address npe_addr = __ pc();
-  __ movl(rbx, Address(rcx, oopDesc::klass_offset_in_bytes()));
+  __ movptr(rbx, Address(rcx, oopDesc::klass_offset_in_bytes()));
 
-  __ movl(rsi, rbx);   // Save klass in free register
+  __ mov(rsi, rbx);   // Save klass in free register
   // Most registers are in use, so save a few
-  __ pushl(rdx);
+  __ push(rdx);
   // compute itable entry offset (in words)
   const int base = instanceKlass::vtable_start_offset() * wordSize;
   assert(vtableEntry::size() * wordSize == 4, "adjust the scaling in the code below");
   __ movl(rdx, Address(rbx, instanceKlass::vtable_length_offset() * wordSize)); // Get length of vtable
-  __ leal(rbx, Address(rbx, rdx, Address::times_4, base));
+  __ lea(rbx, Address(rbx, rdx, Address::times_ptr, base));
   if (HeapWordsPerLong > 1) {
     // Round up to align_object_offset boundary
     __ round_to(rbx, BytesPerLong);
@@ -143,16 +143,16 @@
   __ jmpb(entry);
 
   __ bind(next);
-  __ addl(rbx, itableOffsetEntry::size() * wordSize);
+  __ addptr(rbx, itableOffsetEntry::size() * wordSize);
 
   __ bind(entry);
 
   // If the entry is NULL then we've reached the end of the table
   // without finding the expected interface, so throw an exception
-  __ movl(rdx, Address(rbx, itableOffsetEntry::interface_offset_in_bytes()));
-  __ testl(rdx, rdx);
+  __ movptr(rdx, Address(rbx, itableOffsetEntry::interface_offset_in_bytes()));
+  __ testptr(rdx, rdx);
   __ jcc(Assembler::zero, throw_icce);
-  __ cmpl(rax, rdx);
+  __ cmpptr(rax, rdx);
   __ jcc(Assembler::notEqual, next);
 
   // We found a hit, move offset into rbx,
@@ -163,10 +163,10 @@
 
   // Get methodOop and entrypoint for compiler
   const Register method = rbx;
-  __ movl(method, Address(rsi, rdx, Address::times_1, method_offset));
+  __ movptr(method, Address(rsi, rdx, Address::times_1, method_offset));
 
   // Restore saved register, before possible trap.
-  __ popl(rdx);
+  __ pop(rdx);
 
   // method (rbx): methodOop
   // rcx: receiver
@@ -174,9 +174,9 @@
 #ifdef ASSERT
   if (DebugVtables) {
       Label L1;
-      __ cmpl(method, NULL_WORD);
+      __ cmpptr(method, (int32_t)NULL_WORD);
       __ jcc(Assembler::equal, L1);
-      __ cmpl(Address(method, methodOopDesc::from_compiled_offset()), NULL_WORD);
+      __ cmpptr(Address(method, methodOopDesc::from_compiled_offset()), (int32_t)NULL_WORD);
       __ jcc(Assembler::notZero, L1);
       __ stop("methodOop is null");
       __ bind(L1);
@@ -188,7 +188,7 @@
 
   __ bind(throw_icce);
   // Restore saved register
-  __ popl(rdx);
+  __ pop(rdx);
   __ jump(RuntimeAddress(StubRoutines::throw_IncompatibleClassChangeError_entry()));
 
   masm->flush();
--- a/hotspot/src/cpu/x86/vm/vtableStubs_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/vtableStubs_x86_64.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -79,14 +79,14 @@
   // load methodOop and target address
   const Register method = rbx;
 
-  __ movq(method, Address(rax,
-                          entry_offset * wordSize +
-                          vtableEntry::method_offset_in_bytes()));
+  __ movptr(method, Address(rax,
+                            entry_offset * wordSize +
+                            vtableEntry::method_offset_in_bytes()));
   if (DebugVtables) {
     Label L;
-    __ cmpq(method, (int)NULL);
+    __ cmpptr(method, (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, L);
-    __ cmpq(Address(method, methodOopDesc::from_compiled_offset()), (int)NULL_WORD);
+    __ cmpptr(Address(method, methodOopDesc::from_compiled_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::notZero, L);
     __ stop("Vtable entry is NULL");
     __ bind(L);
@@ -138,7 +138,7 @@
   // when there are mistakes in this assembly code that could generate
   // a spurious fault. Ask me how I know...
 
-  __ pushq(j_rarg1);     // Most registers are in use, so save one
+  __ push(j_rarg1);     // Most registers are in use, so save one
 
   // compute itable entry offset (in words)
   const int base = instanceKlass::vtable_start_offset() * wordSize;
@@ -147,27 +147,27 @@
   // Get length of vtable
   __ movl(j_rarg1,
           Address(rbx, instanceKlass::vtable_length_offset() * wordSize));
-  __ leaq(rbx, Address(rbx, j_rarg1, Address::times_8, base));
+  __ lea(rbx, Address(rbx, j_rarg1, Address::times_8, base));
 
   if (HeapWordsPerLong > 1) {
     // Round up to align_object_offset boundary
-    __ round_to_q(rbx, BytesPerLong);
+    __ round_to(rbx, BytesPerLong);
   }
   Label hit, next, entry, throw_icce;
 
   __ jmpb(entry);
 
   __ bind(next);
-  __ addq(rbx, itableOffsetEntry::size() * wordSize);
+  __ addptr(rbx, itableOffsetEntry::size() * wordSize);
 
   __ bind(entry);
 
   // If the entry is NULL then we've reached the end of the table
   // without finding the expected interface, so throw an exception
-  __ movq(j_rarg1, Address(rbx, itableOffsetEntry::interface_offset_in_bytes()));
-  __ testq(j_rarg1, j_rarg1);
+  __ movptr(j_rarg1, Address(rbx, itableOffsetEntry::interface_offset_in_bytes()));
+  __ testptr(j_rarg1, j_rarg1);
   __ jcc(Assembler::zero, throw_icce);
-  __ cmpq(rax, j_rarg1);
+  __ cmpptr(rax, j_rarg1);
   __ jccb(Assembler::notEqual, next);
 
   // We found a hit, move offset into j_rarg1
@@ -184,10 +184,10 @@
   __ load_klass(rax, j_rarg0);
 
   const Register method = rbx;
-  __ movq(method, Address(rax, j_rarg1, Address::times_1, method_offset));
+  __ movptr(method, Address(rax, j_rarg1, Address::times_1, method_offset));
 
   // Restore saved register, before possible trap.
-  __ popq(j_rarg1);
+  __ pop(j_rarg1);
 
   // method (rbx): methodOop
   // j_rarg0: receiver
@@ -196,9 +196,9 @@
 #ifdef ASSERT
   if (DebugVtables) {
     Label L2;
-    __ cmpq(method, (int)NULL);
+    __ cmpptr(method, (int32_t)NULL_WORD);
     __ jcc(Assembler::equal, L2);
-    __ cmpq(Address(method, methodOopDesc::from_compiled_offset()), (int)NULL_WORD);
+    __ cmpptr(Address(method, methodOopDesc::from_compiled_offset()), (int32_t)NULL_WORD);
     __ jcc(Assembler::notZero, L2);
     __ stop("compiler entrypoint is null");
     __ bind(L2);
@@ -212,7 +212,7 @@
 
   __ bind(throw_icce);
   // Restore saved register
-  __ popq(j_rarg1);
+  __ pop(j_rarg1);
   __ jump(RuntimeAddress(StubRoutines::throw_IncompatibleClassChangeError_entry()));
 
   __ flush();
--- a/hotspot/src/cpu/x86/vm/x86_32.ad	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/x86_32.ad	Wed Jul 05 16:41:01 2017 +0200
@@ -236,7 +236,7 @@
 // This is a block of C++ code which provides values, functions, and
 // definitions necessary in the rest of the architecture description
 source %{
-#define   RELOC_IMM32    Assembler::imm32_operand
+#define   RELOC_IMM32    Assembler::imm_operand
 #define   RELOC_DISP32   Assembler::disp32_operand
 
 #define __ _masm.
@@ -593,11 +593,11 @@
   if (VerifyStackAtCalls) {
     Label L;
     MacroAssembler masm(&cbuf);
-    masm.pushl(rax);
-    masm.movl(rax, rsp);
-    masm.andl(rax, StackAlignmentInBytes-1);
-    masm.cmpl(rax, StackAlignmentInBytes-wordSize);
-    masm.popl(rax);
+    masm.push(rax);
+    masm.mov(rax, rsp);
+    masm.andptr(rax, StackAlignmentInBytes-1);
+    masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
+    masm.pop(rax);
     masm.jcc(Assembler::equal, L);
     masm.stop("Stack is not properly aligned!");
     masm.bind(L);
@@ -1150,7 +1150,8 @@
   __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
   // static stub relocation also tags the methodOop in the code-stream.
   __ movoop(rbx, (jobject)NULL);  // method is zapped till fixup time
-  __ jump(RuntimeAddress((address)-1));
+  // This is recognized as unresolved by relocs/nativeInst/ic code
+  __ jump(RuntimeAddress(__ pc()));
 
   __ end_a_stub();
   // Update current stubs pointer and restore code_end.
@@ -1181,7 +1182,7 @@
 #ifdef ASSERT
   uint code_size = cbuf.code_size();
 #endif
-  masm.cmpl(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
+  masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
   masm.jump_cc(Assembler::notEqual,
                RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
   /* WARNING these NOPs are critical so that verified entry point is properly
@@ -1687,20 +1688,20 @@
     // Compare super with sub directly, since super is not in its own SSA.
     // The compiler used to emit this test, but we fold it in here,
     // to allow platform-specific tweaking on sparc.
-    __ cmpl(Reax, Resi);
+    __ cmpptr(Reax, Resi);
     __ jcc(Assembler::equal, hit);
 #ifndef PRODUCT
-    __ increment(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
+    __ incrementl(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
 #endif //PRODUCT
-    __ movl(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
+    __ movptr(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
     __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes()));
-    __ addl(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+    __ addptr(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
     __ repne_scan();
     __ jcc(Assembler::notEqual, miss);
-    __ movl(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
+    __ movptr(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
     __ bind(hit);
     if( $primary )
-      __ xorl(Redi,Redi);
+      __ xorptr(Redi,Redi);
     __ bind(miss);
   %}
 
@@ -1749,15 +1750,15 @@
         // optimizer if the C function is a pure function.
         __ ffree(0);
       } else if (rt == T_FLOAT) {
-        __ leal(rsp, Address(rsp, -4));
+        __ lea(rsp, Address(rsp, -4));
         __ fstp_s(Address(rsp, 0));
         __ movflt(xmm0, Address(rsp, 0));
-        __ leal(rsp, Address(rsp,  4));
+        __ lea(rsp, Address(rsp,  4));
       } else if (rt == T_DOUBLE) {
-        __ leal(rsp, Address(rsp, -8));
+        __ lea(rsp, Address(rsp, -8));
         __ fstp_d(Address(rsp, 0));
         __ movdbl(xmm0, Address(rsp, 0));
-        __ leal(rsp, Address(rsp,  8));
+        __ lea(rsp, Address(rsp,  8));
       }
     }
   %}
@@ -2888,10 +2889,10 @@
     __ jccb(Assembler::equal,  done);
     __ jccb(Assembler::above,  inc);
     __ bind(nan);
-    __ decrement(as_Register($dst$$reg));
+    __ decrement(as_Register($dst$$reg)); // NO L qqq
     __ jmpb(done);
     __ bind(inc);
-    __ increment(as_Register($dst$$reg));
+    __ increment(as_Register($dst$$reg)); // NO L qqq
     __ bind(done);
   %}
 
@@ -3158,7 +3159,7 @@
   enc_class mov_i2x(regXD dst, eRegI src) %{
     MacroAssembler _masm(&cbuf);
 
-    __ movd(as_XMMRegister($dst$$reg), as_Register($src$$reg));
+    __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
   %}
 
 
@@ -3258,30 +3259,30 @@
     }
     if (EmitSync & 1) {
         // set box->dhw = unused_mark (3)
-        // Force all sync thru slow-path: slow_enter() and slow_exit()
-        masm.movl (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
-        masm.cmpl (rsp, 0) ;
-    } else
-    if (EmitSync & 2) {
-        Label DONE_LABEL ;
+        // Force all sync thru slow-path: slow_enter() and slow_exit() 
+        masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;             
+        masm.cmpptr (rsp, (int32_t)0) ;                        
+    } else 
+    if (EmitSync & 2) { 
+        Label DONE_LABEL ;           
         if (UseBiasedLocking) {
            // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
            masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
         }
 
-        masm.movl  (tmpReg, Address(objReg, 0)) ;          // fetch markword
-        masm.orl   (tmpReg, 0x1);
-        masm.movl  (Address(boxReg, 0), tmpReg);           // Anticipate successful CAS
+        masm.movptr(tmpReg, Address(objReg, 0)) ;          // fetch markword 
+        masm.orptr (tmpReg, 0x1);
+        masm.movptr(Address(boxReg, 0), tmpReg);           // Anticipate successful CAS 
         if (os::is_MP()) { masm.lock();  }
-        masm.cmpxchg(boxReg, Address(objReg, 0));          // Updates tmpReg
+        masm.cmpxchgptr(boxReg, Address(objReg, 0));          // Updates tmpReg
         masm.jcc(Assembler::equal, DONE_LABEL);
         // Recursive locking
-        masm.subl(tmpReg, rsp);
-        masm.andl(tmpReg, 0xFFFFF003 );
-        masm.movl(Address(boxReg, 0), tmpReg);
-        masm.bind(DONE_LABEL) ;
-    } else {
-      // Possible cases that we'll encounter in fast_lock
+        masm.subptr(tmpReg, rsp);
+        masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
+        masm.movptr(Address(boxReg, 0), tmpReg);
+        masm.bind(DONE_LABEL) ; 
+    } else {  
+      // Possible cases that we'll encounter in fast_lock 
       // ------------------------------------------------
       // * Inflated
       //    -- unlocked
@@ -3310,15 +3311,15 @@
         masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
       }
 
-      masm.movl  (tmpReg, Address(objReg, 0)) ;        // [FETCH]
-      masm.testl (tmpReg, 0x02) ;                      // Inflated v (Stack-locked or neutral)
+      masm.movptr(tmpReg, Address(objReg, 0)) ;         // [FETCH]
+      masm.testptr(tmpReg, 0x02) ;                      // Inflated v (Stack-locked or neutral)
       masm.jccb  (Assembler::notZero, IsInflated) ;
 
       // Attempt stack-locking ...
-      masm.orl   (tmpReg, 0x1);
-      masm.movl  (Address(boxReg, 0), tmpReg);            // Anticipate successful CAS
+      masm.orptr (tmpReg, 0x1);
+      masm.movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
       if (os::is_MP()) { masm.lock();  }
-      masm.cmpxchg(boxReg, Address(objReg, 0));           // Updates tmpReg
+      masm.cmpxchgptr(boxReg, Address(objReg, 0));           // Updates tmpReg
       if (_counters != NULL) {
         masm.cond_inc32(Assembler::equal,
                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
@@ -3326,9 +3327,9 @@
       masm.jccb (Assembler::equal, DONE_LABEL);
 
       // Recursive locking
-      masm.subl(tmpReg, rsp);
-      masm.andl(tmpReg, 0xFFFFF003 );
-      masm.movl(Address(boxReg, 0), tmpReg);
+      masm.subptr(tmpReg, rsp);
+      masm.andptr(tmpReg, 0xFFFFF003 );
+      masm.movptr(Address(boxReg, 0), tmpReg);
       if (_counters != NULL) {
         masm.cond_inc32(Assembler::equal,
                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
@@ -3360,36 +3361,33 @@
       // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
       // additional latency as we have another ST in the store buffer that must drain.
 
-      if (EmitSync & 8192) {
-         masm.movl  (Address(boxReg, 0), 3) ;            // results in ST-before-CAS penalty
-         masm.get_thread (scrReg) ;
-         masm.movl  (boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
-         masm.movl  (tmpReg, 0);                         // consider: xor vs mov
-         if (os::is_MP()) { masm.lock(); }
-         masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-      } else
+      if (EmitSync & 8192) { 
+         masm.movptr(Address(boxReg, 0), 3) ;            // results in ST-before-CAS penalty
+         masm.get_thread (scrReg) ; 
+         masm.movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2] 
+         masm.movptr(tmpReg, 0);                         // consider: xor vs mov
+         if (os::is_MP()) { masm.lock(); } 
+         masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
+      } else 
       if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
-         masm.movl (scrReg, boxReg) ;
-         masm.movl (boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
+         masm.movptr(scrReg, boxReg) ; 
+         masm.movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2] 
 
          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
          if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
             // prefetchw [eax + Offset(_owner)-2]
-            masm.emit_raw (0x0F) ;
-            masm.emit_raw (0x0D) ;
-            masm.emit_raw (0x48) ;
-            masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
+            masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
          }
 
          if ((EmitSync & 64) == 0) {
            // Optimistic form: consider XORL tmpReg,tmpReg
-           masm.movl  (tmpReg, 0 ) ;
-         } else {
+           masm.movptr(tmpReg, 0 ) ; 
+         } else { 
            // Can suffer RTS->RTO upgrades on shared or cold $ lines
            // Test-And-CAS instead of CAS
-           masm.movl  (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
-           masm.testl (tmpReg, tmpReg) ;                   // Locked ?
-           masm.jccb  (Assembler::notZero, DONE_LABEL) ;
+           masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
+           masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
+           masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
          }
 
          // Appears unlocked - try to swing _owner from null to non-null.
@@ -3401,41 +3399,38 @@
          // (rsp or the address of the box) into  m->owner is harmless.
          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
          if (os::is_MP()) { masm.lock();  }
-         masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-         masm.movl  (Address(scrReg, 0), 3) ;          // box->_displaced_header = 3
-         masm.jccb  (Assembler::notZero, DONE_LABEL) ;
+         masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
+         masm.movptr(Address(scrReg, 0), 3) ;          // box->_displaced_header = 3
+         masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
          masm.get_thread (scrReg) ;                    // beware: clobbers ICCs
-         masm.movl  (Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
-         masm.xorl  (boxReg, boxReg) ;                 // set icc.ZFlag = 1 to indicate success
-
-         // If the CAS fails we can either retry or pass control to the slow-path.
-         // We use the latter tactic.
+         masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 
+         masm.xorptr(boxReg, boxReg) ;                 // set icc.ZFlag = 1 to indicate success
+                       
+         // If the CAS fails we can either retry or pass control to the slow-path.  
+         // We use the latter tactic.  
          // Pass the CAS result in the icc.ZFlag into DONE_LABEL
          // If the CAS was successful ...
          //   Self has acquired the lock
          //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
          // Intentional fall-through into DONE_LABEL ...
       } else {
-         masm.movl (Address(boxReg, 0), 3) ;       // results in ST-before-CAS penalty
-         masm.movl (boxReg, tmpReg) ;
+         masm.movptr(Address(boxReg, 0), 3) ;       // results in ST-before-CAS penalty
+         masm.movptr(boxReg, tmpReg) ; 
 
          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
          if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
             // prefetchw [eax + Offset(_owner)-2]
-            masm.emit_raw (0x0F) ;
-            masm.emit_raw (0x0D) ;
-            masm.emit_raw (0x48) ;
-            masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
+            masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
          }
 
          if ((EmitSync & 64) == 0) {
            // Optimistic form
-           masm.xorl  (tmpReg, tmpReg) ;
-         } else {
+           masm.xorptr  (tmpReg, tmpReg) ; 
+         } else { 
            // Can suffer RTS->RTO upgrades on shared or cold $ lines
-           masm.movl  (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
-           masm.testl (tmpReg, tmpReg) ;                   // Locked ?
-           masm.jccb  (Assembler::notZero, DONE_LABEL) ;
+           masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
+           masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
+           masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
          }
 
          // Appears unlocked - try to swing _owner from null to non-null.
@@ -3443,7 +3438,7 @@
          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
          masm.get_thread (scrReg) ;
          if (os::is_MP()) { masm.lock(); }
-         masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
+         masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
 
          // If the CAS fails we can either retry or pass control to the slow-path.
          // We use the latter tactic.
@@ -3514,19 +3509,19 @@
 
     if (EmitSync & 4) {
       // Disable - inhibit all inlining.  Force control through the slow-path
-      masm.cmpl (rsp, 0) ;
-    } else
+      masm.cmpptr (rsp, 0) ; 
+    } else 
     if (EmitSync & 8) {
       Label DONE_LABEL ;
       if (UseBiasedLocking) {
          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
       }
       // classic stack-locking code ...
-      masm.movl  (tmpReg, Address(boxReg, 0)) ;
-      masm.testl (tmpReg, tmpReg) ;
+      masm.movptr(tmpReg, Address(boxReg, 0)) ;
+      masm.testptr(tmpReg, tmpReg) ;
       masm.jcc   (Assembler::zero, DONE_LABEL) ;
       if (os::is_MP()) { masm.lock(); }
-      masm.cmpxchg(tmpReg, Address(objReg, 0));          // Uses EAX which is box
+      masm.cmpxchgptr(tmpReg, Address(objReg, 0));          // Uses EAX which is box
       masm.bind(DONE_LABEL);
     } else {
       Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
@@ -3536,12 +3531,12 @@
       if (UseBiasedLocking) {
          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
       }
-
-      masm.cmpl  (Address(boxReg, 0), 0) ;            // Examine the displaced header
-      masm.movl  (tmpReg, Address(objReg, 0)) ;       // Examine the object's markword
+      
+      masm.cmpptr(Address(boxReg, 0), 0) ;            // Examine the displaced header
+      masm.movptr(tmpReg, Address(objReg, 0)) ;       // Examine the object's markword
       masm.jccb  (Assembler::zero, DONE_LABEL) ;      // 0 indicates recursive stack-lock
 
-      masm.testl (tmpReg, 0x02) ;                     // Inflated?
+      masm.testptr(tmpReg, 0x02) ;                     // Inflated? 
       masm.jccb  (Assembler::zero, Stacked) ;
 
       masm.bind  (Inflated) ;
@@ -3571,11 +3566,8 @@
 
       masm.get_thread (boxReg) ;
       if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
-         // prefetchw [ebx + Offset(_owner)-2]
-         masm.emit_raw (0x0F) ;
-         masm.emit_raw (0x0D) ;
-         masm.emit_raw (0x4B) ;
-         masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
+        // prefetchw [ebx + Offset(_owner)-2]
+        masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
       }
 
       // Note that we could employ various encoding schemes to reduce
@@ -3584,22 +3576,22 @@
       // In practice the chain of fetches doesn't seem to impact performance, however.
       if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
          // Attempt to reduce branch density - AMD's branch predictor.
-         masm.xorl  (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-         masm.orl   (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
-         masm.orl   (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
-         masm.orl   (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
-         masm.jccb  (Assembler::notZero, DONE_LABEL) ;
-         masm.movl  (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
-         masm.jmpb  (DONE_LABEL) ;
-      } else {
-         masm.xorl  (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-         masm.orl   (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
-         masm.jccb  (Assembler::notZero, DONE_LABEL) ;
-         masm.movl  (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
-         masm.orl   (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
-         masm.jccb  (Assembler::notZero, CheckSucc) ;
-         masm.movl  (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
-         masm.jmpb  (DONE_LABEL) ;
+         masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
+         masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
+         masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
+         masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
+         masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
+         masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 
+         masm.jmpb  (DONE_LABEL) ; 
+      } else { 
+         masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
+         masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
+         masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
+         masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
+         masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
+         masm.jccb  (Assembler::notZero, CheckSucc) ; 
+         masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 
+         masm.jmpb  (DONE_LABEL) ; 
       }
 
       // The Following code fragment (EmitSync & 65536) improves the performance of
@@ -3615,9 +3607,9 @@
          masm.bind  (CheckSucc) ;
 
          // Optional pre-test ... it's safe to elide this
-         if ((EmitSync & 16) == 0) {
-            masm.cmpl  (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
-            masm.jccb  (Assembler::zero, LGoSlowPath) ;
+         if ((EmitSync & 16) == 0) { 
+            masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
+            masm.jccb  (Assembler::zero, LGoSlowPath) ; 
          }
 
          // We have a classic Dekker-style idiom:
@@ -3645,39 +3637,37 @@
          //
          // We currently use (3), although it's likely that switching to (2)
          // is correct for the future.
-
-         masm.movl  (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
-         if (os::is_MP()) {
-            if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
-              masm.emit_raw (0x0F) ;    // MFENCE ...
-              masm.emit_raw (0xAE) ;
-              masm.emit_raw (0xF0) ;
-            } else {
-              masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
+            
+         masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 
+         if (os::is_MP()) { 
+            if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 
+              masm.mfence();
+            } else { 
+              masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 
             }
          }
          // Ratify _succ remains non-null
-         masm.cmpl  (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
-         masm.jccb  (Assembler::notZero, LSuccess) ;
-
-         masm.xorl  (boxReg, boxReg) ;                  // box is really EAX
+         masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
+         masm.jccb  (Assembler::notZero, LSuccess) ; 
+
+         masm.xorptr(boxReg, boxReg) ;                  // box is really EAX
          if (os::is_MP()) { masm.lock(); }
-         masm.cmpxchg(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
+         masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
          masm.jccb  (Assembler::notEqual, LSuccess) ;
          // Since we're low on registers we installed rsp as a placeholding in _owner.
          // Now install Self over rsp.  This is safe as we're transitioning from
          // non-null to non=null
          masm.get_thread (boxReg) ;
-         masm.movl  (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
+         masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
          // Intentional fall-through into LGoSlowPath ...
 
-         masm.bind  (LGoSlowPath) ;
-         masm.orl   (boxReg, 1) ;                      // set ICC.ZF=0 to indicate failure
-         masm.jmpb  (DONE_LABEL) ;
-
-         masm.bind  (LSuccess) ;
-         masm.xorl  (boxReg, boxReg) ;                 // set ICC.ZF=1 to indicate success
-         masm.jmpb  (DONE_LABEL) ;
+         masm.bind  (LGoSlowPath) ; 
+         masm.orptr(boxReg, 1) ;                      // set ICC.ZF=0 to indicate failure
+         masm.jmpb  (DONE_LABEL) ; 
+
+         masm.bind  (LSuccess) ; 
+         masm.xorptr(boxReg, boxReg) ;                 // set ICC.ZF=1 to indicate success
+         masm.jmpb  (DONE_LABEL) ; 
       }
 
       masm.bind (Stacked) ;
@@ -3686,9 +3676,9 @@
       // Try to reset the header to displaced header.
       // The "box" value on the stack is stable, so we can reload
       // and be assured we observe the same value as above.
-      masm.movl (tmpReg, Address(boxReg, 0)) ;
+      masm.movptr(tmpReg, Address(boxReg, 0)) ;
       if (os::is_MP()) {   masm.lock();    }
-      masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box
+      masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
       // Intention fall-thru into DONE_LABEL
 
 
@@ -3720,12 +3710,12 @@
     int count_offset  = java_lang_String::count_offset_in_bytes();
     int base_offset   = arrayOopDesc::base_offset_in_bytes(T_CHAR);
 
-    masm.movl(rax, Address(rsi, value_offset));
+    masm.movptr(rax, Address(rsi, value_offset));
     masm.movl(rcx, Address(rsi, offset_offset));
-    masm.leal(rax, Address(rax, rcx, Address::times_2, base_offset));
-    masm.movl(rbx, Address(rdi, value_offset));
+    masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
+    masm.movptr(rbx, Address(rdi, value_offset));
     masm.movl(rcx, Address(rdi, offset_offset));
-    masm.leal(rbx, Address(rbx, rcx, Address::times_2, base_offset));
+    masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
 
     // Compute the minimum of the string lengths(rsi) and the
     // difference of the string lengths (stack)
@@ -3736,14 +3726,14 @@
       masm.movl(rsi, Address(rsi, count_offset));
       masm.movl(rcx, rdi);
       masm.subl(rdi, rsi);
-      masm.pushl(rdi);
+      masm.push(rdi);
       masm.cmovl(Assembler::lessEqual, rsi, rcx);
     } else {
       masm.movl(rdi, Address(rdi, count_offset));
       masm.movl(rcx, Address(rsi, count_offset));
       masm.movl(rsi, rdi);
       masm.subl(rdi, rcx);
-      masm.pushl(rdi);
+      masm.push(rdi);
       masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
       masm.movl(rsi, rcx);
       // rsi holds min, rcx is unused
@@ -3761,14 +3751,14 @@
     // Compare first characters
     masm.subl(rcx, rdi);
     masm.jcc(Assembler::notZero,  POP_LABEL);
-    masm.decrement(rsi);
+    masm.decrementl(rsi);
     masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
 
     {
       // Check after comparing first character to see if strings are equivalent
       Label LSkip2;
       // Check if the strings start at same location
-      masm.cmpl(rbx,rax);
+      masm.cmpptr(rbx,rax);
       masm.jcc(Assembler::notEqual, LSkip2);
 
       // Check if the length difference is zero (from stack)
@@ -3780,8 +3770,8 @@
     }
 
     // Shift rax, and rbx, to the end of the arrays, negate min
-    masm.leal(rax, Address(rax, rsi, Address::times_2, 2));
-    masm.leal(rbx, Address(rbx, rsi, Address::times_2, 2));
+    masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
+    masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
     masm.negl(rsi);
 
     // Compare the rest of the characters
@@ -3790,18 +3780,18 @@
     masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
     masm.subl(rcx, rdi);
     masm.jcc(Assembler::notZero, POP_LABEL);
-    masm.increment(rsi);
+    masm.incrementl(rsi);
     masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
 
     // Strings are equal up to min length.  Return the length difference.
     masm.bind(LENGTH_DIFF_LABEL);
-    masm.popl(rcx);
+    masm.pop(rcx);
     masm.jmp(DONE_LABEL);
 
     // Discard the stored length difference
     masm.bind(POP_LABEL);
-    masm.addl(rsp, 4);
-
+    masm.addptr(rsp, 4);
+       
     // That's it
     masm.bind(DONE_LABEL);
   %}
@@ -4315,7 +4305,8 @@
 
   enc_class enc_membar_volatile %{
     MacroAssembler masm(&cbuf);
-    masm.membar();
+    masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
+                                            Assembler::StoreStore));
   %}
 
   // Atomically load the volatile long
@@ -11151,7 +11142,7 @@
   format %{ "MOVD  $dst,$src\n\t"
             "CVTDQ2PD $dst,$dst\t# i2d" %}
   ins_encode %{
-    __ movd($dst$$XMMRegister, $src$$Register);
+    __ movdl($dst$$XMMRegister, $src$$Register);
     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
   %}
   ins_pipe(pipe_slow); // XXX
@@ -11249,7 +11240,7 @@
   format %{ "MOVD  $dst,$src\n\t"
             "CVTDQ2PS $dst,$dst\t# i2f" %}
   ins_encode %{
-    __ movd($dst$$XMMRegister, $src$$Register);
+    __ movdl($dst$$XMMRegister, $src$$Register);
     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
   %}
   ins_pipe(pipe_slow); // XXX
@@ -12262,7 +12253,7 @@
      "done:" %}
   ins_encode %{
     Label p_one, m_one, done;
-    __ xorl($dst$$Register, $dst$$Register);
+    __ xorptr($dst$$Register, $dst$$Register);
     __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
     __ jccb(Assembler::less,    m_one);
     __ jccb(Assembler::greater, p_one);
@@ -12270,10 +12261,10 @@
     __ jccb(Assembler::below,   m_one);
     __ jccb(Assembler::equal,   done);
     __ bind(p_one);
-    __ increment($dst$$Register);
+    __ incrementl($dst$$Register);
     __ jmpb(done);
     __ bind(m_one);
-    __ decrement($dst$$Register);
+    __ decrementl($dst$$Register);
     __ bind(done);
   %}
   ins_pipe( pipe_slow );
--- a/hotspot/src/cpu/x86/vm/x86_64.ad	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/x86_64.ad	Wed Jul 05 16:41:01 2017 +0200
@@ -478,7 +478,7 @@
 
 // Class for all int registers except RAX, RDX (and RSP)
 reg_class int_no_rax_rdx_reg(RBP,
-                             RDI
+                             RDI,
                              RSI,
                              RCX,
                              RBX,
@@ -552,7 +552,7 @@
 // This is a block of C++ code which provides values, functions, and
 // definitions necessary in the rest of the architecture description
 source %{
-#define   RELOC_IMM64    Assembler::imm64_operand
+#define   RELOC_IMM64    Assembler::imm_operand
 #define   RELOC_DISP32   Assembler::disp32_operand
 
 #define __ _masm.
@@ -962,11 +962,11 @@
   if (VerifyStackAtCalls) {
     Label L;
     MacroAssembler masm(&cbuf);
-    masm.pushq(rax);
-    masm.movq(rax, rsp);
-    masm.andq(rax, StackAlignmentInBytes-1);
-    masm.cmpq(rax, StackAlignmentInBytes-wordSize);
-    masm.popq(rax);
+    masm.push(rax);
+    masm.mov(rax, rsp);
+    masm.andptr(rax, StackAlignmentInBytes-1);
+    masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
+    masm.pop(rax);
     masm.jcc(Assembler::equal, L);
     masm.stop("Stack is not properly aligned!");
     masm.bind(L);
@@ -1817,6 +1817,7 @@
   __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
   // static stub relocation also tags the methodOop in the code-stream.
   __ movoop(rbx, (jobject) NULL);  // method is zapped till fixup time
+  // This is recognized as unresolved by relocs/nativeinst/ic code
   __ jump(RuntimeAddress(__ pc()));
 
   // Update current stubs pointer and restore code_end.
@@ -1863,9 +1864,9 @@
 #endif
   if (UseCompressedOops) {
     masm.load_klass(rscratch1, j_rarg0);
-    masm.cmpq(rax, rscratch1);
+    masm.cmpptr(rax, rscratch1);
   } else {
-    masm.cmpq(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
+    masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
   }
 
   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
@@ -1949,7 +1950,7 @@
   __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
   __ bind(next);
   // adjust it so it matches "the_pc"
-  __ subq(Address(rsp, 0), __ offset() - offset);
+  __ subptr(Address(rsp, 0), __ offset() - offset);
   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
   __ end_a_stub();
@@ -2577,23 +2578,23 @@
     // Compare super with sub directly, since super is not in its own SSA.
     // The compiler used to emit this test, but we fold it in here,
     // to allow platform-specific tweaking on sparc.
-    __ cmpq(Rrax, Rrsi);
+    __ cmpptr(Rrax, Rrsi);
     __ jcc(Assembler::equal, hit);
 #ifndef PRODUCT
     __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
     __ incrementl(Address(Rrcx, 0));
 #endif //PRODUCT
-    __ movq(Rrdi, Address(Rrsi,
-                          sizeof(oopDesc) +
+    __ movptr(Rrdi, Address(Rrsi, 
+                          sizeof(oopDesc) + 
                           Klass::secondary_supers_offset_in_bytes()));
     __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
-    __ addq(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+    __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
     if (UseCompressedOops) {
       __ encode_heap_oop(Rrax);
       __ repne_scanl();
       __ jcc(Assembler::notEqual, cmiss);
       __ decode_heap_oop(Rrax);
-      __ movq(Address(Rrsi,
+      __ movptr(Address(Rrsi,
                       sizeof(oopDesc) +
                       Klass::secondary_super_cache_offset_in_bytes()),
               Rrax);
@@ -2602,16 +2603,16 @@
       __ decode_heap_oop(Rrax);
       __ jmp(miss);
     } else {
-      __ repne_scanq();
+      __ repne_scan();
       __ jcc(Assembler::notEqual, miss);
-      __ movq(Address(Rrsi,
+      __ movptr(Address(Rrsi,
                       sizeof(oopDesc) +
                       Klass::secondary_super_cache_offset_in_bytes()),
               Rrax);
     }
     __ bind(hit);
     if ($primary) {
-      __ xorq(Rrdi, Rrdi);
+      __ xorptr(Rrdi, Rrdi);
     }
     __ bind(miss);
   %}
@@ -3527,8 +3528,9 @@
       masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
     }
     if (EmitSync & 1) {
-        masm.movptr (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
-        masm.cmpq   (rsp, 0) ;
+        // Without cast to int32_t a movptr will destroy r10 which is typically obj
+        masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; 
+        masm.cmpptr(rsp, (int32_t)NULL_WORD) ; 
     } else
     if (EmitSync & 2) {
         Label DONE_LABEL;
@@ -3536,29 +3538,30 @@
            // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
           masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
         }
-        masm.movl(tmpReg, 0x1);
-        masm.orq(tmpReg, Address(objReg, 0));
-        masm.movq(Address(boxReg, 0), tmpReg);
+        // QQQ was movl...
+        masm.movptr(tmpReg, 0x1);
+        masm.orptr(tmpReg, Address(objReg, 0));
+        masm.movptr(Address(boxReg, 0), tmpReg);
         if (os::is_MP()) {
           masm.lock();
         }
-        masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg
+        masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
         masm.jcc(Assembler::equal, DONE_LABEL);
 
         // Recursive locking
-        masm.subq(tmpReg, rsp);
-        masm.andq(tmpReg, 7 - os::vm_page_size());
-        masm.movq(Address(boxReg, 0), tmpReg);
+        masm.subptr(tmpReg, rsp);
+        masm.andptr(tmpReg, 7 - os::vm_page_size());
+        masm.movptr(Address(boxReg, 0), tmpReg);
 
         masm.bind(DONE_LABEL);
         masm.nop(); // avoid branch to branch
     } else {
         Label DONE_LABEL, IsInflated, Egress;
 
-        masm.movq  (tmpReg, Address(objReg, 0)) ;
-        masm.testq (tmpReg, 0x02) ;         // inflated vs stack-locked|neutral|biased
-        masm.jcc   (Assembler::notZero, IsInflated) ;
-
+        masm.movptr(tmpReg, Address(objReg, 0)) ; 
+        masm.testl (tmpReg, 0x02) ;         // inflated vs stack-locked|neutral|biased
+        masm.jcc   (Assembler::notZero, IsInflated) ; 
+         
         // it's stack-locked, biased or neutral
         // TODO: optimize markword triage order to reduce the number of
         // conditional branches in the most common cases.
@@ -3568,13 +3571,14 @@
 
         if (UseBiasedLocking) {
           masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
-          masm.movq  (tmpReg, Address(objReg, 0)) ;        // [FETCH]
+          masm.movptr(tmpReg, Address(objReg, 0)) ;        // [FETCH]
         }
 
-        masm.orq   (tmpReg, 1) ;
-        masm.movq  (Address(boxReg, 0), tmpReg) ;
-        if (os::is_MP()) { masm.lock(); }
-        masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg
+        // was q will it destroy high?
+        masm.orl   (tmpReg, 1) ; 
+        masm.movptr(Address(boxReg, 0), tmpReg) ;  
+        if (os::is_MP()) { masm.lock(); } 
+        masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
         if (_counters != NULL) {
            masm.cond_inc32(Assembler::equal,
                            ExternalAddress((address) _counters->fast_path_entry_count_addr()));
@@ -3582,9 +3586,9 @@
         masm.jcc   (Assembler::equal, DONE_LABEL);
 
         // Recursive locking
-        masm.subq  (tmpReg, rsp);
-        masm.andq  (tmpReg, 7 - os::vm_page_size());
-        masm.movq  (Address(boxReg, 0), tmpReg);
+        masm.subptr(tmpReg, rsp);
+        masm.andptr(tmpReg, 7 - os::vm_page_size());
+        masm.movptr(Address(boxReg, 0), tmpReg);
         if (_counters != NULL) {
            masm.cond_inc32(Assembler::equal,
                            ExternalAddress((address) _counters->fast_path_entry_count_addr()));
@@ -3599,16 +3603,17 @@
         // We should also think about trying a CAS without having
         // fetched _owner.  If the CAS is successful we may
         // avoid an RTO->RTS upgrade on the $line.
-        masm.movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
-
-        masm.movq  (boxReg, tmpReg) ;
-        masm.movq  (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-        masm.testq (tmpReg, tmpReg) ;
-        masm.jcc   (Assembler::notZero, DONE_LABEL) ;
+        // Without cast to int32_t a movptr will destroy r10 which is typically obj
+        masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; 
+
+        masm.mov    (boxReg, tmpReg) ; 
+        masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
+        masm.testptr(tmpReg, tmpReg) ;   
+        masm.jcc    (Assembler::notZero, DONE_LABEL) ; 
 
         // It's inflated and appears unlocked
-        if (os::is_MP()) { masm.lock(); }
-        masm.cmpxchgq(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
+        if (os::is_MP()) { masm.lock(); } 
+        masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
         // Intentional fall-through into DONE_LABEL ...
 
         masm.bind  (DONE_LABEL) ;
@@ -3627,8 +3632,8 @@
     Register tmpReg = as_Register($tmp$$reg);
     MacroAssembler masm(&cbuf);
 
-    if (EmitSync & 4) {
-       masm.cmpq  (rsp, 0) ;
+    if (EmitSync & 4) { 
+       masm.cmpptr(rsp, 0) ; 
     } else
     if (EmitSync & 8) {
        Label DONE_LABEL;
@@ -3638,15 +3643,15 @@
 
        // Check whether the displaced header is 0
        //(=> recursive unlock)
-       masm.movq(tmpReg, Address(boxReg, 0));
-       masm.testq(tmpReg, tmpReg);
+       masm.movptr(tmpReg, Address(boxReg, 0));
+       masm.testptr(tmpReg, tmpReg);
        masm.jcc(Assembler::zero, DONE_LABEL);
 
        // If not recursive lock, reset the header to displaced header
        if (os::is_MP()) {
          masm.lock();
        }
-       masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box
+       masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
        masm.bind(DONE_LABEL);
        masm.nop(); // avoid branch to branch
     } else {
@@ -3655,44 +3660,44 @@
        if (UseBiasedLocking) {
          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
        }
-
-       masm.movq  (tmpReg, Address(objReg, 0)) ;
-       masm.cmpq  (Address(boxReg, 0), (int)NULL_WORD) ;
-       masm.jcc   (Assembler::zero, DONE_LABEL) ;
-       masm.testq (tmpReg, 0x02) ;
-       masm.jcc   (Assembler::zero, Stacked) ;
-
+        
+       masm.movptr(tmpReg, Address(objReg, 0)) ; 
+       masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; 
+       masm.jcc   (Assembler::zero, DONE_LABEL) ; 
+       masm.testl (tmpReg, 0x02) ; 
+       masm.jcc   (Assembler::zero, Stacked) ; 
+        
        // It's inflated
-       masm.movq  (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
-       masm.xorq  (boxReg, r15_thread) ;
-       masm.orq   (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
-       masm.jcc   (Assembler::notZero, DONE_LABEL) ;
-       masm.movq  (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
-       masm.orq   (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
-       masm.jcc   (Assembler::notZero, CheckSucc) ;
-       masm.mov64 (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
-       masm.jmp   (DONE_LABEL) ;
-
-       if ((EmitSync & 65536) == 0) {
+       masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
+       masm.xorptr(boxReg, r15_thread) ; 
+       masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 
+       masm.jcc   (Assembler::notZero, DONE_LABEL) ; 
+       masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
+       masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
+       masm.jcc   (Assembler::notZero, CheckSucc) ; 
+       masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; 
+       masm.jmp   (DONE_LABEL) ; 
+        
+       if ((EmitSync & 65536) == 0) { 
          Label LSuccess, LGoSlowPath ;
          masm.bind  (CheckSucc) ;
-         masm.cmpq  (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
+         masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
          masm.jcc   (Assembler::zero, LGoSlowPath) ;
 
          // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
          // the explicit ST;MEMBAR combination, but masm doesn't currently support
          // "ANDQ M,IMM".  Don't use MFENCE here.  lock:add to TOS, xchg, etc
          // are all faster when the write buffer is populated.
-         masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
+         masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
          if (os::is_MP()) {
-            masm.lock () ; masm.addq (Address(rsp, 0), 0) ;
+            masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
          }
-         masm.cmpq  (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
+         masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
          masm.jcc   (Assembler::notZero, LSuccess) ;
 
-         masm.movptr (boxReg, (int)NULL_WORD) ;                   // box is really EAX
+         masm.movptr (boxReg, (int32_t)NULL_WORD) ;                   // box is really EAX
          if (os::is_MP()) { masm.lock(); }
-         masm.cmpxchgq (r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
+         masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
          masm.jcc   (Assembler::notEqual, LSuccess) ;
          // Intentional fall-through into slow-path
 
@@ -3705,10 +3710,10 @@
          masm.jmp   (DONE_LABEL) ;
        }
 
-       masm.bind  (Stacked) ;
-       masm.movq  (tmpReg, Address (boxReg, 0)) ;      // re-fetch
-       if (os::is_MP()) { masm.lock(); }
-       masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box
+       masm.bind  (Stacked) ; 
+       masm.movptr(tmpReg, Address (boxReg, 0)) ;      // re-fetch
+       if (os::is_MP()) { masm.lock(); } 
+       masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
 
        if (EmitSync & 65536) {
           masm.bind (CheckSucc) ;
@@ -3736,10 +3741,10 @@
 
     masm.load_heap_oop(rax, Address(rsi, value_offset));
     masm.movl(rcx, Address(rsi, offset_offset));
-    masm.leaq(rax, Address(rax, rcx, Address::times_2, base_offset));
+    masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
     masm.load_heap_oop(rbx, Address(rdi, value_offset));
     masm.movl(rcx, Address(rdi, offset_offset));
-    masm.leaq(rbx, Address(rbx, rcx, Address::times_2, base_offset));
+    masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
 
     // Compute the minimum of the string lengths(rsi) and the
     // difference of the string lengths (stack)
@@ -3748,8 +3753,8 @@
     masm.movl(rsi, Address(rsi, count_offset));
     masm.movl(rcx, rdi);
     masm.subl(rdi, rsi);
-    masm.pushq(rdi);
-    masm.cmovl(Assembler::lessEqual, rsi, rcx);
+    masm.push(rdi);
+    masm.cmov(Assembler::lessEqual, rsi, rcx);
 
     // Is the minimum length zero?
     masm.bind(RCX_GOOD_LABEL);
@@ -3770,7 +3775,7 @@
       // Check after comparing first character to see if strings are equivalent
       Label LSkip2;
       // Check if the strings start at same location
-      masm.cmpq(rbx, rax);
+      masm.cmpptr(rbx, rax);
       masm.jcc(Assembler::notEqual, LSkip2);
 
       // Check if the length difference is zero (from stack)
@@ -3782,9 +3787,9 @@
     }
 
     // Shift RAX and RBX to the end of the arrays, negate min
-    masm.leaq(rax, Address(rax, rsi, Address::times_2, 2));
-    masm.leaq(rbx, Address(rbx, rsi, Address::times_2, 2));
-    masm.negq(rsi);
+    masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
+    masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
+    masm.negptr(rsi);
 
     // Compare the rest of the characters
     masm.bind(WHILE_HEAD_LABEL);
@@ -3792,18 +3797,18 @@
     masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
     masm.subl(rcx, rdi);
     masm.jcc(Assembler::notZero, POP_LABEL);
-    masm.incrementq(rsi);
+    masm.increment(rsi);
     masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
 
     // Strings are equal up to min length.  Return the length difference.
     masm.bind(LENGTH_DIFF_LABEL);
-    masm.popq(rcx);
+    masm.pop(rcx);
     masm.jmp(DONE_LABEL);
 
     // Discard the stored length difference
     masm.bind(POP_LABEL);
-    masm.addq(rsp, 8);
-
+    masm.addptr(rsp, 8);
+       
     // That's it
     masm.bind(DONE_LABEL);
   %}
@@ -3893,7 +3898,7 @@
   enc_class absF_encoding(regF dst)
   %{
     int dstenc = $dst$$reg;
-    address signmask_address = (address) StubRoutines::amd64::float_sign_mask();
+    address signmask_address = (address) StubRoutines::x86::float_sign_mask();
 
     cbuf.set_inst_mark();
     if (dstenc >= 8) {
@@ -3910,7 +3915,7 @@
   enc_class absD_encoding(regD dst)
   %{
     int dstenc = $dst$$reg;
-    address signmask_address = (address) StubRoutines::amd64::double_sign_mask();
+    address signmask_address = (address) StubRoutines::x86::double_sign_mask();
 
     cbuf.set_inst_mark();
     emit_opcode(cbuf, 0x66);
@@ -3928,7 +3933,7 @@
   enc_class negF_encoding(regF dst)
   %{
     int dstenc = $dst$$reg;
-    address signflip_address = (address) StubRoutines::amd64::float_sign_flip();
+    address signflip_address = (address) StubRoutines::x86::float_sign_flip();
 
     cbuf.set_inst_mark();
     if (dstenc >= 8) {
@@ -3945,7 +3950,7 @@
   enc_class negD_encoding(regD dst)
   %{
     int dstenc = $dst$$reg;
-    address signflip_address = (address) StubRoutines::amd64::double_sign_flip();
+    address signflip_address = (address) StubRoutines::x86::double_sign_flip();
 
     cbuf.set_inst_mark();
     emit_opcode(cbuf, 0x66);
@@ -4003,7 +4008,7 @@
     emit_opcode(cbuf, 0xE8);
     emit_d32_reloc(cbuf,
                    (int)
-                   (StubRoutines::amd64::f2i_fixup() - cbuf.code_end() - 4),
+                   (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4),
                    runtime_call_Relocation::spec(),
                    RELOC_DISP32);
 
@@ -4020,7 +4025,7 @@
   %{
     int dstenc = $dst$$reg;
     int srcenc = $src$$reg;
-    address const_address = (address) StubRoutines::amd64::double_sign_flip();
+    address const_address = (address) StubRoutines::x86::double_sign_flip();
 
     // cmpq $dst, [0x8000000000000000]
     cbuf.set_inst_mark();
@@ -4061,7 +4066,7 @@
     emit_opcode(cbuf, 0xE8);
     emit_d32_reloc(cbuf,
                    (int)
-                   (StubRoutines::amd64::f2l_fixup() - cbuf.code_end() - 4),
+                   (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4),
                    runtime_call_Relocation::spec(),
                    RELOC_DISP32);
 
@@ -4117,7 +4122,7 @@
     emit_opcode(cbuf, 0xE8);
     emit_d32_reloc(cbuf,
                    (int)
-                   (StubRoutines::amd64::d2i_fixup() - cbuf.code_end() - 4),
+                   (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4),
                    runtime_call_Relocation::spec(),
                    RELOC_DISP32);
 
@@ -4134,7 +4139,7 @@
   %{
     int dstenc = $dst$$reg;
     int srcenc = $src$$reg;
-    address const_address = (address) StubRoutines::amd64::double_sign_flip();
+    address const_address = (address) StubRoutines::x86::double_sign_flip();
 
     // cmpq $dst, [0x8000000000000000]
     cbuf.set_inst_mark();
@@ -4175,7 +4180,7 @@
     emit_opcode(cbuf, 0xE8);
     emit_d32_reloc(cbuf,
                    (int)
-                   (StubRoutines::amd64::d2l_fixup() - cbuf.code_end() - 4),
+                   (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4),
                    runtime_call_Relocation::spec(),
                    RELOC_DISP32);
 
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/os_cpu/linux_x86/vm/assembler_linux_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,84 @@
+/*
+ * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_linux_x86.cpp.incl"
+
+#ifndef _LP64
+void MacroAssembler::int3() {
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+}
+
+void MacroAssembler::get_thread(Register thread) {
+  movl(thread, rsp);
+  shrl(thread, PAGE_SHIFT);
+
+  ExternalAddress tls_base((address)ThreadLocalStorage::sp_map_addr());
+  Address index(noreg, thread, Address::times_4);
+  ArrayAddress tls(tls_base, index);
+
+  movptr(thread, tls);
+}
+#else
+void MacroAssembler::int3() {
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+}
+
+void MacroAssembler::get_thread(Register thread) {
+  // call pthread_getspecific
+  // void * pthread_getspecific(pthread_key_t key);
+   if (thread != rax) {
+     push(rax);
+   }
+   push(rdi);
+   push(rsi);
+   push(rdx);
+   push(rcx);
+   push(r8);
+   push(r9);
+   push(r10);
+   // XXX
+   mov(r10, rsp);
+   andq(rsp, -16);
+   push(r10);
+   push(r11);
+
+   movl(rdi, ThreadLocalStorage::thread_index());
+   call(RuntimeAddress(CAST_FROM_FN_PTR(address, pthread_getspecific)));
+
+   pop(r11);
+   pop(rsp);
+   pop(r10);
+   pop(r9);
+   pop(r8);
+   pop(rcx);
+   pop(rdx);
+   pop(rsi);
+   pop(rdi);
+   if (thread != rax) {
+       mov(thread, rax);
+       pop(rax);
+   }
+}
+#endif
--- a/hotspot/src/os_cpu/linux_x86/vm/assembler_linux_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/*
- * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_linux_x86_32.cpp.incl"
-
-void MacroAssembler::int3() {
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-void MacroAssembler::get_thread(Register thread) {
-  movl(thread, rsp);
-  shrl(thread, PAGE_SHIFT);
-
-  ExternalAddress tls_base((address)ThreadLocalStorage::sp_map_addr());
-  Address index(noreg, thread, Address::times_4);
-  ArrayAddress tls(tls_base, index);
-
-  movptr(thread, tls);
-}
--- a/hotspot/src/os_cpu/linux_x86/vm/assembler_linux_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/*
- * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_linux_x86_64.cpp.incl"
-
-void MacroAssembler::int3() {
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-void MacroAssembler::get_thread(Register thread) {
-  // call pthread_getspecific
-  // void * pthread_getspecific(pthread_key_t key);
-   if (thread != rax) {
-     pushq(rax);
-   }
-   pushq(rdi);
-   pushq(rsi);
-   pushq(rdx);
-   pushq(rcx);
-   pushq(r8);
-   pushq(r9);
-   pushq(r10);
-   // XXX
-   movq(r10, rsp);
-   andq(rsp, -16);
-   pushq(r10);
-   pushq(r11);
-
-   movl(rdi, ThreadLocalStorage::thread_index());
-   call(RuntimeAddress(CAST_FROM_FN_PTR(address, pthread_getspecific)));
-
-   popq(r11);
-   popq(rsp);
-   popq(r10);
-   popq(r9);
-   popq(r8);
-   popq(rcx);
-   popq(rdx);
-   popq(rsi);
-   popq(rdi);
-   if (thread != rax) {
-       movq(thread, rax);
-       popq(rax);
-   }
-}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/os_cpu/solaris_x86/vm/assembler_solaris_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,133 @@
+/*
+ * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_solaris_x86.cpp.incl"
+
+
+void MacroAssembler::int3() {
+  push(rax);
+  push(rdx);
+  push(rcx);
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+  pop(rcx);
+  pop(rdx);
+  pop(rax);
+}
+
+#define __  _masm->
+#ifndef _LP64
+static void slow_call_thr_specific(MacroAssembler* _masm, Register thread) {
+
+  // slow call to of thr_getspecific
+  // int thr_getspecific(thread_key_t key, void **value);
+  // Consider using pthread_getspecific instead.
+
+__  push(0);                                                            // allocate space for return value
+  if (thread != rax) __ push(rax);                                      // save rax, if caller still wants it
+__  push(rcx);                                                          // save caller save
+__  push(rdx);                                                          // save caller save
+  if (thread != rax) {
+__    lea(thread, Address(rsp, 3 * sizeof(int)));                       // address of return value
+  } else {
+__    lea(thread, Address(rsp, 2 * sizeof(int)));                       // address of return value
+  }
+__  push(thread);                                                       // and pass the address
+__  push(ThreadLocalStorage::thread_index());                           // the key
+__  call(RuntimeAddress(CAST_FROM_FN_PTR(address, thr_getspecific)));
+__  increment(rsp, 2 * wordSize);
+__  pop(rdx);
+__  pop(rcx);
+  if (thread != rax) __ pop(rax);
+__  pop(thread);
+
+}
+#else
+static void slow_call_thr_specific(MacroAssembler* _masm, Register thread) {
+  // slow call to of thr_getspecific
+  // int thr_getspecific(thread_key_t key, void **value);
+  // Consider using pthread_getspecific instead.
+
+  if (thread != rax) {
+__    push(rax);
+  }
+__  push(0); // space for return value
+__  push(rdi);
+__  push(rsi);
+__  lea(rsi, Address(rsp, 16)); // pass return value address
+__  push(rdx);
+__  push(rcx);
+__  push(r8);
+__  push(r9);
+__  push(r10);
+  // XXX
+__  mov(r10, rsp);
+__  andptr(rsp, -16);
+__  push(r10);
+__  push(r11);
+
+__  movl(rdi, ThreadLocalStorage::thread_index());
+__  call(RuntimeAddress(CAST_FROM_FN_PTR(address, thr_getspecific)));
+
+__  pop(r11);
+__  pop(rsp);
+__  pop(r10);
+__  pop(r9);
+__  pop(r8);
+__  pop(rcx);
+__  pop(rdx);
+__  pop(rsi);
+__  pop(rdi);
+__  pop(thread); // load return value
+  if (thread != rax) {
+__    pop(rax);
+  }
+}
+#endif //LP64
+
+void MacroAssembler::get_thread(Register thread) {
+
+  int segment = NOT_LP64(Assembler::GS_segment) LP64_ONLY(Assembler::FS_segment);
+  // Try to emit a Solaris-specific fast TSD/TLS accessor.
+  ThreadLocalStorage::pd_tlsAccessMode tlsMode = ThreadLocalStorage::pd_getTlsAccessMode ();
+  if (tlsMode == ThreadLocalStorage::pd_tlsAccessIndirect) {            // T1
+     // Use thread as a temporary: mov r, gs:[0]; mov r, [r+tlsOffset]
+     emit_byte (segment);
+     // ExternalAddress doesn't work because it can't take NULL
+     AddressLiteral null(0, relocInfo::none);
+     movptr (thread, null);
+     movptr(thread, Address(thread, ThreadLocalStorage::pd_getTlsOffset())) ;
+     return ;
+  } else
+  if (tlsMode == ThreadLocalStorage::pd_tlsAccessDirect) {              // T2
+     // mov r, gs:[tlsOffset]
+     emit_byte (segment);
+     AddressLiteral tls_off((address)ThreadLocalStorage::pd_getTlsOffset(), relocInfo::none);
+     movptr (thread, tls_off);
+     return ;
+  }
+
+  slow_call_thr_specific(this, thread);
+
+}
--- a/hotspot/src/os_cpu/solaris_x86/vm/assembler_solaris_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/*
- * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_solaris_x86_32.cpp.incl"
-
-
-void MacroAssembler::int3() {
-  pushl(rax);
-  pushl(rdx);
-  pushl(rcx);
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-  popl(rcx);
-  popl(rdx);
-  popl(rax);
-}
-
-void MacroAssembler::get_thread(Register thread) {
-
-  // Try to emit a Solaris-specific fast TSD/TLS accessor.
-  ThreadLocalStorage::pd_tlsAccessMode tlsMode = ThreadLocalStorage::pd_getTlsAccessMode () ;
-  if (tlsMode == ThreadLocalStorage::pd_tlsAccessIndirect) {            // T1
-     // Use thread as a temporary: mov r, gs:[0]; mov r, [r+tlsOffset]
-     emit_byte (Assembler::GS_segment) ;
-     // ExternalAddress doesn't work because it can't take NULL
-     AddressLiteral null(0, relocInfo::none);
-     movptr (thread, null);
-     movl (thread, Address(thread, ThreadLocalStorage::pd_getTlsOffset())) ;
-     return ;
-  } else
-  if (tlsMode == ThreadLocalStorage::pd_tlsAccessDirect) {              // T2
-     // mov r, gs:[tlsOffset]
-     emit_byte (Assembler::GS_segment) ;
-     AddressLiteral tls((address)ThreadLocalStorage::pd_getTlsOffset(), relocInfo::none);
-     movptr (thread, tls);
-     return ;
-  }
-
-  // slow call to of thr_getspecific
-  // int thr_getspecific(thread_key_t key, void **value);
-  // Consider using pthread_getspecific instead.
-
-  pushl(0);                                                             // allocate space for return value
-  if (thread != rax) pushl(rax);                                        // save rax, if caller still wants it
-  pushl(rcx);                                                           // save caller save
-  pushl(rdx);                                                           // save caller save
-  if (thread != rax) {
-    leal(thread, Address(rsp, 3 * sizeof(int)));                        // address of return value
-  } else {
-    leal(thread, Address(rsp, 2 * sizeof(int)));                        // address of return value
-  }
-  pushl(thread);                                                        // and pass the address
-  pushl(ThreadLocalStorage::thread_index());                            // the key
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, thr_getspecific)));
-  increment(rsp, 2 * wordSize);
-  popl(rdx);
-  popl(rcx);
-  if (thread != rax) popl(rax);
-  popl(thread);
-}
--- a/hotspot/src/os_cpu/solaris_x86/vm/assembler_solaris_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-/*
- * Copyright 2004-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_solaris_x86_64.cpp.incl"
-
-void MacroAssembler::int3() {
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-void MacroAssembler::get_thread(Register thread) {
-  // Try to emit a Solaris-specific fast TSD/TLS accessor.
-  ThreadLocalStorage::pd_tlsAccessMode tlsMode = ThreadLocalStorage::pd_getTlsAccessMode();
-  if (tlsMode == ThreadLocalStorage::pd_tlsAccessIndirect) {            // T1
-    // Use thread as a temporary: mov r, fs:[0]; mov r, [r+tlsOffset]
-    emit_byte(Assembler::FS_segment);
-    movq(thread, Address(NULL, relocInfo::none));
-    movq(thread, Address(thread, ThreadLocalStorage::pd_getTlsOffset()));
-    return;
-  } else if (tlsMode == ThreadLocalStorage::pd_tlsAccessDirect) {       // T2
-    // mov r, fs:[tlsOffset]
-    emit_byte(Assembler::FS_segment);
-    ExternalAddress tls_off((address) ThreadLocalStorage::pd_getTlsOffset());
-    movptr(thread, tls_off);
-    return;
-  }
-
-  // slow call to of thr_getspecific
-  // int thr_getspecific(thread_key_t key, void **value);
-  // Consider using pthread_getspecific instead.
-
-  if (thread != rax) {
-    pushq(rax);
-  }
-  pushq(0); // space for return value
-  pushq(rdi);
-  pushq(rsi);
-  leaq(rsi, Address(rsp, 16)); // pass return value address
-  pushq(rdx);
-  pushq(rcx);
-  pushq(r8);
-  pushq(r9);
-  pushq(r10);
-  // XXX
-  movq(r10, rsp);
-  andq(rsp, -16);
-  pushq(r10);
-  pushq(r11);
-
-  movl(rdi, ThreadLocalStorage::thread_index());
-  call(RuntimeAddress(CAST_FROM_FN_PTR(address, thr_getspecific)));
-
-  popq(r11);
-  popq(rsp);
-  popq(r10);
-  popq(r9);
-  popq(r8);
-  popq(rcx);
-  popq(rdx);
-  popq(rsi);
-  popq(rdi);
-  popq(thread); // load return value
-  if (thread != rax) {
-    popq(rax);
-  }
-}
--- a/hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_32.ad	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_32.ad	Wed Jul 05 16:41:01 2017 +0200
@@ -62,13 +62,13 @@
   enc_class solaris_breakpoint  %{
     MacroAssembler* masm = new MacroAssembler(&cbuf);
     // Really need to fix this
-    masm->pushl(rax);
-    masm->pushl(rcx);
-    masm->pushl(rdx);
+    masm->push(rax);
+    masm->push(rcx);
+    masm->push(rdx);
     masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-    masm->popl(rdx);
-    masm->popl(rcx);
-    masm->popl(rax);
+    masm->pop(rdx);
+    masm->pop(rcx);
+    masm->pop(rax);
   %}
 
   enc_class call_epilog %{
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/os_cpu/windows_x86/vm/assembler_windows_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,98 @@
+/*
+ * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_windows_x86.cpp.incl"
+
+
+void MacroAssembler::int3() {
+  emit_byte(0xCC);
+}
+
+#ifndef _LP64
+//  The current scheme to accelerate access to the thread
+//  pointer is to store the current thread in the os_exception_wrapper
+//  and reference the current thread from stubs and compiled code
+//  via the FS register.  FS[0] contains a pointer to the structured
+//  exception block which is actually a stack address.  The first time
+//  we call the os exception wrapper, we calculate and store the
+//  offset from this exception block and use that offset here.
+//
+//  The last mechanism we used was problematic in that the
+//  the offset we had hard coded in the VM kept changing as Microsoft
+//  evolved the OS.
+//
+// Warning: This mechanism assumes that we only attempt to get the
+//          thread when we are nested below a call wrapper.
+//
+// movl reg, fs:[0]                        Get exeception pointer
+// movl reg, [reg + thread_ptr_offset]     Load thread
+//
+void MacroAssembler::get_thread(Register thread) {
+  // can't use ExternalAddress because it can't take NULL
+  AddressLiteral null(0, relocInfo::none);
+
+  prefix(FS_segment);
+  movptr(thread, null);
+  assert(ThreadLocalStorage::get_thread_ptr_offset() != 0,
+         "Thread Pointer Offset has not been initialized");
+  movl(thread, Address(thread, ThreadLocalStorage::get_thread_ptr_offset()));
+}
+#else
+// call (Thread*)TlsGetValue(thread_index());
+void MacroAssembler::get_thread(Register thread) {
+   if (thread != rax) {
+     push(rax);
+   }
+   push(rdi);
+   push(rsi);
+   push(rdx);
+   push(rcx);
+   push(r8);
+   push(r9);
+   push(r10);
+   // XXX
+   mov(r10, rsp);
+   andq(rsp, -16);
+   push(r10);
+   push(r11);
+
+   movl(c_rarg0, ThreadLocalStorage::thread_index());
+   call(RuntimeAddress((address)TlsGetValue));
+
+   pop(r11);
+   pop(rsp);
+   pop(r10);
+   pop(r9);
+   pop(r8);
+   pop(rcx);
+   pop(rdx);
+   pop(rsi);
+   pop(rdi);
+   if (thread != rax) {
+       mov(thread, rax);
+       pop(rax);
+   }
+}
+#endif
--- a/hotspot/src/os_cpu/windows_x86/vm/assembler_windows_x86_32.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/*
- * Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_windows_x86_32.cpp.incl"
-
-
-void MacroAssembler::int3() {
-  emit_byte(0xCC);
-}
-
-//  The current scheme to accelerate access to the thread
-//  pointer is to store the current thread in the os_exception_wrapper
-//  and reference the current thread from stubs and compiled code
-//  via the FS register.  FS[0] contains a pointer to the structured
-//  exception block which is actually a stack address.  The first time
-//  we call the os exception wrapper, we calculate and store the
-//  offset from this exception block and use that offset here.
-//
-//  The last mechanism we used was problematic in that the
-//  the offset we had hard coded in the VM kept changing as Microsoft
-//  evolved the OS.
-//
-// Warning: This mechanism assumes that we only attempt to get the
-//          thread when we are nested below a call wrapper.
-//
-// movl reg, fs:[0]                        Get exeception pointer
-// movl reg, [reg + thread_ptr_offset]     Load thread
-//
-void MacroAssembler::get_thread(Register thread) {
-  // can't use ExternalAddress because it can't take NULL
-  AddressLiteral null(0, relocInfo::none);
-
-  prefix(FS_segment);
-  movptr(thread, null);
-  assert(ThreadLocalStorage::get_thread_ptr_offset() != 0,
-         "Thread Pointer Offset has not been initialized");
-  movl(thread, Address(thread, ThreadLocalStorage::get_thread_ptr_offset()));
-}
--- a/hotspot/src/os_cpu/windows_x86/vm/assembler_windows_x86_64.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/*
- * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_windows_x86_64.cpp.incl"
-
-
-void MacroAssembler::int3() {
-  emit_byte(0xCC);
-}
-
-// call (Thread*)TlsGetValue(thread_index());
-void MacroAssembler::get_thread(Register thread) {
-   if (thread != rax) {
-     pushq(rax);
-   }
-   pushq(rdi);
-   pushq(rsi);
-   pushq(rdx);
-   pushq(rcx);
-   pushq(r8);
-   pushq(r9);
-   pushq(r10);
-   // XXX
-   movq(r10, rsp);
-   andq(rsp, -16);
-   pushq(r10);
-   pushq(r11);
-
-   movl(c_rarg0, ThreadLocalStorage::thread_index());
-   call(RuntimeAddress((address)TlsGetValue));
-
-   popq(r11);
-   popq(rsp);
-   popq(r10);
-   popq(r9);
-   popq(r8);
-   popq(rcx);
-   popq(rdx);
-   popq(rsi);
-   popq(rdi);
-   if (thread != rax) {
-       movq(thread, rax);
-       popq(rax);
-   }
-}
--- a/hotspot/src/os_cpu/windows_x86/vm/os_windows_x86.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/os_cpu/windows_x86/vm/os_windows_x86.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -369,7 +369,7 @@
   // apparently _asm not supported on windows amd64
   typedef intptr_t*      get_fp_func           ();
   get_fp_func* func = CAST_TO_FN_PTR(get_fp_func*,
-                                     StubRoutines::amd64::get_previous_fp_entry());
+                                     StubRoutines::x86::get_previous_fp_entry());
   if (func == NULL) return frame(NULL, NULL, NULL);
   intptr_t* fp = (*func)();
 #else
--- a/hotspot/src/share/vm/adlc/output_h.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/adlc/output_h.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1848,6 +1848,19 @@
       fprintf(fp,"  const Type            *bottom_type() const { const Type *t = in(oper_input_base()+%d)->bottom_type(); return (req() <= oper_input_base()+%d) ? t : t->meet(in(oper_input_base()+%d)->bottom_type()); } // CMoveP\n",
         offset, offset+1, offset+1);
     }
+    else if( instr->_matrule && instr->_matrule->_rChild && !strcmp(instr->_matrule->_rChild->_opType,"CMoveN") ) {
+      int offset = 1;
+      // Special special hack to see if the Cmp? has been incorporated in the conditional move
+      MatchNode *rl = instr->_matrule->_rChild->_lChild;
+      if( rl && !strcmp(rl->_opType, "Binary") ) {
+          MatchNode *rlr = rl->_rChild;
+          if (rlr && strncmp(rlr->_opType, "Cmp", 3) == 0)
+            offset = 2;
+      }
+      // Special hack for ideal CMoveN; ideal type depends on inputs
+      fprintf(fp,"  const Type            *bottom_type() const { const Type *t = in(oper_input_base()+%d)->bottom_type(); return (req() <= oper_input_base()+%d) ? t : t->meet(in(oper_input_base()+%d)->bottom_type()); } // CMoveN\n",
+        offset, offset+1, offset+1);
+    }
     else if( instr->needs_base_oop_edge(_globalNames) ) {
       // Special hack for ideal AddP.  Bottom type is an oop IFF it has a
       // legal base-pointer input.  Otherwise it is NOT an oop.
--- a/hotspot/src/share/vm/c1/c1_FrameMap.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_FrameMap.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -278,7 +278,7 @@
 ByteSize FrameMap::sp_offset_for_monitor_base(const int index) const {
   int end_of_spills = round_to(first_available_sp_in_frame + _reserved_argument_area_size, sizeof(double)) +
     _num_spills * spill_slot_size_in_bytes;
-  int offset = round_to(end_of_spills, HeapWordSize) + index * sizeof(BasicObjectLock);
+  int offset = (int) round_to(end_of_spills, HeapWordSize) + index * sizeof(BasicObjectLock);
   return in_ByteSize(offset);
 }
 
--- a/hotspot/src/share/vm/c1/c1_LIR.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LIR.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -37,7 +37,7 @@
   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
 }
 
-#ifdef IA32
+#if defined(X86)
 
 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
   return FrameMap::nr2xmmreg(xmm_regnr());
@@ -48,7 +48,7 @@
   return FrameMap::nr2xmmreg(xmm_regnrLo());
 }
 
-#endif
+#endif // X86
 
 
 #ifdef SPARC
@@ -81,7 +81,7 @@
   case floatTag  : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
   case longTag   : return LIR_OprFact::longConst(type->as_LongConstant()->value());
   case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
-  default: ShouldNotReachHere();
+  default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
   }
 }
 
@@ -94,7 +94,7 @@
     case floatTag:  return LIR_OprFact::floatConst(0.0);
     case longTag:   return LIR_OprFact::longConst(0);
     case doubleTag: return LIR_OprFact::doubleConst(0.0);
-    default:        ShouldNotReachHere();
+    default:        ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
   }
   return illegalOpr;
 }
@@ -162,6 +162,7 @@
 
     default:
       ShouldNotReachHere();
+      return '?';
   }
 }
 
@@ -1374,7 +1375,7 @@
   } else if (is_double_cpu()) {
     out->print(as_register_hi()->name());
     out->print(as_register_lo()->name());
-#ifdef IA32
+#if defined(X86)
   } else if (is_single_xmm()) {
     out->print(as_xmm_float_reg()->name());
   } else if (is_double_xmm()) {
--- a/hotspot/src/share/vm/c1/c1_LIR.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LIR.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -135,6 +135,13 @@
       return as_jint_hi();
     }
   }
+  jlong      as_jlong_bits() const    {
+    if (type() == T_DOUBLE) {
+      return jlong_cast(_value.get_jdouble());
+    } else {
+      return as_jlong();
+    }
+  }
 
   virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
 
@@ -302,6 +309,7 @@
 
       default:
         ShouldNotReachHere();
+        return single_size;
       }
   }
 
@@ -417,12 +425,12 @@
     return as_register();
   }
 
-#ifdef IA32
+#ifdef X86
   XMMRegister as_xmm_float_reg() const;
   XMMRegister as_xmm_double_reg() const;
   // for compatibility with RInfo
   int fpu () const                                  { return lo_reg_half(); }
-#endif
+#endif // X86
 
 #ifdef SPARC
   FloatRegister as_float_reg   () const;
@@ -503,14 +511,14 @@
      , _type(type)
      , _disp(disp) { verify(); }
 
-#ifdef IA32
+#ifdef X86
   LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, int disp, BasicType type):
        _base(base)
      , _index(index)
      , _scale(scale)
      , _type(type)
      , _disp(disp) { verify(); }
-#endif
+#endif // X86
 
   LIR_Opr base()  const                          { return _base;  }
   LIR_Opr index() const                          { return _index; }
@@ -535,31 +543,93 @@
 
   static LIR_Opr illegalOpr;
 
-  static LIR_Opr single_cpu(int reg)            { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::int_type    | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
-  static LIR_Opr single_cpu_oop(int reg)        { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::object_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
-  static LIR_Opr double_cpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::long_type   | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
+  static LIR_Opr single_cpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::int_type    | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
+  static LIR_Opr single_cpu_oop(int reg)        { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::object_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
+  static LIR_Opr double_cpu(int reg1, int reg2) {
+    LP64_ONLY(assert(reg1 == reg2, "must be identical"));
+    return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+                               (reg2 << LIR_OprDesc::reg2_shift) |
+                               LIR_OprDesc::long_type            |
+                               LIR_OprDesc::cpu_register         |
+                               LIR_OprDesc::double_size);
+  }
 
-  static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::float_type  | LIR_OprDesc::fpu_register | LIR_OprDesc::single_size); }
+  static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
+                                                                             LIR_OprDesc::float_type           |
+                                                                             LIR_OprDesc::fpu_register         |
+                                                                             LIR_OprDesc::single_size); }
 
 #ifdef SPARC
-  static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
+  static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+                                                                             (reg2 << LIR_OprDesc::reg2_shift) |
+                                                                             LIR_OprDesc::double_type          |
+                                                                             LIR_OprDesc::fpu_register         |
+                                                                             LIR_OprDesc::double_size); }
 #endif
-#ifdef IA32
-  static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) | (reg  << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
-  static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) |                                     LIR_OprDesc::float_type  | LIR_OprDesc::fpu_register | LIR_OprDesc::single_size | LIR_OprDesc::is_xmm_mask); }
-  static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)((reg  << LIR_OprDesc::reg1_shift) | (reg  << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size | LIR_OprDesc::is_xmm_mask); }
-#endif
+#ifdef X86
+  static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
+                                                                             (reg  << LIR_OprDesc::reg2_shift) |
+                                                                             LIR_OprDesc::double_type          |
+                                                                             LIR_OprDesc::fpu_register         |
+                                                                             LIR_OprDesc::double_size); }
+
+  static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
+                                                                             LIR_OprDesc::float_type           |
+                                                                             LIR_OprDesc::fpu_register         |
+                                                                             LIR_OprDesc::single_size          |
+                                                                             LIR_OprDesc::is_xmm_mask); }
+  static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
+                                                                             (reg  << LIR_OprDesc::reg2_shift) |
+                                                                             LIR_OprDesc::double_type          |
+                                                                             LIR_OprDesc::fpu_register         |
+                                                                             LIR_OprDesc::double_size          |
+                                                                             LIR_OprDesc::is_xmm_mask); }
+#endif // X86
 
 
   static LIR_Opr virtual_register(int index, BasicType type) {
     LIR_Opr res;
     switch (type) {
       case T_OBJECT: // fall through
-      case T_ARRAY:  res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::object_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size | LIR_OprDesc::virtual_mask); break;
-      case T_INT:    res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::int_type    | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size | LIR_OprDesc::virtual_mask); break;
-      case T_LONG:   res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::long_type   | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size | LIR_OprDesc::virtual_mask); break;
-      case T_FLOAT:  res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::float_type  | LIR_OprDesc::fpu_register | LIR_OprDesc::single_size | LIR_OprDesc::virtual_mask); break;
-      case T_DOUBLE: res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size | LIR_OprDesc::virtual_mask); break;
+      case T_ARRAY:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift)  |
+                                            LIR_OprDesc::object_type  |
+                                            LIR_OprDesc::cpu_register |
+                                            LIR_OprDesc::single_size  |
+                                            LIR_OprDesc::virtual_mask);
+        break;
+
+      case T_INT:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::int_type              |
+                                  LIR_OprDesc::cpu_register          |
+                                  LIR_OprDesc::single_size           |
+                                  LIR_OprDesc::virtual_mask);
+        break;
+
+      case T_LONG:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::long_type             |
+                                  LIR_OprDesc::cpu_register          |
+                                  LIR_OprDesc::double_size           |
+                                  LIR_OprDesc::virtual_mask);
+        break;
+
+      case T_FLOAT:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::float_type           |
+                                  LIR_OprDesc::fpu_register         |
+                                  LIR_OprDesc::single_size          |
+                                  LIR_OprDesc::virtual_mask);
+        break;
+
+      case
+        T_DOUBLE: res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                            LIR_OprDesc::double_type           |
+                                            LIR_OprDesc::fpu_register          |
+                                            LIR_OprDesc::double_size           |
+                                            LIR_OprDesc::virtual_mask);
+        break;
 
       default:       ShouldNotReachHere(); res = illegalOpr;
     }
@@ -572,8 +642,8 @@
 
     // old-style calculation; check if old and new method are equal
     LIR_OprDesc::OprType t = as_OprType(type);
-    LIR_Opr old_res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | t |
-                               ((type == T_FLOAT || type == T_DOUBLE) ? LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) |
+    LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | t |
+                                          ((type == T_FLOAT || type == T_DOUBLE) ?  LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) |
                                LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask);
     assert(res == old_res, "old and new method not equal");
 #endif
@@ -588,11 +658,39 @@
     LIR_Opr res;
     switch (type) {
       case T_OBJECT: // fall through
-      case T_ARRAY:  res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::object_type | LIR_OprDesc::stack_value | LIR_OprDesc::single_size); break;
-      case T_INT:    res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::int_type    | LIR_OprDesc::stack_value | LIR_OprDesc::single_size); break;
-      case T_LONG:   res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::long_type   | LIR_OprDesc::stack_value | LIR_OprDesc::double_size); break;
-      case T_FLOAT:  res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::float_type  | LIR_OprDesc::stack_value | LIR_OprDesc::single_size); break;
-      case T_DOUBLE: res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::double_type | LIR_OprDesc::stack_value | LIR_OprDesc::double_size); break;
+      case T_ARRAY:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::object_type           |
+                                  LIR_OprDesc::stack_value           |
+                                  LIR_OprDesc::single_size);
+        break;
+
+      case T_INT:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::int_type              |
+                                  LIR_OprDesc::stack_value           |
+                                  LIR_OprDesc::single_size);
+        break;
+
+      case T_LONG:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::long_type             |
+                                  LIR_OprDesc::stack_value           |
+                                  LIR_OprDesc::double_size);
+        break;
+
+      case T_FLOAT:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::float_type            |
+                                  LIR_OprDesc::stack_value           |
+                                  LIR_OprDesc::single_size);
+        break;
+      case T_DOUBLE:
+        res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                  LIR_OprDesc::double_type           |
+                                  LIR_OprDesc::stack_value           |
+                                  LIR_OprDesc::double_size);
+        break;
 
       default:       ShouldNotReachHere(); res = illegalOpr;
     }
@@ -601,7 +699,10 @@
     assert(index >= 0, "index must be positive");
     assert(index <= (max_jint >> LIR_OprDesc::data_shift), "index is too big");
 
-    LIR_Opr old_res = (LIR_Opr)((index << LIR_OprDesc::data_shift) | LIR_OprDesc::stack_value | as_OprType(type) | LIR_OprDesc::size_for(type));
+    LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                          LIR_OprDesc::stack_value           |
+                                          as_OprType(type)                   |
+                                          LIR_OprDesc::size_for(type));
     assert(res == old_res, "old and new method not equal");
 #endif
 
--- a/hotspot/src/share/vm/c1/c1_LIRAssembler.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LIRAssembler.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -215,7 +215,7 @@
 #endif /* PRODUCT */
 
   assert(block->lir() != NULL, "must have LIR");
-  IA32_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
+  X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
 
 #ifndef PRODUCT
   if (CommentedAssembly) {
@@ -227,7 +227,7 @@
 
   emit_lir_list(block->lir());
 
-  IA32_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
+  X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
 }
 
 
@@ -434,7 +434,7 @@
     break;
   default: ShouldNotReachHere();
   }
-#if defined(IA32) && defined(TIERED)
+#if defined(X86) && defined(TIERED)
   // C2 leave fpu stack dirty clean it
   if (UseSSE < 2) {
     int i;
@@ -445,7 +445,7 @@
       ffree(0);
     }
   }
-#endif // IA32 && TIERED
+#endif // X86 && TIERED
 }
 
 
--- a/hotspot/src/share/vm/c1/c1_LIRAssembler.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LIRAssembler.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -75,9 +75,9 @@
   void emit_stubs(CodeStubList* stub_list);
 
   // addresses
-  static Address as_Address(LIR_Address* addr);
-  static Address as_Address_lo(LIR_Address* addr);
-  static Address as_Address_hi(LIR_Address* addr);
+  Address as_Address(LIR_Address* addr);
+  Address as_Address_lo(LIR_Address* addr);
+  Address as_Address_hi(LIR_Address* addr);
 
   // debug information
   void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
--- a/hotspot/src/share/vm/c1/c1_LIRGenerator.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LIRGenerator.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1717,7 +1717,7 @@
     assert(log2_scale == 0, "must not have a scale");
     addr = new LIR_Address(base_op, index_op->as_jint(), dst_type);
   } else {
-#ifdef IA32
+#ifdef X86
     addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
 #else
     if (index_op->is_illegal() || log2_scale == 0) {
--- a/hotspot/src/share/vm/c1/c1_LinearScan.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LinearScan.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -80,7 +80,7 @@
  , _scope_value_cache(0) // initialized later with correct length
  , _interval_in_loop(0, 0) // initialized later with correct length
  , _cached_blocks(*ir->linear_scan_order())
-#ifdef IA32
+#ifdef X86
  , _fpu_stack_allocator(NULL)
 #endif
 {
@@ -116,7 +116,7 @@
     return opr->cpu_regnr();
   } else if (opr->is_double_cpu()) {
     return opr->cpu_regnrLo();
-#ifdef IA32
+#ifdef X86
   } else if (opr->is_single_xmm()) {
     return opr->fpu_regnr() + pd_first_xmm_reg;
   } else if (opr->is_double_xmm()) {
@@ -128,6 +128,7 @@
     return opr->fpu_regnrLo() + pd_first_fpu_reg;
   } else {
     ShouldNotReachHere();
+    return -1;
   }
 }
 
@@ -140,7 +141,7 @@
     return -1;
   } else if (opr->is_double_cpu()) {
     return opr->cpu_regnrHi();
-#ifdef IA32
+#ifdef X86
   } else if (opr->is_single_xmm()) {
     return -1;
   } else if (opr->is_double_xmm()) {
@@ -152,6 +153,7 @@
     return opr->fpu_regnrHi() + pd_first_fpu_reg;
   } else {
     ShouldNotReachHere();
+    return -1;
   }
 }
 
@@ -1063,7 +1065,7 @@
   }
 
 
-#ifdef IA32
+#ifdef X86
   if (op->code() == lir_cmove) {
     // conditional moves can handle stack operands
     assert(op->result_opr()->is_register(), "result must always be in a register");
@@ -1128,7 +1130,7 @@
       }
     }
   }
-#endif // IA32
+#endif // X86
 
   // all other operands require a register
   return mustHaveRegister;
@@ -1261,7 +1263,7 @@
   // virtual fpu operands. Otherwise no allocation for fpu registers is
   // perfomed and so the temp ranges would be useless
   if (has_fpu_registers()) {
-#ifdef IA32
+#ifdef X86
     if (UseSSE < 2) {
 #endif
       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
@@ -1270,7 +1272,7 @@
         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
       }
-#ifdef IA32
+#ifdef X86
     }
     if (UseSSE > 0) {
       for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
@@ -1299,8 +1301,8 @@
 
     // Update intervals for registers live at the end of this block;
     BitMap live = block->live_out();
-    int size = live.size();
-    for (int number = live.get_next_one_offset(0, size); number < size; number = live.get_next_one_offset(number + 1, size)) {
+    int size = (int)live.size();
+    for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
       assert(live.at(number), "should not stop here otherwise");
       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
@@ -1654,7 +1656,7 @@
   const BitMap live_at_edge = to_block->live_in();
 
   // visit all registers where the live_at_edge bit is set
-  for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
+  for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
     assert(r < num_regs, "live information set for not exisiting interval");
     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
 
@@ -1824,7 +1826,7 @@
 
   // visit all registers where the live_in bit is set
   int size = live_set_size();
-  for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
+  for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
     resolve_exception_entry(block, r, move_resolver);
   }
 
@@ -1898,7 +1900,7 @@
   // visit all registers where the live_in bit is set
   BlockBegin* block = handler->entry_block();
   int size = live_set_size();
-  for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
+  for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
   }
 
@@ -2032,19 +2034,19 @@
           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
         }
 
-#ifdef SPARC
 #ifdef _LP64
         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
 #else
+#ifdef SPARC
         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
-#endif
 #else
         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
-#endif
+#endif // SPARC
+#endif // LP64
       }
 
       case T_FLOAT: {
-#ifdef IA32
+#ifdef X86
         if (UseSSE >= 1) {
           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
@@ -2058,7 +2060,7 @@
       }
 
       case T_DOUBLE: {
-#ifdef IA32
+#ifdef X86
         if (UseSSE >= 2) {
           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
@@ -2122,7 +2124,7 @@
 
   LIR_Opr res = operand_for_interval(interval);
 
-#ifdef IA32
+#ifdef X86
   // new semantic for is_last_use: not only set on definite end of interval,
   // but also before hole
   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
@@ -2475,6 +2477,7 @@
 
     default:
       ShouldNotReachHere();
+      return -1;
   }
 }
 
@@ -2515,7 +2518,7 @@
     scope_values->append(sv);
     return 1;
 
-#ifdef IA32
+#ifdef X86
   } else if (opr->is_single_xmm()) {
     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
@@ -2525,7 +2528,7 @@
 #endif
 
   } else if (opr->is_single_fpu()) {
-#ifdef IA32
+#ifdef X86
     // the exact location of fpu stack values is only known
     // during fpu stack allocation, so the stack allocator object
     // must be present
@@ -2548,12 +2551,23 @@
     ScopeValue* second;
 
     if (opr->is_double_stack()) {
+#ifdef _LP64
+      Location loc1;
+      Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
+      if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
+        bailout("too large frame");
+      }
+      // Does this reverse on x86 vs. sparc?
+      first =  new LocationValue(loc1);
+      second = &_int_0_scope_value;
+#else
       Location loc1, loc2;
       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
         bailout("too large frame");
       }
       first =  new LocationValue(loc1);
       second = new LocationValue(loc2);
+#endif // _LP64
 
     } else if (opr->is_double_cpu()) {
 #ifdef _LP64
@@ -2573,9 +2587,10 @@
 
       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
-#endif
-
-#ifdef IA32
+#endif //_LP64
+
+
+#ifdef X86
     } else if (opr->is_double_xmm()) {
       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
@@ -2589,13 +2604,13 @@
 
     } else if (opr->is_double_fpu()) {
       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
-      // the double as float registers in the native ordering. On IA32,
+      // the double as float registers in the native ordering. On X86,
       // fpu_regnrLo is a FPU stack slot whose VMReg represents
       // the low-order word of the double and fpu_regnrLo + 1 is the
       // name for the other half.  *first and *second must represent the
       // least and most significant words, respectively.
 
-#ifdef IA32
+#ifdef X86
       // the exact location of fpu stack values is only known
       // during fpu stack allocation, so the stack allocator object
       // must be present
@@ -2865,7 +2880,6 @@
     op->verify();
 #endif
 
-#ifndef _LP64
     // remove useless moves
     if (op->code() == lir_move) {
       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
@@ -2879,7 +2893,6 @@
         has_dead = true;
       }
     }
-#endif
   }
 
   if (has_dead) {
@@ -3192,7 +3205,7 @@
     BitMap live_at_edge = block->live_in();
 
     // visit all registers where the live_at_edge bit is set
-    for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
+    for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
 
       Value value = gen()->instruction_for_vreg(r);
@@ -3438,7 +3451,7 @@
         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
       }
 
-#ifdef IA32
+#ifdef X86
       for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
       }
@@ -4357,7 +4370,7 @@
       opr = LIR_OprFact::single_cpu(assigned_reg());
     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
-#ifdef IA32
+#ifdef X86
     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
 #endif
@@ -5435,7 +5448,7 @@
 }
 
 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
-#ifdef IA32
+#ifdef X86
   // fast calculation of intervals that can never get a register because the
   // the next instruction is a call that blocks all registers
   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
--- a/hotspot/src/share/vm/c1/c1_LinearScan.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_LinearScan.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -177,7 +177,7 @@
   bool          is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); }
 
   // handling of fpu stack allocation (platform dependent, needed for debug information generation)
-#ifdef IA32
+#ifdef X86
   FpuStackAllocator* _fpu_stack_allocator;
   bool use_fpu_stack_allocation() const          { return UseSSE < 2 && has_fpu_registers(); }
 #else
--- a/hotspot/src/share/vm/c1/c1_Runtime1.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/c1/c1_Runtime1.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -336,21 +336,6 @@
 
   assert(oop(klass)->is_klass(), "not a class");
   assert(rank >= 1, "rank must be nonzero");
-#ifdef _LP64
-// In 64 bit mode, the sizes are stored in the top 32 bits
-// of each 64 bit stack entry.
-// dims is actually an intptr_t * because the arguments
-// are pushed onto a 64 bit stack.
-// We must create an array of jints to pass to multi_allocate.
-// We reuse the current stack because it will be popped
-// after this bytecode is completed.
-  if ( rank > 1 ) {
-    int index;
-    for ( index = 1; index < rank; index++ ) {  // First size is ok
-        dims[index] = dims[index*2];
-    }
-  }
-#endif
   oop obj = arrayKlass::cast(klass)->multi_allocate(rank, dims, CHECK);
   thread->set_vm_result(obj);
 JRT_END
--- a/hotspot/src/share/vm/ci/ciTypeFlow.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/ci/ciTypeFlow.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -127,7 +127,7 @@
 
   // Used as a combined index for locals and temps
   enum Cell {
-    Cell_0
+    Cell_0, Cell_max = INT_MAX
   };
 
   // A StateVector summarizes the type information at some
--- a/hotspot/src/share/vm/code/relocInfo.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/code/relocInfo.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1200,11 +1200,13 @@
 class poll_Relocation : public Relocation {
   bool          is_data()                      { return true; }
   relocInfo::relocType type() { return relocInfo::poll_type; }
+  void     fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest);
 };
 
 class poll_return_Relocation : public Relocation {
   bool          is_data()                      { return true; }
   relocInfo::relocType type() { return relocInfo::poll_return_type; }
+  void     fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest);
 };
 
 
--- a/hotspot/src/share/vm/gc_implementation/parNew/parGCAllocBuffer.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/gc_implementation/parNew/parGCAllocBuffer.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -229,7 +229,7 @@
     HeapWord* first_card_start = _bsa->address_for_index(first_card_index);
     if (first_card_start < pre_top) {
       HeapWord* second_card_start =
-        _bsa->address_for_index(first_card_index + 1);
+        _bsa->inc_by_region_size(first_card_start);
 
       // Ensure enough room to fill with the smallest block
       second_card_start = MAX2(second_card_start, pre_top + AlignmentReserve);
--- a/hotspot/src/share/vm/includeDB_compiler1	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/includeDB_compiler1	Wed Jul 05 16:41:01 2017 +0200
@@ -258,6 +258,7 @@
 c1_LIRGenerator_<arch>.cpp             ciObjArrayKlass.hpp
 c1_LIRGenerator_<arch>.cpp             ciTypeArrayKlass.hpp
 c1_LIRGenerator_<arch>.cpp             sharedRuntime.hpp
+c1_LIRGenerator_<arch>.cpp             vmreg_<arch>.inline.hpp
 
 c1_LinearScan.cpp                       c1_CFGPrinter.hpp
 c1_LinearScan.cpp                       c1_Compilation.hpp
@@ -281,7 +282,7 @@
 c1_LinearScan_<arch>.hpp                generate_platform_dependent_include
 
 c1_MacroAssembler.hpp                   assembler.hpp
-c1_MacroAssembler.hpp                   assembler_<arch_model>.inline.hpp
+c1_MacroAssembler.hpp                   assembler_<arch>.inline.hpp
 
 c1_MacroAssembler_<arch>.cpp            arrayOop.hpp
 c1_MacroAssembler_<arch>.cpp            biasedLocking.hpp
--- a/hotspot/src/share/vm/includeDB_compiler2	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/includeDB_compiler2	Wed Jul 05 16:41:01 2017 +0200
@@ -26,7 +26,7 @@
 ad_<arch_model>.cpp                     ad_<arch_model>.hpp
 ad_<arch_model>.cpp                     allocation.inline.hpp
 ad_<arch_model>.cpp                     assembler.hpp
-ad_<arch_model>.cpp                     assembler_<arch_model>.inline.hpp
+ad_<arch_model>.cpp                     assembler_<arch>.inline.hpp
 ad_<arch_model>.cpp                     biasedLocking.hpp
 ad_<arch_model>.cpp                     cfgnode.hpp
 ad_<arch_model>.cpp                     collectedHeap.inline.hpp
@@ -957,7 +957,7 @@
 runtime_<arch_model>.cpp                adGlobals_<arch_model>.hpp
 runtime_<arch_model>.cpp                ad_<arch_model>.hpp
 runtime_<arch_model>.cpp                assembler.hpp
-runtime_<arch_model>.cpp                assembler_<arch_model>.inline.hpp
+runtime_<arch_model>.cpp                assembler_<arch>.inline.hpp
 runtime_<arch_model>.cpp                globalDefinitions.hpp
 runtime_<arch_model>.cpp                interfaceSupport.hpp
 runtime_<arch_model>.cpp                interpreter.hpp
--- a/hotspot/src/share/vm/includeDB_core	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/includeDB_core	Wed Jul 05 16:41:01 2017 +0200
@@ -228,7 +228,7 @@
 
 assembler.cpp                           assembler.hpp
 assembler.cpp                           assembler.inline.hpp
-assembler.cpp                           assembler_<arch_model>.inline.hpp
+assembler.cpp                           assembler_<arch>.inline.hpp
 assembler.cpp                           codeBuffer.hpp
 assembler.cpp                           icache.hpp
 assembler.cpp                           os.hpp
@@ -248,29 +248,29 @@
 assembler.inline.hpp                    disassembler.hpp
 assembler.inline.hpp                    threadLocalStorage.hpp
 
-assembler_<arch_model>.cpp              assembler_<arch_model>.inline.hpp
-assembler_<arch_model>.cpp              biasedLocking.hpp
-assembler_<arch_model>.cpp              cardTableModRefBS.hpp
-assembler_<arch_model>.cpp              collectedHeap.inline.hpp
-assembler_<arch_model>.cpp              interfaceSupport.hpp
-assembler_<arch_model>.cpp              interpreter.hpp
-assembler_<arch_model>.cpp              objectMonitor.hpp
-assembler_<arch_model>.cpp              os.hpp
-assembler_<arch_model>.cpp              resourceArea.hpp
-assembler_<arch_model>.cpp              sharedRuntime.hpp
-assembler_<arch_model>.cpp              stubRoutines.hpp
-
-assembler_<arch_model>.hpp              generate_platform_dependent_include
-
-assembler_<arch_model>.inline.hpp       assembler.inline.hpp
-assembler_<arch_model>.inline.hpp       codeBuffer.hpp
-assembler_<arch_model>.inline.hpp       codeCache.hpp
-assembler_<arch_model>.inline.hpp       handles.inline.hpp
-
-assembler_<os_arch_model>.cpp           assembler.hpp
-assembler_<os_arch_model>.cpp           assembler_<arch_model>.inline.hpp
-assembler_<os_arch_model>.cpp           os.hpp
-assembler_<os_arch_model>.cpp           threadLocalStorage.hpp
+assembler_<arch>.cpp              assembler_<arch>.inline.hpp
+assembler_<arch>.cpp              biasedLocking.hpp
+assembler_<arch>.cpp              cardTableModRefBS.hpp
+assembler_<arch>.cpp              collectedHeap.inline.hpp
+assembler_<arch>.cpp              interfaceSupport.hpp
+assembler_<arch>.cpp              interpreter.hpp
+assembler_<arch>.cpp              objectMonitor.hpp
+assembler_<arch>.cpp              os.hpp
+assembler_<arch>.cpp              resourceArea.hpp
+assembler_<arch>.cpp              sharedRuntime.hpp
+assembler_<arch>.cpp              stubRoutines.hpp
+
+assembler_<arch>.hpp              generate_platform_dependent_include
+
+assembler_<arch>.inline.hpp       assembler.inline.hpp
+assembler_<arch>.inline.hpp       codeBuffer.hpp
+assembler_<arch>.inline.hpp       codeCache.hpp
+assembler_<arch>.inline.hpp       handles.inline.hpp
+
+assembler_<os_arch>.cpp           assembler.hpp
+assembler_<os_arch>.cpp           assembler_<arch>.inline.hpp
+assembler_<os_arch>.cpp           os.hpp
+assembler_<os_arch>.cpp           threadLocalStorage.hpp
 
 atomic.cpp                              atomic.hpp
 atomic.cpp                              atomic_<os_arch>.inline.hpp
@@ -1926,7 +1926,7 @@
 
 hpi_imported.h                          jni.h
 
-icBuffer.cpp                            assembler_<arch_model>.inline.hpp
+icBuffer.cpp                            assembler_<arch>.inline.hpp
 icBuffer.cpp                            collectedHeap.inline.hpp
 icBuffer.cpp                            compiledIC.hpp
 icBuffer.cpp                            icBuffer.hpp
@@ -1947,7 +1947,7 @@
 icBuffer.hpp                            stubs.hpp
 
 icBuffer_<arch>.cpp                     assembler.hpp
-icBuffer_<arch>.cpp                     assembler_<arch_model>.inline.hpp
+icBuffer_<arch>.cpp                     assembler_<arch>.inline.hpp
 icBuffer_<arch>.cpp                     bytecodes.hpp
 icBuffer_<arch>.cpp                     collectedHeap.inline.hpp
 icBuffer_<arch>.cpp                     icBuffer.hpp
@@ -1962,7 +1962,7 @@
 icache.hpp                              allocation.hpp
 icache.hpp                              stubCodeGenerator.hpp
 
-icache_<arch>.cpp                       assembler_<arch_model>.inline.hpp
+icache_<arch>.cpp                       assembler_<arch>.inline.hpp
 icache_<arch>.cpp                       icache.hpp
 
 icache_<arch>.hpp                       generate_platform_dependent_include
@@ -2095,7 +2095,7 @@
 interp_masm_<arch_model>.cpp            synchronizer.hpp
 interp_masm_<arch_model>.cpp            thread_<os_family>.inline.hpp
 
-interp_masm_<arch_model>.hpp            assembler_<arch_model>.inline.hpp
+interp_masm_<arch_model>.hpp            assembler_<arch>.inline.hpp
 interp_masm_<arch_model>.hpp            invocationCounter.hpp
 
 interpreter.cpp                         allocation.inline.hpp
@@ -2402,7 +2402,7 @@
 jniFastGetField.hpp                     allocation.hpp
 jniFastGetField.hpp                     jvm_misc.hpp
 
-jniFastGetField_<arch_model>.cpp        assembler_<arch_model>.inline.hpp
+jniFastGetField_<arch_model>.cpp        assembler_<arch>.inline.hpp
 jniFastGetField_<arch_model>.cpp        jniFastGetField.hpp
 jniFastGetField_<arch_model>.cpp        jvm_misc.hpp
 jniFastGetField_<arch_model>.cpp        resourceArea.hpp
@@ -2905,7 +2905,7 @@
 mutex_<os_family>.inline.hpp            os_<os_family>.inline.hpp
 mutex_<os_family>.inline.hpp            thread_<os_family>.inline.hpp
 
-nativeInst_<arch>.cpp                   assembler_<arch_model>.inline.hpp
+nativeInst_<arch>.cpp                   assembler_<arch>.inline.hpp
 nativeInst_<arch>.cpp                   handles.hpp
 nativeInst_<arch>.cpp                   nativeInst_<arch>.hpp
 nativeInst_<arch>.cpp                   oop.hpp
@@ -3174,7 +3174,7 @@
 
 os_<os_arch>.cpp                        allocation.inline.hpp
 os_<os_arch>.cpp                        arguments.hpp
-os_<os_arch>.cpp                        assembler_<arch_model>.inline.hpp
+os_<os_arch>.cpp                        assembler_<arch>.inline.hpp
 os_<os_arch>.cpp                        classLoader.hpp
 os_<os_arch>.cpp                        events.hpp
 os_<os_arch>.cpp                        extendedPC.hpp
@@ -3208,7 +3208,7 @@
 
 os_<os_family>.cpp                      allocation.inline.hpp
 os_<os_family>.cpp                      arguments.hpp
-os_<os_family>.cpp                      assembler_<arch_model>.inline.hpp
+os_<os_family>.cpp                      assembler_<arch>.inline.hpp
 os_<os_family>.cpp                      attachListener.hpp
 os_<os_family>.cpp                      classLoader.hpp
 os_<os_family>.cpp                      compileBroker.hpp
@@ -3267,7 +3267,7 @@
 osThread.hpp                            objectMonitor.hpp
 osThread.hpp                            top.hpp
 
-osThread_<os_family>.cpp                assembler_<arch_model>.inline.hpp
+osThread_<os_family>.cpp                assembler_<arch>.inline.hpp
 osThread_<os_family>.cpp                atomic.hpp
 osThread_<os_family>.cpp                handles.inline.hpp
 osThread_<os_family>.cpp                mutexLocker.hpp
@@ -3480,7 +3480,7 @@
 register_definitions_<arch>.cpp         register.hpp
 register_definitions_<arch>.cpp         register_<arch>.hpp
 
-relocInfo.cpp                           assembler_<arch_model>.inline.hpp
+relocInfo.cpp                           assembler_<arch>.inline.hpp
 relocInfo.cpp                           compiledIC.hpp
 relocInfo.cpp                           copy.hpp
 relocInfo.cpp                           nativeInst_<arch>.hpp
@@ -3493,7 +3493,7 @@
 relocInfo.hpp                           top.hpp
 
 relocInfo_<arch>.cpp                    assembler.inline.hpp
-relocInfo_<arch>.cpp                    assembler_<arch_model>.inline.hpp
+relocInfo_<arch>.cpp                    assembler_<arch>.inline.hpp
 relocInfo_<arch>.cpp                    nativeInst_<arch>.hpp
 relocInfo_<arch>.cpp                    oop.inline.hpp
 relocInfo_<arch>.cpp                    relocInfo.hpp
@@ -3676,7 +3676,7 @@
 sharedRuntime.hpp                       threadLocalStorage.hpp
 
 sharedRuntime_<arch_model>.cpp          assembler.hpp
-sharedRuntime_<arch_model>.cpp          assembler_<arch_model>.inline.hpp
+sharedRuntime_<arch_model>.cpp          assembler_<arch>.inline.hpp
 sharedRuntime_<arch_model>.cpp          compiledICHolderOop.hpp
 sharedRuntime_<arch_model>.cpp          debugInfoRec.hpp
 sharedRuntime_<arch_model>.cpp          icBuffer.hpp
@@ -3819,7 +3819,7 @@
 statSampler.hpp                         perfData.hpp
 statSampler.hpp                         task.hpp
 
-stubCodeGenerator.cpp                   assembler_<arch_model>.inline.hpp
+stubCodeGenerator.cpp                   assembler_<arch>.inline.hpp
 stubCodeGenerator.cpp                   disassembler.hpp
 stubCodeGenerator.cpp                   forte.hpp
 stubCodeGenerator.cpp                   oop.inline.hpp
@@ -3830,7 +3830,7 @@
 stubCodeGenerator.hpp                   assembler.hpp
 
 stubGenerator_<arch_model>.cpp          assembler.hpp
-stubGenerator_<arch_model>.cpp          assembler_<arch_model>.inline.hpp
+stubGenerator_<arch_model>.cpp          assembler_<arch>.inline.hpp
 stubGenerator_<arch_model>.cpp          frame.inline.hpp
 stubGenerator_<arch_model>.cpp          handles.inline.hpp
 stubGenerator_<arch_model>.cpp          instanceOop.hpp
@@ -4562,7 +4562,7 @@
 vm_version.hpp                          allocation.hpp
 vm_version.hpp                          ostream.hpp
 
-vm_version_<arch_model>.cpp             assembler_<arch_model>.inline.hpp
+vm_version_<arch_model>.cpp             assembler_<arch>.inline.hpp
 vm_version_<arch_model>.cpp             java.hpp
 vm_version_<arch_model>.cpp             os_<os_family>.inline.hpp
 vm_version_<arch_model>.cpp             resourceArea.hpp
@@ -4603,7 +4603,7 @@
 vtableStubs.hpp                         allocation.hpp
 
 vtableStubs_<arch_model>.cpp            assembler.hpp
-vtableStubs_<arch_model>.cpp            assembler_<arch_model>.inline.hpp
+vtableStubs_<arch_model>.cpp            assembler_<arch>.inline.hpp
 vtableStubs_<arch_model>.cpp            instanceKlass.hpp
 vtableStubs_<arch_model>.cpp            interp_masm_<arch_model>.hpp
 vtableStubs_<arch_model>.cpp            klassVtable.hpp
--- a/hotspot/src/share/vm/includeDB_features	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/includeDB_features	Wed Jul 05 16:41:01 2017 +0200
@@ -57,7 +57,7 @@
 dump.cpp                                vmThread.hpp
 dump.cpp                                vm_operations.hpp
 
-dump_<arch_model>.cpp                   assembler_<arch_model>.inline.hpp
+dump_<arch_model>.cpp                   assembler_<arch>.inline.hpp
 dump_<arch_model>.cpp                   compactingPermGenGen.hpp
 
 forte.cpp                               collectedHeap.inline.hpp
--- a/hotspot/src/share/vm/memory/blockOffsetTable.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/memory/blockOffsetTable.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -199,6 +199,12 @@
   // "index" in "_offset_array".
   HeapWord* address_for_index(size_t index) const;
 
+  // Return the address "p" incremented by the size of
+  // a region.  This method does not align the address
+  // returned to the start of a region.  It is a simple
+  // primitive.
+  HeapWord* inc_by_region_size(HeapWord* p) const { return p + N_words; }
+
   // Shared space support
   void serialize(SerializeOopClosure* soc, HeapWord* start, HeapWord* end);
 };
--- a/hotspot/src/share/vm/opto/addnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/addnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -573,8 +573,6 @@
   intptr_t txoffset = Type::OffsetBot;
   if (tx->is_con()) {   // Left input is an add of a constant?
     txoffset = tx->get_con();
-    if (txoffset != (int)txoffset)
-      txoffset = Type::OffsetBot;   // oops:  add_offset will choke on it
   }
   return tp->add_offset(txoffset);
 }
@@ -595,8 +593,6 @@
   intptr_t p2offset = Type::OffsetBot;
   if (p2->is_con()) {   // Left input is an add of a constant?
     p2offset = p2->get_con();
-    if (p2offset != (int)p2offset)
-      p2offset = Type::OffsetBot;   // oops:  add_offset will choke on it
   }
   return p1->add_offset(p2offset);
 }
@@ -675,7 +671,7 @@
     // Check for any interesting operand info.
     // In particular, check for both memory and non-memory operands.
     // %%%%% Clean this up: use xadd_offset
-    int con = opnd->constant();
+    intptr_t con = opnd->constant();
     if ( con == TypePtr::OffsetBot )  goto bottom_out;
     offset += con;
     con = opnd->constant_disp();
@@ -695,6 +691,8 @@
         guarantee(tptr == NULL, "must be only one pointer operand");
         tptr = et->isa_oopptr();
         guarantee(tptr != NULL, "non-int operand must be pointer");
+        if (tptr->higher_equal(tp->add_offset(tptr->offset())))
+          tp = tptr; // Set more precise type for bailout
         continue;
       }
       if ( eti->_hi != eti->_lo )  goto bottom_out;
--- a/hotspot/src/share/vm/opto/block.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/block.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -467,6 +467,10 @@
   // get successor block succ_no
   assert(succ_no < in->_num_succs, "illegal successor number");
   Block* out = in->_succs[succ_no];
+  // Compute frequency of the new block. Do this before inserting
+  // new block in case succ_prob() needs to infer the probability from
+  // surrounding blocks.
+  float freq = in->_freq * in->succ_prob(succ_no);
   // get ProjNode corresponding to the succ_no'th successor of the in block
   ProjNode* proj = in->_nodes[in->_nodes.size() - in->_num_succs + succ_no]->as_Proj();
   // create region for basic block
@@ -491,6 +495,8 @@
   }
   // remap predecessor's successor to new block
   in->_succs.map(succ_no, block);
+  // Set the frequency of the new block
+  block->_freq = freq;
   // add new basic block to basic block list
   _blocks.insert(block_no + 1, block);
   _num_blocks++;
--- a/hotspot/src/share/vm/opto/callGenerator.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/callGenerator.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -464,6 +464,12 @@
     }
   }
 
+  if (kit.stopped()) {
+    // Instance exactly does not matches the desired type.
+    kit.set_jvms(slow_jvms);
+    return kit.transfer_exceptions_into_jvms();
+  }
+
   // fall through if the instance exactly matches the desired type
   kit.replace_in_map(receiver, exact_receiver);
 
--- a/hotspot/src/share/vm/opto/callnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/callnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -829,9 +829,7 @@
 //------------------------------Ideal------------------------------------------
 // Skip over any collapsed Regions
 Node *SafePointNode::Ideal(PhaseGVN *phase, bool can_reshape) {
-  if (remove_dead_region(phase, can_reshape))  return this;
-
-  return NULL;
+  return remove_dead_region(phase, can_reshape) ? this : NULL;
 }
 
 //------------------------------Identity---------------------------------------
--- a/hotspot/src/share/vm/opto/chaitin.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/chaitin.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -43,7 +43,7 @@
   if( _degree_valid ) tty->print( "%d ", _eff_degree );
   else tty->print("? ");
 
-  if( _def == NodeSentinel ) {
+  if( is_multidef() ) {
     tty->print("MultiDef ");
     if (_defs != NULL) {
       tty->print("(");
@@ -765,7 +765,7 @@
         // if the LRG is an unaligned pair, we will have to spill
         // so clear the LRG's register mask if it is not already spilled
         if ( !n->is_SpillCopy() &&
-               (lrg._def == NULL || lrg._def == NodeSentinel || !lrg._def->is_SpillCopy()) &&
+               (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
                lrgmask.is_misaligned_Pair()) {
           lrg.Clear();
         }
@@ -1282,7 +1282,7 @@
     // Live range is live and no colors available
     else {
       assert( lrg->alive(), "" );
-      assert( !lrg->_fat_proj || lrg->_def == NodeSentinel ||
+      assert( !lrg->_fat_proj || lrg->is_multidef() ||
               lrg->_def->outcnt() > 0, "fat_proj cannot spill");
       assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
 
--- a/hotspot/src/share/vm/opto/chaitin.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/chaitin.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -156,6 +156,8 @@
 
   // Alive if non-zero, dead if zero
   bool alive() const { return _def != NULL; }
+  bool is_multidef() const { return _def == NodeSentinel; }
+  bool is_singledef() const { return _def != NodeSentinel; }
 
 #ifndef PRODUCT
   void dump( ) const;
@@ -320,7 +322,8 @@
   uint split_DEF( Node *def, Block *b, int loc, uint max, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx );
   uint split_USE( Node *def, Block *b, Node *use, uint useidx, uint max, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx );
   int clone_projs( Block *b, uint idx, Node *con, Node *copy, uint &maxlrg );
-  Node *split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru );
+  Node *split_Rematerialize(Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits,
+                            int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru);
   // True if lidx is used before any real register is def'd in the block
   bool prompt_use( Block *b, uint lidx );
   Node *get_spillcopy_wide( Node *def, Node *use, uint uidx );
--- a/hotspot/src/share/vm/opto/coalesce.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/coalesce.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -604,8 +604,8 @@
   // If both are single def, then src_def powers one live range
   // and def_copy powers the other.  After merging, src_def powers
   // the combined live range.
-  lrgs(lr1)._def = (lrgs(lr1)._def == NodeSentinel ||
-                        lrgs(lr2)._def == NodeSentinel )
+  lrgs(lr1)._def = (lrgs(lr1).is_multidef() ||
+                        lrgs(lr2).is_multidef() )
     ? NodeSentinel : src_def;
   lrgs(lr2)._def = NULL;    // No def for lrg 2
   lrgs(lr2).Clear();        // Force empty mask for LRG 2
--- a/hotspot/src/share/vm/opto/compile.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/compile.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -2111,6 +2111,7 @@
         n->subsume_by( cmpN );
       }
     }
+    break;
 #endif
 
   case Op_ModI:
--- a/hotspot/src/share/vm/opto/connode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/connode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -101,6 +101,8 @@
 // Move constants to the right.
 Node *CMoveNode::Ideal(PhaseGVN *phase, bool can_reshape) {
   if( in(0) && remove_dead_region(phase, can_reshape) ) return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
   assert( !phase->eqv(in(Condition), this) &&
           !phase->eqv(in(IfFalse), this) &&
           !phase->eqv(in(IfTrue), this), "dead loop in CMoveNode::Ideal" );
--- a/hotspot/src/share/vm/opto/divnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/divnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -264,8 +264,14 @@
 
   Node *t1 = phase->transform(new (phase->C, 3) URShiftLNode(lolo_product, phase->intcon(N / 2)));
   Node *t2 = phase->transform(new (phase->C, 3) AddLNode(hilo_product, t1));
-  Node *t3 = phase->transform(new (phase->C, 3) RShiftLNode(t2, phase->intcon(N / 2)));
-  Node *t4 = phase->transform(new (phase->C, 3) AndLNode(t2, phase->longcon(0xFFFFFFFF)));
+
+  // Construct both t3 and t4 before transforming so t2 doesn't go dead
+  // prematurely.
+  Node *t3 = new (phase->C, 3) RShiftLNode(t2, phase->intcon(N / 2));
+  Node *t4 = new (phase->C, 3) AndLNode(t2, phase->longcon(0xFFFFFFFF));
+  t3 = phase->transform(t3);
+  t4 = phase->transform(t4);
+
   Node *t5 = phase->transform(new (phase->C, 3) AddLNode(t4, lohi_product));
   Node *t6 = phase->transform(new (phase->C, 3) RShiftLNode(t5, phase->intcon(N / 2)));
   Node *t7 = phase->transform(new (phase->C, 3) AddLNode(t3, hihi_product));
@@ -396,6 +402,8 @@
 // Divides can be changed to multiplies and/or shifts
 Node *DivINode::Ideal(PhaseGVN *phase, bool can_reshape) {
   if (in(0) && remove_dead_region(phase, can_reshape))  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   const Type *t = phase->type( in(2) );
   if( t == TypeInt::ONE )       // Identity?
@@ -493,6 +501,8 @@
 // Dividing by a power of 2 is a shift.
 Node *DivLNode::Ideal( PhaseGVN *phase, bool can_reshape) {
   if (in(0) && remove_dead_region(phase, can_reshape))  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   const Type *t = phase->type( in(2) );
   if( t == TypeLong::ONE )      // Identity?
@@ -634,6 +644,8 @@
 //------------------------------Idealize---------------------------------------
 Node *DivFNode::Ideal(PhaseGVN *phase, bool can_reshape) {
   if (in(0) && remove_dead_region(phase, can_reshape))  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   const Type *t2 = phase->type( in(2) );
   if( t2 == TypeF::ONE )         // Identity?
@@ -719,6 +731,8 @@
 //------------------------------Idealize---------------------------------------
 Node *DivDNode::Ideal(PhaseGVN *phase, bool can_reshape) {
   if (in(0) && remove_dead_region(phase, can_reshape))  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   const Type *t2 = phase->type( in(2) );
   if( t2 == TypeD::ONE )         // Identity?
@@ -754,7 +768,9 @@
 //------------------------------Idealize---------------------------------------
 Node *ModINode::Ideal(PhaseGVN *phase, bool can_reshape) {
   // Check for dead control input
-  if( remove_dead_region(phase, can_reshape) )  return this;
+  if( in(0) && remove_dead_region(phase, can_reshape) )  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   // Get the modulus
   const Type *t = phase->type( in(2) );
@@ -923,7 +939,9 @@
 //------------------------------Idealize---------------------------------------
 Node *ModLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
   // Check for dead control input
-  if( remove_dead_region(phase, can_reshape) )  return this;
+  if( in(0) && remove_dead_region(phase, can_reshape) )  return this;
+  // Don't bother trying to transform a dead node
+  if( in(0) && in(0)->is_top() )  return NULL;
 
   // Get the modulus
   const Type *t = phase->type( in(2) );
--- a/hotspot/src/share/vm/opto/escape.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/escape.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -492,22 +492,41 @@
 // Adjust the type and inputs of an AddP which computes the
 // address of a field of an instance
 //
-void ConnectionGraph::split_AddP(Node *addp, Node *base,  PhaseGVN  *igvn) {
+bool ConnectionGraph::split_AddP(Node *addp, Node *base,  PhaseGVN  *igvn) {
   const TypeOopPtr *base_t = igvn->type(base)->isa_oopptr();
   assert(base_t != NULL && base_t->is_known_instance(), "expecting instance oopptr");
   const TypeOopPtr *t = igvn->type(addp)->isa_oopptr();
   if (t == NULL) {
     // We are computing a raw address for a store captured by an Initialize
-    // compute an appropriate address type.
+    // compute an appropriate address type (cases #3 and #5).
     assert(igvn->type(addp) == TypeRawPtr::NOTNULL, "must be raw pointer");
     assert(addp->in(AddPNode::Address)->is_Proj(), "base of raw address must be result projection from allocation");
-    int offs = (int)igvn->find_intptr_t_con(addp->in(AddPNode::Offset), Type::OffsetBot);
+    intptr_t offs = (int)igvn->find_intptr_t_con(addp->in(AddPNode::Offset), Type::OffsetBot);
     assert(offs != Type::OffsetBot, "offset must be a constant");
     t = base_t->add_offset(offs)->is_oopptr();
   }
   int inst_id =  base_t->instance_id();
   assert(!t->is_known_instance() || t->instance_id() == inst_id,
                              "old type must be non-instance or match new type");
+
+  // The type 't' could be subclass of 'base_t'.
+  // As result t->offset() could be large then base_t's size and it will
+  // cause the failure in add_offset() with narrow oops since TypeOopPtr()
+  // constructor verifies correctness of the offset.
+  //
+  // It could happend on subclass's branch (from the type profiling
+  // inlining) which was not eliminated during parsing since the exactness
+  // of the allocation type was not propagated to the subclass type check.
+  //
+  // Do nothing for such AddP node and don't process its users since
+  // this code branch will go away.
+  //
+  if (!t->is_known_instance() &&
+      !t->klass()->equals(base_t->klass()) &&
+      t->klass()->is_subtype_of(base_t->klass())) {
+     return false; // bail out
+  }
+
   const TypeOopPtr *tinst = base_t->add_offset(t->offset())->is_oopptr();
   // Do NOT remove the next call: ensure an new alias index is allocated
   // for the instance type
@@ -542,6 +561,7 @@
   }
   // Put on IGVN worklist since at least addp's type was changed above.
   record_for_optimizer(addp);
+  return true;
 }
 
 //
@@ -969,7 +989,7 @@
       if (elem == _phantom_object)
         continue; // Assume the value was set outside this method.
       Node *base = get_map(elem);  // CheckCastPP node
-      split_AddP(n, base, igvn);
+      if (!split_AddP(n, base, igvn)) continue; // wrong type
       tinst = igvn->type(base)->isa_oopptr();
     } else if (n->is_Phi() ||
                n->is_CheckCastPP() ||
@@ -1012,6 +1032,8 @@
           tn->set_type(tn_type);
           igvn->hash_insert(tn);
           record_for_optimizer(n);
+        } else {
+          continue; // wrong type
         }
       }
     } else {
@@ -1788,6 +1810,7 @@
         } else if (call_analyzer->is_return_local()) {
           // determine whether any arguments are returned
           set_escape_state(call_idx, PointsToNode::NoEscape);
+          bool ret_arg = false;
           for (uint i = TypeFunc::Parms; i < d->cnt(); i++) {
             const Type* at = d->field_at(i);
 
@@ -1795,6 +1818,7 @@
               Node *arg = call->in(i)->uncast();
 
               if (call_analyzer->is_arg_returned(i - TypeFunc::Parms)) {
+                ret_arg = true;
                 PointsToNode *arg_esp = ptnode_adr(arg->_idx);
                 if (arg_esp->node_type() == PointsToNode::UnknownType)
                   done = false;
@@ -1806,6 +1830,11 @@
               }
             }
           }
+          if (done && !ret_arg) {
+            // Returns unknown object.
+            set_escape_state(call_idx, PointsToNode::GlobalEscape);
+            add_pointsto_edge(resproj_idx, _phantom_object);
+          }
           copy_dependencies = true;
         } else {
           set_escape_state(call_idx, PointsToNode::GlobalEscape);
@@ -2212,7 +2241,9 @@
         if (in->is_top() || in == n)
           continue;  // ignore top or inputs which go back this node
         int ti = in->_idx;
-        if (ptnode_adr(in->_idx)->node_type() == PointsToNode::JavaObject) {
+        PointsToNode::NodeType nt = ptnode_adr(ti)->node_type();
+        assert(nt != PointsToNode::UnknownType, "all nodes should be known");
+        if (nt == PointsToNode::JavaObject) {
           add_pointsto_edge(n_idx, ti);
         } else {
           add_deferred_edge(n_idx, ti);
--- a/hotspot/src/share/vm/opto/escape.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/escape.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -286,7 +286,7 @@
                         // MemNode       - new memory input for this node
                         // ChecCastPP    - allocation that this is a cast of
                         // allocation    - CheckCastPP of the allocation
-  void split_AddP(Node *addp, Node *base,  PhaseGVN  *igvn);
+  bool split_AddP(Node *addp, Node *base,  PhaseGVN  *igvn);
   PhiNode *create_split_phi(PhiNode *orig_phi, int alias_idx, GrowableArray<PhiNode *>  &orig_phi_worklist, PhaseGVN  *igvn, bool &new_created);
   PhiNode *split_memory_phi(PhiNode *orig_phi, int alias_idx, GrowableArray<PhiNode *>  &orig_phi_worklist, PhaseGVN  *igvn);
   Node *find_mem(Node *mem, int alias_idx, PhaseGVN  *igvn);
--- a/hotspot/src/share/vm/opto/gcm.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/gcm.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1609,7 +1609,30 @@
 float Block::succ_prob(uint i) {
   int eidx = end_idx();
   Node *n = _nodes[eidx];  // Get ending Node
-  int op = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : n->Opcode();
+
+  int op = n->Opcode();
+  if (n->is_Mach()) {
+    if (n->is_MachNullCheck()) {
+      // Can only reach here if called after lcm. The original Op_If is gone,
+      // so we attempt to infer the probability from one or both of the
+      // successor blocks.
+      assert(_num_succs == 2, "expecting 2 successors of a null check");
+      // If either successor has only one predecessor, then the
+      // probabiltity estimate can be derived using the
+      // relative frequency of the successor and this block.
+      if (_succs[i]->num_preds() == 2) {
+        return _succs[i]->_freq / _freq;
+      } else if (_succs[1-i]->num_preds() == 2) {
+        return 1 - (_succs[1-i]->_freq / _freq);
+      } else {
+        // Estimate using both successor frequencies
+        float freq = _succs[i]->_freq;
+        return freq / (freq + _succs[1-i]->_freq);
+      }
+    }
+    op = n->as_Mach()->ideal_Opcode();
+  }
+
 
   // Switch on branch type
   switch( op ) {
--- a/hotspot/src/share/vm/opto/ifg.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/ifg.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -594,7 +594,7 @@
 
           // Insure high score for immediate-use spill copies so they get a color
           if( n->is_SpillCopy()
-              && lrgs(r)._def != NodeSentinel     // MultiDef live range can still split
+              && lrgs(r).is_singledef()        // MultiDef live range can still split
               && n->outcnt() == 1              // and use must be in this block
               && _cfg._bbs[n->unique_out()->_idx] == b ) {
             // All single-use MachSpillCopy(s) that immediately precede their
--- a/hotspot/src/share/vm/opto/loopnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/loopnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -2625,9 +2625,11 @@
     case Op_LoadF:
     case Op_LoadI:
     case Op_LoadKlass:
+    case Op_LoadNKlass:
     case Op_LoadL:
     case Op_LoadS:
     case Op_LoadP:
+    case Op_LoadN:
     case Op_LoadRange:
     case Op_LoadD_unaligned:
     case Op_LoadL_unaligned:
--- a/hotspot/src/share/vm/opto/loopopts.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/loopopts.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -96,6 +96,10 @@
       // our new node, even though we may throw the node away.
       // (Note: This tweaking with igvn only works because x is a new node.)
       _igvn.set_type(x, t);
+      // If x is a TypeNode, capture any more-precise type permanently into Node
+      // othewise it will be not updated during igvn->transform since
+      // igvn->type(x) is set to x->Value() already.
+      x->raise_bottom_type(t);
       Node *y = x->Identity(&_igvn);
       if( y != x ) {
         wins++;
@@ -464,11 +468,11 @@
     case T_FLOAT:
     case T_DOUBLE:
     case T_ADDRESS:             // (RawPtr)
-    case T_NARROWOOP:
       cost++;
       break;
+    case T_NARROWOOP: // Fall through
     case T_OBJECT: {            // Base oops are OK, but not derived oops
-      const TypeOopPtr *tp = phi->type()->isa_oopptr();
+      const TypeOopPtr *tp = phi->type()->make_ptr()->isa_oopptr();
       // Derived pointers are Bad (tm): what's the Base (for GC purposes) of a
       // CMOVE'd derived pointer?  It's a CMOVE'd derived base.  Thus
       // CMOVE'ing a derived pointer requires we also CMOVE the base.  If we
@@ -499,11 +503,11 @@
             return NULL;        // Too much speculative goo
       }
     }
-    // See if the Phi is used by a Cmp.  This will likely Split-If, a
-    // higher-payoff operation.
+    // See if the Phi is used by a Cmp or Narrow oop Decode/Encode.
+    // This will likely Split-If, a higher-payoff operation.
     for (DUIterator_Fast kmax, k = phi->fast_outs(kmax); k < kmax; k++) {
       Node* use = phi->fast_out(k);
-      if( use->is_Cmp() )
+      if( use->is_Cmp() || use->is_DecodeN() || use->is_EncodeP() )
         return NULL;
     }
   }
--- a/hotspot/src/share/vm/opto/macro.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/macro.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -594,7 +594,7 @@
 
     // Scan object's fields adding an input to the safepoint for each field.
     for (int j = 0; j < nfields; j++) {
-      int offset;
+      intptr_t offset;
       ciField* field = NULL;
       if (iklass != NULL) {
         field = iklass->nonstatic_field_at(j);
@@ -602,7 +602,7 @@
         elem_type = field->type();
         basic_elem_type = field->layout_type();
       } else {
-        offset = array_base + j * element_size;
+        offset = array_base + j * (intptr_t)element_size;
       }
 
       const Type *field_type;
--- a/hotspot/src/share/vm/opto/matcher.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/matcher.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1450,6 +1450,8 @@
   Node *leaf = s->_leaf;
   // Check for instruction or instruction chain rule
   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
+    assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
+           "duplicating node that's already been matched");
     // Instruction
     mach->add_req( leaf->in(0) ); // Set initial control
     // Reduce interior of complex instruction
@@ -1872,6 +1874,12 @@
 
         // Clone addressing expressions as they are "free" in most instructions
         if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
+          if (m->in(AddPNode::Base)->Opcode() == Op_DecodeN) {
+            // Bases used in addresses must be shared but since
+            // they are shared through a DecodeN they may appear
+            // to have a single use so force sharing here.
+            set_shared(m->in(AddPNode::Base)->in(1));
+          }
           Node *off = m->in(AddPNode::Offset);
           if( off->is_Con() ) {
             set_visited(m);  // Flag as visited now
--- a/hotspot/src/share/vm/opto/memnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/memnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -214,6 +214,9 @@
   Node *ctl = in(MemNode::Control);
   if (ctl && remove_dead_region(phase, can_reshape))
     return this;
+  ctl = in(MemNode::Control);
+  // Don't bother trying to transform a dead node
+  if( ctl && ctl->is_top() )  return NodeSentinel;
 
   // Ignore if memory is dead, or self-loop
   Node *mem = in(MemNode::Memory);
@@ -244,6 +247,7 @@
 
   if (mem != old_mem) {
     set_req(MemNode::Memory, mem);
+    if (phase->type( mem ) == Type::TOP) return NodeSentinel;
     return this;
   }
 
@@ -1231,6 +1235,10 @@
       // our new node, even though we may throw the node away.
       // (This tweaking with igvn only works because x is a new node.)
       igvn->set_type(x, t);
+      // If x is a TypeNode, capture any more-precise type permanently into Node
+      // othewise it will be not updated during igvn->transform since
+      // igvn->type(x) is set to x->Value() already.
+      x->raise_bottom_type(t);
       Node *y = x->Identity(igvn);
       if( y != x ) {
         wins++;
@@ -1312,6 +1320,7 @@
     Node* opt_mem = MemNode::optimize_memory_chain(mem, addr_t, phase);
     if (opt_mem != mem) {
       set_req(MemNode::Memory, opt_mem);
+      if (phase->type( opt_mem ) == Type::TOP) return NULL;
       return this;
     }
     const TypeOopPtr *t_oop = addr_t->isa_oopptr();
@@ -1409,7 +1418,7 @@
     // had an original form like p1:(AddP x x (LShiftL quux 3)), where the
     // expression (LShiftL quux 3) independently optimized to the constant 8.
     if ((t->isa_int() == NULL) && (t->isa_long() == NULL)
-        && Opcode() != Op_LoadKlass) {
+        && Opcode() != Op_LoadKlass && Opcode() != Op_LoadNKlass) {
       // t might actually be lower than _type, if _type is a unique
       // concrete subclass of abstract class t.
       // Make sure the reference is not into the header, by comparing
@@ -2443,8 +2452,7 @@
 // Return a node which is more "ideal" than the current node.  Strip out
 // control copies
 Node *MemBarNode::Ideal(PhaseGVN *phase, bool can_reshape) {
-  if (remove_dead_region(phase, can_reshape))  return this;
-  return NULL;
+  return remove_dead_region(phase, can_reshape) ? this : NULL;
 }
 
 //------------------------------Value------------------------------------------
--- a/hotspot/src/share/vm/opto/node.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/node.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1166,16 +1166,15 @@
 // using it dead as well.  This will happen normally via the usual IterGVN
 // worklist but this call is more efficient.  Do not update use-def info
 // inside the dead region, just at the borders.
-static bool kill_dead_code( Node *dead, PhaseIterGVN *igvn ) {
+static void kill_dead_code( Node *dead, PhaseIterGVN *igvn ) {
   // Con's are a popular node to re-hit in the hash table again.
-  if( dead->is_Con() ) return false;
+  if( dead->is_Con() ) return;
 
   // Can't put ResourceMark here since igvn->_worklist uses the same arena
   // for verify pass with +VerifyOpto and we add/remove elements in it here.
   Node_List  nstack(Thread::current()->resource_area());
 
   Node *top = igvn->C->top();
-  bool progress = false;
   nstack.push(dead);
 
   while (nstack.size() > 0) {
@@ -1214,7 +1213,6 @@
       for (uint i=0; i < dead->req(); i++) {
         Node *n = dead->in(i);      // Get input to dead guy
         if (n != NULL && !n->is_top()) { // Input is valid?
-          progress = true;
           dead->set_req(i, top);    // Smash input away
           if (n->outcnt() == 0) {   // Input also goes dead?
             if (!n->is_Con())
@@ -1233,7 +1231,7 @@
       }
     } // (dead->outcnt() == 0)
   }   // while (nstack.size() > 0) for outputs
-  return progress;
+  return;
 }
 
 //------------------------------remove_dead_region-----------------------------
@@ -1243,7 +1241,8 @@
   // Lost control into this guy?  I.e., it became unreachable?
   // Aggressively kill all unreachable code.
   if (can_reshape && n->is_top()) {
-    return kill_dead_code(this, phase->is_IterGVN());
+    kill_dead_code(this, phase->is_IterGVN());
+    return false; // Node is dead.
   }
 
   if( n->is_Region() && n->as_Region()->is_copy() ) {
--- a/hotspot/src/share/vm/opto/phaseX.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/phaseX.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -986,7 +986,9 @@
   // Apply the Ideal call in a loop until it no longer applies
   Node *k = n;
   DEBUG_ONLY(dead_loop_check(k);)
+  DEBUG_ONLY(bool is_new = (k->outcnt() == 0);)
   Node *i = k->Ideal(this, /*can_reshape=*/true);
+  assert(i != k || is_new || i->outcnt() > 0, "don't return dead nodes");
 #ifndef PRODUCT
   if( VerifyIterativeGVN )
     verify_step(k);
@@ -1024,7 +1026,9 @@
     }
     DEBUG_ONLY(dead_loop_check(k);)
     // Try idealizing again
+    DEBUG_ONLY(is_new = (k->outcnt() == 0);)
     i = k->Ideal(this, /*can_reshape=*/true);
+    assert(i != k || is_new || i->outcnt() > 0, "don't return dead nodes");
 #ifndef PRODUCT
     if( VerifyIterativeGVN )
       verify_step(k);
--- a/hotspot/src/share/vm/opto/reg_split.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/reg_split.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -284,7 +284,7 @@
       // Check for single-def (LRG cannot redefined)
       uint lidx = n2lidx(in);
       if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy
-      if( lrgs(lidx)._def != NodeSentinel ) continue;
+      if (lrgs(lidx).is_singledef()) continue;
 
       Block *b_def = _cfg._bbs[def->_idx];
       int idx_def = b_def->find_node(def);
@@ -311,12 +311,20 @@
       uint lidx = Find_id(in);
 
       // Walk backwards thru spill copy node intermediates
-      if( walkThru )
+      if (walkThru) {
         while ( in->is_SpillCopy() && lidx >= _maxlrg ) {
           in = in->in(1);
           lidx = Find_id(in);
         }
 
+        if (lidx < _maxlrg && lrgs(lidx).is_multidef()) {
+          // walkThru found a multidef LRG, which is unsafe to use, so
+          // just keep the original def used in the clone.
+          in = spill->in(i);
+          lidx = Find_id(in);
+        }
+      }
+
       if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) {
         Node *rdef = Reachblock[lrg2reach[lidx]];
         if( rdef ) spill->set_req(i,rdef);
@@ -505,7 +513,7 @@
       // Do not bother splitting or putting in Phis for single-def
       // rematerialized live ranges.  This happens alot to constants
       // with long live ranges.
-      if( lrgs(lidx)._def != NodeSentinel &&
+      if( lrgs(lidx).is_singledef() &&
           lrgs(lidx)._def->rematerialize() ) {
         // reset the Reaches & UP entries
         Reachblock[slidx] = lrgs(lidx)._def;
--- a/hotspot/src/share/vm/opto/subnode.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/subnode.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -633,20 +633,31 @@
         kps != 1 &&             // both or neither are klass pointers
         !klass0->is_interface() && // do not trust interfaces
         !klass1->is_interface()) {
+      bool unrelated_classes = false;
       // See if neither subclasses the other, or if the class on top
-      // is precise.  In either of these cases, the compare must fail.
+      // is precise.  In either of these cases, the compare is known
+      // to fail if at least one of the pointers is provably not null.
       if (klass0->equals(klass1)   ||   // if types are unequal but klasses are
           !klass0->is_java_klass() ||   // types not part of Java language?
           !klass1->is_java_klass()) {   // types not part of Java language?
         // Do nothing; we know nothing for imprecise types
       } else if (klass0->is_subtype_of(klass1)) {
-        // If klass1's type is PRECISE, then we can fail.
-        if (xklass1)  return TypeInt::CC_GT;
+        // If klass1's type is PRECISE, then classes are unrelated.
+        unrelated_classes = xklass1;
       } else if (klass1->is_subtype_of(klass0)) {
-        // If klass0's type is PRECISE, then we can fail.
-        if (xklass0)  return TypeInt::CC_GT;
+        // If klass0's type is PRECISE, then classes are unrelated.
+        unrelated_classes = xklass0;
       } else {                  // Neither subtypes the other
-        return TypeInt::CC_GT;  // ...so always fail
+        unrelated_classes = true;
+      }
+      if (unrelated_classes) {
+        // The oops classes are known to be unrelated. If the joined PTRs of
+        // two oops is not Null and not Bottom, then we are sure that one
+        // of the two oops is non-null, and the comparison will always fail.
+        TypePtr::PTR jp = r0->join_ptr(r1->_ptr);
+        if (jp != TypePtr::Null && jp != TypePtr::BotPTR) {
+          return TypeInt::CC_GT;
+        }
       }
     }
   }
@@ -681,7 +692,11 @@
 
   // Now check for LoadKlass on left.
   Node* ldk1 = in(1);
-  if (ldk1->Opcode() != Op_LoadKlass)
+  if (ldk1->is_DecodeN()) {
+    ldk1 = ldk1->in(1);
+    if (ldk1->Opcode() != Op_LoadNKlass )
+      return NULL;
+  } else if (ldk1->Opcode() != Op_LoadKlass )
     return NULL;
   // Take apart the address of the LoadKlass:
   Node* adr1 = ldk1->in(MemNode::Address);
@@ -702,7 +717,11 @@
 
   // Check for a LoadKlass from primary supertype array.
   // Any nested loadklass from loadklass+con must be from the p.s. array.
-  if (ldk2->Opcode() != Op_LoadKlass)
+  if (ldk2->is_DecodeN()) {
+    // Keep ldk2 as DecodeN since it could be used in CmpP below.
+    if (ldk2->in(1)->Opcode() != Op_LoadNKlass )
+      return NULL;
+  } else if (ldk2->Opcode() != Op_LoadKlass)
     return NULL;
 
   // Verify that we understand the situation
@@ -769,20 +788,31 @@
         kps != 1 &&             // both or neither are klass pointers
         !klass0->is_interface() && // do not trust interfaces
         !klass1->is_interface()) {
+      bool unrelated_classes = false;
       // See if neither subclasses the other, or if the class on top
-      // is precise.  In either of these cases, the compare must fail.
+      // is precise.  In either of these cases, the compare is known
+      // to fail if at least one of the pointers is provably not null.
       if (klass0->equals(klass1)   ||   // if types are unequal but klasses are
           !klass0->is_java_klass() ||   // types not part of Java language?
           !klass1->is_java_klass()) {   // types not part of Java language?
         // Do nothing; we know nothing for imprecise types
       } else if (klass0->is_subtype_of(klass1)) {
-        // If klass1's type is PRECISE, then we can fail.
-        if (xklass1)  return TypeInt::CC_GT;
+        // If klass1's type is PRECISE, then classes are unrelated.
+        unrelated_classes = xklass1;
       } else if (klass1->is_subtype_of(klass0)) {
-        // If klass0's type is PRECISE, then we can fail.
-        if (xklass0)  return TypeInt::CC_GT;
+        // If klass0's type is PRECISE, then classes are unrelated.
+        unrelated_classes = xklass0;
       } else {                  // Neither subtypes the other
-        return TypeInt::CC_GT;  // ...so always fail
+        unrelated_classes = true;
+      }
+      if (unrelated_classes) {
+        // The oops classes are known to be unrelated. If the joined PTRs of
+        // two oops is not Null and not Bottom, then we are sure that one
+        // of the two oops is non-null, and the comparison will always fail.
+        TypePtr::PTR jp = r0->join_ptr(r1->_ptr);
+        if (jp != TypePtr::Null && jp != TypePtr::BotPTR) {
+          return TypeInt::CC_GT;
+        }
       }
     }
   }
--- a/hotspot/src/share/vm/opto/type.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/type.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -804,6 +804,7 @@
   case InstPtr:
   case KlassPtr:
   case AryPtr:
+  case NarrowOop:
   case Int:
   case Long:
   case DoubleTop:
@@ -1955,14 +1956,25 @@
   return new TypePtr( AnyPtr, dual_ptr(), dual_offset() );
 }
 
+//------------------------------xadd_offset------------------------------------
+int TypePtr::xadd_offset( intptr_t offset ) const {
+  // Adding to 'TOP' offset?  Return 'TOP'!
+  if( _offset == OffsetTop || offset == OffsetTop ) return OffsetTop;
+  // Adding to 'BOTTOM' offset?  Return 'BOTTOM'!
+  if( _offset == OffsetBot || offset == OffsetBot ) return OffsetBot;
+  // Addition overflows or "accidentally" equals to OffsetTop? Return 'BOTTOM'!
+  offset += (intptr_t)_offset;
+  if (offset != (int)offset || offset == OffsetTop) return OffsetBot;
+
+  // assert( _offset >= 0 && _offset+offset >= 0, "" );
+  // It is possible to construct a negative offset during PhaseCCP
+
+  return (int)offset;        // Sum valid offsets
+}
+
 //------------------------------add_offset-------------------------------------
-const TypePtr *TypePtr::add_offset( int offset ) const {
-  if( offset == 0 ) return this; // No change
-  if( _offset == OffsetBot ) return this;
-  if(  offset == OffsetBot ) offset = OffsetBot;
-  else if( _offset == OffsetTop || offset == OffsetTop ) offset = OffsetTop;
-  else offset += _offset;
-  return make( AnyPtr, _ptr, offset );
+const TypePtr *TypePtr::add_offset( intptr_t offset ) const {
+  return make( AnyPtr, _ptr, xadd_offset(offset) );
 }
 
 //------------------------------eq---------------------------------------------
@@ -2095,7 +2107,7 @@
 }
 
 //------------------------------add_offset-------------------------------------
-const TypePtr *TypeRawPtr::add_offset( int offset ) const {
+const TypePtr *TypeRawPtr::add_offset( intptr_t offset ) const {
   if( offset == OffsetTop ) return BOTTOM; // Undefined offset-> undefined pointer
   if( offset == OffsetBot ) return BOTTOM; // Unknown offset-> unknown pointer
   if( offset == 0 ) return this; // No change
@@ -2263,6 +2275,7 @@
   case DoubleTop:
   case DoubleCon:
   case DoubleBot:
+  case NarrowOop:
   case Bottom:                  // Ye Olde Default
     return Type::BOTTOM;
   case Top:
@@ -2543,21 +2556,8 @@
   return (_offset == 0) && !below_centerline(_ptr);
 }
 
-//------------------------------xadd_offset------------------------------------
-int TypeOopPtr::xadd_offset( int offset ) const {
-  // Adding to 'TOP' offset?  Return 'TOP'!
-  if( _offset == OffsetTop || offset == OffsetTop ) return OffsetTop;
-  // Adding to 'BOTTOM' offset?  Return 'BOTTOM'!
-  if( _offset == OffsetBot || offset == OffsetBot ) return OffsetBot;
-
-  // assert( _offset >= 0 && _offset+offset >= 0, "" );
-  // It is possible to construct a negative offset during PhaseCCP
-
-  return _offset+offset;        // Sum valid offsets
-}
-
 //------------------------------add_offset-------------------------------------
-const TypePtr *TypeOopPtr::add_offset( int offset ) const {
+const TypePtr *TypeOopPtr::add_offset( intptr_t offset ) const {
   return make( _ptr, xadd_offset(offset) );
 }
 
@@ -3074,7 +3074,7 @@
 #endif
 
 //------------------------------add_offset-------------------------------------
-const TypePtr *TypeInstPtr::add_offset( int offset ) const {
+const TypePtr *TypeInstPtr::add_offset( intptr_t offset ) const {
   return make( _ptr, klass(), klass_is_exact(), const_oop(), xadd_offset(offset), _instance_id );
 }
 
@@ -3425,7 +3425,7 @@
 }
 
 //------------------------------add_offset-------------------------------------
-const TypePtr *TypeAryPtr::add_offset( int offset ) const {
+const TypePtr *TypeAryPtr::add_offset( intptr_t offset ) const {
   return make( _ptr, _const_oop, _ary, _klass, _klass_is_exact, xadd_offset(offset), _instance_id );
 }
 
@@ -3465,7 +3465,7 @@
   return _ooptype->empty();
 }
 
-//------------------------------meet-------------------------------------------
+//------------------------------xmeet------------------------------------------
 // Compute the MEET of two types.  It returns a new Type object.
 const Type *TypeNarrowOop::xmeet( const Type *t ) const {
   // Perform a fast test for common case; meeting the same types together.
@@ -3483,6 +3483,13 @@
   case DoubleTop:
   case DoubleCon:
   case DoubleBot:
+  case AnyPtr:
+  case RawPtr:
+  case OopPtr:
+  case InstPtr:
+  case KlassPtr:
+  case AryPtr:
+
   case Bottom:                  // Ye Olde Default
     return Type::BOTTOM;
   case Top:
@@ -3499,16 +3506,9 @@
   default:                      // All else is a mistake
     typerr(t);
 
-  case RawPtr:
-  case AnyPtr:
-  case OopPtr:
-  case InstPtr:
-  case KlassPtr:
-  case AryPtr:
-    typerr(t);
-    return Type::BOTTOM;
-
   } // End of switch
+
+  return this;
 }
 
 const Type *TypeNarrowOop::xdual() const {    // Compute dual right now.
@@ -3652,7 +3652,7 @@
 
 //------------------------------add_offset-------------------------------------
 // Access internals of klass object
-const TypePtr *TypeKlassPtr::add_offset( int offset ) const {
+const TypePtr *TypeKlassPtr::add_offset( intptr_t offset ) const {
   return make( _ptr, klass(), xadd_offset(offset) );
 }
 
@@ -3702,6 +3702,7 @@
   case DoubleTop:
   case DoubleCon:
   case DoubleBot:
+  case NarrowOop:
   case Bottom:                  // Ye Olde Default
     return Type::BOTTOM;
   case Top:
--- a/hotspot/src/share/vm/opto/type.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/opto/type.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -581,7 +581,8 @@
 
   virtual intptr_t get_con() const;
 
-  virtual const TypePtr *add_offset( int offset ) const;
+  int xadd_offset( intptr_t offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
 
   virtual bool singleton(void) const;    // TRUE if type is a singleton
   virtual bool empty(void) const;        // TRUE if type is vacuous
@@ -632,7 +633,7 @@
 
   virtual intptr_t get_con() const;
 
-  virtual const TypePtr *add_offset( int offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
 
   virtual const Type *xmeet( const Type *t ) const;
   virtual const Type *xdual() const;    // Compute dual right now.
@@ -659,7 +660,6 @@
   };
 protected:
 
-  int xadd_offset( int offset ) const;
   // Oop is NULL, unless this is a constant oop.
   ciObject*     _const_oop;   // Constant oop
   // If _klass is NULL, then so is _sig.  This is an unloaded klass.
@@ -724,7 +724,7 @@
   // corresponding pointer to klass, for a given instance
   const TypeKlassPtr* as_klass_type() const;
 
-  virtual const TypePtr *add_offset( int offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
 
   virtual const Type *xmeet( const Type *t ) const;
   virtual const Type *xdual() const;    // Compute dual right now.
@@ -793,7 +793,7 @@
 
   virtual const TypeOopPtr *cast_to_instance_id(int instance_id) const;
 
-  virtual const TypePtr *add_offset( int offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
 
   virtual const Type *xmeet( const Type *t ) const;
   virtual const TypeInstPtr *xmeet_unloaded( const TypeInstPtr *t ) const;
@@ -842,7 +842,7 @@
   virtual const TypeAryPtr* cast_to_size(const TypeInt* size) const;
 
   virtual bool empty(void) const;        // TRUE if type is vacuous
-  virtual const TypePtr *add_offset( int offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
 
   virtual const Type *xmeet( const Type *t ) const;
   virtual const Type *xdual() const;    // Compute dual right now.
@@ -896,7 +896,7 @@
   // corresponding pointer to instance, for a given class
   const TypeOopPtr* as_instance_type() const;
 
-  virtual const TypePtr *add_offset( int offset ) const;
+  virtual const TypePtr *add_offset( intptr_t offset ) const;
   virtual const Type    *xmeet( const Type *t ) const;
   virtual const Type    *xdual() const;      // Compute dual right now.
 
--- a/hotspot/src/share/vm/runtime/globals.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/runtime/globals.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1443,7 +1443,7 @@
           "CMSPrecleanNumerator:CMSPrecleanDenominator yields convergence"  \
           " ratio")                                                         \
                                                                             \
-  product(bool, CMSPrecleanRefLists1, true,                                 \
+  product(bool, CMSPrecleanRefLists1, false,                                \
           "Preclean ref lists during (initial) preclean phase")             \
                                                                             \
   product(bool, CMSPrecleanRefLists2, false,                                \
--- a/hotspot/src/share/vm/runtime/vmStructs.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/runtime/vmStructs.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -583,7 +583,7 @@
   /***********************************/                                                                                              \
                                                                                                                                      \
      static_field(StubRoutines,                _call_stub_return_address,                     address)                               \
-     IA32_ONLY(static_field(StubRoutines::i486,_call_stub_compiled_return,                    address))                              \
+     IA32_ONLY(static_field(StubRoutines::x86,_call_stub_compiled_return,                     address))                              \
                                                                                                                                      \
   /***************************************/                                                                                          \
   /* PcDesc and other compiled code info */                                                                                          \
@@ -1107,7 +1107,7 @@
                                                                           \
   declare_toplevel_type(StubQueue)                                        \
   declare_toplevel_type(StubRoutines)                                     \
-  IA32_ONLY(declare_toplevel_type(StubRoutines::i486))                    \
+  IA32_ONLY(declare_toplevel_type(StubRoutines::x86))                     \
   declare_toplevel_type(Stub)                                             \
            declare_type(InterpreterCodelet, Stub)                         \
                                                                           \
--- a/hotspot/src/share/vm/utilities/macros.hpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/hotspot/src/share/vm/utilities/macros.hpp	Wed Jul 05 16:41:01 2017 +0200
@@ -144,6 +144,14 @@
 #define NOT_WINDOWS(code) code
 #endif
 
+#if defined(IA32) || defined(AMD64)
+#define X86
+#define X86_ONLY(code) code
+#else
+#undef X86
+#define X86_ONLY(code)
+#endif
+
 #ifdef IA32
 #define IA32_ONLY(code) code
 #define NOT_IA32(code)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/test/compiler/6741738/Tester.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/*
+ * @test
+ * @bug 6741738
+ * @summary TypePtr::add_offset() set incorrect offset when the add overflows
+ * @run main/othervm -Xcomp -XX:CompileOnly=Tester.foo Tester
+ */
+
+public class Tester {
+        private String[] values;
+        private int count;
+
+        String foo() {
+                int i = Integer.MAX_VALUE-1;
+                String s;
+                try {
+                    s = values[i];
+                } catch (Throwable e) {
+                    s = "";
+                }
+                return s;
+        }
+
+        public static void main(String[] args) {
+                Tester t = new Tester();
+                String s = t.foo();
+        }
+}
--- a/jaxp/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/jaxp/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 255d64ee287e926e8629dd80bc67690e65eeba30 jdk7-b31
 400a5ee432cc2db9031e06852ddde9264a192b48 jdk7-b32
 95375835527f0bf06124ce984266e2ad5de8a6dc jdk7-b33
+01facdf8cabdeaaf68cca037aef56cc5f074897f jdk7-b34
--- a/jaxws/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/jaxws/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 f978623825364a2ad9c6f51d02fc9424a8b0bc86 jdk7-b31
 e6daca2eced9d84b01255cabcfcc49164c26405e jdk7-b32
 6dcbcfb9551aaa2a80906c28ab48c9a8564e0e64 jdk7-b33
+7a9f629cd957e3169a1a769f763fe060d078785c jdk7-b34
--- a/jdk/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 b7474b739d13bacd9972f88ac91f6350b7b0be12 jdk7-b31
 c51121419e30eac5f0fbbce45ff1711c4ce0de28 jdk7-b32
 fa4c0a6cdd25d97d4e6f5d7aa180bcbb0e0d56af jdk7-b33
+434055a0716ee44bca712ebca02fc04b20e6e288 jdk7-b34
--- a/jdk/make/common/Defs.gmk	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/make/common/Defs.gmk	Wed Jul 05 16:41:01 2017 +0200
@@ -451,7 +451,7 @@
 # namely jni.h, jvm.h, and jni_utils.h, plus their platform-specific
 # relatives.
 #
-VPATH.h =   $(PLATFORM_SRC)/javavm/export$(CLASSPATH_SEPARATOR)$(SHARE_SRC)/javavm/export$(CLASSPATH_SEPARATOR)$(SHARE_SRC)/javavm/include$(CLASSPATH_SEPARATOR)$(PLATFORM_SRC)/javavm/include
+VPATH.h =   $(PLATFORM_SRC)/javavm/export$(CLASSPATH_SEPARATOR)$(SHARE_SRC)/javavm/export
 vpath %.h   $(VPATH.h)
 
 #
--- a/jdk/make/java/net/mapfile-vers	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/make/java/net/mapfile-vers	Wed Jul 05 16:41:01 2017 +0200
@@ -57,7 +57,7 @@
 		Java_java_net_Inet6AddressImpl_isReachable0;
 		Java_java_net_NetworkInterface_init;
 		Java_java_net_NetworkInterface_getByName0;
-		Java_java_net_NetworkInterface_getByIndex;
+		Java_java_net_NetworkInterface_getByIndex0;
 		Java_java_net_NetworkInterface_getByInetAddress0;
 		Java_java_net_NetworkInterface_getAll;
 		Java_java_net_NetworkInterface_isUp0;
--- a/jdk/make/java/verify/Makefile	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/make/java/verify/Makefile	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 #
-# Copyright 1999-2005 Sun Microsystems, Inc.  All Rights Reserved.
+# Copyright 1999-2008 Sun Microsystems, Inc.  All Rights Reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -53,12 +53,6 @@
 	check_format.c
 
 #
-# libverify.so needs these 2 header files (opcodes.h opcodes.length) 
-# from the VM.
-#
-CPPFLAGS += -I$(SHARE_SRC)/javavm/include 
-
-#
 # Targets.
 #
 ifeq ($(PLATFORM), solaris)
--- a/jdk/make/netbeans/awt2d/README	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/make/netbeans/awt2d/README	Wed Jul 05 16:41:01 2017 +0200
@@ -145,7 +145,6 @@
   (a somewhat complete list of awt and 2d native directories on windows):
 
   ../../src/share/javavm/export;
-  ../../src/share/javavm/include;
   ../../src/share/native/common;
   ../../src/share/native/sun/awt/debug;
   ../../src/share/native/sun/awt/image/cvutils;
--- a/jdk/make/tools/GenerateCharacter/check_class.c.template	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/make/tools/GenerateCharacter/check_class.c.template	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2002 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2002-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -37,7 +37,6 @@
 #include "bool.h"
 #include "utf.h"
 #include "tree.h"
-#include "sys_api.h"
 
 extern bool_t verify_class_codes(ClassClass *cb);
 
--- a/jdk/src/share/back/debugDispatch.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/back/debugDispatch.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -41,7 +41,6 @@
 #include "ArrayReferenceImpl.h"
 #include "EventRequestImpl.h"
 #include "StackFrameImpl.h"
-#include "typedefs.h"
 
 static void **l1Array;
 
--- a/jdk/src/share/back/error_messages.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/back/error_messages.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2003-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -48,7 +48,6 @@
 
 #include "util.h"
 #include "proc_md.h"
-#include "typedefs.h"
 
 /* Maximim length of a message */
 #define MAX_MESSAGE_LEN MAXPATHLEN*2+512
--- a/jdk/src/share/back/inStream.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/back/inStream.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2006 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -30,7 +30,6 @@
 #include "bag.h"
 #include "commonRef.h"
 #include "FrameID.h"
-#include "typedefs.h"
 
 #define INITIAL_REF_ALLOC 50
 #define SMALLEST(a, b) ((a) < (b)) ? (a) : (b)
--- a/jdk/src/share/back/outStream.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/back/outStream.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,8 +26,6 @@
 #ifndef JDWP_OUTSTREAM_H
 #define JDWP_OUTSTREAM_H
 
-#include "typedefs.h"
-
 #include "transport.h"
 #include "FrameID.h"
 
--- a/jdk/src/share/classes/java/net/NetworkInterface.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/java/net/NetworkInterface.java	Wed Jul 05 16:41:01 2017 +0200
@@ -203,11 +203,17 @@
     }
 
     /**
-     * Get the index of this network interface.
+     * Returns the index of this network interface. The index is an integer greater
+     * or equal to zero, or {@code -1} for unknown. This is a system specific value
+     * and interfaces with the same name can have different indexes on different
+     * machines.
      *
-     * @return the index of this network interface
+     * @return the index of this network interface or {@code -1} if the index is
+     *         unknown
+     * @see #getByIndex(int)
+     * @since 1.7
      */
-    int getIndex() {
+    public int getIndex() {
         return index;
     }
 
@@ -249,11 +255,18 @@
      * Get a network interface given its index.
      *
      * @param index an integer, the index of the interface
-     * @return the NetworkInterface obtained from its index
-     * @exception  SocketException  if an I/O error occurs.
+     * @return the NetworkInterface obtained from its index, or {@code null} if
+     *         there is no interface with such an index on the system
+     * @throws  SocketException  if an I/O error occurs.
+     * @throws  IllegalArgumentException if index has a negative value
+     * @see #getIndex()
+     * @since 1.7
      */
-    native static NetworkInterface getByIndex(int index)
-        throws SocketException;
+    public static NetworkInterface getByIndex(int index) throws SocketException {
+        if (index < 0)
+            throw new IllegalArgumentException("Interface index can't be negative");
+        return getByIndex0(index);
+    }
 
     /**
      * Convenience method to search for a network interface that
@@ -325,6 +338,9 @@
     private native static NetworkInterface getByName0(String name)
         throws SocketException;
 
+    private native static NetworkInterface getByIndex0(int index)
+        throws SocketException;
+
     private native static NetworkInterface getByInetAddress0(InetAddress addr)
         throws SocketException;
 
--- a/jdk/src/share/classes/java/net/ServerSocket.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/java/net/ServerSocket.java	Wed Jul 05 16:41:01 2017 +0200
@@ -142,14 +142,18 @@
      * as its argument to ensure the operation is allowed.
      * This could result in a SecurityException.
      *
-     * <P>The <code>backlog</code> argument must be a positive
-     * value greater than 0. If the value passed is equal or less
-     * than 0, then the default value will be assumed.
+     * The <code>backlog</code> argument is the requested maximum number of
+     * pending connections on the socket. Its exact semantics are implementation
+     * specific. In particular, an implementation may impose a maximum length
+     * or may choose to ignore the parameter altogther. The value provided
+     * should be greater than <code>0</code>. If it is less than or equal to
+     * <code>0</code>, then an implementation specific default will be used.
      * <P>
      *
      * @param      port     the port number, or <code>0</code> to use a port
      *                      number that is automatically allocated.
-     * @param      backlog  the maximum length of the queue.
+     * @param      backlog  requested maximum length of the queue of incoming
+     *                      connections.
      *
      * @exception  IOException  if an I/O error occurs when opening the socket.
      * @exception  SecurityException
@@ -187,13 +191,17 @@
      * as its argument to ensure the operation is allowed.
      * This could result in a SecurityException.
      *
-     * <P>The <code>backlog</code> argument must be a positive
-     * value greater than 0. If the value passed is equal or less
-     * than 0, then the default value will be assumed.
+     * The <code>backlog</code> argument is the requested maximum number of
+     * pending connections on the socket. Its exact semantics are implementation
+     * specific. In particular, an implementation may impose a maximum length
+     * or may choose to ignore the parameter altogther. The value provided
+     * should be greater than <code>0</code>. If it is less than or equal to
+     * <code>0</code>, then an implementation specific default will be used.
      * <P>
      * @param port  the port number, or <code>0</code> to use a port
      *              number that is automatically allocated.
-     * @param backlog the listen backlog
+     * @param backlog requested maximum length of the queue of incoming
+     *                connections.
      * @param bindAddr the local InetAddress the server will bind to
      *
      * @throws  SecurityException if a security manager exists and
@@ -321,11 +329,15 @@
      * If the address is <code>null</code>, then the system will pick up
      * an ephemeral port and a valid local address to bind the socket.
      * <P>
-     * The <code>backlog</code> argument must be a positive
-     * value greater than 0. If the value passed is equal or less
-     * than 0, then the default value will be assumed.
+     * The <code>backlog</code> argument is the requested maximum number of
+     * pending connections on the socket. Its exact semantics are implementation
+     * specific. In particular, an implementation may impose a maximum length
+     * or may choose to ignore the parameter altogther. The value provided
+     * should be greater than <code>0</code>. If it is less than or equal to
+     * <code>0</code>, then an implementation specific default will be used.
      * @param   endpoint        The IP address & port number to bind to.
-     * @param   backlog         The listen backlog length.
+     * @param   backlog         requested maximum length of the queue of
+     *                          incoming connections.
      * @throws  IOException if the bind operation fails, or if the socket
      *                     is already bound.
      * @throws  SecurityException       if a <code>SecurityManager</code> is present and
--- a/jdk/src/share/classes/java/util/EnumSet.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/java/util/EnumSet.java	Wed Jul 05 16:41:01 2017 +0200
@@ -432,4 +432,11 @@
     Object writeReplace() {
         return new SerializationProxy<E>(this);
     }
+
+    // readObject method for the serialization proxy pattern
+    // See Effective Java, Second Ed., Item 78.
+    private void readObject(java.io.ObjectInputStream stream)
+        throws java.io.InvalidObjectException {
+        throw new java.io.InvalidObjectException("Proxy required");
+    }
 }
--- a/jdk/src/share/classes/javax/net/ssl/SSLServerSocket.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/javax/net/ssl/SSLServerSocket.java	Wed Jul 05 16:41:01 2017 +0200
@@ -108,9 +108,12 @@
      * <P>
      * A port number of <code>0</code> creates a socket on any free port.
      * <P>
-     * The <code>backlog</code> argument must be a positive
-     * value greater than 0. If the value passed if equal or less
-     * than 0, then the default value will be assumed.
+     * The <code>backlog</code> argument is the requested maximum number of
+     * pending connections on the socket. Its exact semantics are implementation
+     * specific. In particular, an implementation may impose a maximum length
+     * or may choose to ignore the parameter altogther. The value provided
+     * should be greater than <code>0</code>. If it is less than or equal to
+     * <code>0</code>, then an implementation specific default will be used.
      * <P>
      * If there is a security manager, its <code>checkListen</code>
      * method is called with the <code>port</code> argument as its
@@ -118,8 +121,8 @@
      * in a SecurityException.
      *
      * @param port the port on which to listen
-     * @param backlog how many connections may be pending before
-     *          the system should start rejecting new requests
+     * @param backlog  requested maximum length of the queue of incoming
+     *                  connections.
      * @throws IOException if an I/O error occurs when creating the socket
      * @throws SecurityException if a security manager exists and its
      *         <code>checkListen</code> method doesn't allow the operation.
@@ -150,16 +153,19 @@
      * <P>
      * A port number of <code>0</code> creates a socket on any free port.
      * <P>
-     * <P>The <code>backlog</code> argument must be a positive
-     * value greater than 0. If the value passed if equal or less
-     * than 0, then the default value will be assumed.
+     * The <code>backlog</code> argument is the requested maximum number of
+     * pending connections on the socket. Its exact semantics are implementation
+     * specific. In particular, an implementation may impose a maximum length
+     * or may choose to ignore the parameter altogther. The value provided
+     * should be greater than <code>0</code>. If it is less than or equal to
+     * <code>0</code>, then an implementation specific default will be used.
      * <P>
      * If <i>address</i> is null, it will default accepting connections
      * on any/all local addresses.
      *
      * @param port the port on which to listen
-     * @param backlog how many connections may be pending before
-     *          the system should start rejecting new requests
+     * @param backlog  requested maximum length of the queue of incoming
+     *                  connections.
      * @param address the address of the network interface through
      *          which connections will be accepted
      * @throws IOException if an I/O error occurs when creating the socket
--- a/jdk/src/share/classes/sun/nio/cs/UTF_8.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/sun/nio/cs/UTF_8.java	Wed Jul 05 16:41:01 2017 +0200
@@ -25,34 +25,36 @@
 
 package sun.nio.cs;
 
+import java.nio.Buffer;
 import java.nio.ByteBuffer;
 import java.nio.CharBuffer;
-import java.nio.BufferOverflowException;
-import java.nio.BufferUnderflowException;
 import java.nio.charset.Charset;
 import java.nio.charset.CharsetDecoder;
 import java.nio.charset.CharsetEncoder;
 import java.nio.charset.CoderResult;
-import java.nio.charset.CharacterCodingException;
-import java.nio.charset.MalformedInputException;
-import java.nio.charset.UnmappableCharacterException;
 
-
-/*
- * # Bits   Bit pattern
- * 1    7   0xxxxxxx
- * 2   11   110xxxxx 10xxxxxx
- * 3   16   1110xxxx 10xxxxxx 10xxxxxx
- * 4   21   11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
- * 5   26   111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
- * 6   31   1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
+/* Legal UTF-8 Byte Sequences
+ *
+ * #    Code Points      Bits   Bit/Byte pattern
+ * 1                     7      0xxxxxxx
+ *      U+0000..U+007F          00..7F
+ *
+ * 2                     11     110xxxxx    10xxxxxx
+ *      U+0080..U+07FF          C2..DF      80..BF
  *
- * UCS-2 uses 1-3, UTF-16 uses 1-4, UCS-4 uses 1-6
+ * 3                     16     1110xxxx    10xxxxxx    10xxxxxx
+ *      U+0800..U+0FFF          E0          A0..BF      80..BF
+ *      U+1000..U+FFFF          E1..EF      80..BF      80..BF
+ *
+ * 4                     21     11110xxx    10xxxxxx    10xxxxxx    10xxxxxx
+ *     U+10000..U+3FFFF         F0          90..BF      80..BF      80..BF
+ *     U+40000..U+FFFFF         F1..F3      80..BF      80..BF      80..BF
+ *    U+100000..U10FFFF         F4          80..8F      80..BF      80..BF
+ *
  */
 
 class UTF_8 extends Unicode
 {
-
     public UTF_8() {
         super("UTF-8", StandardCharsets.aliases_UTF_8);
     }
@@ -69,304 +71,250 @@
         return new Encoder(this);
     }
 
+    static final void updatePositions(Buffer src, int sp,
+                                      Buffer dst, int dp) {
+        src.position(sp - src.arrayOffset());
+        dst.position(dp - dst.arrayOffset());
+    }
 
     private static class Decoder extends CharsetDecoder {
         private Decoder(Charset cs) {
             super(cs, 1.0f, 1.0f);
         }
 
-        private boolean isContinuation(int b) {
-            return ((b & 0xc0) == 0x80);
+        private static boolean isNotContinuation(int b) {
+            return (b & 0xc0) != 0x80;
+        }
+
+        //  [C2..DF] [80..BF]
+        private static boolean isMalformed2(int b1, int b2) {
+            return (b1 & 0x1e) == 0x0 || (b2 & 0xc0) != 0x80;
+        }
+
+        //  [E0]     [A0..BF] [80..BF]
+        //  [E1..EF] [80..BF] [80..BF]
+        private static boolean isMalformed3(int b1, int b2, int b3) {
+            return (b1 == (byte)0xe0 && (b2 & 0xe0) == 0x80) ||
+                   (b2 & 0xc0) != 0x80 || (b3 & 0xc0) != 0x80;
+        }
+
+        //  [F0]     [90..BF] [80..BF] [80..BF]
+        //  [F1..F3] [80..BF] [80..BF] [80..BF]
+        //  [F4]     [80..8F] [80..BF] [80..BF]
+        //  only check 80-be range here, the [0xf0,0x80...] and [0xf4,0x90-...]
+        //  will be checked by Surrogate.neededFor(uc)
+        private static boolean isMalformed4(int b2, int b3, int b4) {
+            return (b2 & 0xc0) != 0x80 || (b3 & 0xc0) != 0x80 ||
+                   (b4 & 0xc0) != 0x80;
+        }
+
+        private static CoderResult lookupN(ByteBuffer src, int n)
+        {
+            for (int i = 1; i < n; i++) {
+               if (isNotContinuation(src.get()))
+                   return CoderResult.malformedForLength(i);
+            }
+            return CoderResult.malformedForLength(n);
         }
 
-        private final Surrogate.Generator sgg = new Surrogate.Generator();
+        private static CoderResult malformedN(ByteBuffer src, int nb) {
+            switch (nb) {
+            case 1:
+                int b1 = src.get();
+                if ((b1 >> 2) == -2) {
+                    // 5 bytes 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
+                    if (src.remaining() < 4)
+                        return CoderResult.UNDERFLOW;
+                    return lookupN(src, 5);
+                }
+                if ((b1 >> 1) == -2) {
+                    // 6 bytes 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
+                    if (src.remaining() < 5)
+                        return CoderResult.UNDERFLOW;
+                    return lookupN(src, 6);
+                }
+                return CoderResult.malformedForLength(1);
+            case 2:                    // always 1
+                return CoderResult.malformedForLength(1);
+            case 3:
+                b1 = src.get();
+                int b2 = src.get();    // no need to lookup b3
+                return CoderResult.malformedForLength(
+                    ((b1 == (byte)0xe0 && (b2 & 0xe0) == 0x80) ||
+                     isNotContinuation(b2))?1:2);
+            case 4:  // we don't care the speed here
+                b1 = src.get() & 0xff;
+                b2 = src.get() & 0xff;
+                if (b1 > 0xf4 ||
+                    (b1 == 0xf0 && (b2 < 0x90 || b2 > 0xbf)) ||
+                    (b1 == 0xf4 && (b2 & 0xf0) != 0x80) ||
+                    isNotContinuation(b2))
+                    return CoderResult.malformedForLength(1);
+                if (isNotContinuation(src.get()))
+                    return CoderResult.malformedForLength(2);
+                return CoderResult.malformedForLength(3);
+            default:
+                assert false;
+                return null;
+            }
+        }
+
+        private static CoderResult malformed(ByteBuffer src, int sp,
+                                             CharBuffer dst, int dp,
+                                             int nb)
+        {
+            src.position(sp - src.arrayOffset());
+            CoderResult cr = malformedN(src, nb);
+            updatePositions(src, sp, dst, dp);
+            return cr;
+        }
+
+        private static CoderResult malformed(ByteBuffer src,
+                                             int mark, int nb)
+        {
+            src.position(mark);
+            CoderResult cr = malformedN(src, nb);
+            src.position(mark);
+            return cr;
+        }
+
+        private static CoderResult xflow(Buffer src, int sp, int sl,
+                                         Buffer dst, int dp, int nb) {
+            updatePositions(src, sp, dst, dp);
+            return (nb == 0 || sl - sp < nb)
+                   ?CoderResult.UNDERFLOW:CoderResult.OVERFLOW;
+        }
+
+        private static CoderResult xflow(Buffer src, int mark, int nb) {
+            CoderResult cr = (nb == 0 || src.remaining() < (nb - 1))
+                             ?CoderResult.UNDERFLOW:CoderResult.OVERFLOW;
+            src.position(mark);
+            return cr;
+        }
 
         private CoderResult decodeArrayLoop(ByteBuffer src,
                                             CharBuffer dst)
         {
+            // This method is optimized for ASCII input.
             byte[] sa = src.array();
             int sp = src.arrayOffset() + src.position();
             int sl = src.arrayOffset() + src.limit();
-            assert (sp <= sl);
-            sp = (sp <= sl ? sp : sl);
+
             char[] da = dst.array();
             int dp = dst.arrayOffset() + dst.position();
             int dl = dst.arrayOffset() + dst.limit();
-            assert (dp <= dl);
-            dp = (dp <= dl ? dp : dl);
-
-            try {
-                while (sp < sl) {
-                    int b1 = sa[sp];
-                    int b2, b3;
-                    switch ((b1 >> 4) & 0x0f) {
-
-                    case 0: case 1: case 2: case 3:
-                    case 4: case 5: case 6: case 7:
-                        // 1 byte, 7 bits: 0xxxxxxx
-                        if (dl - dp < 1)
-                            return CoderResult.OVERFLOW;
-                        da[dp++] = (char)(b1 & 0x7f);
-                        sp++;
-                        continue;
+            int dlASCII = dp + Math.min(sl - sp, dl - dp);
 
-                    case 12: case 13:
-                        // 2 bytes, 11 bits: 110xxxxx 10xxxxxx
-                        if (sl - sp < 2)
-                            return CoderResult.UNDERFLOW;
-                        if (dl - dp < 1)
-                            return CoderResult.OVERFLOW;
-                        if (!isContinuation(b2 = sa[sp + 1]))
-                            return CoderResult.malformedForLength(1);
-                        da[dp++] = ((char)(((b1 & 0x1f) << 6) |
-                                           ((b2 & 0x3f) << 0)));
-                        sp += 2;
-                        continue;
-
-                    case 14:
-                        // 3 bytes, 16 bits: 1110xxxx 10xxxxxx 10xxxxxx
-                        if (sl - sp < 3)
-                            return CoderResult.UNDERFLOW;
-                        if (dl - dp < 1)
-                            return CoderResult.OVERFLOW;
-                        if (!isContinuation(b2 = sa[sp + 1]))
-                            return CoderResult.malformedForLength(1);
-                        if (!isContinuation(b3 = sa[sp + 2]))
-                            return CoderResult.malformedForLength(2);
-                        da[dp++] = ((char)(((b1 & 0x0f) << 12) |
-                                           ((b2 & 0x3f) << 06) |
-                                           ((b3 & 0x3f) << 0)));
-                        sp += 3;
-                        continue;
-
-                    case 15:
-                        // 4, 5, or 6 bytes
-
-                        int b4, b5, b6, uc, n;
-                        switch (b1 & 0x0f) {
+            // ASCII only loop
+            while (dp < dlASCII && sa[sp] >= 0)
+                da[dp++] = (char)sa[sp++];
 
-                        case 0: case 1: case 2: case 3:
-                        case 4: case 5: case 6: case 7:
-                            // 4 bytes, 21 bits
-                            if (sl - sp < 4)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = sa[sp + 1]))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = sa[sp + 2]))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = sa[sp + 3]))
-                                return CoderResult.malformedForLength(3);
-                            uc = (((b1 & 0x07) << 18) |
-                                  ((b2 & 0x3f) << 12) |
-                                  ((b3 & 0x3f) << 06) |
-                                  ((b4 & 0x3f) << 00));
-                            n = 4;
-                            break;
-
-                        case 8: case 9: case 10: case 11:
-                            // 5 bytes, 26 bits
-                            if (sl - sp < 5)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = sa[sp + 1]))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = sa[sp + 2]))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = sa[sp + 3]))
-                                return CoderResult.malformedForLength(3);
-                            if (!isContinuation(b5 = sa[sp + 4]))
-                                return CoderResult.malformedForLength(4);
-                            uc = (((b1 & 0x03) << 24) |
-                                  ((b2 & 0x3f) << 18) |
-                                  ((b3 & 0x3f) << 12) |
-                                  ((b4 & 0x3f) << 06) |
-                                  ((b5 & 0x3f) << 00));
-                            n = 5;
-                            break;
-
-                        case 12: case 13:
-                            // 6 bytes, 31 bits
-                            if (sl - sp < 6)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = sa[sp + 1]))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = sa[sp + 2]))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = sa[sp + 3]))
-                                return CoderResult.malformedForLength(3);
-                            if (!isContinuation(b5 = sa[sp + 4]))
-                                return CoderResult.malformedForLength(4);
-                            if (!isContinuation(b6 = sa[sp + 5]))
-                                return CoderResult.malformedForLength(5);
-                            uc = (((b1 & 0x01) << 30) |
-                                  ((b2 & 0x3f) << 24) |
-                                  ((b3 & 0x3f) << 18) |
-                                  ((b4 & 0x3f) << 12) |
-                                  ((b5 & 0x3f) << 06) |
-                                  ((b6 & 0x3f)));
-                            n = 6;
-                            break;
-
-                        default:
-                            return CoderResult.malformedForLength(1);
-
-                        }
-
-                        int gn = sgg.generate(uc, n, da, dp, dl);
-                        if (gn < 0)
-                            return sgg.error();
-                        dp += gn;
-                        sp += n;
-                        continue;
-
-                    default:
-                        return CoderResult.malformedForLength(1);
-
+            while (sp < sl) {
+                int b1 = sa[sp];
+                if (b1  >= 0) {
+                    // 1 byte, 7 bits: 0xxxxxxx
+                    if (dp >= dl)
+                        return xflow(src, sp, sl, dst, dp, 1);
+                    da[dp++] = (char)b1;
+                    sp++;
+                } else if ((b1 >> 5) == -2) {
+                    // 2 bytes, 11 bits: 110xxxxx 10xxxxxx
+                    if (sl - sp < 2 || dp >= dl)
+                        return xflow(src, sp, sl, dst, dp, 2);
+                    int b2 = sa[sp + 1];
+                    if (isMalformed2(b1, b2))
+                        return malformed(src, sp, dst, dp, 2);
+                    da[dp++] = (char) (((b1 << 6) ^ b2) ^ 0x0f80);
+                    sp += 2;
+                } else if ((b1 >> 4) == -2) {
+                    // 3 bytes, 16 bits: 1110xxxx 10xxxxxx 10xxxxxx
+                    if (sl - sp < 3 || dp >= dl)
+                        return xflow(src, sp, sl, dst, dp, 3);
+                    int b2 = sa[sp + 1];
+                    int b3 = sa[sp + 2];
+                    if (isMalformed3(b1, b2, b3))
+                        return malformed(src, sp, dst, dp, 3);
+                    da[dp++] = (char) (((b1 << 12) ^ (b2 << 6) ^ b3) ^ 0x1f80);
+                    sp += 3;
+                } else if ((b1 >> 3) == -2) {
+                    // 4 bytes, 21 bits: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
+                    if (sl - sp < 4 || dl - dp < 2)
+                        return xflow(src, sp, sl, dst, dp, 4);
+                    int b2 = sa[sp + 1];
+                    int b3 = sa[sp + 2];
+                    int b4 = sa[sp + 3];
+                    int uc = ((b1 & 0x07) << 18) |
+                             ((b2 & 0x3f) << 12) |
+                             ((b3 & 0x3f) << 06) |
+                             (b4 & 0x3f);
+                    if (isMalformed4(b2, b3, b4) ||
+                        !Surrogate.neededFor(uc)) {
+                        return malformed(src, sp, dst, dp, 4);
                     }
-
-                }
-
-                return CoderResult.UNDERFLOW;
-            } finally {
-                src.position(sp - src.arrayOffset());
-                dst.position(dp - dst.arrayOffset());
+                    da[dp++] = Surrogate.high(uc);
+                    da[dp++] = Surrogate.low(uc);
+                    sp += 4;
+                } else
+                    return malformed(src, sp, dst, dp, 1);
             }
+            return xflow(src, sp, sl, dst, dp, 0);
         }
 
         private CoderResult decodeBufferLoop(ByteBuffer src,
                                              CharBuffer dst)
         {
             int mark = src.position();
-            try {
-                while (src.hasRemaining()) {
-                    int b1 = src.get();
-                    int b2, b3;
-                    switch ((b1 >> 4) & 0x0f) {
-
-                    case 0: case 1: case 2: case 3:
-                    case 4: case 5: case 6: case 7:
-                        // 1 byte, 7 bits: 0xxxxxxx
-                        if (dst.remaining() < 1)
-                            return CoderResult.OVERFLOW;
-                        dst.put((char)b1);
-                        mark++;
-                        continue;
-
-                    case 12: case 13:
-                        // 2 bytes, 11 bits: 110xxxxx 10xxxxxx
-                        if (src.remaining() < 1)
-                            return CoderResult.UNDERFLOW;
-                        if (dst.remaining() < 1)
-                            return CoderResult.OVERFLOW;
-                        if (!isContinuation(b2 = src.get()))
-                            return CoderResult.malformedForLength(1);
-                        dst.put((char)(((b1 & 0x1f) << 6) |
-                                       ((b2 & 0x3f) << 0)));
-                        mark += 2;
-                        continue;
-
-                    case 14:
-                        // 3 bytes, 16 bits: 1110xxxx 10xxxxxx 10xxxxxx
-                        if (src.remaining() < 2)
-                            return CoderResult.UNDERFLOW;
-                        if (dst.remaining() < 1)
-                            return CoderResult.OVERFLOW;
-                        if (!isContinuation(b2 = src.get()))
-                            return CoderResult.malformedForLength(1);
-                        if (!isContinuation(b3 = src.get()))
-                            return CoderResult.malformedForLength(2);
-                        dst.put((char)(((b1 & 0x0f) << 12) |
-                                       ((b2 & 0x3f) << 06) |
-                                       ((b3 & 0x3f) << 0)));
-                        mark += 3;
-                        continue;
-
-                    case 15:
-                        // 4, 5, or 6 bytes
-
-                        int b4, b5, b6, uc, n;
-                        switch (b1 & 0x0f) {
-
-                        case 0: case 1: case 2: case 3:
-                        case 4: case 5: case 6: case 7:
-                            // 4 bytes, 21 bits
-                            if (src.remaining() < 3)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = src.get()))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = src.get()))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = src.get()))
-                                return CoderResult.malformedForLength(3);
-                            uc = (((b1 & 0x07) << 18) |
-                                  ((b2 & 0x3f) << 12) |
-                                  ((b3 & 0x3f) << 06) |
-                                  ((b4 & 0x3f) << 00));
-                            n = 4;
-                            break;
-
-                        case 8: case 9: case 10: case 11:
-                            // 5 bytes, 26 bits
-                            if (src.remaining() < 4)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = src.get()))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = src.get()))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = src.get()))
-                                return CoderResult.malformedForLength(3);
-                            if (!isContinuation(b5 = src.get()))
-                                return CoderResult.malformedForLength(4);
-                            uc = (((b1 & 0x03) << 24) |
-                                  ((b2 & 0x3f) << 18) |
-                                  ((b3 & 0x3f) << 12) |
-                                  ((b4 & 0x3f) << 06) |
-                                  ((b5 & 0x3f) << 00));
-                            n = 5;
-                            break;
-
-                        case 12: case 13:
-                            // 6 bytes, 31 bits
-                            if (src.remaining() < 5)
-                                return CoderResult.UNDERFLOW;
-                            if (!isContinuation(b2 = src.get()))
-                                return CoderResult.malformedForLength(1);
-                            if (!isContinuation(b3 = src.get()))
-                                return CoderResult.malformedForLength(2);
-                            if (!isContinuation(b4 = src.get()))
-                                return CoderResult.malformedForLength(3);
-                            if (!isContinuation(b5 = src.get()))
-                                return CoderResult.malformedForLength(4);
-                            if (!isContinuation(b6 = src.get()))
-                                return CoderResult.malformedForLength(5);
-                            uc = (((b1 & 0x01) << 30) |
-                                  ((b2 & 0x3f) << 24) |
-                                  ((b3 & 0x3f) << 18) |
-                                  ((b4 & 0x3f) << 12) |
-                                  ((b5 & 0x3f) << 06) |
-                                  ((b6 & 0x3f)));
-                            n = 6;
-                            break;
-
-                        default:
-                            return CoderResult.malformedForLength(1);
-
-                        }
-
-                        if (sgg.generate(uc, n, dst) < 0)
-                            return sgg.error();
-                        mark += n;
-                        continue;
-
-                    default:
-                        return CoderResult.malformedForLength(1);
-
+            int limit = src.limit();
+            while (mark < limit) {
+                int b1 = src.get();
+                if (b1 >= 0) {
+                    // 1 byte, 7 bits: 0xxxxxxx
+                    if (dst.remaining() < 1)
+                        return xflow(src, mark, 1);  //overflow
+                    dst.put((char)b1);
+                    mark++;
+                } else if ((b1 >> 5) == -2) {
+                    // 2 bytes, 11 bits: 110xxxxx 10xxxxxx
+                    if (limit - mark < 2|| dst.remaining() < 1)
+                        return xflow(src, mark, 2);
+                    int b2 = src.get();
+                    if (isMalformed2(b1, b2))
+                        return malformed(src, mark, 2);
+                    dst.put((char) (((b1 << 6) ^ b2) ^ 0x0f80));
+                    mark += 2;
+                } else if ((b1 >> 4) == -2) {
+                    // 3 bytes, 16 bits: 1110xxxx 10xxxxxx 10xxxxxx
+                    if (limit - mark < 3 || dst.remaining() < 1)
+                        return xflow(src, mark, 3);
+                    int b2 = src.get();
+                    int b3 = src.get();
+                    if (isMalformed3(b1, b2, b3))
+                        return malformed(src, mark, 3);
+                    dst.put((char) (((b1 << 12) ^ (b2 << 6) ^ b3) ^ 0x1f80));
+                    mark += 3;
+                } else if ((b1 >> 3) == -2) {
+                    // 4 bytes, 21 bits: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
+                    if (limit - mark < 4 || dst.remaining() < 2)
+                        return xflow(src, mark, 4);
+                    int b2 = src.get();
+                    int b3 = src.get();
+                    int b4 = src.get();
+                    int uc = ((b1 & 0x07) << 18) |
+                             ((b2 & 0x3f) << 12) |
+                             ((b3 & 0x3f) << 06) |
+                             (b4 & 0x3f);
+                    if (isMalformed4(b2, b3, b4) ||
+                        !Surrogate.neededFor(uc)) { // shortest form check
+                        return malformed(src, mark, 4);
                     }
-
+                    dst.put(Surrogate.high(uc));
+                    dst.put(Surrogate.low(uc));
+                    mark += 4;
+                } else {
+                    return malformed(src, mark, 1);
                 }
-                return CoderResult.UNDERFLOW;
-            } finally {
-                src.position(mark);
             }
+            return xflow(src, mark, 0);
         }
 
         protected CoderResult decodeLoop(ByteBuffer src,
@@ -377,10 +325,8 @@
             else
                 return decodeBufferLoop(src, dst);
         }
-
     }
 
-
     private static class Encoder extends CharsetEncoder {
 
         private Encoder(Charset cs) {
@@ -391,141 +337,126 @@
             return !Surrogate.is(c);
         }
 
-        private final Surrogate.Parser sgp = new Surrogate.Parser();
+        public boolean isLegalReplacement(byte[] repl) {
+            return ((repl.length == 1 && repl[0] >= 0) ||
+                    super.isLegalReplacement(repl));
+        }
 
+        private static CoderResult overflow(CharBuffer src, int sp,
+                                            ByteBuffer dst, int dp) {
+            updatePositions(src, sp, dst, dp);
+            return CoderResult.OVERFLOW;
+        }
+
+        private static CoderResult overflow(CharBuffer src, int mark) {
+            src.position(mark);
+            return CoderResult.OVERFLOW;
+        }
+
+        private Surrogate.Parser sgp;
         private CoderResult encodeArrayLoop(CharBuffer src,
                                             ByteBuffer dst)
         {
             char[] sa = src.array();
             int sp = src.arrayOffset() + src.position();
             int sl = src.arrayOffset() + src.limit();
-            assert (sp <= sl);
-            sp = (sp <= sl ? sp : sl);
+
             byte[] da = dst.array();
             int dp = dst.arrayOffset() + dst.position();
             int dl = dst.arrayOffset() + dst.limit();
-            assert (dp <= dl);
-            dp = (dp <= dl ? dp : dl);
-
-            try {
-                while (sp < sl) {
-                    char c = sa[sp];
-
-                    if (c < 0x80) {
-                        // Have at most seven bits
-                        if (dp >= dl)
-                            return CoderResult.OVERFLOW;
-                        da[dp++] = (byte)c;
-                        sp++;
-                        continue;
-                    }
+            int dlASCII = dp + Math.min(sl - sp, dl - dp);
 
-                    if (!Surrogate.is(c)) {
-                        // 2 bytes, 11 bits
-                        if (c < 0x800) {
-                            if (dl - dp < 2)
-                                return CoderResult.OVERFLOW;
-                            da[dp++] = (byte)(0xc0 | ((c >> 06)));
-                            da[dp++] = (byte)(0x80 | ((c >> 00) & 0x3f));
-                            sp++;
-                            continue;
-                        }
-                        if (c <= '\uFFFF') {
-                            // 3 bytes, 16 bits
-                            if (dl - dp < 3)
-                                return CoderResult.OVERFLOW;
-                            da[dp++] = (byte)(0xe0 | ((c >> 12)));
-                            da[dp++] = (byte)(0x80 | ((c >> 06) & 0x3f));
-                            da[dp++] = (byte)(0x80 | ((c >> 00) & 0x3f));
-                            sp++;
-                            continue;
-                        }
+            //ASCII only loop
+            while (dp < dlASCII && sa[sp] < '\u0080')
+                da[dp++] = (byte) sa[sp++];
+            while (sp < sl) {
+                int c = sa[sp];
+                if (c < 0x80) {
+                    // Have at most seven bits
+                    if (dp >= dl)
+                        return overflow(src, sp, dst, dp);
+                    da[dp++] = (byte)c;
+                } else if (c < 0x800) {
+                    // 2 bytes, 11 bits
+                    if (dl - dp < 2)
+                        return overflow(src, sp, dst, dp);
+                    da[dp++] = (byte)(0xc0 | ((c >> 06)));
+                    da[dp++] = (byte)(0x80 | (c & 0x3f));
+                } else if (Surrogate.is(c)) {
+                    // Have a surrogate pair
+                    if (sgp == null)
+                        sgp = new Surrogate.Parser();
+                    int uc = sgp.parse((char)c, sa, sp, sl);
+                    if (uc < 0) {
+                        updatePositions(src, sp, dst, dp);
+                        return sgp.error();
                     }
-
-                    // Have a surrogate pair
-                    int uc = sgp.parse(c, sa, sp, sl);
-                    if (uc < 0)
-                        return sgp.error();
-                    if (uc < 0x200000) {
-                        if (dl - dp < 4)
-                            return CoderResult.OVERFLOW;
-                        da[dp++] = (byte)(0xf0 | ((uc >> 18)));
-                        da[dp++] = (byte)(0x80 | ((uc >> 12) & 0x3f));
-                        da[dp++] = (byte)(0x80 | ((uc >> 06) & 0x3f));
-                        da[dp++] = (byte)(0x80 | ((uc >> 00) & 0x3f));
-                        sp += sgp.increment();
-                        continue;
-                    }
-                    assert false;
-
+                    if (dl - dp < 4)
+                        return overflow(src, sp, dst, dp);
+                    da[dp++] = (byte)(0xf0 | ((uc >> 18)));
+                    da[dp++] = (byte)(0x80 | ((uc >> 12) & 0x3f));
+                    da[dp++] = (byte)(0x80 | ((uc >> 06) & 0x3f));
+                    da[dp++] = (byte)(0x80 | (uc & 0x3f));
+                    sp++;  // 2 chars
+                } else {
+                    // 3 bytes, 16 bits
+                    if (dl - dp < 3)
+                        return overflow(src, sp, dst, dp);
+                    da[dp++] = (byte)(0xe0 | ((c >> 12)));
+                    da[dp++] = (byte)(0x80 | ((c >> 06) & 0x3f));
+                    da[dp++] = (byte)(0x80 | (c & 0x3f));
                 }
-                return CoderResult.UNDERFLOW;
-            } finally {
-                src.position(sp - src.arrayOffset());
-                dst.position(dp - dst.arrayOffset());
+                sp++;
             }
+            updatePositions(src, sp, dst, dp);
+            return CoderResult.UNDERFLOW;
         }
 
         private CoderResult encodeBufferLoop(CharBuffer src,
                                              ByteBuffer dst)
         {
             int mark = src.position();
-            try {
-                while (src.hasRemaining()) {
-                    char c = src.get();
-
-                    if (c < 0x80) {
-                        // Have at most seven bits
-                        if (!dst.hasRemaining())
-                            return CoderResult.OVERFLOW;
-                        dst.put((byte)c);
-                        mark++;
-                        continue;
+            while (src.hasRemaining()) {
+                int c = src.get();
+                if (c < 0x80) {
+                    // Have at most seven bits
+                    if (!dst.hasRemaining())
+                        return overflow(src, mark);
+                    dst.put((byte)c);
+                } else if (c < 0x800) {
+                    // 2 bytes, 11 bits
+                    if (dst.remaining() < 2)
+                        return overflow(src, mark);
+                    dst.put((byte)(0xc0 | ((c >> 06))));
+                    dst.put((byte)(0x80 | (c & 0x3f)));
+                } else if (Surrogate.is(c)) {
+                    // Have a surrogate pair
+                    if (sgp == null)
+                        sgp = new Surrogate.Parser();
+                    int uc = sgp.parse((char)c, src);
+                    if (uc < 0) {
+                        src.position(mark);
+                        return sgp.error();
                     }
-
-                    if (!Surrogate.is(c)) {
-                        if (c < 0x800) {
-                            // 2 bytes, 11 bits
-                            if (dst.remaining() < 2)
-                                return CoderResult.OVERFLOW;
-                            dst.put((byte)(0xc0 | ((c >> 06))));
-                            dst.put((byte)(0x80 | ((c >> 00) & 0x3f)));
-                            mark++;
-                            continue;
-                        }
-                        if (c <= '\uFFFF') {
-                            // 3 bytes, 16 bits
-                            if (dst.remaining() < 3)
-                                return CoderResult.OVERFLOW;
-                            dst.put((byte)(0xe0 | ((c >> 12))));
-                            dst.put((byte)(0x80 | ((c >> 06) & 0x3f)));
-                            dst.put((byte)(0x80 | ((c >> 00) & 0x3f)));
-                            mark++;
-                            continue;
-                        }
-                    }
-
-                    // Have a surrogate pair
-                    int uc = sgp.parse(c, src);
-                    if (uc < 0)
-                        return sgp.error();
-                    if (uc < 0x200000) {
-                        if (dst.remaining() < 4)
-                            return CoderResult.OVERFLOW;
-                        dst.put((byte)(0xf0 | ((uc >> 18))));
-                        dst.put((byte)(0x80 | ((uc >> 12) & 0x3f)));
-                        dst.put((byte)(0x80 | ((uc >> 06) & 0x3f)));
-                        dst.put((byte)(0x80 | ((uc >> 00) & 0x3f)));
-                        mark += sgp.increment();
-                        continue;
-                    }
-                    assert false;
-
+                    if (dst.remaining() < 4)
+                        return overflow(src, mark);
+                    dst.put((byte)(0xf0 | ((uc >> 18))));
+                    dst.put((byte)(0x80 | ((uc >> 12) & 0x3f)));
+                    dst.put((byte)(0x80 | ((uc >> 06) & 0x3f)));
+                    dst.put((byte)(0x80 | (uc & 0x3f)));
+                    mark++;  //2 chars
+                } else {
+                    // 3 bytes, 16 bits
+                    if (dst.remaining() < 3)
+                        return overflow(src, mark);
+                    dst.put((byte)(0xe0 | ((c >> 12))));
+                    dst.put((byte)(0x80 | ((c >> 06) & 0x3f)));
+                    dst.put((byte)(0x80 | (c & 0x3f)));
                 }
-                return CoderResult.UNDERFLOW;
-            } finally {
-                src.position(mark);
+                mark++;
             }
+            src.position(mark);
+            return CoderResult.UNDERFLOW;
         }
 
         protected final CoderResult encodeLoop(CharBuffer src,
@@ -536,7 +467,5 @@
             else
                 return encodeBufferLoop(src, dst);
         }
-
     }
-
 }
--- a/jdk/src/share/classes/sun/security/util/DerIndefLenConverter.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/sun/security/util/DerIndefLenConverter.java	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2006 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -50,6 +50,7 @@
 
     private byte[] data, newData;
     private int newDataPos, dataPos, dataSize, index;
+    private int unresolved = 0;
 
     private ArrayList<Object> ndefsList = new ArrayList<Object>();
 
@@ -113,6 +114,7 @@
                              numOfEncapsulatedLenBytes;
             byte[] sectionLenBytes = getLengthBytes(sectionLen);
             ndefsList.set(index, sectionLenBytes);
+            unresolved--;
 
             // Add the number of bytes required to represent this section
             // to the total number of length bytes,
@@ -149,6 +151,7 @@
         int lenByte = data[dataPos++] & 0xff;
         if (isIndefinite(lenByte)) {
             ndefsList.add(new Integer(dataPos));
+            unresolved++;
             return curLen;
         }
         if (isLongForm(lenByte)) {
@@ -308,15 +311,21 @@
         dataPos=0; index=0;
         dataSize = data.length;
         int len=0;
+        int unused = 0;
 
         // parse and set up the vectors of all the indefinite-lengths
         while (dataPos < dataSize) {
             parseTag();
             len = parseLength();
             parseValue(len);
+            if (unresolved == 0) {
+                unused = dataSize - dataPos;
+                dataSize = dataPos;
+                break;
+            }
         }
 
-        newData = new byte[dataSize + numOfTotalLenBytes];
+        newData = new byte[dataSize + numOfTotalLenBytes + unused];
         dataPos=0; newDataPos=0; index=0;
 
         // write out the new byte array replacing all the indefinite-lengths
@@ -325,6 +334,8 @@
            writeTag();
            writeLengthAndValue();
         }
+        System.arraycopy(indefData, dataSize,
+                         newData, dataSize + numOfTotalLenBytes, unused);
 
         return newData;
     }
--- a/jdk/src/share/classes/sun/tools/jmap/JMap.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/classes/sun/tools/jmap/JMap.java	Wed Jul 05 16:41:01 2017 +0200
@@ -56,7 +56,7 @@
     private static String FORCE_SA_OPTION = "-F";
 
     // Default option (if nothing provided)
-    private static String DEFAULT_OPTION = "-heap";
+    private static String DEFAULT_OPTION = "-pmap";
 
     public static void main(String[] args) throws Exception {
         if (args.length == 0) {
@@ -147,6 +147,7 @@
     // Invoke SA tool  with the given arguments
     private static void runTool(String option, String args[]) throws Exception {
         String[][] tools = {
+            { "-pmap",           "sun.jvm.hotspot.tools.PMap"     },
             { "-heap",           "sun.jvm.hotspot.tools.HeapSummary"     },
             { "-heap:format=b",  "sun.jvm.hotspot.tools.HeapDumper"      },
             { "-histo",          "sun.jvm.hotspot.tools.ObjectHistogram" },
--- a/jdk/src/share/instrument/InstrumentationImplNativeMethods.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/instrument/InstrumentationImplNativeMethods.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2003-2007 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -23,15 +23,14 @@
  * have any questions.
  */
 
-
 #include    <jni.h>
 
 #include    "JPLISAgent.h"
 #include    "JPLISAssert.h"
 #include    "Utilities.h"
 #include    "JavaExceptions.h"
+#include    "FileSystemSupport.h"   /* For uintptr_t */
 #include    "sun_instrument_InstrumentationImpl.h"
-#include    "typedefs.h"
 
 /*
  * Copyright 2003 Wily Technology, Inc.
--- a/jdk/src/share/instrument/JPLISAgent.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/instrument/JPLISAgent.c	Wed Jul 05 16:41:01 2017 +0200
@@ -38,10 +38,9 @@
 #include    "JavaExceptions.h"
 
 #include    "EncodingSupport.h"
-#include    "FileSystemSupport.h"               /* MAXPATHLEN */
+#include    "FileSystemSupport.h"    /* For MAXPATHLEN & uintptr_t */
 
 #include    "sun_instrument_InstrumentationImpl.h"
-#include    "typedefs.h"
 
 /*
  *  The JPLISAgent manages the initialization all of the Java programming language Agents.
--- a/jdk/src/share/javavm/export/jvm.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/javavm/export/jvm.h	Wed Jul 05 16:41:01 2017 +0200
@@ -948,90 +948,8 @@
 JNIEXPORT jboolean JNICALL
 JVM_IsSameClassPackage(JNIEnv *env, jclass class1, jclass class2);
 
-/* Constants in class files */
-
-#define JVM_ACC_PUBLIC        0x0001  /* visible to everyone */
-#define JVM_ACC_PRIVATE       0x0002  /* visible only to the defining class */
-#define JVM_ACC_PROTECTED     0x0004  /* visible to subclasses */
-#define JVM_ACC_STATIC        0x0008  /* instance variable is static */
-#define JVM_ACC_FINAL         0x0010  /* no further subclassing, overriding */
-#define JVM_ACC_SYNCHRONIZED  0x0020  /* wrap method call in monitor lock */
-#define JVM_ACC_SUPER         0x0020  /* funky handling of invokespecial */
-#define JVM_ACC_VOLATILE      0x0040  /* can not cache in registers */
-#define JVM_ACC_BRIDGE        0x0040  /* bridge method generated by compiler */
-#define JVM_ACC_TRANSIENT     0x0080  /* not persistant */
-#define JVM_ACC_VARARGS       0x0080  /* method declared with variable number of args */
-#define JVM_ACC_NATIVE        0x0100  /* implemented in C */
-#define JVM_ACC_INTERFACE     0x0200  /* class is an interface */
-#define JVM_ACC_ABSTRACT      0x0400  /* no definition provided */
-#define JVM_ACC_STRICT        0x0800  /* strict floating point */
-#define JVM_ACC_SYNTHETIC     0x1000  /* compiler-generated class, method or field */
-
-#define JVM_ACC_ANNOTATION    0x2000  /* annotation type */
-#define JVM_ACC_ENUM          0x4000  /* field is declared as element of enum */
-
-#define JVM_ACC_PUBLIC_BIT        0
-#define JVM_ACC_PRIVATE_BIT       1
-#define JVM_ACC_PROTECTED_BIT     2
-#define JVM_ACC_STATIC_BIT        3
-#define JVM_ACC_FINAL_BIT         4
-#define JVM_ACC_SYNCHRONIZED_BIT  5
-#define JVM_ACC_SUPER_BIT         5
-#define JVM_ACC_VOLATILE_BIT      6
-#define JVM_ACC_BRIDGE_BIT        6
-#define JVM_ACC_TRANSIENT_BIT     7
-#define JVM_ACC_VARARGS_BIT       7
-#define JVM_ACC_NATIVE_BIT        8
-#define JVM_ACC_INTERFACE_BIT     9
-#define JVM_ACC_ABSTRACT_BIT      10
-#define JVM_ACC_STRICT_BIT        11
-#define JVM_ACC_SYNTHETIC_BIT     12
-#define JVM_ACC_ANNOTATION_BIT    13
-#define JVM_ACC_ENUM_BIT          14
-
-enum {
-    JVM_CONSTANT_Utf8 = 1,
-    JVM_CONSTANT_Unicode,               /* unused */
-    JVM_CONSTANT_Integer,
-    JVM_CONSTANT_Float,
-    JVM_CONSTANT_Long,
-    JVM_CONSTANT_Double,
-    JVM_CONSTANT_Class,
-    JVM_CONSTANT_String,
-    JVM_CONSTANT_Fieldref,
-    JVM_CONSTANT_Methodref,
-    JVM_CONSTANT_InterfaceMethodref,
-    JVM_CONSTANT_NameAndType
-};
-
-/* Used in the newarray instruction. */
-
-#define JVM_T_BOOLEAN 4
-#define JVM_T_CHAR    5
-#define JVM_T_FLOAT   6
-#define JVM_T_DOUBLE  7
-#define JVM_T_BYTE    8
-#define JVM_T_SHORT   9
-#define JVM_T_INT    10
-#define JVM_T_LONG   11
-
-/* JVM method signatures */
-
-#define JVM_SIGNATURE_ARRAY             '['
-#define JVM_SIGNATURE_BYTE              'B'
-#define JVM_SIGNATURE_CHAR              'C'
-#define JVM_SIGNATURE_CLASS             'L'
-#define JVM_SIGNATURE_ENDCLASS          ';'
-#define JVM_SIGNATURE_ENUM              'E'
-#define JVM_SIGNATURE_FLOAT             'F'
-#define JVM_SIGNATURE_DOUBLE            'D'
-#define JVM_SIGNATURE_FUNC              '('
-#define JVM_SIGNATURE_ENDFUNC           ')'
-#define JVM_SIGNATURE_INT               'I'
-#define JVM_SIGNATURE_LONG              'J'
-#define JVM_SIGNATURE_SHORT             'S'
-#define JVM_SIGNATURE_VOID              'V'
-#define JVM_SIGNATURE_BOOLEAN           'Z'
+/* Get classfile constants */
+#include "classfile_constants.h"
 
 /*
  * A function defined by the byte-code verifier and called by the VM.
@@ -1329,23 +1247,6 @@
 JNIEXPORT jint JNICALL
 JVM_SetSockOpt(jint fd, int level, int optname, const char *optval, int optlen);
 
-/*
- * These routines are only reentrant on Windows
- */
-
-#ifdef WIN32
-
-JNIEXPORT struct protoent * JNICALL
-JVM_GetProtoByName(char* name);
-
-JNIEXPORT struct hostent* JNICALL
-JVM_GetHostByAddr(const char* name, int len, int type);
-
-JNIEXPORT struct hostent* JNICALL
-JVM_GetHostByName(char* name);
-
-#endif /* _WINDOWS */
-
 JNIEXPORT int JNICALL
 JVM_GetHostName(char* name, int namelen);
 
--- a/jdk/src/share/javavm/include/opcodes.h	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,268 +0,0 @@
-/*
- * Copyright 1998-2003 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-#ifndef _JAVASOFT_OPCODES_H_
-#define _JAVASOFT_OPCODES_H_
-
-typedef enum {
-  opc_nop = 0,
-  opc_aconst_null = 1,
-  opc_iconst_m1 = 2,
-  opc_iconst_0 = 3,
-  opc_iconst_1 = 4,
-  opc_iconst_2 = 5,
-  opc_iconst_3 = 6,
-  opc_iconst_4 = 7,
-  opc_iconst_5 = 8,
-  opc_lconst_0 = 9,
-  opc_lconst_1 = 10,
-  opc_fconst_0 = 11,
-  opc_fconst_1 = 12,
-  opc_fconst_2 = 13,
-  opc_dconst_0 = 14,
-  opc_dconst_1 = 15,
-  opc_bipush = 16,
-  opc_sipush = 17,
-  opc_ldc = 18,
-  opc_ldc_w = 19,
-  opc_ldc2_w = 20,
-  opc_iload = 21,
-  opc_lload = 22,
-  opc_fload = 23,
-  opc_dload = 24,
-  opc_aload = 25,
-  opc_iload_0 = 26,
-  opc_iload_1 = 27,
-  opc_iload_2 = 28,
-  opc_iload_3 = 29,
-  opc_lload_0 = 30,
-  opc_lload_1 = 31,
-  opc_lload_2 = 32,
-  opc_lload_3 = 33,
-  opc_fload_0 = 34,
-  opc_fload_1 = 35,
-  opc_fload_2 = 36,
-  opc_fload_3 = 37,
-  opc_dload_0 = 38,
-  opc_dload_1 = 39,
-  opc_dload_2 = 40,
-  opc_dload_3 = 41,
-  opc_aload_0 = 42,
-  opc_aload_1 = 43,
-  opc_aload_2 = 44,
-  opc_aload_3 = 45,
-  opc_iaload = 46,
-  opc_laload = 47,
-  opc_faload = 48,
-  opc_daload = 49,
-  opc_aaload = 50,
-  opc_baload = 51,
-  opc_caload = 52,
-  opc_saload = 53,
-  opc_istore = 54,
-  opc_lstore = 55,
-  opc_fstore = 56,
-  opc_dstore = 57,
-  opc_astore = 58,
-  opc_istore_0 = 59,
-  opc_istore_1 = 60,
-  opc_istore_2 = 61,
-  opc_istore_3 = 62,
-  opc_lstore_0 = 63,
-  opc_lstore_1 = 64,
-  opc_lstore_2 = 65,
-  opc_lstore_3 = 66,
-  opc_fstore_0 = 67,
-  opc_fstore_1 = 68,
-  opc_fstore_2 = 69,
-  opc_fstore_3 = 70,
-  opc_dstore_0 = 71,
-  opc_dstore_1 = 72,
-  opc_dstore_2 = 73,
-  opc_dstore_3 = 74,
-  opc_astore_0 = 75,
-  opc_astore_1 = 76,
-  opc_astore_2 = 77,
-  opc_astore_3 = 78,
-  opc_iastore = 79,
-  opc_lastore = 80,
-  opc_fastore = 81,
-  opc_dastore = 82,
-  opc_aastore = 83,
-  opc_bastore = 84,
-  opc_castore = 85,
-  opc_sastore = 86,
-  opc_pop = 87,
-  opc_pop2 = 88,
-  opc_dup = 89,
-  opc_dup_x1 = 90,
-  opc_dup_x2 = 91,
-  opc_dup2 = 92,
-  opc_dup2_x1 = 93,
-  opc_dup2_x2 = 94,
-  opc_swap = 95,
-  opc_iadd = 96,
-  opc_ladd = 97,
-  opc_fadd = 98,
-  opc_dadd = 99,
-  opc_isub = 100,
-  opc_lsub = 101,
-  opc_fsub = 102,
-  opc_dsub = 103,
-  opc_imul = 104,
-  opc_lmul = 105,
-  opc_fmul = 106,
-  opc_dmul = 107,
-  opc_idiv = 108,
-  opc_ldiv = 109,
-  opc_fdiv = 110,
-  opc_ddiv = 111,
-  opc_irem = 112,
-  opc_lrem = 113,
-  opc_frem = 114,
-  opc_drem = 115,
-  opc_ineg = 116,
-  opc_lneg = 117,
-  opc_fneg = 118,
-  opc_dneg = 119,
-  opc_ishl = 120,
-  opc_lshl = 121,
-  opc_ishr = 122,
-  opc_lshr = 123,
-  opc_iushr = 124,
-  opc_lushr = 125,
-  opc_iand = 126,
-  opc_land = 127,
-  opc_ior = 128,
-  opc_lor = 129,
-  opc_ixor = 130,
-  opc_lxor = 131,
-  opc_iinc = 132,
-  opc_i2l = 133,
-  opc_i2f = 134,
-  opc_i2d = 135,
-  opc_l2i = 136,
-  opc_l2f = 137,
-  opc_l2d = 138,
-  opc_f2i = 139,
-  opc_f2l = 140,
-  opc_f2d = 141,
-  opc_d2i = 142,
-  opc_d2l = 143,
-  opc_d2f = 144,
-  opc_i2b = 145,
-  opc_i2c = 146,
-  opc_i2s = 147,
-  opc_lcmp = 148,
-  opc_fcmpl = 149,
-  opc_fcmpg = 150,
-  opc_dcmpl = 151,
-  opc_dcmpg = 152,
-  opc_ifeq = 153,
-  opc_ifne = 154,
-  opc_iflt = 155,
-  opc_ifge = 156,
-  opc_ifgt = 157,
-  opc_ifle = 158,
-  opc_if_icmpeq = 159,
-  opc_if_icmpne = 160,
-  opc_if_icmplt = 161,
-  opc_if_icmpge = 162,
-  opc_if_icmpgt = 163,
-  opc_if_icmple = 164,
-  opc_if_acmpeq = 165,
-  opc_if_acmpne = 166,
-  opc_goto = 167,
-  opc_jsr = 168,
-  opc_ret = 169,
-  opc_tableswitch = 170,
-  opc_lookupswitch = 171,
-  opc_ireturn = 172,
-  opc_lreturn = 173,
-  opc_freturn = 174,
-  opc_dreturn = 175,
-  opc_areturn = 176,
-  opc_return = 177,
-  opc_getstatic = 178,
-  opc_putstatic = 179,
-  opc_getfield = 180,
-  opc_putfield = 181,
-  opc_invokevirtual = 182,
-  opc_invokespecial = 183,
-  opc_invokestatic = 184,
-  opc_invokeinterface = 185,
-  opc_xxxunusedxxx = 186,
-  opc_new = 187,
-  opc_newarray = 188,
-  opc_anewarray = 189,
-  opc_arraylength = 190,
-  opc_athrow = 191,
-  opc_checkcast = 192,
-  opc_instanceof = 193,
-  opc_monitorenter = 194,
-  opc_monitorexit = 195,
-  opc_wide = 196,
-  opc_multianewarray = 197,
-  opc_ifnull = 198,
-  opc_ifnonnull = 199,
-  opc_goto_w = 200,
-  opc_jsr_w = 201,
-  opc_breakpoint = 202,
-  opc_ldc_quick = 203,
-  opc_ldc_w_quick = 204,
-  opc_ldc2_w_quick = 205,
-  opc_getfield_quick = 206,
-  opc_putfield_quick = 207,
-  opc_getfield2_quick = 208,
-  opc_putfield2_quick = 209,
-  opc_getstatic_quick = 210,
-  opc_putstatic_quick = 211,
-  opc_getstatic2_quick = 212,
-  opc_putstatic2_quick = 213,
-  opc_invokevirtual_quick = 214,
-  opc_invokenonvirtual_quick = 215,
-  opc_invokesuper_quick = 216,
-  opc_invokestatic_quick = 217,
-  opc_invokeinterface_quick = 218,
-  opc_invokevirtualobject_quick = 219,
-  opc_invokeignored_quick = 220,
-  opc_new_quick = 221,
-  opc_anewarray_quick = 222,
-  opc_multianewarray_quick = 223,
-  opc_checkcast_quick = 224,
-  opc_instanceof_quick = 225,
-  opc_invokevirtual_quick_w = 226,
-  opc_getfield_quick_w = 227,
-  opc_putfield_quick_w = 228,
-  opc_nonnull_quick = 229,
-  opc_first_unused_index = 230,
-  opc_software = 254,
-  opc_hardware = 255,
-  opc_dummy = (int)0xF0000000U      /* portability change, opc_invokeinit in the
-                                     * verifier requires more than 8 bits.
-                                     */
-} opcode_type;
-
-#endif /* !_JAVASOFT_OPCODES_H_ */
--- a/jdk/src/share/javavm/include/opcodes.length	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/* 
- * Copyright 1998-2007 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-const short opcode_length[256] = {
-   1,		/* nop */
-   1,		/* aconst_null */
-   1,		/* iconst_m1 */
-   1,		/* iconst_0 */
-   1,		/* iconst_1 */
-   1,		/* iconst_2 */
-   1,		/* iconst_3 */
-   1,		/* iconst_4 */
-   1,		/* iconst_5 */
-   1,		/* lconst_0 */
-   1,		/* lconst_1 */
-   1,		/* fconst_0 */
-   1,		/* fconst_1 */
-   1,		/* fconst_2 */
-   1,		/* dconst_0 */
-   1,		/* dconst_1 */
-   2,		/* bipush */
-   3,		/* sipush */
-   2,		/* ldc */
-   3,		/* ldc_w */
-   3,		/* ldc2_w */
-   2,		/* iload */
-   2,		/* lload */
-   2,		/* fload */
-   2,		/* dload */
-   2,		/* aload */
-   1,		/* iload_0 */
-   1,		/* iload_1 */
-   1,		/* iload_2 */
-   1,		/* iload_3 */
-   1,		/* lload_0 */
-   1,		/* lload_1 */
-   1,		/* lload_2 */
-   1,		/* lload_3 */
-   1,		/* fload_0 */
-   1,		/* fload_1 */
-   1,		/* fload_2 */
-   1,		/* fload_3 */
-   1,		/* dload_0 */
-   1,		/* dload_1 */
-   1,		/* dload_2 */
-   1,		/* dload_3 */
-   1,		/* aload_0 */
-   1,		/* aload_1 */
-   1,		/* aload_2 */
-   1,		/* aload_3 */
-   1,		/* iaload */
-   1,		/* laload */
-   1,		/* faload */
-   1,		/* daload */
-   1,		/* aaload */
-   1,		/* baload */
-   1,		/* caload */
-   1,		/* saload */
-   2,		/* istore */
-   2,		/* lstore */
-   2,		/* fstore */
-   2,		/* dstore */
-   2,		/* astore */
-   1,		/* istore_0 */
-   1,		/* istore_1 */
-   1,		/* istore_2 */
-   1,		/* istore_3 */
-   1,		/* lstore_0 */
-   1,		/* lstore_1 */
-   1,		/* lstore_2 */
-   1,		/* lstore_3 */
-   1,		/* fstore_0 */
-   1,		/* fstore_1 */
-   1,		/* fstore_2 */
-   1,		/* fstore_3 */
-   1,		/* dstore_0 */
-   1,		/* dstore_1 */
-   1,		/* dstore_2 */
-   1,		/* dstore_3 */
-   1,		/* astore_0 */
-   1,		/* astore_1 */
-   1,		/* astore_2 */
-   1,		/* astore_3 */
-   1,		/* iastore */
-   1,		/* lastore */
-   1,		/* fastore */
-   1,		/* dastore */
-   1,		/* aastore */
-   1,		/* bastore */
-   1,		/* castore */
-   1,		/* sastore */
-   1,		/* pop */
-   1,		/* pop2 */
-   1,		/* dup */
-   1,		/* dup_x1 */
-   1,		/* dup_x2 */
-   1,		/* dup2 */
-   1,		/* dup2_x1 */
-   1,		/* dup2_x2 */
-   1,		/* swap */
-   1,		/* iadd */
-   1,		/* ladd */
-   1,		/* fadd */
-   1,		/* dadd */
-   1,		/* isub */
-   1,		/* lsub */
-   1,		/* fsub */
-   1,		/* dsub */
-   1,		/* imul */
-   1,		/* lmul */
-   1,		/* fmul */
-   1,		/* dmul */
-   1,		/* idiv */
-   1,		/* ldiv */
-   1,		/* fdiv */
-   1,		/* ddiv */
-   1,		/* irem */
-   1,		/* lrem */
-   1,		/* frem */
-   1,		/* drem */
-   1,		/* ineg */
-   1,		/* lneg */
-   1,		/* fneg */
-   1,		/* dneg */
-   1,		/* ishl */
-   1,		/* lshl */
-   1,		/* ishr */
-   1,		/* lshr */
-   1,		/* iushr */
-   1,		/* lushr */
-   1,		/* iand */
-   1,		/* land */
-   1,		/* ior */
-   1,		/* lor */
-   1,		/* ixor */
-   1,		/* lxor */
-   3,		/* iinc */
-   1,		/* i2l */
-   1,		/* i2f */
-   1,		/* i2d */
-   1,		/* l2i */
-   1,		/* l2f */
-   1,		/* l2d */
-   1,		/* f2i */
-   1,		/* f2l */
-   1,		/* f2d */
-   1,		/* d2i */
-   1,		/* d2l */
-   1,		/* d2f */
-   1,		/* i2b */
-   1,		/* i2c */
-   1,		/* i2s */
-   1,		/* lcmp */
-   1,		/* fcmpl */
-   1,		/* fcmpg */
-   1,		/* dcmpl */
-   1,		/* dcmpg */
-   3,		/* ifeq */
-   3,		/* ifne */
-   3,		/* iflt */
-   3,		/* ifge */
-   3,		/* ifgt */
-   3,		/* ifle */
-   3,		/* if_icmpeq */
-   3,		/* if_icmpne */
-   3,		/* if_icmplt */
-   3,		/* if_icmpge */
-   3,		/* if_icmpgt */
-   3,		/* if_icmple */
-   3,		/* if_acmpeq */
-   3,		/* if_acmpne */
-   3,		/* goto */
-   3,		/* jsr */
-   2,		/* ret */
-   99,		/* tableswitch */
-   99,		/* lookupswitch */
-   1,		/* ireturn */
-   1,		/* lreturn */
-   1,		/* freturn */
-   1,		/* dreturn */
-   1,		/* areturn */
-   1,		/* return */
-   3,		/* getstatic */
-   3,		/* putstatic */
-   3,		/* getfield */
-   3,		/* putfield */
-   3,		/* invokevirtual */
-   3,		/* invokespecial */
-   3,		/* invokestatic */
-   5,		/* invokeinterface */
-   0,		/* xxxunusedxxx */
-   3,		/* new */
-   2,		/* newarray */
-   3,		/* anewarray */
-   1,		/* arraylength */
-   1,		/* athrow */
-   3,		/* checkcast */
-   3,		/* instanceof */
-   1,		/* monitorenter */
-   1,		/* monitorexit */
-   0,		/* wide */
-   4,		/* multianewarray */
-   3,		/* ifnull */
-   3,		/* ifnonnull */
-   5,		/* goto_w */
-   5,		/* jsr_w */
-   1,		/* breakpoint */
-   2,		/* ldc_quick */
-   3,		/* ldc_w_quick */
-   3,		/* ldc2_w_quick */
-   3,		/* getfield_quick */
-   3,		/* putfield_quick */
-   3,		/* getfield2_quick */
-   3,		/* putfield2_quick */
-   3,		/* getstatic_quick */
-   3,		/* putstatic_quick */
-   3,		/* getstatic2_quick */
-   3,		/* putstatic2_quick */
-   3,		/* invokevirtual_quick */
-   3,		/* invokenonvirtual_quick */
-   3,		/* invokesuper_quick */
-   3,		/* invokestatic_quick */
-   5,		/* invokeinterface_quick */
-   3,		/* invokevirtualobject_quick */
-   3,		/* invokeignored_quick */
-   3,		/* new_quick */
-   3,		/* anewarray_quick */
-   4,		/* multianewarray_quick */
-   3,		/* checkcast_quick */
-   3,		/* instanceof_quick */
-   3,		/* invokevirtual_quick_w */
-   3,		/* getfield_quick_w */
-   3,		/* putfield_quick_w */
-   1,		/* nonnull_quick */
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-   -1,
-};
--- a/jdk/src/share/javavm/include/opcodes.list	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,301 +0,0 @@
-# Copyright 1994-2007 Sun Microsystems, Inc.  All Rights Reserved.
-# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-#
-# This code is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 only, as
-# published by the Free Software Foundation.  Sun designates this
-# particular file as subject to the "Classpath" exception as provided
-# by Sun in the LICENSE file that accompanied this code.
-#
-# This code is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-# version 2 for more details (a copy is included in the LICENSE file that
-# accompanied this code).
-#
-# You should have received a copy of the GNU General Public License version
-# 2 along with this work; if not, write to the Free Software Foundation,
-# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-#
-# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
-# CA 95054 USA or visit www.sun.com if you need additional information or
-# have any questions.
-#
-
-# Any line that doesn't have a-z in the 1st column is a comment.
-#
-# The first column is the name of the opcodes.  The second column is the
-# total length of the instruction.  We use 99 for tableswitch and
-# tablelookup, which must always be treated as special cases.
-#
-# The third and fourth colum give what the opcode pops off the stack, and
-# what it then pushes back onto the stack
-#    -       <no effect on stack>   
-#    I       integer
-#    L       long integer
-#    F       float
-#    D       double float
-#    A       address [array or object]
-#    O       object only
-#    R       return address (for jsr)
-#    a       integer, array, or object
-#    ?       unknown
-#    [I], [L], [F], [D], [A], [B], [C], [?]
-#            array of integer, long, float, double, address, bytes, 
-#                  chars, or anything
-#    1,2,3,4,+ used by stack duplicating/popping routines.  
-# 
-# 1,2,3,4 represent >>any<< stack type except long or double.  Two numbers
-# separated by a + (in the third column) indicate that the two, together, can
-# be used for a double or long.  (Or they can represent two non-long items).
-#
-# The fifth column provides an *approximate* relative cost of executing the
-# opcode. It is used by the instruction profiler. See profiler.h for
-# blurb.
-
-nop			1 -     -	1 /* nop */
-aconst_null		1 -     A	1 /* push null object */
-iconst_m1	    	1 -     I	1 /* push integer constant -1 */
-iconst_0	    	1 -     I	1 /* push integer constant 0 */
-iconst_1	    	1 -     I	1 /* push integer constant 1 */
-iconst_2	    	1 -     I	1 /* push integer constant 2 */
-iconst_3	    	1 -     I	1 /* push integer constant 3 */
-iconst_4	    	1 -     I	1 /* push integer constant 4 */
-iconst_5	    	1 -     I	1 /* push integer constant 5 */
-lconst_0	    	1 -     L	1 /* push long 0L */
-lconst_1	    	1 -     L	1 /* push long 1L */
-fconst_0	    	1 -     F	1 /* push float constant 0.0 */
-fconst_1	    	1 -     F	1 /* push float constant 1.0 */
-fconst_2	    	1 -     F	1 /* push float constant 2.0 */
-dconst_0	    	1 -     D	1 /* push double float constant 0.0d */
-dconst_1	    	1 -     D	1 /* push double float constant 1.0d */
-bipush		    	2 -     I	1 /* push byte-sized value */
-sipush		    	3 -     I	1 /* push two-byte value */
-ldc                	2 -     ?      	1 /* load a const from constant table */
-ldc_w	    	    	3 -     ?	1
-ldc2_w	    	    	3 -     ?	1 /* load a 2-word constant . . . */
-iload		    	2 -     I	1 /* load local integer variable */
-lload		    	2 -     L	1 /* load local long variable */
-fload		    	2 -     F	1 /* load local floating variable */
-dload		    	2 -     D	1 /* load local double variable */
-aload		    	2 -     A	1 /* load local object variable */
-iload_0		    	1 -     I	1 /* load local integer variable #0 */
-iload_1		    	1 -     I	1 /* load local integer variable #1 */
-iload_2		    	1 -     I	1 /* load local integer variable #2 */
-iload_3		    	1 -     I	1 /* load local integer variable #3 */
-lload_0		    	1 -     L	1 /* load local long variable #0 */
-lload_1		    	1 -     L	1 /* load local long variable #1 */
-lload_2		    	1 -     L	1 /* load local long variable #2 */
-lload_3		    	1 -     L	1 /* load local long variable #3 */
-fload_0		    	1 -     F	1 /* load local float variable #0 */
-fload_1		    	1 -     F	1 /* load local float variable #1 */
-fload_2		    	1 -     F	1 /* load local float variable #2 */
-fload_3		    	1 -     F	1 /* load local float variable #3 */
-dload_0		    	1 -     D	1 /* load lcl double float variable #0 */
-dload_1		    	1 -     D	1 /* load lcl double float variable #1 */
-dload_2		    	1 -     D	1 /* load lcl double float variable #2 */
-dload_3		    	1 -     D	1 /* load lcl double float variable #3 */
-aload_0		    	1 -     A	1 /* load local object variable #0 */
-aload_1		    	1 -     A	1 /* load local object variable #1 */
-aload_2		    	1 -     A	1 /* load local object variable #2 */
-aload_3		    	1 -     A	1 /* load local object variable #3 */
-iaload		    	1 [I]I  I	1 /* load from array of integer */
-laload		    	1 [L]I  L	1 /* load from array of long */
-faload		    	1 [F]I  F	1 /* load from array of float */
-daload		    	1 [D]I  D	1 /* load from array of double */
-aaload		    	1 [A]I  A	1 /* load from array of object */
-baload		    	1 [B]I  I	1 /* load from array of (signed) bytes */
-caload		    	1 [C]I  I	1 /* load from array of chars */
-saload		    	1 [S]I  I	1 /* load from array of (signed) shorts */
-istore		    	2 I     -	1 /* store local integer variable */
-lstore		    	2 L     -	1 /* store local long variable */
-fstore		    	2 F     -	1 /* store local float variable */
-dstore		    	2 D     -	1 /* store local double variable */
-astore		    	2 A     -	1 /* store local object variable */
-istore_0	    	1 I     -	1 /* store local integer variable #0 */
-istore_1	    	1 I     -	1 /* store local integer variable #1 */
-istore_2	    	1 I     -	1 /* store local integer variable #2 */
-istore_3	    	1 I     -	1 /* store local integer variable #3 */
-lstore_0	    	1 L     -	1 /* store local long variable #0 */
-lstore_1	    	1 L     -	1 /* store local long variable #1 */
-lstore_2	    	1 L     -	1 /* store local long variable #2 */
-lstore_3	    	1 L     -	1 /* store local long variable #3 */
-fstore_0	    	1 F     -	1 /* store local float variable #0 */
-fstore_1	    	1 F     -	1 /* store local float variable #1 */
-fstore_2	    	1 F     -	1 /* store local float variable #2 */
-fstore_3	    	1 F     -	1 /* store local float variable #3 */
-dstore_0	    	1 D     -	1 /* store lcl double float variable #0 */
-dstore_1	    	1 D     -	1 /* store lcl double float variable #1 */
-dstore_2	    	1 D     -	1 /* store lcl double float variable #2 */
-dstore_3	    	1 D     -	1 /* store lcl double float variable #3 */
-astore_0	    	1 A     -	1 /* store local object variable #0 */
-astore_1	    	1 A     -	1 /* store local object variable #1 */
-astore_2	    	1 A     -	1 /* store local object variable #2 */
-astore_3	    	1 A     -	1 /* store local object variable #3 */
-iastore		    	1 [I]II -	1 /* store into array of int */
-lastore		    	1 [L]IL -	1 /* store into array of long */
-fastore		    	1 [F]IF -	1 /* store into array of float */
-dastore		    	1 [D]ID -	1 /* store into array of double float  */
-aastore		    	1 [A]IA -	1 /* store into array of object */
-bastore		    	1 [B]II -	1 /* store into array of (signed) bytes */
-castore		    	1 [C]II -	1 /* store into array of chars */
-sastore		    	1 [S]II -	1 /* store into array of (signed) shorts*/
-pop		    	1 1     -	1 /* pop top element */
-pop2		    	1 2+1   -	1 /* pop top two elements */
-dup		    	1 1     11	1 /* dup top element */
-dup_x1		    	1 21    121	1 /* dup top element. Skip one */
-dup_x2		    	1 3+21  1321	1 /* dup top element. Skip two */
-dup2		    	1 2+1   2121	1 /* dup top two elements.  */
-dup2_x1		    	1 32+1  21321	1 /* dup top two elements.  Skip one */
-dup2_x2		    	1 4+32+1 214321	1 /* dup top two elements.  Skip two */
-swap                	1 21    12   	1 /* swap top two elements of stack. */
-iadd		    	1 II    I	1 /* integer add */
-ladd		    	1 LL    L	1 /* long add */
-fadd		    	1 FF    F	1 /* floating add */
-dadd		    	1 DD    D	1 /* double float add */
-isub		    	1 II    I	1 /* integer subtract */
-lsub		    	1 LL    L	1 /* long subtract */
-fsub		    	1 FF    F	1 /* floating subtract */
-dsub		    	1 DD    D	1 /* floating double subtract */
-imul		    	1 II    I	1 /* integer multiply */
-lmul		    	1 LL    L	1 /* long multiply */
-fmul		    	1 FF    F	1 /* floating multiply */
-dmul		    	1 DD    D	1 /* double float multiply */
-idiv		    	1 II    I	1 /* integer divide */
-ldiv		    	1 LL    L	1 /* long divide */
-fdiv		    	1 FF    F	1 /* floating divide */
-ddiv		    	1 DD    D	1 /* double float divide */
-irem		    	1 II    I	1 /* integer mod */
-lrem		    	1 LL    L	1 /* long mod */
-frem		    	1 FF    F	1 /* floating mod */
-drem		    	1 DD    D	1 /* double float mod */
-ineg		    	1 I     I	1 /* integer negate */
-lneg		    	1 L     L	1 /* long negate */
-fneg		    	1 F     F	1 /* floating negate */
-dneg		    	1 D     D	1 /* double float negate */
-ishl		    	1 II    I	1 /* shift left */
-lshl		    	1 LI    L	1 /* long shift left */
-ishr		    	1 II    I	1 /* shift right */
-lshr		    	1 LI    L	1 /* long shift right */
-iushr		    	1 II    I	1 /* unsigned shift right */
-lushr		    	1 LI    L	1 /* long unsigned shift right */
-iand		    	1 II    I	1 /* boolean and */
-land		    	1 LL    L	1 /* long boolean and */
-ior		    	1 II    I	1 /* boolean or */
-lor		    	1 LL    L	1 /* long boolean or */
-ixor		    	1 II    I	1 /* boolean xor */
-lxor		    	1 LL    L	1 /* long boolean xor */
-iinc		    	3 -     -	1 /* increment lcl variable by constant */
-i2l		    	1 I     L	1 /* integer to long */
-i2f		    	1 I     F	1 /* integer to float */
-i2d		    	1 I     D	1 /* integer to double */
-l2i		    	1 L     I	1 /* long to integer */
-l2f		    	1 L     F	1 /* long to float */
-l2d		    	1 L     D	1 /* long to double */
-f2i		    	1 F     I	1 /* float to integer */
-f2l		    	1 F     L	1 /* float to long */
-f2d		    	1 F     D	1 /* float to double */
-d2i		    	1 D     I	1 /* double to integer */
-d2l		    	1 D     L	1 /* double to long */
-d2f		    	1 D     F	1 /* double to float */
-i2b		    	1 I     I	1 /* integer to byte */
-i2c		    	1 I     I	1 /* integer to character */
-i2s	   	    	1 I     I     	1 /* integer to signed short */
-lcmp		    	1 LL    I	1 /* long compare */
-fcmpl		    	1 FF    I	1 /* float compare.  -1 on incomparable */
-fcmpg		    	1 FF    I	1 /* float compare.  1 on incomparable */
-dcmpl		    	1 DD    I	1 /* dbl floating cmp.  -1 on incomp */
-dcmpg		    	1 DD    I	1 /* dbl floating cmp.  1 on incomp */
-ifeq		    	3 I     -	1 /* goto if equal */
-ifne		    	3 I     -	1 /* goto if not equal */
-iflt		    	3 I     -	1 /* goto if less than */
-ifge		    	3 I     -	1 /* goto if greater than or equal */
-ifgt		    	3 I     -	1 /* goto if greater than */
-ifle		    	3 I     -	1 /* goto if less than or equal */
-if_icmpeq	    	3 II    -	1 /* compare top two elements of stack */
-if_icmpne	    	3 II    -	1 /* compare top two elements of stack */
-if_icmplt	    	3 II    -	1 /* compare top two elements of stack */
-if_icmpge	    	3 II    -	1 /* compare top two elements of stack */
-if_icmpgt	    	3 II    -	1 /* compare top two elements of stack */
-if_icmple	    	3 II    -	1 /* compare top two elements of stack */
-if_acmpeq	    	3 AA    -	1 /* compare top two objects of stack */
-if_acmpne	    	3 AA    -	1 /* compare top two objects of stack */
-goto		    	3 -     -	1 /* unconditional goto */
-jsr		    	3 -     R	1 /* jump subroutine */
-ret		    	2 -     -	1 /* return from subroutine */
-tableswitch	       99 I     -	1 /* goto (case) */
-lookupswitch	       99 I     -	1 /* goto (case) */
-ireturn		    	1 I     -	1 /* return integer from procedure */
-lreturn		    	1 L     -	1 /* return long from procedure */
-freturn		    	1 F     -	1 /* return float from procedure */
-dreturn		    	1 D     -	1 /* return double from procedure */
-areturn		    	1 A     -	1 /* return object from procedure */
-return		    	1 -     -	1 /* return (void) from procedure */
-getstatic       	3 -     ?	1 /* get static field value. */
-putstatic       	3 ?     -	1 /* assign static field value */
-getfield        	3 A     ?	1 /* get field value from object. */
-putfield        	3 ?     -	1 /* assign field value to object. */
-invokevirtual   	3 ?     ?      	1 /* call method, based on object. */
-invokespecial    	3 ?     ?      	1 /* call method, not based on object. */
-invokestatic       	3 ?     ?      	1 /* call a static method. */
-invokeinterface    	5 ?     ?      	1 /* call an interface method */
-xxxunusedxxx            0 ?     ?       1 /* was newfromname */        
-new                 	3 -     A     	1 /* Create a new object */
-newarray            	2 I     A     	1 /* Create a new array of non-objects*/
-anewarray           	3 I     A     	1 /* Create a new array of objects */
-arraylength	    	1 [?]   I	1 /* get length of array */
-athrow		    	1 O     -	1 /* throw an exception */
-checkcast           	3 A     A     	1 /* error if object not of given type */
-instanceof          	3 A     I     	1 /* is object of given type? */
-monitorenter	    	1 A     -	1 /* enter a monitored region of code */
-monitorexit	    	1 A     -	1 /* exit a monitored region of code */
-wide	        	0 -     -	1 /* prefix operation.   */
-multianewarray          4 ?     A       1 /* create multidimensional array */
-ifnull		    	3 A     -	1 /* goto if null */
-ifnonnull	    	3 A     -	1 /* goto if not null */
-
-# The following instructions are "long" versions.  They allow access to
-# variables with index greater than 255.
-
-goto_w		    	5 -     -	1 /* unconditional goto.  4byte offset */
-jsr_w		    	5 -     R	1 /* jump subroutine.  4byte offset */
-
-breakpoint	    	1 -     -	1 /* call breakpoint handler */
-
-# The compiler will not generate any of the following instructions.  That
-# are created by the interpreter from the non _quick versions of the
-# instructions.  
-
-ldc_quick 	     	2 -     ?	1
-ldc_w_quick      	3 -     ?	1
-ldc2_w_quick     	3 -     ?	1
-getfield_quick  	3 A     ?	1
-putfield_quick  	3 ?     -	1
-getfield2_quick        	3 A     ?	1
-putfield2_quick 	3 ?     -	1
-getstatic_quick 	3 -     ?	1
-putstatic_quick 	3 ?     -	1
-getstatic2_quick 	3 -     ?	1
-putstatic2_quick 	3 ?     _	1
-invokevirtual_quick 	3 ?     ?	1
-invokenonvirtual_quick  3 ?     ?	1
-invokesuper_quick       3 ?     ?	1
-invokestatic_quick 	3 ?     ?	1
-invokeinterface_quick 	5 ?     ?	1
-invokevirtualobject_quick 3 ?     ?	1
-invokeignored_quick     3 ?     ?	1
-new_quick          	3 -     A	1
-anewarray_quick    	3 I     A	1
-multianewarray_quick    4 ?     A	1
-checkcast_quick    	3 A     A	1
-instanceof_quick   	3 A     I	1
-
-# The following are generated when the offset is bigger than 255
-
-invokevirtual_quick_w   3 ?     ?	1
-getfield_quick_w  	3 A     ?	1
-putfield_quick_w  	3 ?     -	1
-
-# used for simplification
-
-nonnull_quick           1 A     -       1 /* throw exception if stacktop null */
--- a/jdk/src/share/javavm/include/opcodes.weight	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/* 
- * Copyright 1998-2007 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-char const opcode_weight[256] = {
-    1, 		/* nop */
-    1, 		/* aconst_null */
-    1, 		/* iconst_m1 */
-    1, 		/* iconst_0 */
-    1, 		/* iconst_1 */
-    1, 		/* iconst_2 */
-    1, 		/* iconst_3 */
-    1, 		/* iconst_4 */
-    1, 		/* iconst_5 */
-    1, 		/* lconst_0 */
-    1, 		/* lconst_1 */
-    1, 		/* fconst_0 */
-    1, 		/* fconst_1 */
-    1, 		/* fconst_2 */
-    1, 		/* dconst_0 */
-    1, 		/* dconst_1 */
-    1, 		/* bipush */
-    1, 		/* sipush */
-    1, 		/* ldc */
-    1, 		/* ldc_w */
-    1, 		/* ldc2_w */
-    1, 		/* iload */
-    1, 		/* lload */
-    1, 		/* fload */
-    1, 		/* dload */
-    1, 		/* aload */
-    1, 		/* iload_0 */
-    1, 		/* iload_1 */
-    1, 		/* iload_2 */
-    1, 		/* iload_3 */
-    1, 		/* lload_0 */
-    1, 		/* lload_1 */
-    1, 		/* lload_2 */
-    1, 		/* lload_3 */
-    1, 		/* fload_0 */
-    1, 		/* fload_1 */
-    1, 		/* fload_2 */
-    1, 		/* fload_3 */
-    1, 		/* dload_0 */
-    1, 		/* dload_1 */
-    1, 		/* dload_2 */
-    1, 		/* dload_3 */
-    1, 		/* aload_0 */
-    1, 		/* aload_1 */
-    1, 		/* aload_2 */
-    1, 		/* aload_3 */
-    1, 		/* iaload */
-    1, 		/* laload */
-    1, 		/* faload */
-    1, 		/* daload */
-    1, 		/* aaload */
-    1, 		/* baload */
-    1, 		/* caload */
-    1, 		/* saload */
-    1, 		/* istore */
-    1, 		/* lstore */
-    1, 		/* fstore */
-    1, 		/* dstore */
-    1, 		/* astore */
-    1, 		/* istore_0 */
-    1, 		/* istore_1 */
-    1, 		/* istore_2 */
-    1, 		/* istore_3 */
-    1, 		/* lstore_0 */
-    1, 		/* lstore_1 */
-    1, 		/* lstore_2 */
-    1, 		/* lstore_3 */
-    1, 		/* fstore_0 */
-    1, 		/* fstore_1 */
-    1, 		/* fstore_2 */
-    1, 		/* fstore_3 */
-    1, 		/* dstore_0 */
-    1, 		/* dstore_1 */
-    1, 		/* dstore_2 */
-    1, 		/* dstore_3 */
-    1, 		/* astore_0 */
-    1, 		/* astore_1 */
-    1, 		/* astore_2 */
-    1, 		/* astore_3 */
-    1, 		/* iastore */
-    1, 		/* lastore */
-    1, 		/* fastore */
-    1, 		/* dastore */
-    1, 		/* aastore */
-    1, 		/* bastore */
-    1, 		/* castore */
-    1, 		/* sastore */
-    1, 		/* pop */
-    1, 		/* pop2 */
-    1, 		/* dup */
-    1, 		/* dup_x1 */
-    1, 		/* dup_x2 */
-    1, 		/* dup2 */
-    1, 		/* dup2_x1 */
-    1, 		/* dup2_x2 */
-    1, 		/* swap */
-    1, 		/* iadd */
-    1, 		/* ladd */
-    1, 		/* fadd */
-    1, 		/* dadd */
-    1, 		/* isub */
-    1, 		/* lsub */
-    1, 		/* fsub */
-    1, 		/* dsub */
-    1, 		/* imul */
-    1, 		/* lmul */
-    1, 		/* fmul */
-    1, 		/* dmul */
-    1, 		/* idiv */
-    1, 		/* ldiv */
-    1, 		/* fdiv */
-    1, 		/* ddiv */
-    1, 		/* irem */
-    1, 		/* lrem */
-    1, 		/* frem */
-    1, 		/* drem */
-    1, 		/* ineg */
-    1, 		/* lneg */
-    1, 		/* fneg */
-    1, 		/* dneg */
-    1, 		/* ishl */
-    1, 		/* lshl */
-    1, 		/* ishr */
-    1, 		/* lshr */
-    1, 		/* iushr */
-    1, 		/* lushr */
-    1, 		/* iand */
-    1, 		/* land */
-    1, 		/* ior */
-    1, 		/* lor */
-    1, 		/* ixor */
-    1, 		/* lxor */
-    1, 		/* iinc */
-    1, 		/* i2l */
-    1, 		/* i2f */
-    1, 		/* i2d */
-    1, 		/* l2i */
-    1, 		/* l2f */
-    1, 		/* l2d */
-    1, 		/* f2i */
-    1, 		/* f2l */
-    1, 		/* f2d */
-    1, 		/* d2i */
-    1, 		/* d2l */
-    1, 		/* d2f */
-    1, 		/* i2b */
-    1, 		/* i2c */
-    1, 		/* i2s */
-    1, 		/* lcmp */
-    1, 		/* fcmpl */
-    1, 		/* fcmpg */
-    1, 		/* dcmpl */
-    1, 		/* dcmpg */
-    1, 		/* ifeq */
-    1, 		/* ifne */
-    1, 		/* iflt */
-    1, 		/* ifge */
-    1, 		/* ifgt */
-    1, 		/* ifle */
-    1, 		/* if_icmpeq */
-    1, 		/* if_icmpne */
-    1, 		/* if_icmplt */
-    1, 		/* if_icmpge */
-    1, 		/* if_icmpgt */
-    1, 		/* if_icmple */
-    1, 		/* if_acmpeq */
-    1, 		/* if_acmpne */
-    1, 		/* goto */
-    1, 		/* jsr */
-    1, 		/* ret */
-    1, 		/* tableswitch */
-    1, 		/* lookupswitch */
-    1, 		/* ireturn */
-    1, 		/* lreturn */
-    1, 		/* freturn */
-    1, 		/* dreturn */
-    1, 		/* areturn */
-    1, 		/* return */
-    1, 		/* getstatic */
-    1, 		/* putstatic */
-    1, 		/* getfield */
-    1, 		/* putfield */
-    1, 		/* invokevirtual */
-    1, 		/* invokespecial */
-    1, 		/* invokestatic */
-    1, 		/* invokeinterface */
-    1, 		/* xxxunusedxxx */
-    1, 		/* new */
-    1, 		/* newarray */
-    1, 		/* anewarray */
-    1, 		/* arraylength */
-    1, 		/* athrow */
-    1, 		/* checkcast */
-    1, 		/* instanceof */
-    1, 		/* monitorenter */
-    1, 		/* monitorexit */
-    1, 		/* wide */
-    1, 		/* multianewarray */
-    1, 		/* ifnull */
-    1, 		/* ifnonnull */
-    1, 		/* goto_w */
-    1, 		/* jsr_w */
-    1, 		/* breakpoint */
-    1, 		/* ldc_quick */
-    1, 		/* ldc_w_quick */
-    1, 		/* ldc2_w_quick */
-    1, 		/* getfield_quick */
-    1, 		/* putfield_quick */
-    1, 		/* getfield2_quick */
-    1, 		/* putfield2_quick */
-    1, 		/* getstatic_quick */
-    1, 		/* putstatic_quick */
-    1, 		/* getstatic2_quick */
-    1, 		/* putstatic2_quick */
-    1, 		/* invokevirtual_quick */
-    1, 		/* invokenonvirtual_quick */
-    1, 		/* invokesuper_quick */
-    1, 		/* invokestatic_quick */
-    1, 		/* invokeinterface_quick */
-    1, 		/* invokevirtualobject_quick */
-    1, 		/* invokeignored_quick */
-    1, 		/* new_quick */
-    1, 		/* anewarray_quick */
-    1, 		/* multianewarray_quick */
-    1, 		/* checkcast_quick */
-    1, 		/* instanceof_quick */
-    1, 		/* invokevirtual_quick_w */
-    1, 		/* getfield_quick_w */
-    1, 		/* putfield_quick_w */
-    1, 		/* nonnull_quick */
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-};
--- a/jdk/src/share/javavm/include/opcodes.wide	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,256 +0,0 @@
-NoWideOpcode(nop)
-NoWideOpcode(aconst_null)
-NoWideOpcode(iconst_m1)
-NoWideOpcode(iconst_0)
-NoWideOpcode(iconst_1)
-NoWideOpcode(iconst_2)
-NoWideOpcode(iconst_3)
-NoWideOpcode(iconst_4)
-NoWideOpcode(iconst_5)
-NoWideOpcode(lconst_0)
-NoWideOpcode(lconst_1)
-NoWideOpcode(fconst_0)
-NoWideOpcode(fconst_1)
-NoWideOpcode(fconst_2)
-NoWideOpcode(dconst_0)
-NoWideOpcode(dconst_1)
-NoWideOpcode(bipush)
-NoWideOpcode(sipush)
-NoWideOpcode(ldc)
-NoWideOpcode(ldc_w)
-NoWideOpcode(ldc2_w)
-WideOpcode(iload)
-WideOpcode(lload)
-WideOpcode(fload)
-WideOpcode(dload)
-WideOpcode(aload)
-NoWideOpcode(iload_0)
-NoWideOpcode(iload_1)
-NoWideOpcode(iload_2)
-NoWideOpcode(iload_3)
-NoWideOpcode(lload_0)
-NoWideOpcode(lload_1)
-NoWideOpcode(lload_2)
-NoWideOpcode(lload_3)
-NoWideOpcode(fload_0)
-NoWideOpcode(fload_1)
-NoWideOpcode(fload_2)
-NoWideOpcode(fload_3)
-NoWideOpcode(dload_0)
-NoWideOpcode(dload_1)
-NoWideOpcode(dload_2)
-NoWideOpcode(dload_3)
-NoWideOpcode(aload_0)
-NoWideOpcode(aload_1)
-NoWideOpcode(aload_2)
-NoWideOpcode(aload_3)
-NoWideOpcode(iaload)
-NoWideOpcode(laload)
-NoWideOpcode(faload)
-NoWideOpcode(daload)
-NoWideOpcode(aaload)
-NoWideOpcode(baload)
-NoWideOpcode(caload)
-NoWideOpcode(saload)
-WideOpcode(istore)
-WideOpcode(lstore)
-WideOpcode(fstore)
-WideOpcode(dstore)
-WideOpcode(astore)
-NoWideOpcode(istore_0)
-NoWideOpcode(istore_1)
-NoWideOpcode(istore_2)
-NoWideOpcode(istore_3)
-NoWideOpcode(lstore_0)
-NoWideOpcode(lstore_1)
-NoWideOpcode(lstore_2)
-NoWideOpcode(lstore_3)
-NoWideOpcode(fstore_0)
-NoWideOpcode(fstore_1)
-NoWideOpcode(fstore_2)
-NoWideOpcode(fstore_3)
-NoWideOpcode(dstore_0)
-NoWideOpcode(dstore_1)
-NoWideOpcode(dstore_2)
-NoWideOpcode(dstore_3)
-NoWideOpcode(astore_0)
-NoWideOpcode(astore_1)
-NoWideOpcode(astore_2)
-NoWideOpcode(astore_3)
-NoWideOpcode(iastore)
-NoWideOpcode(lastore)
-NoWideOpcode(fastore)
-NoWideOpcode(dastore)
-NoWideOpcode(aastore)
-NoWideOpcode(bastore)
-NoWideOpcode(castore)
-NoWideOpcode(sastore)
-NoWideOpcode(pop)
-NoWideOpcode(pop2)
-NoWideOpcode(dup)
-NoWideOpcode(dup_x1)
-NoWideOpcode(dup_x2)
-NoWideOpcode(dup2)
-NoWideOpcode(dup2_x1)
-NoWideOpcode(dup2_x2)
-NoWideOpcode(swap)
-NoWideOpcode(iadd)
-NoWideOpcode(ladd)
-NoWideOpcode(fadd)
-NoWideOpcode(dadd)
-NoWideOpcode(isub)
-NoWideOpcode(lsub)
-NoWideOpcode(fsub)
-NoWideOpcode(dsub)
-NoWideOpcode(imul)
-NoWideOpcode(lmul)
-NoWideOpcode(fmul)
-NoWideOpcode(dmul)
-NoWideOpcode(idiv)
-NoWideOpcode(ldiv)
-NoWideOpcode(fdiv)
-NoWideOpcode(ddiv)
-NoWideOpcode(irem)
-NoWideOpcode(lrem)
-NoWideOpcode(frem)
-NoWideOpcode(drem)
-NoWideOpcode(ineg)
-NoWideOpcode(lneg)
-NoWideOpcode(fneg)
-NoWideOpcode(dneg)
-NoWideOpcode(ishl)
-NoWideOpcode(lshl)
-NoWideOpcode(ishr)
-NoWideOpcode(lshr)
-NoWideOpcode(iushr)
-NoWideOpcode(lushr)
-NoWideOpcode(iand)
-NoWideOpcode(land)
-NoWideOpcode(ior)
-NoWideOpcode(lor)
-NoWideOpcode(ixor)
-NoWideOpcode(lxor)
-WideOpcode(iinc)
-NoWideOpcode(i2l)
-NoWideOpcode(i2f)
-NoWideOpcode(i2d)
-NoWideOpcode(l2i)
-NoWideOpcode(l2f)
-NoWideOpcode(l2d)
-NoWideOpcode(f2i)
-NoWideOpcode(f2l)
-NoWideOpcode(f2d)
-NoWideOpcode(d2i)
-NoWideOpcode(d2l)
-NoWideOpcode(d2f)
-NoWideOpcode(i2b)
-NoWideOpcode(i2c)
-NoWideOpcode(i2s)
-NoWideOpcode(lcmp)
-NoWideOpcode(fcmpl)
-NoWideOpcode(fcmpg)
-NoWideOpcode(dcmpl)
-NoWideOpcode(dcmpg)
-NoWideOpcode(ifeq)
-NoWideOpcode(ifne)
-NoWideOpcode(iflt)
-NoWideOpcode(ifge)
-NoWideOpcode(ifgt)
-NoWideOpcode(ifle)
-NoWideOpcode(if_icmpeq)
-NoWideOpcode(if_icmpne)
-NoWideOpcode(if_icmplt)
-NoWideOpcode(if_icmpge)
-NoWideOpcode(if_icmpgt)
-NoWideOpcode(if_icmple)
-NoWideOpcode(if_acmpeq)
-NoWideOpcode(if_acmpne)
-NoWideOpcode(goto)
-NoWideOpcode(jsr)
-WideOpcode(ret)
-NoWideOpcode(tableswitch)
-NoWideOpcode(lookupswitch)
-NoWideOpcode(ireturn)
-NoWideOpcode(lreturn)
-NoWideOpcode(freturn)
-NoWideOpcode(dreturn)
-NoWideOpcode(areturn)
-NoWideOpcode(return)
-NoWideOpcode(getstatic)
-NoWideOpcode(putstatic)
-NoWideOpcode(getfield)
-NoWideOpcode(putfield)
-NoWideOpcode(invokevirtual)
-NoWideOpcode(invokespecial)
-NoWideOpcode(invokestatic)
-NoWideOpcode(invokeinterface)
-NoWideOpcode(xxxunusedxxx)
-NoWideOpcode(new)
-NoWideOpcode(newarray)
-NoWideOpcode(anewarray)
-NoWideOpcode(arraylength)
-NoWideOpcode(athrow)
-NoWideOpcode(checkcast)
-NoWideOpcode(instanceof)
-NoWideOpcode(monitorenter)
-NoWideOpcode(monitorexit)
-NoWideOpcode(wide)
-NoWideOpcode(multianewarray)
-NoWideOpcode(ifnull)
-NoWideOpcode(ifnonnull)
-NoWideOpcode(goto_w)
-NoWideOpcode(jsr_w)
-NoWideOpcode(breakpoint)
-NoWideOpcode(ldc_quick)
-NoWideOpcode(ldc_w_quick)
-NoWideOpcode(ldc2_w_quick)
-NoWideOpcode(getfield_quick)
-NoWideOpcode(putfield_quick)
-NoWideOpcode(getfield2_quick)
-NoWideOpcode(putfield2_quick)
-NoWideOpcode(getstatic_quick)
-NoWideOpcode(putstatic_quick)
-NoWideOpcode(getstatic2_quick)
-NoWideOpcode(putstatic2_quick)
-NoWideOpcode(invokevirtual_quick)
-NoWideOpcode(invokenonvirtual_quick)
-NoWideOpcode(invokesuper_quick)
-NoWideOpcode(invokestatic_quick)
-NoWideOpcode(invokeinterface_quick)
-NoWideOpcode(invokevirtualobject_quick)
-NoWideOpcode(invokeignored_quick)
-NoWideOpcode(new_quick)
-NoWideOpcode(anewarray_quick)
-NoWideOpcode(multianewarray_quick)
-NoWideOpcode(checkcast_quick)
-NoWideOpcode(instanceof_quick)
-NoWideOpcode(invokevirtual_quick_w)
-NoWideOpcode(getfield_quick_w)
-NoWideOpcode(putfield_quick_w)
-NoWideOpcode(nonnull_quick)
-NoWideOpcode(Illegal230)
-NoWideOpcode(Illegal231)
-NoWideOpcode(Illegal232)
-NoWideOpcode(Illegal233)
-NoWideOpcode(Illegal234)
-NoWideOpcode(Illegal235)
-NoWideOpcode(Illegal236)
-NoWideOpcode(Illegal237)
-NoWideOpcode(Illegal238)
-NoWideOpcode(Illegal239)
-NoWideOpcode(Illegal240)
-NoWideOpcode(Illegal241)
-NoWideOpcode(Illegal242)
-NoWideOpcode(Illegal243)
-NoWideOpcode(Illegal244)
-NoWideOpcode(Illegal245)
-NoWideOpcode(Illegal246)
-NoWideOpcode(Illegal247)
-NoWideOpcode(Illegal248)
-NoWideOpcode(Illegal249)
-NoWideOpcode(Illegal250)
-NoWideOpcode(Illegal251)
-NoWideOpcode(Illegal252)
-NoWideOpcode(Illegal253)
-NoWideOpcode(Illegal254)
-NoWideOpcode(Illegal255)
--- a/jdk/src/share/javavm/include/sys_api.h	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/*
- * Copyright 1994-1999 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-#ifndef _JAVASOFT_SYS_API_H_
-#define _JAVASOFT_SYS_API_H_
-
-#include "hpi.h"
-
-extern HPI_MemoryInterface  *hpi_memory_interface;
-extern HPI_LibraryInterface *hpi_library_interface;
-extern HPI_SystemInterface  *hpi_system_interface;
-extern HPI_ThreadInterface  *hpi_thread_interface;
-extern HPI_FileInterface    *hpi_file_interface;
-extern HPI_SocketInterface  *hpi_socket_interface;
-
-#define sysMalloc(x)          hpi_memory_interface->Malloc(x)
-#define sysRealloc(x,y)       hpi_memory_interface->Realloc(x,y)
-#define sysFree(x)            hpi_memory_interface->Free(x)
-#define sysCalloc(x,y)        hpi_memory_interface->Calloc(x,y)
-#define sysStrdup(x)          hpi_memory_interface->Strdup(x)
-#define sysMapMem(x,y)        hpi_memory_interface->MapMem(x,y)
-#define sysUnmapMem(x,y,z)    hpi_memory_interface->UnmapMem(x,y,z)
-#define sysCommitMem(x,y,z)   hpi_memory_interface->CommitMem(x,y,z)
-#define sysDecommitMem(x,y,z) hpi_memory_interface->DecommitMem(x,y,z)
-#define sysAllocBlock(x,y)    hpi_memory_interface->AllocBlock(x,y)
-#define sysFreeBlock(x)       hpi_memory_interface->FreeBlock(x)
-
-#define sysBuildLibName(a,b,c,d) hpi_library_interface->BuildLibName(a,b,c,d)
-#define sysBuildFunName(a,b,c,d) hpi_library_interface->BuildFunName(a,b,c,d)
-#define sysLoadLibrary(a,b,c)        hpi_library_interface->LoadLibrary(a,b,c)
-#define sysUnloadLibrary(a)      hpi_library_interface->UnloadLibrary(a)
-#define sysFindLibraryEntry(a,b) hpi_library_interface->FindLibraryEntry(a,b)
-
-#define sysGetSysInfo()          hpi_system_interface->GetSysInfo()
-#define sysGetMilliTicks()       hpi_system_interface->GetMilliTicks()
-#define sysTimeMillis()          hpi_system_interface->TimeMillis()
-
-#define sysSignal(a,b)             hpi_system_interface->Signal(a,b)
-#define sysRaise(a)                hpi_system_interface->Raise(a)
-#define sysSignalNotify(a)         hpi_system_interface->SignalNotify(a)
-#define sysSignalWait()            hpi_system_interface->SignalWait()
-#define sysShutdown()              hpi_system_interface->Shutdown()
-#define sysSetLoggingLevel(a)      hpi_system_interface->SetLoggingLevel(a)
-#define sysSetMonitoringOn(a)      hpi_system_interface->SetMonitoringOn(a)
-#define sysGetLastErrorString(a,b) hpi_system_interface->GetLastErrorString(a,b)
-
-#define sysThreadBootstrap(a,b,c)  hpi_thread_interface->ThreadBootstrap(a,b,c)
-#define sysThreadCreate(a,b,c,d)   hpi_thread_interface->ThreadCreate(a,b,c,d)
-#define sysThreadSelf()            hpi_thread_interface->ThreadSelf()
-#define sysThreadYield()           hpi_thread_interface->ThreadYield()
-#define sysThreadSuspend(a)        hpi_thread_interface->ThreadSuspend(a)
-#define sysThreadResume(a)         hpi_thread_interface->ThreadResume(a)
-#define sysThreadSetPriority(a,b)  hpi_thread_interface->ThreadSetPriority(a,b)
-#define sysThreadGetPriority(a,b)  hpi_thread_interface->ThreadGetPriority(a,b)
-#define sysThreadStackPointer(a)   hpi_thread_interface->ThreadStackPointer(a)
-#define sysThreadStackTop(a)       hpi_thread_interface->ThreadStackTop(a)
-#define sysThreadRegs(a,b)         hpi_thread_interface->ThreadRegs(a,b)
-#define sysThreadSingle()          hpi_thread_interface->ThreadSingle()
-#define sysThreadMulti()           hpi_thread_interface->ThreadMulti()
-#define sysThreadCheckStack()      hpi_thread_interface->ThreadCheckStack()
-#define sysThreadPostException(a,b) \
-    hpi_thread_interface->ThreadPostException(a,b)
-#define sysThreadInterrupt(a)      hpi_thread_interface->ThreadInterrupt(a)
-#define sysThreadIsInterrupted(a,b) \
-    hpi_thread_interface->ThreadIsInterrupted(a,b)
-#define sysThreadAlloc(a)          hpi_thread_interface->ThreadAlloc(a)
-#define sysThreadFree()            hpi_thread_interface->ThreadFree()
-#define sysThreadCPUTime()         hpi_thread_interface->ThreadCPUTime()
-#define sysThreadGetStatus(a,b)    hpi_thread_interface->ThreadGetStatus(a,b)
-#define sysThreadEnumerateOver(a,b) \
-    hpi_thread_interface->ThreadEnumerateOver(a,b)
-#define sysThreadIsRunning(a)      hpi_thread_interface->ThreadIsRunning(a)
-#define sysThreadProfSuspend(a)    hpi_thread_interface->ThreadProfSuspend(a)
-#define sysThreadProfResume(a)     hpi_thread_interface->ThreadProfResume(a)
-#define sysAdjustTimeSlice(a)      hpi_thread_interface->AdjustTimeSlice(a)
-
-#define sysMonitorSizeof()         hpi_thread_interface->MonitorSizeof()
-#define sysMonitorInit(a)          hpi_thread_interface->MonitorInit(a)
-#define sysMonitorDestroy(a)       hpi_thread_interface->MonitorDestroy(a)
-#define sysMonitorEnter(a,b)       hpi_thread_interface->MonitorEnter(a,b)
-#define sysMonitorEntered(a,b)     hpi_thread_interface->MonitorEntered(a,b)
-#define sysMonitorExit(a,b)        hpi_thread_interface->MonitorExit(a,b)
-#define sysMonitorNotify(a,b)      hpi_thread_interface->MonitorNotify(a,b)
-#define sysMonitorNotifyAll(a,b)   hpi_thread_interface->MonitorNotifyAll(a,b)
-#define sysMonitorWait(a,b,c)      hpi_thread_interface->MonitorWait(a,b,c)
-#define sysMonitorInUse(a)         hpi_thread_interface->MonitorInUse(a)
-#define sysMonitorOwner(a)         hpi_thread_interface->MonitorOwner(a)
-#define sysMonitorGetInfo(a,b)     hpi_thread_interface->MonitorGetInfo(a,b)
-
-#define sysThreadInterruptEvent()  hpi_thread_interface->ThreadInterruptEvent()
-#define sysThreadNativeID(a)       hpi_thread_interface->ThreadNativeID(a)
-
-#define sysNativePath(a)        hpi_file_interface->NativePath(a)
-#define sysFileType(a)          hpi_file_interface->FileType(a)
-#define sysOpen(a,b,c)          hpi_file_interface->Open(a,b,c)
-#define sysClose(a)             hpi_file_interface->Close(a)
-#define sysSeek(a,b,c)          hpi_file_interface->Seek(a,b,c)
-#define sysSetLength(a,b)       hpi_file_interface->SetLength(a,b)
-#define sysSync(a)              hpi_file_interface->Sync(a)
-#define sysAvailable(a,b)       hpi_file_interface->Available(a,b)
-#define sysRead(a,b,c)          hpi_file_interface->Read(a,b,c)
-#define sysWrite(a,b,c)         hpi_file_interface->Write(a,b,c)
-#define sysFileSizeFD(a,b)      hpi_file_interface->FileSizeFD(a,b)
-
-#define sysSocketClose(a)        hpi_socket_interface->Close(a)
-#define sysSocketShutdown(a,b)   hpi_socket_interface->SocketShutdown(a,b)
-#define sysSocketAvailable(a,b)  hpi_socket_interface->Available(a,b)
-#define sysConnect(a,b,c)        hpi_socket_interface->Connect(a,b,c)
-#define sysBind(a,b,c)           hpi_socket_interface->Bind(a,b,c)
-#define sysAccept(a,b,c)         hpi_socket_interface->Accept(a,b,c)
-#define sysGetSockName(a,b,c)  hpi_socket_interface->GetSocketName(a,b,c)
-#define sysSendTo(a,b,c,d,e,f)   hpi_socket_interface->SendTo(a,b,c,d,e,f)
-#define sysRecvFrom(a,b,c,d,e,f) hpi_socket_interface->RecvFrom(a,b,c,d,e,f)
-#define sysListen(a,b)           hpi_socket_interface->Listen(a,b)
-#define sysRecv(a,b,c,d)         hpi_socket_interface->Recv(a,b,c,d)
-#define sysSend(a,b,c,d)         hpi_socket_interface->Send(a,b,c,d)
-#define sysTimeout(a,b)          hpi_socket_interface->Timeout(a,b)
-#define sysGetHostName(a, b)     hpi_socket_interface->GetHostName(a, b)
-#define sysGetHostByAddr(a, b, c) hpi_socket_interface->GetHostByAddr(a, b, c)
-#define sysGetHostByName(a)      hpi_socket_interface->GetHostByName(a)
-#define sysSocket(a,b,c)         hpi_socket_interface->Socket(a,b,c)
-#define sysGetSockOpt(a, b, c, d, e) hpi_socket_interface->SocketGetOption(a, b, c, d, e)
-#define sysSetSockOpt(a, b, c, d, e) hpi_socket_interface->SocketSetOption(a, b, c, d, e)
-#define sysGetProtoByName(a) hpi_socket_interface->GetProtoByName(a)
-
-#define SYS_SIG_DFL HPI_SIG_DFL
-#define SYS_SIG_ERR HPI_SIG_ERR
-#define SYS_SIG_IGN HPI_SIG_IGN
-
-#define SYS_OK         HPI_OK
-#define SYS_ERR        HPI_ERR
-#define SYS_INTRPT     HPI_INTRPT
-#define SYS_TIMEOUT    HPI_TIMEOUT
-#define SYS_NOMEM      HPI_NOMEM
-#define SYS_NORESOURCE HPI_NORESOURCE
-
-#define SYS_THREAD_RUNNABLE     HPI_THREAD_RUNNABLE
-#define SYS_THREAD_MONITOR_WAIT HPI_THREAD_MONITOR_WAIT
-#define SYS_THREAD_CONDVAR_WAIT HPI_THREAD_CONDVAR_WAIT
-
-#define MinimumPriority     HPI_MINIMUM_PRIORITY
-#define MaximumPriority     HPI_MAXIMUM_PRIORITY
-#define NormalPriority      HPI_NORMAL_PRIORITY
-
-#define SYS_THREAD_SUSPENDED   HPI_THREAD_SUSPENDED
-#define SYS_THREAD_INTERRUPTED HPI_THREAD_INTERRUPTED
-
-#define PAGE_ALIGNMENT      HPI_PAGE_ALIGNMENT
-
-#define SYS_TIMEOUT_INFINITY HPI_TIMEOUT_INFINITY
-
-#define SYS_FILETYPE_REGULAR      HPI_FILETYPE_REGULAR
-#define SYS_FILETYPE_DIRECTORY    HPI_FILETYPE_DIRECTORY
-#define SYS_FILETYPE_OTHER        HPI_FILETYPE_OTHER
-
-#endif /* !_JAVASOFT_SYS_API_H_ */
--- a/jdk/src/share/javavm/include/typedefs.h	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,120 +0,0 @@
-/*
- * Copyright 1994-2002 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-#ifndef _JAVASOFT_TYPEDEFS_H_
-#define _JAVASOFT_TYPEDEFS_H_
-
-#include "typedefs_md.h"        /* for int64_t */
-
-/*
- * Macros to deal with the JavaVM's stack alignment. Many machines
- * require doublewords to be double aligned.  This union is used by
- * code in math.h as a more portable way do alingnment on machines
- * that require it.  This union and the macros that use it came from
- * Netscape.
- */
-
-#ifdef HAVE_ALIGNED_LONGLONGS
-#define GET_INT64(_t,_addr)                                \
-        ((((int32_t*) &(_t))[0] = ((int32_t*)(_addr))[0]), \
-         (((int32_t*) &(_t))[1] = ((int32_t*)(_addr))[1]), \
-         (_t).j )
-#define SET_INT64(_t, _addr, _v)                           \
-        ( (_t).j = (_v),                                   \
-          ((int32_t*)(_addr))[0] = ((int32_t*) &(_t))[0],  \
-          ((int32_t*)(_addr))[1] = ((int32_t*) &(_t))[1] )
-#else
-#define GET_INT64(_t,_addr) (*(int64_t*)(_addr))
-#define SET_INT64(_t, _addr, _v) (*(int64_t*)(_addr) = (_v))
-#endif
-
-/* If double's must be aligned on doubleword boundaries then define this */
-#ifdef HAVE_ALIGNED_DOUBLES
-#define GET_DOUBLE(_t,_addr)                               \
-        ((((int32_t*) &(_t))[0] = ((int32_t*)(_addr))[0]), \
-         (((int32_t*) &(_t))[1] = ((int32_t*)(_addr))[1]), \
-         (_t).d )
-#define SET_DOUBLE(_t, _addr, _v)                          \
-        ( (_t).d = (_v),                                   \
-          ((int32_t*)(_addr))[0] = ((int32_t*) &(_t))[0],  \
-          ((int32_t*)(_addr))[1] = ((int32_t*) &(_t))[1] )
-#else
-#define GET_DOUBLE(_t,_addr) (*(jdouble*)(_addr))
-#define SET_DOUBLE(_t, _addr, _v) (*(jdouble*)(_addr) = (_v))
-#endif
-
-/* If pointers are 64bits then define this */
-#ifdef HAVE_64BIT_POINTERS
-#define GET_HANDLE(_t,_addr)                               \
-        ( ((int32_t*) &(_t))[0] = ((int32_t*)(_addr))[0]), \
-          ((int32_t*) &(_t))[1] = ((int32_t*)(_addr))[1]), \
-          (void*) (_t).l )
-#define SET_HANDLE(_t, _addr, _v)                          \
-        ( *(void**) &((_t).l) = (_v),                      \
-          ((int32_t*)(_addr))[0] = ((int32_t*) &(_t))[0],  \
-          ((int32_t*)(_addr))[1] = ((int32_t*) &(_t))[1] )
-#else
-#define GET_HANDLE(_t,_addr) (*(JHandle*)(_addr))
-#define SET_HANDLE(_t, _addr, _v) (*(JHandle*)(_addr) = (_v))
-#endif
-
-
-/*
- *   Printf-style formatters for fixed- and variable-width types as pointers and
- *   integers.
- *
- * Each platform-specific definitions file "typedefs_md.h"
- * must define the macro FORMAT64_MODIFIER, which is the modifier for '%x' or
- * '%d' formats to indicate a 64-bit quantity; commonly "l" (in LP64) or "ll"
- * (in ILP32).
- */
-
-/* Format 32-bit quantities. */
-#define INT32_FORMAT  "%d"
-#define UINT32_FORMAT "%u"
-#define PTR32_FORMAT  "0x%08x"
-
-/* Format 64-bit quantities. */
-#define INT64_FORMAT  "%" FORMAT64_MODIFIER "d"
-#define UINT64_FORMAT "%" FORMAT64_MODIFIER "u"
-#define PTR64_FORMAT  "0x%016" FORMAT64_MODIFIER "x"
-
-/* Format pointers and size_t (or size_t-like integer types) which change size
- *  between 32- and 64-bit.
- */
-#if defined(_LP64) || defined(_WIN64)
-#define PTR_FORMAT    PTR64_FORMAT
-#define SIZE_FORMAT   UINT64_FORMAT
-#define SSIZE_FORMAT  INT64_FORMAT
-#else
-#define PTR_FORMAT    PTR32_FORMAT
-#define SIZE_FORMAT   UINT32_FORMAT
-#define SSIZE_FORMAT  INT32_FORMAT
-#endif
-
-#define INTPTR_FORMAT PTR_FORMAT
-
-
-#endif /* !_JAVASOFT_TYPEDEFS_H_ */
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/bands.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/bands.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2002-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2002-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -126,15 +126,15 @@
     (*save_meta_rp) = (byte) XB;
     cm.init(u->rp, u->rplimit, u->meta_rp, 0, defc, length, null);
     (*save_meta_rp) = save_meta_xb;  // put it back, just to be tidy
-    NOT_PRODUCT(cp2 = (u->meta_rp - meta_rp0));
+    NOT_PRODUCT(cp2 = (int)(u->meta_rp - meta_rp0));
   }
   rplimit = u->rp;
 
   rewind();
 
 #ifndef PRODUCT
-  printcr(3,"readFrom %s at %p [%d values, %d bytes, cp=%d/%d]",
-           (name?name:"(band)"), minRP(), length, size(), cp1, cp2);
+  PRINTCR((3,"readFrom %s at %p [%d values, %d bytes, cp=%d/%d]",
+           (name?name:"(band)"), minRP(), length, size(), cp1, cp2));
   if (u->verbose_bands || u->verbose >= 4) dump();
 
   if (ix != null && u->verbose != 0 && length > 0) {
@@ -421,18 +421,22 @@
   BAND_INIT(file_modtime, DELTA5_spec, 0),
   BAND_INIT(file_options, UNSIGNED5_spec, 0),
 //BAND_INIT(file_bits, BYTE1_spec, 0),
-  {0}
+#ifndef PRODUCT
+  { 0, 0, 0, 0 }
+#else
+  { 0, 0 }
+#endif
 };
 #define NUM_BAND_INITS \
         (sizeof(all_band_inits)/sizeof(all_band_inits[0]))
 
 band* band::makeBands(unpacker* u) {
-  band* all_bands = U_NEW(band, BAND_LIMIT);
+  band* tmp_all_bands = U_NEW(band, BAND_LIMIT);
   for (int i = 0; i < BAND_LIMIT; i++) {
     assert((byte*)&all_band_inits[i+1]
            < (byte*)all_band_inits+sizeof(all_band_inits));
     const band_init& bi = all_band_inits[i];
-    band&            b  = all_bands[i];
+    band&            b  = tmp_all_bands[i];
     coding*          defc = coding::findBySpec(bi.defc);
     assert((defc == null) == (bi.defc == -1));  // no garbage, please
     assert(defc == null || !defc->isMalloc);
@@ -446,13 +450,13 @@
     b.name = bi.name;
 #endif
   }
-  return all_bands;
+  return tmp_all_bands;
 }
 
 void band::initIndexes(unpacker* u) {
-  band* all_bands = u->all_bands;
+  band* tmp_all_bands = u->all_bands;
   for (int i = 0; i < BAND_LIMIT; i++) {
-    band* scan = &all_bands[i];
+    band* scan = &tmp_all_bands[i];
     uint tag = scan->ixTag;  // Cf. #define INDEX(tag) above
     if (tag != 0 && tag != CONSTANT_Literal && (tag & SUBINDEX_BIT) == 0) {
       scan->setIndex(u->cp.getIndex(tag));
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/bytes.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/bytes.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2003 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -71,15 +71,17 @@
 
 void bytes::free() {
   if (ptr == dummy)  return;  // escaping from an error
-  if (ptr != null) mtrace('f', ptr, 0);
-  if (ptr != null) ::free(ptr);
+  if (ptr != null) {
+    mtrace('f', ptr, 0);
+    ::free(ptr);
+  }
   len = 0;
   ptr = 0;
 }
 
 int bytes::indexOf(byte c) {
   byte* p = (byte*) memchr(ptr, c, len);
-  return (p == 0) ? -1 : p - ptr;
+  return (p == 0) ? -1 : (int)(p - ptr);
 }
 
 byte* bytes::writeTo(byte* bp) {
@@ -174,8 +176,10 @@
   int len = length();
   for (int i = 0; i < len; i++) {
     void* p = (void*) get(i);
-    if (p != null)  mtrace('f', p, 0);
-    if (p != null)  ::free(p);
+    if (p != null)  {
+      mtrace('f', p, 0);
+      ::free(p);
+    }
   }
   free();
 }
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/bytes.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/bytes.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -117,7 +117,7 @@
 
 struct ptrlist : fillbytes {
   typedef const void* cvptr;
-  int    length()     { return size() / sizeof(cvptr); }
+  int    length()     { return (int)(size() / sizeof(cvptr)); }
   cvptr* base()       { return (cvptr*) fillbytes::base(); }
   cvptr& get(int i)   { return *(cvptr*)loc(i * sizeof(cvptr)); }
   cvptr* limit()      { return (cvptr*) fillbytes::limit(); }
@@ -133,7 +133,7 @@
   ::qsort((ptrls).base(), (ptrls).length(), sizeof(void*), fn)
 
 struct intlist : fillbytes {
-  int    length()     { return size() / sizeof(int); }
+  int    length()     { return (int)(size() / sizeof(int)); }
   int*   base()       { return (int*) fillbytes::base(); }
   int&   get(int i)   { return *(int*)loc(i * sizeof(int)); }
   int*   limit()      { return (int*) fillbytes::limit(); }
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/coding.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/coding.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2002-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2002-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -113,7 +113,7 @@
       jlong maxNegCode = range-1;
       while (IS_NEG_CODE(S,  maxPosCode))  --maxPosCode;
       while (!IS_NEG_CODE(S, maxNegCode))  --maxNegCode;
-      int maxPos = decode_sign(S, maxPosCode);
+      int maxPos = decode_sign(S, (uint)maxPosCode);
       if (maxPos < 0)
         this->max = INT_MAX_VALUE;  // 32-bit wraparound
       else
@@ -121,7 +121,7 @@
       if (maxNegCode < 0)
         this->min = 0;  // No negative codings at all.
       else
-        this->min = decode_sign(S, maxNegCode);
+        this->min = decode_sign(S, (uint)maxNegCode);
     }
   }
 
@@ -149,10 +149,10 @@
   coding* ptr = NEW(coding, 1);
   CHECK_NULL_0(ptr);
   coding* c = ptr->initFrom(spec);
-  if (c == null)  mtrace('f', ptr, 0);
-  if (c == null)
+  if (c == null) {
+    mtrace('f', ptr, 0);
     ::free(ptr);
-  else
+  } else
     // else caller should free it...
     c->isMalloc = true;
   return c;
@@ -167,9 +167,10 @@
 }
 
 void coding::free() {
-  if (isMalloc) mtrace('f', this, 0);
-  if (isMalloc)
+  if (isMalloc) {
+    mtrace('f', this, 0);
     ::free(this);
+  }
 }
 
 void coding_method::reset(value_stream* state) {
@@ -187,7 +188,7 @@
   byte* ptr = rp;
   // hand peel the i==0 part of the loop:
   uint b_i = *ptr++ & 0xFF;
-  if (B == 1 || b_i < L)
+  if (B == 1 || b_i < (uint)L)
     { rp = ptr; return b_i; }
   uint sum = b_i;
   uint H_i = H;
@@ -195,7 +196,7 @@
   for (int i = 2; i <= B_MAX; i++) { // easy for compilers to unroll if desired
     b_i = *ptr++ & 0xFF;
     sum += b_i * H_i;
-    if (i == B || b_i < L)
+    if (i == B || b_i < (uint)L)
       { rp = ptr; return sum; }
     H_i *= H;
   }
@@ -210,7 +211,7 @@
   byte* ptr = rp;
   // hand peel the i==0 part of the loop:
   uint b_i = *ptr++ & 0xFF;
-  if (B == 1 || b_i < L)
+  if (B == 1 || b_i < (uint)L)
     { rp = ptr; return b_i; }
   uint sum = b_i;
   uint lg_H_i = lgH;
@@ -218,7 +219,7 @@
   for (int i = 2; i <= B_MAX; i++) { // easy for compilers to unroll if desired
     b_i = *ptr++ & 0xFF;
     sum += b_i << lg_H_i;
-    if (i == B || b_i < L)
+    if (i == B || b_i < (uint)L)
       { rp = ptr; return sum; }
     lg_H_i += lgH;
   }
@@ -237,7 +238,7 @@
   byte* ptr = rp;
   if (B == 1 || H == 256) {
     size_t len = (size_t)N*B;
-    if (len / B != N || ptr+len > limit) {
+    if (len / B != (size_t)N || ptr+len > limit) {
       abort(ERB);
       return;
     }
@@ -325,7 +326,7 @@
 int getPopValue(value_stream* self, uint uval) {
   if (uval > 0) {
     // note that the initial parse performed a range check
-    assert(uval <= self->cm->fVlength);
+    assert(uval <= (uint)self->cm->fVlength);
     return self->cm->fValues[uval-1];
   } else {
     // take an unfavored value
@@ -368,7 +369,7 @@
 
 static maybe_inline
 int getDeltaValue(value_stream* self, uint uval, bool isSubrange) {
-  assert((bool)(self->c.isSubrange) == isSubrange);
+  assert((uint)(self->c.isSubrange) == (uint)isSubrange);
   assert(self->c.isSubrange | self->c.isFullRange);
   if (isSubrange)
     return self->sum = self->c.sumInUnsignedRange(self->sum, (int)uval);
@@ -443,7 +444,7 @@
     uval = coding::parse(rp, B, H);
     if (S != 0)
       uval = (uint) decode_sign(S, uval);
-    return getDeltaValue(this, uval, c.isSubrange);
+    return getDeltaValue(this, uval, (bool)c.isSubrange);
 
   case cmk_BHS1D1full:
     assert(S == 1 && D == 1 && c.isFullRange);
@@ -499,6 +500,9 @@
     assert(c.spec == BYTE1_spec);
     assert(B == 1 && H == 256 && S == 0 && D == 0);
     return getPopValue(this, *rp++ & 0xFF);
+
+  default:
+    break;
   }
   assert(false);
   return 0;
@@ -695,7 +699,7 @@
     for (int i = 0; i < N; i++) {
       uint val = vs.getInt();
       if (val == 0)  UN += 1;
-      if (!(val <= fVlength)) {
+      if (!(val <= (uint)fVlength)) {
         abort("pop token out of range");
         return;
       }
@@ -728,6 +732,7 @@
         switch (self->vs0.cmk) {
         case cmk_BHS0:   cmk2 = cmk_pop_BHS0;   break;
         case cmk_BYTE1:  cmk2 = cmk_pop_BYTE1;  break;
+        default: break;
         }
         self->vs0.cmk = cmk2;
         if (self != this) {
@@ -947,15 +952,17 @@
   CODING_INIT(4,240,1,1),
   CODING_INIT(4,248,0,1),
   CODING_INIT(4,248,1,1),
-
-  0
+  CODING_INIT(0,0,0,0)
 };
 #define BASIC_INDEX_LIMIT \
-        (sizeof(basic_codings)/sizeof(basic_codings[0])-1)
+        (int)(sizeof(basic_codings)/sizeof(basic_codings[0])-1)
 
 coding* coding::findByIndex(int idx) {
-  assert(_meta_canon_min == 1);
-  assert(_meta_canon_max+1 == BASIC_INDEX_LIMIT);
+#ifndef PRODUCT
+  /* Tricky assert here, constants and gcc complains about it without local. */
+  int index_limit = BASIC_INDEX_LIMIT;
+  assert(_meta_canon_min == 1 && _meta_canon_max+1 == index_limit);
+#endif
   if (idx >= _meta_canon_min && idx <= _meta_canon_max)
     return basic_codings[idx].init();
   else
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/coding.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/coding.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2002-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2002-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -35,9 +35,11 @@
 #define CODING_D(x) ((x)>>0  & 0xF)
 
 #define CODING_INIT(B, H, S, D) \
-  { CODING_SPEC(B, H, S, D) }
+  { CODING_SPEC(B, H, S, D) , 0, 0, 0, 0, 0, 0, 0, 0}
 
-#define long do_not_use_C_long_types_use_jlong_or_int
+// For debugging purposes, some compilers do not like this and will complain.
+//    #define long do_not_use_C_long_types_use_jlong_or_int
+// Use of the type "long" is problematic, do not use it.
 
 struct coding {
   int  spec;  // B,H,S,D
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/defines.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/defines.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -45,15 +45,15 @@
 #ifdef PRODUCT
 #define IF_PRODUCT(xxx) xxx
 #define NOT_PRODUCT(xxx)
-#define assert(p) (0)
-#define printcr false &&
+#define assert(p)
+#define PRINTCR(args)
 #else
 #define IF_PRODUCT(xxx)
 #define NOT_PRODUCT(xxx) xxx
-#define assert(p) ((p) || (assert_failed(#p), 1))
-#define printcr u->verbose && u->printcr_if_verbose
+#define assert(p) ((p) || assert_failed(#p))
+#define PRINTCR(args)  u->verbose && u->printcr_if_verbose args
 extern "C" void breakpoint();
-extern void assert_failed(const char*);
+extern int assert_failed(const char*);
 #define BREAK (breakpoint())
 #endif
 
@@ -79,7 +79,7 @@
 
 #define lengthof(array) (sizeof(array)/sizeof(array[0]))
 
-#define NEW(T, n)    (T*) must_malloc(sizeof(T)*(n))
+#define NEW(T, n)    (T*) must_malloc((int)(sizeof(T)*(n)))
 #define U_NEW(T, n)  (T*) u->alloc(sizeof(T)*(n))
 #define T_NEW(T, n)  (T*) u->temp_alloc(sizeof(T)*(n))
 
@@ -121,12 +121,12 @@
 
 #define null (0)
 
-#ifndef __sparc
-#define intptr_t jlong
-#endif
+/* Must cast to void *, then size_t, then int. */
+#define ptrlowbits(x)  ((int)(size_t)(void*)(x))
 
-#define ptrlowbits(x)  ((int) (intptr_t)(x))
-
+/* Back and forth from jlong to pointer */
+#define ptr2jlong(x)  ((jlong)(size_t)(void*)(x))
+#define jlong2ptr(x)  ((void*)(size_t)(x))
 
 // Keys used by Java:
 #define UNPACK_DEFLATE_HINT             "unpack.deflate.hint"
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/jni.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/jni.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2003 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -59,7 +59,8 @@
                                 void* buf, jlong minlen, jlong maxlen);
 
 static unpacker* get_unpacker(JNIEnv *env, jobject pObj, bool noCreate=false) {
-  unpacker* uPtr = (unpacker*) env->GetLongField(pObj, unpackerPtrFID);
+  unpacker* uPtr;
+  uPtr = (unpacker*)jlong2ptr(env->GetLongField(pObj, unpackerPtrFID));
   //fprintf(stderr, "get_unpacker(%p) uPtr=%p\n", pObj, uPtr);
   if (uPtr == null) {
     if (noCreate)  return null;
@@ -71,7 +72,7 @@
     //fprintf(stderr, "get_unpacker(%p) uPtr=%p initializing\n", pObj, uPtr);
     uPtr->init(read_input_via_jni);
     uPtr->jniobj = (void*) env->NewGlobalRef(pObj);
-    env->SetLongField(pObj, unpackerPtrFID, (jlong)uPtr);
+    env->SetLongField(pObj, unpackerPtrFID, ptr2jlong(uPtr));
   }
   uPtr->jnienv = env;  // keep refreshing this in case of MT access
   return uPtr;
@@ -150,7 +151,7 @@
   size_t buflen = 0;
   if (pBuf != null) {
     buf    = env->GetDirectBufferAddress(pBuf);
-    buflen = env->GetDirectBufferCapacity(pBuf);
+    buflen = (size_t)env->GetDirectBufferCapacity(pBuf);
     if (buflen == 0)  buf = null;
     if (buf == null) { THROW_IOE(ERROR_INTERNAL); return 0; }
     if ((size_t)offset >= buflen)
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/main.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/main.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2003-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -86,13 +86,13 @@
       readlen = (int)(maxlen - numread);
     int nr = 0;
     if (u->infileptr != null) {
-      nr = fread(bufptr, 1, readlen, u->infileptr);
+      nr = (int)fread(bufptr, 1, readlen, u->infileptr);
     } else {
 #ifndef WIN32
       // we prefer unbuffered inputs
-      nr = read(u->infileno, bufptr, readlen);
+      nr = (int)read(u->infileno, bufptr, readlen);
 #else
-      nr = fread(bufptr, 1, readlen, stdin);
+      nr = (int)fread(bufptr, 1, readlen, stdin);
 #endif
     }
     if (nr <= 0) {
@@ -279,7 +279,6 @@
   char** argbuf = init_args(argc, argv, envargc);
   char** arg0 = argbuf+envargc;
   char** argp = argbuf;
-  int ach;
 
   int verbose = 0;
   char* logfile = null;
@@ -370,7 +369,7 @@
   int magic;
 
   // check for GZIP input
-  magic = read_magic(&u, peek, sizeof(peek));
+  magic = read_magic(&u, peek, (int)sizeof(peek));
   if ((magic & GZIP_MAGIC_MASK) == GZIP_MAGIC) {
     // Oops; must slap an input filter on this data.
     setup_gzin(&u);
@@ -397,8 +396,8 @@
     if (u.aborting())  break;
 
     // Peek ahead for more data.
-    magic = read_magic(&u, peek, sizeof(peek));
-    if (magic != JAVA_PACKAGE_MAGIC) {
+    magic = read_magic(&u, peek, (int)sizeof(peek));
+    if (magic != (int)JAVA_PACKAGE_MAGIC) {
       if (magic != EOF_MAGIC)
         u.abort("garbage after end of pack archive");
       break;   // all done
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/unpack.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/unpack.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -27,6 +27,21 @@
 // Program for unpacking specially compressed Java packages.
 // John R. Rose
 
+/*
+ * When compiling for a 64bit LP64 system (longs and pointers being 64bits),
+ *    the printf format %ld is correct and use of %lld will cause warning
+ *    errors from some compilers (gcc/g++).
+ * _LP64 can be explicitly set (used on Linux).
+ * Solaris compilers will define __sparcv9 or __x86_64 on 64bit compilations.
+ */
+#if defined(_LP64) || defined(__sparcv9) || defined(__x86_64)
+  #define LONG_LONG_FORMAT "%ld"
+  #define LONG_LONG_HEX_FORMAT "%lx"
+#else
+  #define LONG_LONG_FORMAT "%lld"
+  #define LONG_LONG_HEX_FORMAT "%016llx"
+#endif
+
 #include <sys/types.h>
 
 #include <stdio.h>
@@ -253,12 +268,12 @@
 
 inline cpindex* cpool::getFieldIndex(entry* classRef) {
   assert(classRef->tagMatches(CONSTANT_Class));
-  assert((uint)classRef->inord < tag_count[CONSTANT_Class]);
+  assert((uint)classRef->inord < (uint)tag_count[CONSTANT_Class]);
   return &member_indexes[classRef->inord*2+0];
 }
 inline cpindex* cpool::getMethodIndex(entry* classRef) {
   assert(classRef->tagMatches(CONSTANT_Class));
-  assert((uint)classRef->inord < tag_count[CONSTANT_Class]);
+  assert((uint)classRef->inord < (uint)tag_count[CONSTANT_Class]);
   return &member_indexes[classRef->inord*2+1];
 }
 
@@ -341,7 +356,7 @@
     rplimit += nr;
     fetch -= nr;
     bytes_read += nr;
-    assert(remaining == (input.limit() - rplimit));
+    assert(remaining == (julong)(input.limit() - rplimit));
   }
   return true;
 }
@@ -441,9 +456,13 @@
     e->requestOutputIndex(cp, -size);
     // Later on we'll fix the bits.
     class_fixup_type.addByte(size);
-    class_fixup_offset.add(wpoffset());
+    class_fixup_offset.add((int)wpoffset());
     class_fixup_ref.add(e);
-    return !assert(1) ? 0 : 0x20+size;  // 0x22 is easy to eyeball
+#ifdef PRODUCT
+    return 0;
+#else
+    return 0x20+size;  // 0x22 is easy to eyeball
+#endif
   }
 }
 
@@ -472,7 +491,7 @@
 void* unpacker::alloc_heap(size_t size, bool smallOK, bool temp) {
   CHECK_0;
   if (!smallOK || size > SMALL) {
-    void* res = must_malloc(size);
+    void* res = must_malloc((int)size);
     (temp ? &tmallocs : &mallocs)->add(res);
     return res;
   }
@@ -481,7 +500,7 @@
     xsmallbuf.init(CHUNK);
     (temp ? &tmallocs : &mallocs)->add(xsmallbuf.base());
   }
-  int growBy = size;
+  int growBy = (int)size;
   growBy += -growBy & 7;  // round up mod 8
   return xsmallbuf.grow(growBy);
 }
@@ -514,7 +533,7 @@
     FIRST_READ  = MAGIC_BYTES + AH_LENGTH_MIN
   };
   bool foreign_buf = (read_input_fn == null);
-  byte initbuf[FIRST_READ + C_SLOP + 200];  // 200 is for JAR I/O
+  byte initbuf[(int)FIRST_READ + (int)C_SLOP + 200];  // 200 is for JAR I/O
   if (foreign_buf) {
     // inbytes is all there is
     input.set(inbytes);
@@ -553,7 +572,7 @@
     // Copy until EOF; assume the JAR file is the last segment.
     fprintf(errstrm, "Copy-mode.\n");
     for (;;) {
-      jarout->write_data(rp, input_remaining());
+      jarout->write_data(rp, (int)input_remaining());
       if (foreign_buf)
         break;  // one-time use of a passed in buffer
       if (input.size() < CHUNK) {
@@ -572,7 +591,7 @@
 
   // Read the magic number.
   magic = 0;
-  for (int i1 = 0; i1 < sizeof(magic); i1++) {
+  for (int i1 = 0; i1 < (int)sizeof(magic); i1++) {
     magic <<= 8;
     magic += (*rp++ & 0xFF);
   }
@@ -586,7 +605,7 @@
   majver = hdr.getInt();
   hdrVals += 2;
 
-  if (magic != JAVA_PACKAGE_MAGIC ||
+  if (magic != (int)JAVA_PACKAGE_MAGIC ||
       (majver != JAVA5_PACKAGE_MAJOR_VERSION  &&
        majver != JAVA6_PACKAGE_MAJOR_VERSION) ||
       (minver != JAVA5_PACKAGE_MINOR_VERSION  &&
@@ -633,19 +652,19 @@
   // Now we can size the whole archive.
   // Read everything else into a mega-buffer.
   rp = hdr.rp;
-  int header_size_0 = (rp - input.base()); // used-up header (4byte + 3int)
-  int header_size_1 = (rplimit - rp);      // buffered unused initial fragment
+  int header_size_0 = (int)(rp - input.base()); // used-up header (4byte + 3int)
+  int header_size_1 = (int)(rplimit - rp);      // buffered unused initial fragment
   int header_size   = header_size_0+header_size_1;
   unsized_bytes_read = header_size_0;
   CHECK;
   if (foreign_buf) {
-    if (archive_size > header_size_1) {
+    if (archive_size > (size_t)header_size_1) {
       abort("EOF reading fixed input buffer");
       return;
     }
   } else if (archive_size > 0) {
-    input.set(U_NEW(byte, (size_t) header_size_0 + archive_size + C_SLOP),
-              (size_t) header_size_0 + archive_size);
+    input.set(U_NEW(byte, (size_t)(header_size_0 + archive_size + C_SLOP)),
+              (size_t) header_size_0 + (size_t)archive_size);
     assert(input.limit()[0] == 0);
     // Move all the bytes we read initially into the real buffer.
     input.b.copyFrom(initbuf, header_size);
@@ -712,7 +731,7 @@
   }
 
   int cp_counts[N_TAGS_IN_ORDER];
-  for (int k = 0; k < N_TAGS_IN_ORDER; k++) {
+  for (int k = 0; k < (int)N_TAGS_IN_ORDER; k++) {
     if (!(archive_options & AO_HAVE_CP_NUMBERS)) {
       switch (TAGS_IN_ORDER[k]) {
       case CONSTANT_Integer:
@@ -753,7 +772,10 @@
     abort("EOF reading archive header");
 
   // Now size the CP.
-  assert(N_TAGS_IN_ORDER == cpool::NUM_COUNTS);
+#ifndef PRODUCT
+  bool x = (N_TAGS_IN_ORDER == cpool::NUM_COUNTS);
+  assert(x);
+#endif //PRODUCT
   cp.init(this, cp_counts);
   CHECK;
 
@@ -766,7 +788,7 @@
   // meta-bytes, if any, immediately follow archive header
   //band_headers.readData(band_headers_size);
   ensure_input(band_headers_size);
-  if (input_remaining() < band_headers_size) {
+  if (input_remaining() < (size_t)band_headers_size) {
     abort("EOF reading band headers");
     return;
   }
@@ -789,12 +811,14 @@
 void unpacker::finish() {
   if (verbose >= 1) {
     fprintf(errstrm,
-            "A total of %lld bytes were read in %d segment(s).\n",
-            bytes_read_before_reset+bytes_read,
+            "A total of "
+            LONG_LONG_FORMAT " bytes were read in %d segment(s).\n",
+            (bytes_read_before_reset+bytes_read),
             segments_read_before_reset+1);
     fprintf(errstrm,
-            "A total of %lld file content bytes were written.\n",
-            bytes_written_before_reset+bytes_written);
+            "A total of "
+            LONG_LONG_FORMAT " file content bytes were written.\n",
+            (bytes_written_before_reset+bytes_written));
     fprintf(errstrm,
             "A total of %d files (of which %d are classes) were written to output.\n",
             files_written_before_reset+files_written,
@@ -822,7 +846,7 @@
   int next_entry = 0;
 
   // Size the constant pool:
-  for (int k = 0; k < N_TAGS_IN_ORDER; k++) {
+  for (int k = 0; k < (int)N_TAGS_IN_ORDER; k++) {
     byte tag = TAGS_IN_ORDER[k];
     int  len = counts[k];
     tag_count[tag] = len;
@@ -902,8 +926,8 @@
 }
 
 static int compare_Utf8_chars(bytes& b1, bytes& b2) {
-  int l1 = b1.len;
-  int l2 = b2.len;
+  int l1 = (int)b1.len;
+  int l2 = (int)b2.len;
   int l0 = (l1 < l2) ? l1 : l2;
   byte* p1 = b1.ptr;
   byte* p2 = b2.ptr;
@@ -949,10 +973,12 @@
   // First band:  Read lengths of shared prefixes.
   if (len > PREFIX_SKIP_2)
     cp_Utf8_prefix.readData(len - PREFIX_SKIP_2);
+  NOT_PRODUCT(else cp_Utf8_prefix.readData(0));  // for asserts
 
   // Second band:  Read lengths of unshared suffixes:
   if (len > SUFFIX_SKIP_1)
     cp_Utf8_suffix.readData(len - SUFFIX_SKIP_1);
+  NOT_PRODUCT(else cp_Utf8_suffix.readData(0));  // for asserts
 
   bytes* allsuffixes = T_NEW(bytes, len);
   CHECK;
@@ -999,7 +1025,7 @@
       CHECK;
       tmallocs.add(chars.ptr); // free it later
     } else {
-      int shrink = chars.limit() - chp;
+      int shrink = (int)(chars.limit() - chp);
       chars.len -= shrink;
       charbuf.b.len -= shrink;  // ungrow to reclaim buffer space
       // Note that we did not reclaim the final '\0'.
@@ -1008,7 +1034,9 @@
     }
   }
   //cp_Utf8_chars.done();
-  if (assert(1))  charbuf.b.set(null, 0); // tidy
+#ifndef PRODUCT
+  charbuf.b.set(null, 0); // tidy
+#endif
 
   // Fourth band:  Go back and size the specially packed strings.
   int maxlen = 0;
@@ -1041,7 +1069,7 @@
   for (i = 0; i < len; i++) {
     bytes& chars = allsuffixes[i];
     if (chars.ptr != null)  continue;  // already input
-    int suffix = chars.len;  // pick up the hack
+    int suffix = (int)chars.len;  // pick up the hack
     uint size3 = suffix * 3;
     if (suffix == 0)  continue;  // done with empty string
     chars.malloc(size3);
@@ -1071,7 +1099,7 @@
   for (i = 0; i < len; i++) {
     bytes& chars = allsuffixes[i];
     int prefix = (i < PREFIX_SKIP_2)? 0: cp_Utf8_prefix.getInt();
-    int suffix = chars.len;
+    int suffix = (int)chars.len;
     byte* fillp;
     // by induction, the buffer is already filled with the prefix
     // make sure the prefix value is not corrupted, though:
@@ -1084,7 +1112,7 @@
     fillp = chars.writeTo(fillp);
     assert(bigbuf.inBounds(fillp));
     *fillp = 0;  // bigbuf must contain a well-formed Utf8 string
-    int length = fillp - bigbuf.ptr;
+    int length = (int)(fillp - bigbuf.ptr);
     bytes& value = cpMap[i].value.b;
     value.set(U_NEW(byte, length+1), length);
     value.copyFrom(bigbuf.ptr, length);
@@ -1215,12 +1243,12 @@
 
   int i;
 
-  for (int k = 0; k < N_TAGS_IN_ORDER; k++) {
+  for (int k = 0; k < (int)N_TAGS_IN_ORDER; k++) {
     byte tag = TAGS_IN_ORDER[k];
     int  len = cp.tag_count[tag];
     int base = cp.tag_base[tag];
 
-    printcr(1,"Reading %d %s entries...", len, NOT_PRODUCT(TAG_NAME[tag])+0);
+    PRINTCR((1,"Reading %d %s entries...", len, NOT_PRODUCT(TAG_NAME[tag])+0));
     entry* cpMap = &cp.entries[base];
     for (i = 0; i < len; i++) {
       cpMap[i].tag = tag;
@@ -1282,7 +1310,7 @@
 #ifndef PRODUCT
     cpindex* ix = &cp.tag_index[tag];
     assert(ix->ixTag == tag);
-    assert(ix->len   == len);
+    assert((int)ix->len   == len);
     assert(ix->base1 == cpMap);
 #endif
     CHECK;
@@ -1293,7 +1321,7 @@
   cp.initMemberIndexes();
   CHECK;
 
-  printcr(1,"parsed %d constant pool entries in %d bytes", cp.nentries, (rp - rp0));
+  PRINTCR((1,"parsed %d constant pool entries in %d bytes", cp.nentries, (rp - rp0)));
 
   #define SNAME(n,s) #s "\0"
   const char* symNames = (
@@ -1307,7 +1335,7 @@
     bytes name; name.set(symNames);
     if (name.len > 0 && name.ptr[0] != '0') {
       cp.sym[sn] = cp.ensureUtf8(name);
-      printcr(4, "well-known sym %d=%s", sn, cp.sym[sn]->string());
+      PRINTCR((4, "well-known sym %d=%s", sn, cp.sym[sn]->string()));
     }
     symNames += name.len + 1;  // skip trailing null to next name
   }
@@ -1352,7 +1380,7 @@
   assert(flag_limit != 0);  // must be set up already
   if (idx >= 0) {
     // Fixed attr.
-    if (idx >= flag_limit)
+    if (idx >= (int)flag_limit)
       abort("attribute index too large");
     if (isRedefined(idx))
       abort("redefined attribute index");
@@ -1635,7 +1663,7 @@
             for (;;) {
               int caseval = 0;
               lp = parseNumeral(lp, caseval);
-              band_stack.add((void*)caseval);
+              band_stack.add((void*)(size_t)caseval);
               if (*lp == '-') {
                 // new in version 160, allow (1-5) for (1,2,3,4,5)
                 if (u->majver < JAVA6_PACKAGE_MAJOR_VERSION) {
@@ -1654,7 +1682,7 @@
                 }
                 for (;;) {
                   ++caseval;
-                  band_stack.add((void*)caseval);
+                  band_stack.add((void*)(size_t)caseval);
                   if (caseval == caselimit)  break;
                 }
               }
@@ -1921,7 +1949,7 @@
   for (byte* cp = ptr + pos; --cp >= ptr; ) {
     assert(x.inBounds(cp));
     if (*cp >= chmin && *cp <= chmax)
-      return cp - ptr;
+      return (int)(cp - ptr);
   }
   return -1;
 }
@@ -1976,7 +2004,7 @@
     entry* inner = ic_this_class.getRef();
     CHECK;
     uint inord = inner->inord;
-    assert(inord < cp.tag_count[CONSTANT_Class]);
+    assert(inord < (uint)cp.tag_count[CONSTANT_Class]);
     if (ic_index[inord] != null) {
       abort("identical inner class");
       break;
@@ -2003,10 +2031,10 @@
       bytes number;
       bytes name;
       // Parse n into pkgOuter and name (and number).
-      printcr(5, "parse short IC name %s", n.ptr);
+      PRINTCR((5, "parse short IC name %s", n.ptr));
       int dollar1, dollar2;  // pointers to $ in the pattern
       // parse n = (<pkg>/)*<outer>($<number>)?($<name>)?
-      int nlen = n.len;
+      int nlen = (int)n.len;
       int pkglen = lastIndexOf(SLASH_MIN,  SLASH_MAX,  n, nlen) + 1;
       dollar2    = lastIndexOf(DOLLAR_MIN, DOLLAR_MAX, n, nlen);
       if (dollar2 < 0) {
@@ -2035,8 +2063,8 @@
         pkgOuter = n.slice(0, dollar1);
       else
         pkgOuter.set(null,0);
-      printcr(5,"=> %s$ 0%s $%s",
-              pkgOuter.string(), number.string(), name.string());
+      PRINTCR((5,"=> %s$ 0%s $%s",
+              pkgOuter.string(), number.string(), name.string()));
 
       if (pkgOuter.ptr != null)
         ics[i].outer = cp.ensureClass(pkgOuter);
@@ -2049,7 +2077,7 @@
     if (ics[i].outer != null) {
       uint outord = ics[i].outer->inord;
       if (outord != NO_INORD) {
-        assert(outord < cp.tag_count[CONSTANT_Class]);
+        assert(outord < (uint)cp.tag_count[CONSTANT_Class]);
         ics[i].next_sibling = ic_child_index[outord];
         ic_child_index[outord] = &ics[i];
       }
@@ -2060,8 +2088,7 @@
 }
 
 void unpacker::read_classes() {
-  int i;
-  printcr(1,"  ...scanning %d classes...", class_count);
+  PRINTCR((1,"  ...scanning %d classes...", class_count));
   class_this.readData(class_count);
   class_super.readData(class_count);
   class_interface_count.readData(class_count);
@@ -2070,6 +2097,7 @@
   CHECK;
 
   #if 0
+  int i;
   // Make a little mark on super-classes.
   for (i = 0; i < class_count; i++) {
     entry* e = class_super.getRefN();
@@ -2099,8 +2127,8 @@
 
   read_code_headers();
 
-  printcr(1,"scanned %d classes, %d fields, %d methods, %d code headers",
-          class_count, field_count, method_count, code_count);
+  PRINTCR((1,"scanned %d classes, %d fields, %d methods, %d code headers",
+          class_count, field_count, method_count, code_count));
 }
 
 maybe_inline
@@ -2137,7 +2165,7 @@
     }
     indexBits &= indexMask;  // ignore classfile flag bits
     for (idx = 0; indexBits != 0; idx++, indexBits >>= 1) {
-      ad.flag_count[idx] += (indexBits & 1);
+      ad.flag_count[idx] += (int)(indexBits & 1);
     }
   }
   // we'll scan these again later for output:
@@ -2337,7 +2365,7 @@
   for (idx = 0; idx < ad.layouts.length(); idx++) {
     if (ad.getLayout(idx) == null)
       continue;  // none at this fixed index <32
-    if (idx < ad.flag_limit && ad.isPredefined(idx))
+    if (idx < (int)ad.flag_limit && ad.isPredefined(idx))
       continue;  // already handled
     if (ad.getCount(idx) == 0)
       continue;  // no attributes of this type (then why transmit layouts?)
@@ -2351,9 +2379,9 @@
   if (count == 0)  return;
   layout_definition* lo = getLayout(idx);
   if (lo != null) {
-    printcr(1, "counted %d [redefined = %d predefined = %d] attributes of type %s.%s",
+    PRINTCR((1, "counted %d [redefined = %d predefined = %d] attributes of type %s.%s",
             count, isRedefined(idx), isPredefined(idx),
-            ATTR_CONTEXT_NAME[attrc], lo->name);
+            ATTR_CONTEXT_NAME[attrc], lo->name));
   }
   bool hasCallables = lo->hasCallables();
   band** bands = lo->bands();
@@ -2376,13 +2404,13 @@
       }
     }
     // Now consult whichever callables have non-zero entry counts.
-    readBandData(bands, -1);
+    readBandData(bands, (uint)-1);
   }
 }
 
 // Recursive helper to the previous function:
 void unpacker::attr_definitions::readBandData(band** body, uint count) {
-  int i, j, k;
+  int j, k;
   for (j = 0; body[j] != null; j++) {
     band& b = *body[j];
     if (b.defc != null) {
@@ -2427,7 +2455,7 @@
       }
       break;
     case EK_CBLE:
-      assert(count == -1);  // incoming count is meaningless
+      assert((int)count == -1);  // incoming count is meaningless
       k = b.length;
       assert(k >= 0);
       // This is intended and required for non production mode.
@@ -2490,7 +2518,7 @@
         assert(le_kind == EK_INT || le_kind == EK_REPL || le_kind == EK_UN);
         x = b.getInt();
 
-        assert(!b.le_bci || prevBCI == to_bci(prevBII));
+        assert(!b.le_bci || prevBCI == (int)to_bci(prevBII));
         switch (b.le_bci) {
         case EK_BCI:   // PH:  transmit R(bci), store bci
           x = to_bci(prevBII = x);
@@ -2505,7 +2533,7 @@
           prevBCI += x;
           break;
         }
-        assert(!b.le_bci || prevBCI == to_bci(prevBII));
+        assert(!b.le_bci || prevBCI == (int)to_bci(prevBII));
 
         switch (b.le_len) {
         case 0: break;
@@ -2721,8 +2749,8 @@
 // Cf. PackageReader.readByteCodes
 inline  // called exactly once => inline
 void unpacker::read_bcs() {
-  printcr(3, "reading compressed bytecodes and operands for %d codes...",
-          code_count);
+  PRINTCR((3, "reading compressed bytecodes and operands for %d codes...",
+          code_count));
 
   // read from bc_codes and bc_case_count
   fillbytes all_switch_ops;
@@ -2825,18 +2853,18 @@
 
   // Go through the formality, so we can use it in a regular fashion later:
   assert(rp == rp0);
-  bc_codes.readData(opptr - rp);
+  bc_codes.readData((int)(opptr - rp));
 
   int i = 0;
 
   // To size instruction bands correctly, we need info on switches:
-  bc_case_count.readData(all_switch_ops.size());
-  for (i = 0; i < all_switch_ops.size(); i++) {
+  bc_case_count.readData((int)all_switch_ops.size());
+  for (i = 0; i < (int)all_switch_ops.size(); i++) {
     int caseCount = bc_case_count.getInt();
     int bc        = all_switch_ops.getByte(i);
     bc_label.expectMoreLength(1+caseCount); // default label + cases
     bc_case_value.expectMoreLength(bc == bc_tableswitch ? 1 : caseCount);
-    printcr(2, "switch bc=%d caseCount=%d", bc, caseCount);
+    PRINTCR((2, "switch bc=%d caseCount=%d", bc, caseCount));
   }
   bc_case_count.rewind();  // uses again for output
 
@@ -2849,15 +2877,14 @@
   // The bc_escbyte band is counted by the immediately previous band.
   bc_escbyte.readData(bc_escsize.getIntTotal());
 
-  printcr(3, "scanned %d opcode and %d operand bytes for %d codes...",
+  PRINTCR((3, "scanned %d opcode and %d operand bytes for %d codes...",
           (int)(bc_codes.size()),
           (int)(bc_escsize.maxRP() - bc_case_value.minRP()),
-          code_count);
+          code_count));
 }
 
 void unpacker::read_bands() {
   byte* rp0 = rp;
-  int i;
 
   read_file_header();
   CHECK;
@@ -2886,9 +2913,9 @@
 /// CP routines
 
 entry*& cpool::hashTabRef(byte tag, bytes& b) {
-  printcr(5, "hashTabRef tag=%d %s[%d]", tag, b.string(), b.len);
-  uint hash = tag + b.len;
-  for (int i = 0; i < b.len; i++) {
+  PRINTCR((5, "hashTabRef tag=%d %s[%d]", tag, b.string(), b.len));
+  uint hash = tag + (int)b.len;
+  for (int i = 0; i < (int)b.len; i++) {
     hash = hash * 31 + (0xFF & b.ptr[i]);
   }
   entry**  ht = hashTab;
@@ -2905,15 +2932,15 @@
       // Note:  hash2 must be relatively prime to hlen, hence the "|1".
       hash2 = (((hash % 499) & (hlen-1)) | 1);
     hash1 += hash2;
-    if (hash1 >= hlen)  hash1 -= hlen;
-    assert(hash1 < hlen);
+    if (hash1 >= (uint)hlen)  hash1 -= hlen;
+    assert(hash1 < (uint)hlen);
     assert(++probes < hlen);
   }
   #ifndef PRODUCT
   hash_probes[0] += 1;
   hash_probes[1] += probes;
   #endif
-  printcr(5, " => @%d %p", hash1, ht[hash1]);
+  PRINTCR((5, " => @%d %p", hash1, ht[hash1]));
   return ht[hash1];
 }
 
@@ -2939,7 +2966,7 @@
   u->saveTo(e.value.b, b);
   assert(&e >= first_extra_entry);
   insert_extra(&e, tag_extras[CONSTANT_Utf8]);
-  printcr(4,"ensureUtf8 miss %s", e.string());
+  PRINTCR((4,"ensureUtf8 miss %s", e.string()));
   return ix = &e;
 }
 
@@ -2961,7 +2988,7 @@
   e.value.b = utf->value.b;
   assert(&e >= first_extra_entry);
   insert_extra(&e, tag_extras[CONSTANT_Class]);
-  printcr(4,"ensureClass miss %s", e.string());
+  PRINTCR((4,"ensureClass miss %s", e.string()));
   return &e;
 }
 
@@ -2980,7 +3007,7 @@
     int refnum = 0;
     bytes form = e.refs[refnum++]->asUtf8();
     buf.empty();
-    for (int j = 0; j < form.len; j++) {
+    for (int j = 0; j < (int)form.len; j++) {
       int c = form.ptr[j];
       buf.addByte(c);
       if (c == 'L') {
@@ -2990,7 +3017,7 @@
     }
     assert(refnum == e.nrefs);
     bytes& sig = buf.b;
-    printcr(5,"signature %d %s -> %s", i, form.ptr, sig.ptr);
+    PRINTCR((5,"signature %d %s -> %s", i, form.ptr, sig.ptr));
 
     // try to find a pre-existing Utf8:
     entry* &e2 = hashTabRef(CONSTANT_Utf8, sig);
@@ -2999,7 +3026,7 @@
       e.value.b = e2->value.b;
       e.refs[0] = e2;
       e.nrefs = 1;
-      printcr(5,"signature replaced %d => %s", i, e.string());
+      PRINTCR((5,"signature replaced %d => %s", i, e.string()));
       nreused++;
     } else {
       // there is no other replacement; reuse this CP entry as a Utf8
@@ -3007,15 +3034,15 @@
       e.tag = CONSTANT_Utf8;
       e.nrefs = 0;
       e2 = &e;
-      printcr(5,"signature changed %d => %s", e.inord, e.string());
+      PRINTCR((5,"signature changed %d => %s", e.inord, e.string()));
     }
     nsigs++;
   }
-  printcr(1,"expanded %d signatures (reused %d utfs)", nsigs, nreused);
+  PRINTCR((1,"expanded %d signatures (reused %d utfs)", nsigs, nreused));
   buf.free();
 
   // go expunge all references to remaining signatures:
-  for (i = 0; i < nentries; i++) {
+  for (i = 0; i < (int)nentries; i++) {
     entry& e = entries[i];
     for (int j = 0; j < e.nrefs; j++) {
       entry*& e2 = e.refs[j];
@@ -3028,7 +3055,7 @@
 void cpool::initMemberIndexes() {
   // This function does NOT refer to any class schema.
   // It is totally internal to the cpool.
-  int i, j, len;
+  int i, j;
 
   // Get the pre-existing indexes:
   int   nclasses = tag_count[CONSTANT_Class];
@@ -3047,13 +3074,13 @@
   for (j = 0; j < nfields; j++) {
     entry& f = fields[j];
     i = f.memberClass()->inord;
-    assert((uint)i < nclasses);
+    assert(i < nclasses);
     field_counts[i]++;
   }
   for (j = 0; j < nmethods; j++) {
     entry& m = methods[j];
     i = m.memberClass()->inord;
-    assert((uint)i < nclasses);
+    assert(i < nclasses);
     method_counts[i]++;
   }
 
@@ -3068,8 +3095,8 @@
     // reuse field_counts and member_counts as fill pointers:
     field_counts[i] = fbase;
     method_counts[i] = mbase;
-    printcr(3, "class %d fields @%d[%d] methods @%d[%d]",
-            i, fbase, fc, mbase, mc);
+    PRINTCR((3, "class %d fields @%d[%d] methods @%d[%d]",
+            i, fbase, fc, mbase, mc));
     fbase += fc+1;
     mbase += mc+1;
     // (the +1 leaves a space between every subarray)
@@ -3093,18 +3120,18 @@
 #ifndef PRODUCT
   // Test the result immediately on every class and field.
   int fvisited = 0, mvisited = 0;
-  int prevord;
+  int prevord, len;
   for (i = 0; i < nclasses; i++) {
     entry*   cls = &classes[i];
     cpindex* fix = getFieldIndex(cls);
     cpindex* mix = getMethodIndex(cls);
-    printcr(2, "field and method index for %s [%d] [%d]",
-            cls->string(), mix->len, fix->len);
+    PRINTCR((2, "field and method index for %s [%d] [%d]",
+            cls->string(), mix->len, fix->len));
     prevord = -1;
     for (j = 0, len = fix->len; j < len; j++) {
       entry* f = fix->get(j);
       assert(f != null);
-      printcr(3, "- field %s", f->string());
+      PRINTCR((3, "- field %s", f->string()));
       assert(f->memberClass() == cls);
       assert(prevord < (int)f->inord);
       prevord = f->inord;
@@ -3115,7 +3142,7 @@
     for (j = 0, len = mix->len; j < len; j++) {
       entry* m = mix->get(j);
       assert(m != null);
-      printcr(3, "- method %s", m->string());
+      PRINTCR((3, "- method %s", m->string()));
       assert(m->memberClass() == cls);
       assert(prevord < (int)m->inord);
       prevord = m->inord;
@@ -3164,7 +3191,7 @@
   outputEntries.empty();
 #ifndef PRODUCT
   // they must all be clear now
-  for (i = 0; i < nentries; i++)
+  for (i = 0; i < (int)nentries; i++)
     assert(entries[i].outputIndex == NOT_REQUESTED);
 #endif
 }
@@ -3215,7 +3242,7 @@
   static uint checkStart = 0;
   int checkStep = 1;
   if (nentries > 100)  checkStep = nentries / 100;
-  for (i = (checkStart++ % checkStep); i < nentries; i += checkStep) {
+  for (i = (int)(checkStart++ % checkStep); i < (int)nentries; i += checkStep) {
     entry& e = entries[i];
     if (e.outputIndex != NOT_REQUESTED) {
       assert(outputEntries.contains(&e));
@@ -3225,7 +3252,7 @@
   }
 
   // check hand-initialization of TAG_ORDER
-  for (i = 0; i < N_TAGS_IN_ORDER; i++) {
+  for (i = 0; i < (int)N_TAGS_IN_ORDER; i++) {
     byte tag = TAGS_IN_ORDER[i];
     assert(TAG_ORDER[tag] == i+1);
   }
@@ -3247,7 +3274,7 @@
     if (e.isDoubleWord())  nextIndex++;  // do not use the next index
   }
   outputIndexLimit = nextIndex;
-  printcr(3,"renumbering CP to %d entries", outputIndexLimit);
+  PRINTCR((3,"renumbering CP to %d entries", outputIndexLimit));
 }
 
 #ifndef PRODUCT
@@ -3257,9 +3284,9 @@
 
 static bytes& getbuf(int len) {  // for debugging only!
   static int bn = 0;
-  static bytes bufs[8] = { 0 };
+  static bytes bufs[8];
   bytes& buf = bufs[bn++ & 7];
-  while (buf.len < len+10)
+  while ((int)buf.len < len+10)
     buf.realloc(buf.len ? buf.len * 2 : 1000);
   buf.ptr[0] = 0;  // for the sake of strcat
   return buf;
@@ -3285,7 +3312,7 @@
   case CONSTANT_Long:
   case CONSTANT_Double:
     buf = getbuf(24);
-    sprintf((char*)buf.ptr, "0x%016llx", value.l);
+    sprintf((char*)buf.ptr, "0x" LONG_LONG_HEX_FORMAT, value.l);
     break;
   default:
     if (nrefs == 0) {
@@ -3296,7 +3323,7 @@
     } else {
       char* s1 = refs[0]->string();
       char* s2 = refs[1]->string();
-      buf = getbuf(strlen(s1) + 1 + strlen(s2) + 4 + 1);
+      buf = getbuf((int)strlen(s1) + 1 + (int)strlen(s2) + 4 + 1);
       buf.strcat(s1).strcat(" ").strcat(s2);
       if (nrefs > 2)  buf.strcat(" ...");
     }
@@ -3409,7 +3436,9 @@
   segments_read_before_reset   += 1;
   if (verbose >= 2) {
     fprintf(errstrm,
-            "After segment %d, %lld bytes read and %lld bytes written.\n",
+            "After segment %d, "
+            LONG_LONG_FORMAT " bytes read and "
+            LONG_LONG_FORMAT " bytes written.\n",
             segments_read_before_reset-1,
             bytes_read_before_reset, bytes_written_before_reset);
     fprintf(errstrm,
@@ -3475,7 +3504,9 @@
   int i;
   NOT_PRODUCT(debug_u = this);
   BYTES_OF(*this).clear();
-  if (assert(1))  free();  // just to make sure freeing is idempotent
+#ifndef PRODUCT
+  free();  // just to make sure freeing is idempotent
+#endif
   this->u = this;    // self-reference for U_NEW macro
   errstrm = stdout;  // default error-output
   log_file = LOGFILE_STDOUT;
@@ -3621,7 +3652,7 @@
 maybe_inline
 void unpacker::put_label(int curIP, int size) {
   code_fixup_type.addByte(size);
-  code_fixup_offset.add(put_empty(size));
+  code_fixup_offset.add((int)put_empty(size));
   code_fixup_source.add(curIP);
 }
 
@@ -3658,7 +3689,7 @@
   }
 
   for (int curIP = 0; ; curIP++) {
-    int curPC = wpoffset() - codeBase;
+    int curPC = (int)(wpoffset() - codeBase);
     bcimap.add(curPC);
     ensure_put_space(10);  // covers most instrs w/o further bounds check
     int bc = *opptr++ & 0xFF;
@@ -3702,7 +3733,7 @@
             put_label(curIP, 4); //int lVal = bc_label.getInt();
           }
         }
-        assert(to_bci(curIP) == curPC);
+        assert((int)to_bci(curIP) == curPC);
         continue;
       }
     case bc_iinc:
@@ -3805,7 +3836,7 @@
           assert(bc <= bc_jsr_w);
           put_label(curIP, 4);  //putu4(lVal);
         }
-        assert(to_bci(curIP) == curPC);
+        assert((int)to_bci(curIP) == curPC);
         continue;
       }
       bc_which = ref_band_for_op(bc);
@@ -3880,7 +3911,7 @@
   //bcimap.add(curPC);  // PC limit is already also in map, from bc_end_marker
 
   // Armed with a bcimap, we can now fix up all the labels.
-  for (int i = 0; i < code_fixup_type.size(); i++) {
+  for (int i = 0; i < (int)code_fixup_type.size(); i++) {
     int   type   = code_fixup_type.getByte(i);
     byte* bp     = wp_at(code_fixup_offset.get(i));
     int   curIP  = code_fixup_source.get(i);
@@ -3896,7 +3927,7 @@
 
 inline  // called exactly once => inline
 void unpacker::write_code() {
-  int i, j;
+  int j;
 
   int max_stack, max_locals, handler_count, cflags;
   get_code_header(max_stack, max_locals, handler_count, cflags);
@@ -3919,7 +3950,7 @@
   CHECK;
 
   byte* bcbasewp = wp_at(bcbase);
-  putu4_at(bcbasewp, wp - (bcbasewp+4));  // size of code attr
+  putu4_at(bcbasewp, (int)(wp - (bcbasewp+4)));  // size of code attr
 
   putu2(handler_count);
   for (j = 0; j < handler_count; j++) {
@@ -3968,10 +3999,10 @@
     if ((indexBits & 1) != 0)
       bitIndexes[biCount++] = idx;
   }
-  assert(biCount <= lengthof(bitIndexes));
+  assert(biCount <= (int)lengthof(bitIndexes));
 
   // Write a provisional attribute count, perhaps to be corrected later.
-  int naOffset = wpoffset();
+  int naOffset = (int)wpoffset();
   int na0 = biCount + oiCount;
   putu2(na0);
 
@@ -3986,7 +4017,7 @@
     entry* ref;  // scratch
     size_t abase = put_empty(2+4);
     CHECK_0;
-    if (idx < ad.flag_limit && ad.isPredefined(idx)) {
+    if (idx < (int)ad.flag_limit && ad.isPredefined(idx)) {
       // Switch on the attrc and idx simultaneously.
       switch (ADH_BYTE(attrc, idx)) {
 
@@ -4020,16 +4051,16 @@
         if (ref == null) {
           bytes& n = cur_class->ref(0)->value.b;
           // parse n = (<pkg>/)*<outer>?($<id>)*
-          int pkglen = lastIndexOf(SLASH_MIN,  SLASH_MAX,  n, n.len)+1;
+          int pkglen = lastIndexOf(SLASH_MIN,  SLASH_MAX,  n, (int)n.len)+1;
           bytes prefix = n.slice(pkglen, n.len);
           for (;;) {
             // Work backwards, finding all '$', '#', etc.
-            int dollar = lastIndexOf(DOLLAR_MIN, DOLLAR_MAX, prefix, prefix.len);
+            int dollar = lastIndexOf(DOLLAR_MIN, DOLLAR_MAX, prefix, (int)prefix.len);
             if (dollar < 0)  break;
             prefix = prefix.slice(0, dollar);
           }
           const char* suffix = ".java";
-          int len = prefix.len + strlen(suffix);
+          int len = (int)(prefix.len + strlen(suffix));
           bytes name; name.set(T_NEW(byte, len + 1), len);
           name.strcat(prefix).strcat(suffix);
           ref = cp.ensureUtf8(name);
@@ -4081,7 +4112,7 @@
             // (253)     [(1)(2)(2)]
             // (254)     [(1)(2)(2)(2)]
             putu2(code_StackMapTable_offset.getInt());
-            for (int j2 = (tag - 251); j2 > 0; j2--) {
+            for (int k = (tag - 251); k > 0; k--) {
               put_stackmap_type();
             }
           } else {
@@ -4165,7 +4196,7 @@
         abort("bad layout index");
         break;
       }
-      assert(lo->idx == idx);
+      assert((int)lo->idx == idx);
       aname = lo->nameEntry;
       if (aname == null) {
         bytes nameb; nameb.set(lo->name);
@@ -4198,7 +4229,7 @@
 
     // patch the name and length
     putref(aname);
-    putu4(wp1 - (wp+4));  // put the attr size
+    putu4((int)(wp1 - (wp+4)));  // put the attr size
     wp = wp1;
     na++;  // count the attrs actually written
   }
@@ -4279,7 +4310,7 @@
   cur_class_has_local_ics = false;  // may be set true by write_attrs
 
 
-  int naOffset = wpoffset();
+  int naOffset = (int)wpoffset();
   int na = write_attrs(ATTR_CONTEXT_CLASS, (kflags & indexMask));
 
 
@@ -4448,7 +4479,7 @@
     putu1(tag);
     switch (tag) {
     case CONSTANT_Utf8:
-      putu2(e.value.b.len);
+      putu2((int)e.value.b.len);
       put_bytes(e.value.b);
       break;
     case CONSTANT_Integer:
@@ -4479,7 +4510,7 @@
 
 #ifndef PRODUCT
   total_cp_size[0] += cp.outputIndexLimit;
-  total_cp_size[1] += cur_classfile_head.size();
+  total_cp_size[1] += (int)cur_classfile_head.size();
 #endif
   close_output();
 }
@@ -4544,7 +4575,7 @@
     if (cur_file.name[0] == '\0') {
       bytes& prefix = cur_class->ref(0)->value.b;
       const char* suffix = ".class";
-      int len = prefix.len + strlen(suffix);
+      int len = (int)(prefix.len + strlen(suffix));
       bytes name; name.set(T_NEW(byte, len + 1), len);
       cur_file.name = name.strcat(prefix).strcat(suffix).strval();
     }
@@ -4564,7 +4595,7 @@
     }
     if (rpleft < cur_file.size) {
       // Caller must read the rest.
-      size_t fleft = cur_file.size - rpleft;
+      size_t fleft = (size_t)cur_file.size - rpleft;
       bytes_read += fleft;  // Credit it to the overall archive size.
     }
   }
@@ -4580,7 +4611,7 @@
   julong fsize = f->size;
 #ifndef PRODUCT
   if (nowrite NOT_PRODUCT(|| skipfiles-- > 0)) {
-    printcr(2,"would write %d bytes to %s", (int) fsize, f->name);
+    PRINTCR((2,"would write %d bytes to %s", (int) fsize, f->name));
     return;
   }
 #endif
@@ -4623,7 +4654,8 @@
                         part1, part2);
   }
   if (verbose >= 3) {
-    fprintf(errstrm, "Wrote %lld bytes to: %s\n", fsize, f->name);
+    fprintf(errstrm, "Wrote "
+                     LONG_LONG_FORMAT " bytes to: %s\n", fsize, f->name);
   }
 }
 
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/unpack.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/unpack.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2002-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2002-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -314,7 +314,7 @@
     void readBandData(band** body, uint count);  // recursive helper
 
     layout_definition* getLayout(uint idx) {
-      if (idx >= layouts.length())  return null;
+      if (idx >= (uint)layouts.length())  return null;
       return (layout_definition*) layouts.get(idx);
     }
 
@@ -332,12 +332,12 @@
     int predefCount(uint idx);
 
     bool isRedefined(uint idx) {
-     assert(idx < flag_limit);
-      return ((redef >> idx) & 1);
+      if (idx >= flag_limit) return false;
+      return (bool)((redef >> idx) & 1);
     }
     bool isPredefined(uint idx) {
-      assert(idx < flag_limit);
-      return (((predef & ~redef) >> idx) & 1);
+      if (idx >= flag_limit) return false;
+      return (bool)(((predef & ~redef) >> idx) & 1);
     }
     julong flagIndexMask() {
       return (predef | redef);
@@ -345,9 +345,9 @@
     bool isIndex(uint idx) {
       assert(flag_limit != 0);  // must be set up already
       if (idx < flag_limit)
-        return (((predef | redef) >> idx) & 1);
+        return (bool)(((predef | redef) >> idx) & 1);
       else
-        return (idx - flag_limit < overflow_count.length());
+        return (idx - flag_limit < (uint)overflow_count.length());
     }
     int& getCount(uint idx) {
       assert(isIndex(idx));
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/utils.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/utils.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -65,7 +65,7 @@
 
 void mkdirs(int oklen, char* path) {
 
-  if (strlen(path) <= oklen)  return;
+  if (strlen(path) <= (size_t)oklen)  return;
   char dir[PATH_MAX];
 
   strcpy(dir, path);
@@ -79,12 +79,13 @@
 
 #ifndef PRODUCT
 void breakpoint() { }  // hook for debugger
-void assert_failed(const char* p) {
+int assert_failed(const char* p) {
   char message[1<<12];
   sprintf(message, "@assert failed: %s\n", p);
   fprintf(stdout, 1+message);
   breakpoint();
   unpack_abort(message);
+  return 0;
 }
 #endif
 
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/utils.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/utils.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2003 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
 
 void* must_malloc(int size);
 #ifndef USE_MTRACE
-#define mtrace(c, ptr, size) (0)
+#define mtrace(c, ptr, size)
 #else
 void mtrace(char c, void* ptr, size_t size);
 #endif
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/zip.cpp	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/zip.cpp	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -85,7 +85,7 @@
 // Write data to the ZIP output stream.
 void jar::write_data(void* buff, int len) {
   while (len > 0) {
-    int rc = fwrite(buff, 1, len, jarfp);
+    int rc = (int)fwrite(buff, 1, len, jarfp);
     if (rc <= 0) {
       fprintf(u->errstrm, "Error: write on output file failed err=%d\n",errno);
       exit(1); // Called only from the native standalone unpacker
@@ -98,17 +98,17 @@
 
 void jar::add_to_jar_directory(const char* fname, bool store, int modtime,
                                int len, int clen, uLong crc) {
-  uint fname_length = strlen(fname);
+  uint fname_length = (uint)strlen(fname);
   ushort header[23];
   if (modtime == 0)  modtime = default_modtime;
   uLong dostime = get_dostime(modtime);
 
-  header[0] = SWAP_BYTES(0x4B50);
-  header[1] = SWAP_BYTES(0x0201);
-  header[2] = SWAP_BYTES(0xA);
+  header[0] = (ushort)SWAP_BYTES(0x4B50);
+  header[1] = (ushort)SWAP_BYTES(0x0201);
+  header[2] = (ushort)SWAP_BYTES(0xA);
 
   // required version
-  header[3] = SWAP_BYTES(0xA);
+  header[3] = (ushort)SWAP_BYTES(0xA);
 
   // flags 02 = maximum  sub-compression flag
   header[4] = ( store ) ? 0x0 : SWAP_BYTES(0x2);
@@ -117,23 +117,23 @@
   header[5] = ( store ) ? 0x0 : SWAP_BYTES(0x08);
 
   // Last modified date and time.
-  header[6] = GET_INT_LO(dostime);
-  header[7] = GET_INT_HI(dostime);
+  header[6] = (ushort)GET_INT_LO(dostime);
+  header[7] = (ushort)GET_INT_HI(dostime);
 
   // CRC
-  header[8] = GET_INT_LO(crc);
-  header[9] = GET_INT_HI(crc);
+  header[8] = (ushort)GET_INT_LO(crc);
+  header[9] = (ushort)GET_INT_HI(crc);
 
   // Compressed length:
-  header[10] = GET_INT_LO(clen);
-  header[11] = GET_INT_HI(clen);
+  header[10] = (ushort)GET_INT_LO(clen);
+  header[11] = (ushort)GET_INT_HI(clen);
 
   // Uncompressed length.
-  header[12] = GET_INT_LO(len);
-  header[13] = GET_INT_HI(len);
+  header[12] = (ushort)GET_INT_LO(len);
+  header[13] = (ushort)GET_INT_HI(len);
 
   // Filename length
-  header[14] = SWAP_BYTES(fname_length);
+  header[14] = (ushort)SWAP_BYTES(fname_length);
   // So called "extra field" length.
   header[15] = 0;
   // So called "comment" length.
@@ -146,8 +146,8 @@
   header[19] = 0;
   header[20] = 0;
   // Offset within ZIP file.
-  header[21] = GET_INT_LO(output_file_offset);
-  header[22] = GET_INT_HI(output_file_offset);
+  header[21] = (ushort)GET_INT_LO(output_file_offset);
+  header[22] = (ushort)GET_INT_HI(output_file_offset);
 
   // Copy the whole thing into the central directory.
   central_directory.append(header, sizeof(header));
@@ -160,17 +160,17 @@
 
 void jar::write_jar_header(const char* fname, bool store, int modtime,
                            int len, int clen, uint crc) {
-  uint fname_length = strlen(fname);
+  uint fname_length = (uint)strlen(fname);
   ushort header[15];
   if (modtime == 0)  modtime = default_modtime;
   uLong dostime = get_dostime(modtime);
 
   // ZIP LOC magic.
-  header[0] = SWAP_BYTES(0x4B50);
-  header[1] = SWAP_BYTES(0x0403);
+  header[0] = (ushort)SWAP_BYTES(0x4B50);
+  header[1] = (ushort)SWAP_BYTES(0x0403);
 
   // Version
-  header[2] = SWAP_BYTES(0xA);
+  header[2] = (ushort)SWAP_BYTES(0xA);
 
   // flags 02 = maximum  sub-compression flag
   header[3] = ( store ) ? 0x0 : SWAP_BYTES(0x2);
@@ -179,31 +179,31 @@
   header[4] = ( store ) ? 0x0 : SWAP_BYTES(0x08);
 
   // Last modified date and time.
-  header[5] = GET_INT_LO(dostime);
-  header[6] = GET_INT_HI(dostime);
+  header[5] = (ushort)GET_INT_LO(dostime);
+  header[6] = (ushort)GET_INT_HI(dostime);
 
   // CRC
-  header[7] = GET_INT_LO(crc);
-  header[8] = GET_INT_HI(crc);
+  header[7] = (ushort)GET_INT_LO(crc);
+  header[8] = (ushort)GET_INT_HI(crc);
 
   // Compressed length:
-  header[9] = GET_INT_LO(clen);
-  header[10] = GET_INT_HI(clen);
+  header[9] = (ushort)GET_INT_LO(clen);
+  header[10] = (ushort)GET_INT_HI(clen);
 
   // Uncompressed length.
-  header[11] = GET_INT_LO(len);
-  header[12] = GET_INT_HI(len);
+  header[11] = (ushort)GET_INT_LO(len);
+  header[12] = (ushort)GET_INT_HI(len);
 
   // Filename length
-  header[13] = SWAP_BYTES(fname_length);
+  header[13] = (ushort)SWAP_BYTES(fname_length);
   // So called "extra field" length.
   header[14] = 0;
 
   // Write the LOC header to the output file.
-  write_data(header, sizeof(header));
+  write_data(header, (int)sizeof(header));
 
   // Copy the fname to the header.
-  write_data((char*)fname, fname_length);
+  write_data((char*)fname, (int)fname_length);
 }
 
 static const char marker_comment[] = ZIP_ARCHIVE_MARKER_COMMENT;
@@ -214,32 +214,32 @@
   ushort header[11];
 
   // Create the End of Central Directory structure.
-  header[0] = SWAP_BYTES(0x4B50);
-  header[1] = SWAP_BYTES(0x0605);
+  header[0] = (ushort)SWAP_BYTES(0x4B50);
+  header[1] = (ushort)SWAP_BYTES(0x0605);
   // disk numbers
   header[2] = 0;
   header[3] = 0;
   // Number of entries in central directory.
-  header[4] = SWAP_BYTES(central_directory_count);
-  header[5] = SWAP_BYTES(central_directory_count);
+  header[4] = (ushort)SWAP_BYTES(central_directory_count);
+  header[5] = (ushort)SWAP_BYTES(central_directory_count);
   // Size of the central directory}
-  header[6] = GET_INT_LO(central_directory.size());
-  header[7] = GET_INT_HI(central_directory.size());
+  header[6] = (ushort)GET_INT_LO((int)central_directory.size());
+  header[7] = (ushort)GET_INT_HI((int)central_directory.size());
   // Offset of central directory within disk.
-  header[8] = GET_INT_LO(output_file_offset);
-  header[9] = GET_INT_HI(output_file_offset);
+  header[8] = (ushort)GET_INT_LO(output_file_offset);
+  header[9] = (ushort)GET_INT_HI(output_file_offset);
   // zipfile comment length;
-  header [10] = SWAP_BYTES(mc.len);
+  header [10] = (ushort)SWAP_BYTES((int)mc.len);
 
   // Write the central directory.
-  printcr(2, "Central directory at %d\n", output_file_offset);
+  PRINTCR((2, "Central directory at %d\n", output_file_offset));
   write_data(central_directory.b);
 
   // Write the End of Central Directory structure.
-  printcr(2, "end-of-directory at %d\n", output_file_offset);
-  write_data(header, sizeof(header));
+  PRINTCR((2, "end-of-directory at %d\n", output_file_offset));
+  write_data(header, (int)sizeof(header));
 
-  printcr(2, "writing zip comment\n");
+  PRINTCR((2, "writing zip comment\n"));
   // Write the comment.
   write_data(mc);
 }
@@ -249,7 +249,7 @@
 // Open a Jar file and initialize.
 void jar::openJarFile(const char* fname) {
   if (!jarfp) {
-    printcr(1, "jar::openJarFile: opening %s\n",fname);
+    PRINTCR((1, "jar::openJarFile: opening %s\n",fname));
     jarfp = fopen(fname, "wb");
     if (!jarfp) {
       fprintf(u->errstrm, "Error: Could not open jar file: %s\n",fname);
@@ -262,25 +262,25 @@
 void jar::addJarEntry(const char* fname,
                       bool deflate_hint, int modtime,
                       bytes& head, bytes& tail) {
-  int len = head.len + tail.len;
+  int len = (int)(head.len + tail.len);
   int clen = 0;
 
-  uint crc = get_crc32(0L,Z_NULL,0);
+  uint crc = get_crc32(0,Z_NULL,0);
   if (head.len != 0)
-    crc = get_crc32(crc, (uchar *)head.ptr, head.len);
+    crc = get_crc32(crc, (uchar *)head.ptr, (uint)head.len);
   if (tail.len != 0)
-    crc = get_crc32(crc, (uchar *)tail.ptr, tail.len);
+    crc = get_crc32(crc, (uchar *)tail.ptr, (uint)tail.len);
 
   bool deflate = (deflate_hint && len > 0);
 
   if (deflate) {
     if (deflate_bytes(head, tail) == false) {
-      printcr(2, "Reverting to store fn=%s\t%d -> %d\n",
-              fname, len, deflated.size());
+      PRINTCR((2, "Reverting to store fn=%s\t%d -> %d\n",
+              fname, len, deflated.size()));
       deflate = false;
     }
   }
-  clen = (deflate) ? deflated.size() : len;
+  clen = (int)((deflate) ? deflated.size() : len);
   add_to_jar_directory(fname, !deflate, modtime, len, clen, crc);
   write_jar_header(    fname, !deflate, modtime, len, clen, crc);
 
@@ -306,7 +306,7 @@
     if (central) write_central_directory();
     fflush(jarfp);
     fclose(jarfp);
-    printcr(2, "jar::closeJarFile:closed jar-file\n");
+    PRINTCR((2, "jar::closeJarFile:closed jar-file\n"));
   }
   reset();
 }
@@ -338,6 +338,7 @@
     default_modtime = modtime;  // catch a reasonable default
   time_t t = modtime;
   struct tm sbuf;
+  (void)memset((void*)&sbuf,0, sizeof(sbuf));
   struct tm* s = gmtime_r(&t, &sbuf);
   modtime_cache = modtime;
   dostime_cache = dostime(s->tm_year + 1900, s->tm_mon + 1, s->tm_mday,
@@ -355,7 +356,7 @@
    input data
 */
 bool jar::deflate_bytes(bytes& head, bytes& tail) {
-  int len = head.len + tail.len;
+  int len = (int)(head.len + tail.len);
 
   z_stream zs;
   BYTES_OF(zs).clear();
@@ -368,26 +369,26 @@
   if (error != Z_OK) {
     switch (error) {
     case Z_MEM_ERROR:
-      printcr(2, "Error: deflate error : Out of memory \n");
+      PRINTCR((2, "Error: deflate error : Out of memory \n"));
       break;
     case Z_STREAM_ERROR:
-      printcr(2,"Error: deflate error : Invalid compression level \n");
+      PRINTCR((2,"Error: deflate error : Invalid compression level \n"));
       break;
     case Z_VERSION_ERROR:
-      printcr(2,"Error: deflate error : Invalid version\n");
+      PRINTCR((2,"Error: deflate error : Invalid version\n"));
       break;
     default:
-      printcr(2,"Error: Internal deflate error error = %d\n", error);
+      PRINTCR((2,"Error: Internal deflate error error = %d\n", error));
     }
     return false;
   }
 
   deflated.empty();
   zs.next_out  = (uchar*) deflated.grow(len + (len/2));
-  zs.avail_out = deflated.size();
+  zs.avail_out = (int)deflated.size();
 
   zs.next_in = (uchar*)head.ptr;
-  zs.avail_in = head.len;
+  zs.avail_in = (int)head.len;
 
   bytes* first = &head;
   bytes* last  = &tail;
@@ -400,28 +401,28 @@
 
   if (first != null && error == Z_OK) {
     zs.next_in = (uchar*) first->ptr;
-    zs.avail_in = first->len;
+    zs.avail_in = (int)first->len;
     error = deflate(&zs, Z_NO_FLUSH);
   }
   if (error == Z_OK) {
     zs.next_in = (uchar*) last->ptr;
-    zs.avail_in = last->len;
+    zs.avail_in = (int)last->len;
     error = deflate(&zs, Z_FINISH);
   }
   if (error == Z_STREAM_END) {
-    if (len > zs.total_out ) {
-      printcr(2, "deflate compressed data %d -> %d\n", len, zs.total_out);
+    if (len > (int)zs.total_out ) {
+      PRINTCR((2, "deflate compressed data %d -> %d\n", len, zs.total_out));
       deflated.b.len = zs.total_out;
       deflateEnd(&zs);
       return true;
     }
-    printcr(2, "deflate expanded data %d -> %d\n", len, zs.total_out);
+    PRINTCR((2, "deflate expanded data %d -> %d\n", len, zs.total_out));
     deflateEnd(&zs);
     return false;
   }
 
   deflateEnd(&zs);
-  printcr(2, "Error: deflate error deflate did not finish error=%d\n",error);
+  PRINTCR((2, "Error: deflate error deflate did not finish error=%d\n",error));
   return false;
 }
 
@@ -486,7 +487,7 @@
   BYTES_OF(*this).clear();
   u = u_;
   assert(u->gzin == null);  // once only, please
-  read_input_fn = (void*)(intptr_t)u->read_input_fn;
+  read_input_fn = (void*)u->read_input_fn;
   zstream = NEW(z_stream, 1);
   u->gzin = this;
   u->read_input_fn = read_input_via_gzip;
@@ -555,7 +556,7 @@
   if (aborting())  return;
   jlong nr = ((unpacker::read_input_fn_t)read_input_fn)
     (u, buf, buflen, buflen);
-  if (nr != buflen)
+  if ((size_t)nr != buflen)
     u->abort("short stream header");
 }
 
--- a/jdk/src/share/native/com/sun/java/util/jar/pack/zip.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/com/sun/java/util/jar/pack/zip.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2001-2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2001-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -69,7 +69,7 @@
 
   // Private Methods
   void write_data(void* ptr, int len);
-  void write_data(bytes& b) { write_data(b.ptr, b.len); }
+  void write_data(bytes& b) { write_data(b.ptr, (int)b.len); }
   void add_to_jar_directory(const char* fname, bool store, int modtime,
                             int len, int clen, uLong crc);
   void write_jar_header(const char* fname, bool store, int modtime,
--- a/jdk/src/share/native/common/check_code.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/common/check_code.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1994-2007 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1994-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -87,10 +87,7 @@
 
 #include "jni.h"
 #include "jvm.h"
-#include "typedefs.h"
-
-#include "opcodes.h"
-#include "opcodes.length"
+#include "classfile_constants.h"
 #include "opcodes.in_out"
 
 #define MAX_ARRAY_DIMENSIONS 255
@@ -161,8 +158,8 @@
 
 #define NULL_FULLINFO MAKE_FULLINFO(ITEM_Object, 0, 0)
 
-/* opc_invokespecial calls to <init> need to be treated special */
-#define opc_invokeinit 0x100
+/* JVM_OPC_invokespecial calls to <init> need to be treated special */
+#define JVM_OPC_invokeinit 0x100
 
 /* A hash mechanism used by the verifier.
  * Maps class names to unique 16 bit integers.
@@ -301,7 +298,7 @@
 typedef unsigned short flag_type;
 
 struct instruction_data_type {
-    opcode_type opcode;         /* may turn into "canonical" opcode */
+    int opcode;         /* may turn into "canonical" opcode */
     unsigned changed:1;         /* has it changed */
     unsigned protected:1;       /* must accessor be a subclass of "this" */
     union {
@@ -345,7 +342,7 @@
 static void verify_field(context_type *context, jclass cb, int index);
 
 static void verify_opcode_operands (context_type *, unsigned int inumber, int offset);
-static void set_protected(context_type *, unsigned int inumber, int key, opcode_type);
+static void set_protected(context_type *, unsigned int inumber, int key, int);
 static jboolean is_superclass(context_type *, fullinfo_type);
 
 static void initialize_exception_table(context_type *);
@@ -1084,7 +1081,7 @@
     int *code_data = context->code_data;
     int mi = context->method_index;
     unsigned char *code = context->code;
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     int var;
 
     /*
@@ -1096,17 +1093,17 @@
 
     switch (opcode) {
 
-    case opc_jsr:
+    case JVM_OPC_jsr:
         /* instruction of ret statement */
         this_idata->operand2.i = UNKNOWN_RET_INSTRUCTION;
         /* FALLTHROUGH */
-    case opc_ifeq: case opc_ifne: case opc_iflt:
-    case opc_ifge: case opc_ifgt: case opc_ifle:
-    case opc_ifnull: case opc_ifnonnull:
-    case opc_if_icmpeq: case opc_if_icmpne: case opc_if_icmplt:
-    case opc_if_icmpge: case opc_if_icmpgt: case opc_if_icmple:
-    case opc_if_acmpeq: case opc_if_acmpne:
-    case opc_goto: {
+    case JVM_OPC_ifeq: case JVM_OPC_ifne: case JVM_OPC_iflt:
+    case JVM_OPC_ifge: case JVM_OPC_ifgt: case JVM_OPC_ifle:
+    case JVM_OPC_ifnull: case JVM_OPC_ifnonnull:
+    case JVM_OPC_if_icmpeq: case JVM_OPC_if_icmpne: case JVM_OPC_if_icmplt:
+    case JVM_OPC_if_icmpge: case JVM_OPC_if_icmpgt: case JVM_OPC_if_icmple:
+    case JVM_OPC_if_acmpeq: case JVM_OPC_if_acmpne:
+    case JVM_OPC_goto: {
         /* Set the ->operand to be the instruction number of the target. */
         int jump = (((signed char)(code[offset+1])) << 8) + code[offset+2];
         int target = offset + jump;
@@ -1116,11 +1113,11 @@
         break;
     }
 
-    case opc_jsr_w:
+    case JVM_OPC_jsr_w:
         /* instruction of ret statement */
         this_idata->operand2.i = UNKNOWN_RET_INSTRUCTION;
         /* FALLTHROUGH */
-    case opc_goto_w: {
+    case JVM_OPC_goto_w: {
         /* Set the ->operand to be the instruction number of the target. */
         int jump = (((signed char)(code[offset+1])) << 24) +
                      (code[offset+2] << 16) + (code[offset+3] << 8) +
@@ -1132,8 +1129,8 @@
         break;
     }
 
-    case opc_tableswitch:
-    case opc_lookupswitch: {
+    case JVM_OPC_tableswitch:
+    case JVM_OPC_lookupswitch: {
         /* Set the ->operand to be a table of possible instruction targets. */
         int *lpc = (int *) UCALIGN(code + offset + 1);
         int *lptr;
@@ -1147,7 +1144,7 @@
                 CCerror(context, "Non zero padding bytes in switch");
             }
         }
-        if (opcode == opc_tableswitch) {
+        if (opcode == JVM_OPC_tableswitch) {
             keys = ntohl(lpc[2]) -  ntohl(lpc[1]) + 1;
             delta = 1;
         } else {
@@ -1169,7 +1166,7 @@
         for (k = keys, lptr = &lpc[3]; --k >= 0; lptr += delta) {
             int target = offset + ntohl(lptr[0]);
             if (!isLegalTarget(context, target))
-                CCerror(context, "Illegal branch in opc_tableswitch");
+                CCerror(context, "Illegal branch in tableswitch");
             saved_operand[k + 1] = code_data[target];
         }
         saved_operand[0] = keys + 1; /* number of successors */
@@ -1177,7 +1174,7 @@
         break;
     }
 
-    case opc_ldc: {
+    case JVM_OPC_ldc: {
         /* Make sure the constant pool item is the right type. */
         int key = code[offset + 1];
         int types = (1 << JVM_CONSTANT_Integer) | (1 << JVM_CONSTANT_Float) |
@@ -1190,7 +1187,7 @@
         break;
     }
 
-    case opc_ldc_w: {
+    case JVM_OPC_ldc_w: {
         /* Make sure the constant pool item is the right type. */
         int key = (code[offset + 1] << 8) + code[offset + 2];
         int types = (1 << JVM_CONSTANT_Integer) | (1 << JVM_CONSTANT_Float) |
@@ -1203,7 +1200,7 @@
         break;
     }
 
-    case opc_ldc2_w: {
+    case JVM_OPC_ldc2_w: {
         /* Make sure the constant pool item is the right type. */
         int key = (code[offset + 1] << 8) + code[offset + 2];
         int types = (1 << JVM_CONSTANT_Double) | (1 << JVM_CONSTANT_Long);
@@ -1212,28 +1209,28 @@
         break;
     }
 
-    case opc_getfield: case opc_putfield:
-    case opc_getstatic: case opc_putstatic: {
+    case JVM_OPC_getfield: case JVM_OPC_putfield:
+    case JVM_OPC_getstatic: case JVM_OPC_putstatic: {
         /* Make sure the constant pool item is the right type. */
         int key = (code[offset + 1] << 8) + code[offset + 2];
         this_idata->operand.i = key;
         verify_constant_pool_type(context, key, 1 << JVM_CONSTANT_Fieldref);
-        if (opcode == opc_getfield || opcode == opc_putfield)
+        if (opcode == JVM_OPC_getfield || opcode == JVM_OPC_putfield)
             set_protected(context, inumber, key, opcode);
         break;
     }
 
-    case opc_invokevirtual:
-    case opc_invokespecial:
-    case opc_invokestatic:
-    case opc_invokeinterface: {
+    case JVM_OPC_invokevirtual:
+    case JVM_OPC_invokespecial:
+    case JVM_OPC_invokestatic:
+    case JVM_OPC_invokeinterface: {
         /* Make sure the constant pool item is the right type. */
         int key = (code[offset + 1] << 8) + code[offset + 2];
         const char *methodname;
         jclass cb = context->class;
         fullinfo_type clazz_info;
         int is_constructor, is_internal;
-        int kind = (opcode == opc_invokeinterface
+        int kind = (opcode == JVM_OPC_invokeinterface
                             ? 1 << JVM_CONSTANT_InterfaceMethodref
                             : 1 << JVM_CONSTANT_Methodref);
         /* Make sure the constant pool item is the right type. */
@@ -1249,16 +1246,16 @@
         this_idata->operand.i = key;
         this_idata->operand2.fi = clazz_info;
         if (is_constructor) {
-            if (opcode != opc_invokespecial) {
+            if (opcode != JVM_OPC_invokespecial) {
                 CCerror(context,
                         "Must call initializers using invokespecial");
             }
-            this_idata->opcode = opc_invokeinit;
+            this_idata->opcode = JVM_OPC_invokeinit;
         } else {
             if (is_internal) {
                 CCerror(context, "Illegal call to internal method");
             }
-            if (opcode == opc_invokespecial
+            if (opcode == JVM_OPC_invokespecial
                    && clazz_info != context->currentclass_info
                    && clazz_info != context->superclass_info) {
                 int not_found = 1;
@@ -1290,7 +1287,7 @@
                 }
             }
         }
-        if (opcode == opc_invokeinterface) {
+        if (opcode == JVM_OPC_invokeinterface) {
             unsigned int args1;
             unsigned int args2;
             const char *signature =
@@ -1300,25 +1297,25 @@
             args2 = code[offset + 3];
             if (args1 != args2) {
                 CCerror(context,
-                        "Inconsistent args_size for opc_invokeinterface");
+                        "Inconsistent args_size for invokeinterface");
             }
             if (code[offset + 4] != 0) {
                 CCerror(context,
                         "Fourth operand byte of invokeinterface must be zero");
             }
             pop_and_free(context);
-        } else if (opcode == opc_invokevirtual
-                      || opcode == opc_invokespecial)
+        } else if (opcode == JVM_OPC_invokevirtual
+                      || opcode == JVM_OPC_invokespecial)
             set_protected(context, inumber, key, opcode);
         break;
     }
 
 
-    case opc_instanceof:
-    case opc_checkcast:
-    case opc_new:
-    case opc_anewarray:
-    case opc_multianewarray: {
+    case JVM_OPC_instanceof:
+    case JVM_OPC_checkcast:
+    case JVM_OPC_new:
+    case JVM_OPC_anewarray:
+    case JVM_OPC_multianewarray: {
         /* Make sure the constant pool item is a class */
         int key = (code[offset + 1] << 8) + code[offset + 2];
         fullinfo_type target;
@@ -1327,14 +1324,14 @@
         if (GET_ITEM_TYPE(target) == ITEM_Bogus)
             CCerror(context, "Illegal type");
         switch(opcode) {
-        case opc_anewarray:
+        case JVM_OPC_anewarray:
             if ((GET_INDIRECTION(target)) >= MAX_ARRAY_DIMENSIONS)
                 CCerror(context, "Array with too many dimensions");
             this_idata->operand.fi = MAKE_FULLINFO(GET_ITEM_TYPE(target),
                                                    GET_INDIRECTION(target) + 1,
                                                    GET_EXTRA_INFO(target));
             break;
-        case opc_new:
+        case JVM_OPC_new:
             if (WITH_ZERO_EXTRA_INFO(target) !=
                              MAKE_FULLINFO(ITEM_Object, 0, 0))
                 CCerror(context, "Illegal creation of multi-dimensional array");
@@ -1343,10 +1340,10 @@
             this_idata->operand.fi = MAKE_FULLINFO(ITEM_NewObject, 0, inumber);
             this_idata->operand2.fi = target;
             break;
-        case opc_multianewarray:
+        case JVM_OPC_multianewarray:
             this_idata->operand.fi = target;
             this_idata->operand2.i = code[offset + 3];
-            if (    (this_idata->operand2.i > GET_INDIRECTION(target))
+            if (    (this_idata->operand2.i > (int)GET_INDIRECTION(target))
                  || (this_idata->operand2.i == 0))
                 CCerror(context, "Illegal dimension argument");
             break;
@@ -1356,8 +1353,8 @@
         break;
     }
 
-    case opc_newarray: {
-        /* Cache the result of the opc_newarray into the operand slot */
+    case JVM_OPC_newarray: {
+        /* Cache the result of the JVM_OPC_newarray into the operand slot */
         fullinfo_type full_info;
         switch (code[offset + 1]) {
             case JVM_T_INT:
@@ -1376,78 +1373,78 @@
                 full_info = MAKE_FULLINFO(ITEM_Short, 1, 0); break;
             default:
                 full_info = 0;          /* Keep lint happy */
-                CCerror(context, "Bad type passed to opc_newarray");
+                CCerror(context, "Bad type passed to newarray");
         }
         this_idata->operand.fi = full_info;
         break;
     }
 
     /* Fudge iload_x, aload_x, etc to look like their generic cousin. */
-    case opc_iload_0: case opc_iload_1: case opc_iload_2: case opc_iload_3:
-        this_idata->opcode = opc_iload;
-        var = opcode - opc_iload_0;
+    case JVM_OPC_iload_0: case JVM_OPC_iload_1: case JVM_OPC_iload_2: case JVM_OPC_iload_3:
+        this_idata->opcode = JVM_OPC_iload;
+        var = opcode - JVM_OPC_iload_0;
         goto check_local_variable;
 
-    case opc_fload_0: case opc_fload_1: case opc_fload_2: case opc_fload_3:
-        this_idata->opcode = opc_fload;
-        var = opcode - opc_fload_0;
+    case JVM_OPC_fload_0: case JVM_OPC_fload_1: case JVM_OPC_fload_2: case JVM_OPC_fload_3:
+        this_idata->opcode = JVM_OPC_fload;
+        var = opcode - JVM_OPC_fload_0;
         goto check_local_variable;
 
-    case opc_aload_0: case opc_aload_1: case opc_aload_2: case opc_aload_3:
-        this_idata->opcode = opc_aload;
-        var = opcode - opc_aload_0;
+    case JVM_OPC_aload_0: case JVM_OPC_aload_1: case JVM_OPC_aload_2: case JVM_OPC_aload_3:
+        this_idata->opcode = JVM_OPC_aload;
+        var = opcode - JVM_OPC_aload_0;
         goto check_local_variable;
 
-    case opc_lload_0: case opc_lload_1: case opc_lload_2: case opc_lload_3:
-        this_idata->opcode = opc_lload;
-        var = opcode - opc_lload_0;
+    case JVM_OPC_lload_0: case JVM_OPC_lload_1: case JVM_OPC_lload_2: case JVM_OPC_lload_3:
+        this_idata->opcode = JVM_OPC_lload;
+        var = opcode - JVM_OPC_lload_0;
         goto check_local_variable2;
 
-    case opc_dload_0: case opc_dload_1: case opc_dload_2: case opc_dload_3:
-        this_idata->opcode = opc_dload;
-        var = opcode - opc_dload_0;
+    case JVM_OPC_dload_0: case JVM_OPC_dload_1: case JVM_OPC_dload_2: case JVM_OPC_dload_3:
+        this_idata->opcode = JVM_OPC_dload;
+        var = opcode - JVM_OPC_dload_0;
         goto check_local_variable2;
 
-    case opc_istore_0: case opc_istore_1: case opc_istore_2: case opc_istore_3:
-        this_idata->opcode = opc_istore;
-        var = opcode - opc_istore_0;
+    case JVM_OPC_istore_0: case JVM_OPC_istore_1: case JVM_OPC_istore_2: case JVM_OPC_istore_3:
+        this_idata->opcode = JVM_OPC_istore;
+        var = opcode - JVM_OPC_istore_0;
         goto check_local_variable;
 
-    case opc_fstore_0: case opc_fstore_1: case opc_fstore_2: case opc_fstore_3:
-        this_idata->opcode = opc_fstore;
-        var = opcode - opc_fstore_0;
+    case JVM_OPC_fstore_0: case JVM_OPC_fstore_1: case JVM_OPC_fstore_2: case JVM_OPC_fstore_3:
+        this_idata->opcode = JVM_OPC_fstore;
+        var = opcode - JVM_OPC_fstore_0;
         goto check_local_variable;
 
-    case opc_astore_0: case opc_astore_1: case opc_astore_2: case opc_astore_3:
-        this_idata->opcode = opc_astore;
-        var = opcode - opc_astore_0;
+    case JVM_OPC_astore_0: case JVM_OPC_astore_1: case JVM_OPC_astore_2: case JVM_OPC_astore_3:
+        this_idata->opcode = JVM_OPC_astore;
+        var = opcode - JVM_OPC_astore_0;
         goto check_local_variable;
 
-    case opc_lstore_0: case opc_lstore_1: case opc_lstore_2: case opc_lstore_3:
-        this_idata->opcode = opc_lstore;
-        var = opcode - opc_lstore_0;
+    case JVM_OPC_lstore_0: case JVM_OPC_lstore_1: case JVM_OPC_lstore_2: case JVM_OPC_lstore_3:
+        this_idata->opcode = JVM_OPC_lstore;
+        var = opcode - JVM_OPC_lstore_0;
         goto check_local_variable2;
 
-    case opc_dstore_0: case opc_dstore_1: case opc_dstore_2: case opc_dstore_3:
-        this_idata->opcode = opc_dstore;
-        var = opcode - opc_dstore_0;
+    case JVM_OPC_dstore_0: case JVM_OPC_dstore_1: case JVM_OPC_dstore_2: case JVM_OPC_dstore_3:
+        this_idata->opcode = JVM_OPC_dstore;
+        var = opcode - JVM_OPC_dstore_0;
         goto check_local_variable2;
 
-    case opc_wide:
+    case JVM_OPC_wide:
         this_idata->opcode = code[offset + 1];
         var = (code[offset + 2] << 8) + code[offset + 3];
         switch(this_idata->opcode) {
-            case opc_lload:  case opc_dload:
-            case opc_lstore: case opc_dstore:
+            case JVM_OPC_lload:  case JVM_OPC_dload:
+            case JVM_OPC_lstore: case JVM_OPC_dstore:
                 goto check_local_variable2;
             default:
                 goto check_local_variable;
         }
 
-    case opc_iinc:              /* the increment amount doesn't matter */
-    case opc_ret:
-    case opc_aload: case opc_iload: case opc_fload:
-    case opc_astore: case opc_istore: case opc_fstore:
+    case JVM_OPC_iinc:              /* the increment amount doesn't matter */
+    case JVM_OPC_ret:
+    case JVM_OPC_aload: case JVM_OPC_iload: case JVM_OPC_fload:
+    case JVM_OPC_astore: case JVM_OPC_istore: case JVM_OPC_fstore:
         var = code[offset + 1];
     check_local_variable:
         /* Make sure that the variable number isn't illegal. */
@@ -1456,7 +1453,7 @@
             CCerror(context, "Illegal local variable number");
         break;
 
-    case opc_lload: case opc_dload: case opc_lstore: case opc_dstore:
+    case JVM_OPC_lload: case JVM_OPC_dload: case JVM_OPC_lstore: case JVM_OPC_dstore:
         var = code[offset + 1];
     check_local_variable2:
         /* Make sure that the variable number isn't illegal. */
@@ -1466,7 +1463,7 @@
         break;
 
     default:
-        if (opcode >= opc_breakpoint)
+        if (opcode > JVM_OPC_MAX)
             CCerror(context, "Quick instructions shouldn't appear yet.");
         break;
     } /* of switch */
@@ -1474,11 +1471,11 @@
 
 
 static void
-set_protected(context_type *context, unsigned int inumber, int key, opcode_type opcode)
+set_protected(context_type *context, unsigned int inumber, int key, int opcode)
 {
     JNIEnv *env = context->env;
     fullinfo_type clazz_info;
-    if (opcode != opc_invokevirtual && opcode != opc_invokespecial) {
+    if (opcode != JVM_OPC_invokevirtual && opcode != JVM_OPC_invokespecial) {
         clazz_info = cp_index_to_class_fullinfo(context, key,
                                                 JVM_CONSTANT_Fieldref);
     } else {
@@ -1497,7 +1494,7 @@
         calledClass = (*env)->NewLocalRef(env, calledClass);
         do {
             jclass tmp_cb;
-            if (opcode != opc_invokevirtual && opcode != opc_invokespecial) {
+            if (opcode != JVM_OPC_invokevirtual && opcode != JVM_OPC_invokespecial) {
                 access = JVM_GetCPFieldModifiers
                     (env, context->class, key, calledClass);
             } else {
@@ -1607,9 +1604,10 @@
  */
 static int instruction_length(unsigned char *iptr, unsigned char *end)
 {
+    static unsigned char opcode_length[] = JVM_OPCODE_LENGTH_INITIALIZER;
     int instruction = *iptr;
     switch (instruction) {
-        case opc_tableswitch: {
+        case JVM_OPC_tableswitch: {
             int *lpc = (int *)UCALIGN(iptr + 1);
             int index;
             if (lpc + 2 >= (int *)end) {
@@ -1623,7 +1621,7 @@
             }
         }
 
-        case opc_lookupswitch: {
+        case JVM_OPC_lookupswitch: {
             int *lpc = (int *) UCALIGN(iptr + 1);
             int npairs;
             if (lpc + 1 >= (int *)end)
@@ -1638,18 +1636,18 @@
                 return (unsigned char *)(&lpc[2 * (npairs + 1)]) - iptr;
         }
 
-        case opc_wide:
+        case JVM_OPC_wide:
             if (iptr + 1 >= end)
                 return -1; /* do not read pass the end */
             switch(iptr[1]) {
-                case opc_ret:
-                case opc_iload: case opc_istore:
-                case opc_fload: case opc_fstore:
-                case opc_aload: case opc_astore:
-                case opc_lload: case opc_lstore:
-                case opc_dload: case opc_dstore:
+                case JVM_OPC_ret:
+                case JVM_OPC_iload: case JVM_OPC_istore:
+                case JVM_OPC_fload: case JVM_OPC_fstore:
+                case JVM_OPC_aload: case JVM_OPC_astore:
+                case JVM_OPC_lload: case JVM_OPC_lstore:
+                case JVM_OPC_dload: case JVM_OPC_dstore:
                     return 4;
-                case opc_iinc:
+                case JVM_OPC_iinc:
                     return 6;
                 default:
                     return -1;
@@ -1767,7 +1765,7 @@
     jclass cb = context->class;
     int max_stack_size = JVM_GetMethodIxMaxStack(env, cb, mi);
     instruction_data_type *idata = context->instruction_data;
-    int icount = context->instruction_count;
+    unsigned int icount = context->instruction_count;
     jboolean work_to_do = JNI_TRUE;
     unsigned int inumber;
 
@@ -1839,7 +1837,7 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     int operand = this_idata->operand.i;
     int register_count = this_idata->register_info.register_count;
     fullinfo_type *registers = this_idata->register_info.registers;
@@ -1849,17 +1847,17 @@
     switch (opcode) {
         default:
             return;
-        case opc_iload: case opc_iinc:
+        case JVM_OPC_iload: case JVM_OPC_iinc:
             type = ITEM_Integer; break;
-        case opc_fload:
+        case JVM_OPC_fload:
             type = ITEM_Float; break;
-        case opc_aload:
+        case JVM_OPC_aload:
             type = ITEM_Object; break;
-        case opc_ret:
+        case JVM_OPC_ret:
             type = ITEM_ReturnAddress; break;
-        case opc_lload:
+        case JVM_OPC_lload:
             type = ITEM_Long; double_word = JNI_TRUE; break;
-        case opc_dload:
+        case JVM_OPC_dload:
             type = ITEM_Double; double_word = JNI_TRUE; break;
     }
     if (!double_word) {
@@ -1871,7 +1869,7 @@
         }
         reg = registers[operand];
 
-        if (WITH_ZERO_EXTRA_INFO(reg) == MAKE_FULLINFO(type, 0, 0)) {
+        if (WITH_ZERO_EXTRA_INFO(reg) == (unsigned)MAKE_FULLINFO(type, 0, 0)) {
             /* the register is obviously of the given type */
             return;
         } else if (GET_INDIRECTION(reg) > 0 && type == ITEM_Object) {
@@ -1882,7 +1880,7 @@
                               operand);
             /* alternatively
                       (GET_ITEM_TYPE(reg) == ITEM_ReturnAddress)
-                   && (opcode == opc_iload)
+                   && (opcode == JVM_OPC_iload)
                    && (type == ITEM_Object || type == ITEM_Integer)
                but this never occurs
             */
@@ -1902,8 +1900,8 @@
                     "Accessing value from uninitialized register pair %d/%d",
                     operand, operand+1);
         } else {
-            if ((registers[operand] == MAKE_FULLINFO(type, 0, 0)) &&
-                (registers[operand + 1] == MAKE_FULLINFO(type + 1, 0, 0))) {
+            if ((registers[operand] == (unsigned)MAKE_FULLINFO(type, 0, 0)) &&
+                (registers[operand + 1] == (unsigned)MAKE_FULLINFO(type + 1, 0, 0))) {
                 return;
             } else {
                 CCerror(context, "Register pair %d/%d contains wrong type",
@@ -1922,16 +1920,16 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     switch (opcode) {
-        case opc_return:
+        case JVM_OPC_return:
             /* We need a constructor, but we aren't guaranteed it's called */
             if ((this_idata->or_flags & FLAG_NEED_CONSTRUCTOR) &&
                    !(this_idata->and_flags & FLAG_CONSTRUCTED))
                 CCerror(context, "Constructor must call super() or this()");
             /* fall through */
-        case opc_ireturn: case opc_lreturn:
-        case opc_freturn: case opc_dreturn: case opc_areturn:
+        case JVM_OPC_ireturn: case JVM_OPC_lreturn:
+        case JVM_OPC_freturn: case JVM_OPC_dreturn: case JVM_OPC_areturn:
             if (this_idata->or_flags & FLAG_NO_RETURN)
                 /* This method cannot exit normally */
                 CCerror(context, "Cannot return normally");
@@ -1950,7 +1948,7 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     stack_item_type *stack = this_idata->stack_info.stack;
     int stack_size = this_idata->stack_info.stack_size;
     char *stack_operands, *p;
@@ -1958,7 +1956,7 @@
     fullinfo_type stack_extra_info_buffer[256]; /* save info popped off stack */
     fullinfo_type *stack_extra_info = &stack_extra_info_buffer[256];
     fullinfo_type full_info;    /* only used in case of invoke instructions */
-    fullinfo_type put_full_info; /* only used in case opc_putstatic and opc_putfield */
+    fullinfo_type put_full_info; /* only used in case JVM_OPC_putstatic and JVM_OPC_putfield */
 
     switch(opcode) {
         default:
@@ -1966,7 +1964,7 @@
             stack_operands = opcode_in_out[opcode][0];
             break;
 
-        case opc_putstatic: case opc_putfield: {
+        case JVM_OPC_putstatic: case JVM_OPC_putfield: {
             /* The top thing on the stack depends on the signature of
              * the object.                         */
             int operand = this_idata->operand.i;
@@ -1981,7 +1979,7 @@
                 print_formatted_fieldname(context, operand);
             }
 #endif
-            if (opcode == opc_putfield)
+            if (opcode == JVM_OPC_putfield)
                 *ip++ = 'A';    /* object for putfield */
             *ip++ = signature_to_fieldtype(context, &signature, &put_full_info);
             *ip = '\0';
@@ -1990,9 +1988,9 @@
             break;
         }
 
-        case opc_invokevirtual: case opc_invokespecial:
-        case opc_invokeinit:    /* invokespecial call to <init> */
-        case opc_invokestatic: case opc_invokeinterface: {
+        case JVM_OPC_invokevirtual: case JVM_OPC_invokespecial:
+        case JVM_OPC_invokeinit:    /* invokespecial call to <init> */
+        case JVM_OPC_invokestatic: case JVM_OPC_invokeinterface: {
             /* The top stuff on the stack depends on the method signature */
             int operand = this_idata->operand.i;
             const char *signature =
@@ -2007,9 +2005,9 @@
                 print_formatted_methodname(context, operand);
             }
 #endif
-            if (opcode != opc_invokestatic)
+            if (opcode != JVM_OPC_invokestatic)
                 /* First, push the object */
-                *ip++ = (opcode == opc_invokeinit ? '@' : 'A');
+                *ip++ = (opcode == JVM_OPC_invokeinit ? '@' : 'A');
             for (p = signature + 1; *p != JVM_SIGNATURE_ENDFUNC; ) {
                 *ip++ = signature_to_fieldtype(context, &p, &full_info);
                 if (ip >= buffer + sizeof(buffer) - 1)
@@ -2022,7 +2020,7 @@
             break;
         }
 
-        case opc_multianewarray: {
+        case JVM_OPC_multianewarray: {
             /* Count can't be larger than 255. So can't overflow buffer */
             int count = this_idata->operand2.i; /* number of ints on stack */
             memset(buffer, 'I', count);
@@ -2062,19 +2060,19 @@
                      * one of the special cases  */
                     if (  (WITH_ZERO_EXTRA_INFO(top_type) ==
                                 MAKE_FULLINFO(ITEM_ReturnAddress, 0, 0))
-                        && (opcode == opc_astore))
+                        && (opcode == JVM_OPC_astore))
                         break;
                     if (   (GET_ITEM_TYPE(top_type) == ITEM_NewObject
                             || (GET_ITEM_TYPE(top_type) == ITEM_InitObject))
-                        && ((opcode == opc_astore) || (opcode == opc_aload)
-                            || (opcode == opc_ifnull) || (opcode == opc_ifnonnull)))
+                        && ((opcode == JVM_OPC_astore) || (opcode == JVM_OPC_aload)
+                            || (opcode == JVM_OPC_ifnull) || (opcode == JVM_OPC_ifnonnull)))
                         break;
                     /* The 2nd edition VM of the specification allows field
                      * initializations before the superclass initializer,
                      * if the field is defined within the current class.
                      */
                      if (   (GET_ITEM_TYPE(top_type) == ITEM_InitObject)
-                         && (opcode == opc_putfield)) {
+                         && (opcode == JVM_OPC_putfield)) {
                         int operand = this_idata->operand.i;
                         int access_bits = JVM_GetCPFieldModifiers(context->env,
                                                                   context->class,
@@ -2231,7 +2229,7 @@
      */
     switch (opcode) {
         default: break;
-        case opc_aastore: {     /* array index object  */
+        case JVM_OPC_aastore: {     /* array index object  */
             fullinfo_type array_type = stack_extra_info[0];
             fullinfo_type object_type = stack_extra_info[2];
             fullinfo_type target_type = decrement_indirection(array_type);
@@ -2246,12 +2244,12 @@
             break;
         }
 
-        case opc_putfield:
-        case opc_getfield:
-        case opc_putstatic: {
+        case JVM_OPC_putfield:
+        case JVM_OPC_getfield:
+        case JVM_OPC_putstatic: {
             int operand = this_idata->operand.i;
             fullinfo_type stack_object = stack_extra_info[0];
-            if (opcode == opc_putfield || opcode == opc_getfield) {
+            if (opcode == JVM_OPC_putfield || opcode == JVM_OPC_getfield) {
                 if (!isAssignableTo
                         (context,
                          stack_object,
@@ -2266,8 +2264,8 @@
                     CCerror(context, "Bad access to protected data");
                 }
             }
-            if (opcode == opc_putfield || opcode == opc_putstatic) {
-                int item = (opcode == opc_putfield ? 1 : 0);
+            if (opcode == JVM_OPC_putfield || opcode == JVM_OPC_putstatic) {
+                int item = (opcode == JVM_OPC_putfield ? 1 : 0);
                 if (!isAssignableTo(context,
                                     stack_extra_info[item], put_full_info)) {
                     CCerror(context, "Bad type in putfield/putstatic");
@@ -2276,23 +2274,23 @@
             break;
         }
 
-        case opc_athrow:
+        case JVM_OPC_athrow:
             if (!isAssignableTo(context, stack_extra_info[0],
                                 context->throwable_info)) {
                 CCerror(context, "Can only throw Throwable objects");
             }
             break;
 
-        case opc_aaload: {      /* array index */
+        case JVM_OPC_aaload: {      /* array index */
             /* We need to pass the information to the stack updater */
             fullinfo_type array_type = stack_extra_info[0];
             context->swap_table[0] = decrement_indirection(array_type);
             break;
         }
 
-        case opc_invokevirtual: case opc_invokespecial:
-        case opc_invokeinit:
-        case opc_invokeinterface: case opc_invokestatic: {
+        case JVM_OPC_invokevirtual: case JVM_OPC_invokespecial:
+        case JVM_OPC_invokeinit:
+        case JVM_OPC_invokeinterface: case JVM_OPC_invokestatic: {
             int operand = this_idata->operand.i;
             const char *signature =
                 JVM_GetCPMethodSignatureUTF(context->env,
@@ -2301,15 +2299,15 @@
             int item;
             const char *p;
             check_and_push(context, signature, VM_STRING_UTF);
-            if (opcode == opc_invokestatic) {
+            if (opcode == JVM_OPC_invokestatic) {
                 item = 0;
-            } else if (opcode == opc_invokeinit) {
+            } else if (opcode == JVM_OPC_invokeinit) {
                 fullinfo_type init_type = this_idata->operand2.fi;
                 fullinfo_type object_type = stack_extra_info[0];
                 context->swap_table[0] = object_type; /* save value */
                 if (GET_ITEM_TYPE(stack_extra_info[0]) == ITEM_NewObject) {
                     /* We better be calling the appropriate init.  Find the
-                     * inumber of the "opc_new" instruction", and figure
+                     * inumber of the "JVM_OPC_new" instruction", and figure
                      * out what the type really is.
                      */
                     unsigned int new_inumber = GET_EXTRA_INFO(stack_extra_info[0]);
@@ -2341,7 +2339,7 @@
                     CCerror(context,
                             "Incompatible object argument for function call");
                 }
-                if (opcode == opc_invokespecial
+                if (opcode == JVM_OPC_invokespecial
                     && !isAssignableTo(context, object_type,
                                        context->currentclass_info)) {
                     /* Make sure object argument is assignment compatible to current class */
@@ -2381,13 +2379,13 @@
             break;
         }
 
-        case opc_return:
+        case JVM_OPC_return:
             if (context->return_type != MAKE_FULLINFO(ITEM_Void, 0, 0))
                 CCerror(context, "Wrong return type in function");
             break;
 
-        case opc_ireturn: case opc_lreturn: case opc_freturn:
-        case opc_dreturn: case opc_areturn: {
+        case JVM_OPC_ireturn: case JVM_OPC_lreturn: case JVM_OPC_freturn:
+        case JVM_OPC_dreturn: case JVM_OPC_areturn: {
             fullinfo_type target_type = context->return_type;
             fullinfo_type object_type = stack_extra_info[0];
             if (!isAssignableTo(context, object_type, target_type)) {
@@ -2396,7 +2394,7 @@
             break;
         }
 
-        case opc_new: {
+        case JVM_OPC_new: {
             /* Make sure that nothing on the stack already looks like what
              * we want to create.  I can't image how this could possibly happen
              * but we should test for it anyway, since if it could happen, the
@@ -2433,7 +2431,7 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     int operand = this_idata->operand.i;
     int register_count = this_idata->register_info.register_count;
     fullinfo_type *registers = this_idata->register_info.registers;
@@ -2453,11 +2451,11 @@
     /* Remember, we've already verified the type at the top of the stack. */
     switch (opcode) {
         default: break;
-        case opc_istore: case opc_fstore: case opc_astore:
+        case JVM_OPC_istore: case JVM_OPC_fstore: case JVM_OPC_astore:
             access = ACCESS_SINGLE;
             goto continue_store;
 
-        case opc_lstore: case opc_dstore:
+        case JVM_OPC_lstore: case JVM_OPC_dstore:
             access = ACCESS_DOUBLE;
             goto continue_store;
 
@@ -2484,16 +2482,16 @@
             break;
         }
 
-        case opc_iload: case opc_fload: case opc_aload:
-        case opc_iinc: case opc_ret:
+        case JVM_OPC_iload: case JVM_OPC_fload: case JVM_OPC_aload:
+        case JVM_OPC_iinc: case JVM_OPC_ret:
             access = ACCESS_SINGLE;
             break;
 
-        case opc_lload: case opc_dload:
+        case JVM_OPC_lload: case JVM_OPC_dload:
             access = ACCESS_DOUBLE;
             break;
 
-        case opc_jsr: case opc_jsr_w:
+        case JVM_OPC_jsr: case JVM_OPC_jsr_w:
             for (i = 0; i < new_mask_count; i++)
                 if (new_masks[i].entry == operand)
                     CCerror(context, "Recursive call to jsr entry");
@@ -2501,8 +2499,8 @@
             new_mask_count++;
             break;
 
-        case opc_invokeinit:
-        case opc_new: {
+        case JVM_OPC_invokeinit:
+        case JVM_OPC_new: {
             /* For invokeinit, an uninitialized object has been initialized.
              * For new, all previous occurrences of an uninitialized object
              * from the same instruction must be made bogus.
@@ -2588,7 +2586,7 @@
     flag_type or_flags = this_idata->or_flags;
 
     /* Set the "we've done a constructor" flag */
-    if (this_idata->opcode == opc_invokeinit) {
+    if (this_idata->opcode == JVM_OPC_invokeinit) {
         fullinfo_type from = context->swap_table[0];
         if (from == MAKE_FULLINFO(ITEM_InitObject, 0, 0))
             and_flags |= FLAG_CONSTRUCTED;
@@ -2611,7 +2609,7 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     int operand = this_idata->operand.i;
 
     int stack_size = new_stack_info->stack_size;
@@ -2631,7 +2629,7 @@
             stack_results = opcode_in_out[opcode][1];
             break;
 
-        case opc_ldc: case opc_ldc_w: case opc_ldc2_w: {
+        case JVM_OPC_ldc: case JVM_OPC_ldc_w: case JVM_OPC_ldc2_w: {
             /* Look to constant pool to determine correct result. */
             unsigned char *type_table = context->constant_types;
             switch (type_table[operand]) {
@@ -2661,7 +2659,7 @@
             break;
         }
 
-        case opc_getstatic: case opc_getfield: {
+        case JVM_OPC_getstatic: case JVM_OPC_getfield: {
             /* Look to signature to determine correct result. */
             int operand = this_idata->operand.i;
             const char *signature = JVM_GetCPFieldSignatureUTF(context->env,
@@ -2680,9 +2678,9 @@
             break;
         }
 
-        case opc_invokevirtual: case opc_invokespecial:
-        case opc_invokeinit:
-        case opc_invokestatic: case opc_invokeinterface: {
+        case JVM_OPC_invokevirtual: case JVM_OPC_invokespecial:
+        case JVM_OPC_invokeinit:
+        case JVM_OPC_invokestatic: case JVM_OPC_invokeinterface: {
             /* Look to signature to determine correct result. */
             int operand = this_idata->operand.i;
             const char *signature = JVM_GetCPMethodSignatureUTF(context->env,
@@ -2703,28 +2701,28 @@
             break;
         }
 
-        case opc_aconst_null:
+        case JVM_OPC_aconst_null:
             stack_results = opcode_in_out[opcode][1];
             full_info = NULL_FULLINFO; /* special NULL */
             break;
 
-        case opc_new:
-        case opc_checkcast:
-        case opc_newarray:
-        case opc_anewarray:
-        case opc_multianewarray:
+        case JVM_OPC_new:
+        case JVM_OPC_checkcast:
+        case JVM_OPC_newarray:
+        case JVM_OPC_anewarray:
+        case JVM_OPC_multianewarray:
             stack_results = opcode_in_out[opcode][1];
             /* Conveniently, this result type is stored here */
             full_info = this_idata->operand.fi;
             break;
 
-        case opc_aaload:
+        case JVM_OPC_aaload:
             stack_results = opcode_in_out[opcode][1];
             /* pop_stack() saved value for us. */
             full_info = context->swap_table[0];
             break;
 
-        case opc_aload:
+        case JVM_OPC_aload:
             stack_results = opcode_in_out[opcode][1];
             /* The register hasn't been modified, so we can use its value. */
             full_info = this_idata->register_info.registers[operand];
@@ -2772,7 +2770,7 @@
         stack_size++;
     } /* outer for loop */
 
-    if (opcode == opc_invokeinit) {
+    if (opcode == JVM_OPC_invokeinit) {
         /* If there are any instances of "from" on the stack, we need to
          * replace it with "to", since calling <init> initializes all versions
          * of the object, obviously.     */
@@ -2807,7 +2805,7 @@
 {
     instruction_data_type *idata = context->instruction_data;
     instruction_data_type *this_idata = &idata[inumber];
-    opcode_type opcode = this_idata->opcode;
+    int opcode = this_idata->opcode;
     int operand = this_idata->operand.i;
     struct handler_info_type *handler_info = context->handler_info;
     int handler_info_length =
@@ -2827,35 +2825,35 @@
         buffer[0] = inumber + 1;
         break;
 
-    case opc_ifeq: case opc_ifne: case opc_ifgt:
-    case opc_ifge: case opc_iflt: case opc_ifle:
-    case opc_ifnull: case opc_ifnonnull:
-    case opc_if_icmpeq: case opc_if_icmpne: case opc_if_icmpgt:
-    case opc_if_icmpge: case opc_if_icmplt: case opc_if_icmple:
-    case opc_if_acmpeq: case opc_if_acmpne:
+    case JVM_OPC_ifeq: case JVM_OPC_ifne: case JVM_OPC_ifgt:
+    case JVM_OPC_ifge: case JVM_OPC_iflt: case JVM_OPC_ifle:
+    case JVM_OPC_ifnull: case JVM_OPC_ifnonnull:
+    case JVM_OPC_if_icmpeq: case JVM_OPC_if_icmpne: case JVM_OPC_if_icmpgt:
+    case JVM_OPC_if_icmpge: case JVM_OPC_if_icmplt: case JVM_OPC_if_icmple:
+    case JVM_OPC_if_acmpeq: case JVM_OPC_if_acmpne:
         successors_count = 2;
         buffer[0] = inumber + 1;
         buffer[1] = operand;
         break;
 
-    case opc_jsr: case opc_jsr_w:
+    case JVM_OPC_jsr: case JVM_OPC_jsr_w:
         if (this_idata->operand2.i != UNKNOWN_RET_INSTRUCTION)
             idata[this_idata->operand2.i].changed = JNI_TRUE;
         /* FALLTHROUGH */
-    case opc_goto: case opc_goto_w:
+    case JVM_OPC_goto: case JVM_OPC_goto_w:
         successors_count = 1;
         buffer[0] = operand;
         break;
 
 
-    case opc_ireturn: case opc_lreturn: case opc_return:
-    case opc_freturn: case opc_dreturn: case opc_areturn:
-    case opc_athrow:
+    case JVM_OPC_ireturn: case JVM_OPC_lreturn: case JVM_OPC_return:
+    case JVM_OPC_freturn: case JVM_OPC_dreturn: case JVM_OPC_areturn:
+    case JVM_OPC_athrow:
         /* The testing for the returns is handled in pop_stack() */
         successors_count = 0;
         break;
 
-    case opc_ret: {
+    case JVM_OPC_ret: {
         /* This is slightly slow, but good enough for a seldom used instruction.
          * The EXTRA_ITEM_INFO of the ITEM_ReturnAddress indicates the
          * address of the first instruction of the subroutine.  We can return
@@ -2866,16 +2864,16 @@
             int called_instruction = GET_EXTRA_INFO(registers[operand]);
             int i, count, *ptr;;
             for (i = context->instruction_count, count = 0; --i >= 0; ) {
-                if (((idata[i].opcode == opc_jsr) ||
-                     (idata[i].opcode == opc_jsr_w)) &&
+                if (((idata[i].opcode == JVM_OPC_jsr) ||
+                     (idata[i].opcode == JVM_OPC_jsr_w)) &&
                     (idata[i].operand.i == called_instruction))
                     count++;
             }
             this_idata->operand2.ip = ptr = NEW(int, count + 1);
             *ptr++ = count;
             for (i = context->instruction_count, count = 0; --i >= 0; ) {
-                if (((idata[i].opcode == opc_jsr) ||
-                     (idata[i].opcode == opc_jsr_w)) &&
+                if (((idata[i].opcode == JVM_OPC_jsr) ||
+                     (idata[i].opcode == JVM_OPC_jsr_w)) &&
                     (idata[i].operand.i == called_instruction))
                     *ptr++ = i + 1;
             }
@@ -2886,8 +2884,8 @@
 
     }
 
-    case opc_tableswitch:
-    case opc_lookupswitch:
+    case JVM_OPC_tableswitch:
+    case JVM_OPC_lookupswitch:
         successors = this_idata->operand.ip; /* use this instead */
         successors_count = *successors++;
         break;
@@ -2907,9 +2905,9 @@
 
     handler_info = context->handler_info;
     for (i = handler_info_length; --i >= 0; handler_info++) {
-        if (handler_info->start <= inumber && handler_info->end > inumber) {
+        if (handler_info->start <= (int)inumber && handler_info->end > (int)inumber) {
             int handler = handler_info->handler;
-            if (opcode != opc_invokeinit) {
+            if (opcode != JVM_OPC_invokeinit) {
                 merge_into_one_successor(context, inumber, handler,
                                          &this_idata->register_info, /* old */
                                          &handler_info->stack_info,
@@ -2984,9 +2982,9 @@
      * ret are executed. Thus uninitialized objects can't propagate
      * into or out of a subroutine.
      */
-    if (idata[from_inumber].opcode == opc_ret ||
-        idata[from_inumber].opcode == opc_jsr ||
-        idata[from_inumber].opcode == opc_jsr_w) {
+    if (idata[from_inumber].opcode == JVM_OPC_ret ||
+        idata[from_inumber].opcode == JVM_OPC_jsr ||
+        idata[from_inumber].opcode == JVM_OPC_jsr_w) {
         int new_register_count = new_register_info->register_count;
         fullinfo_type *new_registers = new_register_info->registers;
         int i;
@@ -3036,7 +3034,7 @@
      * that needs to get merged into the new instruction is a joining
      * of info from the ret instruction with stuff in the jsr instruction
      */
-    if (idata[from_inumber].opcode == opc_ret && !isException) {
+    if (idata[from_inumber].opcode == JVM_OPC_ret && !isException) {
         int new_register_count = new_register_info->register_count;
         fullinfo_type *new_registers = new_register_info->registers;
         int new_mask_count = new_register_info->mask_count;
@@ -3045,7 +3043,7 @@
         int called_instruction = GET_EXTRA_INFO(new_registers[operand]);
         instruction_data_type *jsr_idata = &idata[to_inumber - 1];
         register_info_type *jsr_reginfo = &jsr_idata->register_info;
-        if (jsr_idata->operand2.i != from_inumber) {
+        if (jsr_idata->operand2.i != (int)from_inumber) {
             if (jsr_idata->operand2.i != UNKNOWN_RET_INSTRUCTION)
                 CCerror(context, "Multiple returns to single jsr");
             jsr_idata->operand2.i = from_inumber;
@@ -3675,7 +3673,7 @@
                 char *buffer = buffer_space;
                 char *finish = strchr(p, JVM_SIGNATURE_ENDCLASS);
                 int length = finish - p;
-                if (length + 1 > sizeof(buffer_space)) {
+                if (length + 1 > (int)sizeof(buffer_space)) {
                     buffer = malloc(length + 1);
                     check_and_push(context, buffer, VM_MALLOC_BLK);
                 }
--- a/jdk/src/share/native/common/check_format.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/share/native/common/check_format.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1997-2006 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -246,7 +246,7 @@
         /* skip over the fieldname.  Slashes are okay */
         p = skip_over_fieldname(name, JNI_TRUE, length);
     }
-    return (p != 0 && p - name == length);
+    return (p != 0 && p - name == (ptrdiff_t)length);
 }
 
 /*
--- a/jdk/src/solaris/back/util_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/back/util_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,6 +26,9 @@
 #ifndef JDWP_UTIL_MD_H
 #define JDWP_UTIL_MD_H
 
+#include <stddef.h>
+#include <stdint.h>  /* To get uintptr_t */
+
 #include <limits.h>
 #include <sys/types.h>
 
--- a/jdk/src/solaris/instrument/FileSystemSupport_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/instrument/FileSystemSupport_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2004-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -23,5 +23,8 @@
  * have any questions.
  */
 
+#include <stddef.h>
+#include <stdint.h>             /* For uintprt_t */
 #include <stdlib.h>
 #include <sys/param.h>          /* For MAXPATHLEN */
+
--- a/jdk/src/solaris/javavm/export/jvm_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/javavm/export/jvm_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1997-1999 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -34,6 +34,8 @@
 #include <dirent.h>             /* For DIR */
 #include <sys/param.h>          /* For MAXPATHLEN */
 #include <unistd.h>             /* For F_OK, R_OK, W_OK */
+#include <stddef.h>             /* For ptrdiff_t */
+#include <stdint.h>             /* For uintptr_t */
 
 #define JNI_ONLOAD_SYMBOLS   {"JNI_OnLoad"}
 #define JNI_ONUNLOAD_SYMBOLS {"JNI_OnUnload"}
--- a/jdk/src/solaris/javavm/include/typedefs_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,174 +0,0 @@
-/*
- * Copyright 1994-2002 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-/*
- * Solaris-dependent types for Green threads
- */
-
-#ifndef _JAVASOFT_SOLARIS_TYPES_MD_H_
-#define _JAVASOFT_SOLARIS_TYPES_MD_H_
-
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#ifdef __linux__
-#include <stdint.h>
-#define HAVE_INTPTR_T
-#define _UINT64_T
-#endif
-
-#define int8_t char
-
-/* Fix for varargs differences on PowerPC */
-#if defined(__powerpc__)
-#define VARGS(x) (x)
-#else
-#define VARGS(x) (&x)
-#endif /* __powerpc__ */
-
-
-#if defined(__alpha__)
-#define PTR_IS_64 1
-#define LONG_IS_64 1
-#else
-#define PTR_IS_32 1
-#endif
-
-/* don't redefine typedef's on Solaris 2.6 or Later */
-
-#if !defined(_ILP32) && !defined(_LP64)
-
-#ifndef HAVE_INTPTR_T
-#ifdef LONG_IS_64
-typedef long intptr_t;
-typedef unsigned long uintptr_t;
-#else
-typedef int intptr_t;
-typedef unsigned int uintptr_t;
-#endif  /* LONG_IS_64 */
-#endif /* don't HAVE_INTPTR_T */
-
-#ifndef _UINT64_T
-#define _UINT64_T
-#ifdef LONG_IS_64
-typedef unsigned long uint64_t;
-#else
-typedef unsigned long long uint64_t;
-#endif
-#define _UINT32_T
-#ifndef uint32_t /* [sbb] scaffolding */
-typedef unsigned int uint32_t;
-#endif /* [sbb] scaffolding */
-#if defined(__linux__)
-typedef unsigned int uint_t;
-#endif
-#endif
-
-#ifndef __BIT_TYPES_DEFINED__
-/* that should get Linux, at least */
-#ifndef _INT64_T
-#define _INT64_T
-#ifdef LONG_IS_64
-typedef long int64_t;
-#else
-typedef long long int64_t;
-#endif
-#define _INT32_T
-#ifndef int32_t /* [sbb] scaffolding */
-typedef int int32_t;
-#endif /* [sbb] scaffolding */
-#if defined(__linux__)
-typedef int int_t;
-#endif
-#endif
-#endif /* __BIT_TYPES_DEFINED__ */
-
-#endif   /* !defined(_ILP32) && !defined(_LP64) */
-
-/* use these macros when the compiler supports the long long type */
-
-#define ll_high(a)    ((uint32_t)(((uint64_t)(a))>>32))
-#define ll_low(a)     ((uint32_t)(a))
-#define int2ll(a)       ((int64_t)(a))
-#define ll2int(a)       ((int)(a))
-#define ll_add(a, b)    ((int64_t)(a) + (int64_t)(b))
-#define ll_and(a, b)    ((int64_t)(a) & (int64_t)(b))
-#define ll_div(a, b)    ((int64_t)(a) / (int64_t)(b))
-#define ll_mul(a, b)    ((int64_t)(a) * (int64_t)(b))
-#define ll_neg(a)       (-(a))
-#define ll_not(a)     (~(uint64_t)(a))
-#define ll_or(a, b)   ((uint64_t)(a) | (b))
-#define ll_shl(a, n)  ((uint64_t)(a) << (n))
-#define ll_shr(a, n)  ((int64_t)(a) >> (n))
-#define ll_sub(a, b)  ((uint64_t)(a) - (b))
-#define ll_ushr(a, n) ((uint64_t)(a) >>(n))
-#define ll_xor(a, b)  ((int64_t)(a) ^ (int64_t)(b))
-#define uint2ll(a)    ((uint64_t)(a))
-#define ll_rem(a,b)     ((int64_t)(a) % (int64_t)(b))
-
-extern int32_t float2l(float f);
-extern int32_t double2l(double d);
-extern int64_t float2ll(float f);
-extern int64_t double2ll(double d);
-
-#define ll2float(a)     ((float) (a))
-#define ll2double(a)    ((double) (a))
-
-/* Useful on machines where jlong and jdouble have different endianness. */
-#define ll2double_bits(a)  ((void) 0)
-
-/* comparison operators */
-#define ll_ltz(ll)      ((ll)<0)
-#define ll_gez(ll)      ((ll)>=0)
-#define ll_eqz(a)       ((a) == 0)
-#define ll_nez(a)       ((a) != 0)
-#define ll_eq(a, b)     ((a) == (b))
-#define ll_ne(a,b)      ((a) != (b))
-#define ll_ge(a,b)      ((a) >= (b))
-#define ll_le(a,b)      ((a) <= (b))
-#define ll_lt(a,b)      ((a) < (b))
-#define ll_gt(a,b)      ((a) > (b))
-
-#define ll_zero_const   ((int64_t) 0)
-#define ll_one_const    ((int64_t) 1)
-
-extern void ll2str(int64_t a, char *s, char *limit);
-
-#define ll2ptr(a) ((void*)(uintptr_t)(a))
-#define ptr2ll(a) ((int64_t)(uintptr_t)(a))
-
-#ifdef ppc
-#define HAVE_ALIGNED_DOUBLES
-#define HAVE_ALIGNED_LONGLONGS
-#endif
-
-/* printf format modifier for printing pointers */
-#ifdef _LP64
-#define FORMAT64_MODIFIER "l"
-#else
-#define FORMAT64_MODIFIER "ll"
-#endif
-
-#endif /* !_JAVASOFT_SOLARIS_TYPES_MD_H_ */
--- a/jdk/src/solaris/native/common/gdefs_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/native/common/gdefs_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2000-2002 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2000-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -24,15 +24,12 @@
  */
 
 /*
- * Solaris dependent type definitions  includes intptr_t, etc
+ * Solaris/Linux dependent type definitions  includes intptr_t, etc
  */
 
+#include <stddef.h>
+#include <stdint.h>  /* For uintptr_t */
+#include <stdlib.h>
 
 #include <sys/types.h>
-/*
- * Linux version of <sys/types.h> does not define intptr_t
- */
-#ifdef __linux__
-#include <stdint.h>
-#include <malloc.h>
-#endif /* __linux__ */
+
--- a/jdk/src/solaris/native/common/jlong_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/native/common/jlong_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1997-2002 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,7 @@
 
 /* Make sure ptrdiff_t is defined */
 #include <stddef.h>
-#include "typedefs.h"
+#include <stdint.h>  /* For uintptr_t */
 
 #define jlong_high(a)   ((jint)((a)>>32))
 #define jlong_low(a)    ((jint)(a))
--- a/jdk/src/solaris/native/java/net/NetworkInterface.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/native/java/net/NetworkInterface.c	Wed Jul 05 16:41:01 2017 +0200
@@ -206,10 +206,10 @@
 
 /*
  * Class:     java_net_NetworkInterface
- * Method:    getByIndex
+ * Method:    getByIndex0
  * Signature: (Ljava/lang/String;)Ljava/net/NetworkInterface;
  */
-JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex
+JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex0
     (JNIEnv *env, jclass cls, jint index) {
 
     netif *ifs, *curr;
--- a/jdk/src/solaris/native/java/net/PlainDatagramSocketImpl.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/solaris/native/java/net/PlainDatagramSocketImpl.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1741,7 +1741,7 @@
          * (for IF).
          */
         if (index > 0) {
-            ni = Java_java_net_NetworkInterface_getByIndex(env, ni_class,
+            ni = Java_java_net_NetworkInterface_getByIndex0(env, ni_class,
                                                                    index);
             if (ni == NULL) {
                 char errmsg[255];
--- a/jdk/src/windows/back/util_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/back/util_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1998-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,6 +26,7 @@
 #ifndef JDWP_UTIL_MD_H
 #define JDWP_UTIL_MD_H
 
+#include <stddef.h>      /* for uintptr_t */
 #include <stdlib.h>      /* for _MAx_PATH */
 
 typedef unsigned __int64 UNSIGNED_JLONG;
--- a/jdk/src/windows/hpi/src/socket_md.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/hpi/src/socket_md.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1997-2005 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -29,7 +29,6 @@
 #include "hpi_impl.h"
 
 #include "mutex_md.h"
-#include "typedefs.h"
 
 struct sockaddr;
 
--- a/jdk/src/windows/hpi/src/threads_md.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/hpi/src/threads_md.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1994-2003 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1994-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -35,7 +35,6 @@
 
 #include "threads_md.h"
 #include "monitor_md.h"
-#include "typedefs.h"
 
 
 /*
--- a/jdk/src/windows/instrument/FileSystemSupport_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/instrument/FileSystemSupport_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 2004-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -23,6 +23,7 @@
  * have any questions.
  */
 
+#include <stddef.h> /* For uintprt_t */
 #include <stdlib.h>
 
 #define MAXPATHLEN  _MAX_PATH
--- a/jdk/src/windows/javavm/export/jvm_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/javavm/export/jvm_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -53,6 +53,7 @@
     WIN32_FIND_DATA find_data;
 } DIR;
 
+#include <stddef.h>  /* For uintptr_t */
 #include <stdlib.h>
 
 #define JVM_MAXPATHLEN _MAX_PATH
@@ -66,6 +67,19 @@
 JVM_GetThreadInterruptEvent();
 
 /*
+ * These routines are only reentrant on Windows
+ */
+
+JNIEXPORT struct protoent * JNICALL
+JVM_GetProtoByName(char* name);
+
+JNIEXPORT struct hostent* JNICALL
+JVM_GetHostByAddr(const char* name, int len, int type);
+
+JNIEXPORT struct hostent* JNICALL
+JVM_GetHostByName(char* name);
+
+/*
  * File I/O
  */
 
--- a/jdk/src/windows/javavm/include/typedefs_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,125 +0,0 @@
-/*
- * Copyright 1994-2002 Sun Microsystems, Inc.  All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.  Sun designates this
- * particular file as subject to the "Classpath" exception as provided
- * by Sun in the LICENSE file that accompanied this code.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- */
-
-/*
- * Win32 dependent type definitions
- */
-
-#ifndef _JAVASOFT_WIN32_TYPEDEF_MD_H_
-#define _JAVASOFT_WIN32_TYPEDEF_MD_H_
-
-#include <windows.h>
-
-#define VARGS(x) (&x)
-
-typedef char             int8_t;
-typedef __int16          int16_t;
-typedef __int32          int32_t;
-typedef __int64          int64_t;
-
-typedef unsigned char    uint8_t;
-typedef unsigned __int16 uint16_t;
-typedef unsigned int     uint_t;
-typedef unsigned __int32 uint32_t;
-typedef unsigned __int64 uint64_t;
-
-/* Make sure that we have the intptr_t and uintptr_t definitions */
-#ifndef _INTPTR_T_DEFINED
-#ifdef _WIN64
-typedef __int64 intptr_t;
-#else
-typedef int intptr_t;
-#endif
-#define _INTPTR_T_DEFINED
-#endif
-
-#ifndef _UINTPTR_T_DEFINED
-#ifdef _WIN64
-typedef unsigned __int64 uintptr_t;
-#else
-typedef unsigned int uintptr_t;
-#endif
-#define _UINTPTR_T_DEFINED
-#endif
-
-typedef intptr_t ssize_t;
-
-/* use these macros when the compiler supports the long long type */
-
-#define ll_high(a)      ((long)((a)>>32))
-#define ll_low(a)       ((long)(a))
-#define int2ll(a)       ((int64_t)(a))
-#define ll2int(a)       ((int)(a))
-#define ll_add(a, b)    ((a) + (b))
-#define ll_and(a, b)    ((a) & (b))
-#define ll_div(a, b)    ((a) / (b))
-#define ll_mul(a, b)    ((a) * (b))
-#define ll_neg(a)       (-(a))
-#define ll_not(a)       (~(a))
-#define ll_or(a, b)     ((a) | (b))
-/* THE FOLLOWING DEFINITION IS NOW A FUNCTION CALL IN ORDER TO WORKAROUND
-   OPTIMIZER BUG IN MSVC++ 2.1 (see system_md.c)
-   #define ll_shl(a, n) ((a) << (n)) */
-#define ll_shr(a, n)    ((a) >> (n))
-#define ll_sub(a, b)    ((a) - (b))
-#define ll_ushr(a, n)   ((uint64_t)(a) >> (n))
-#define ll_xor(a, b)    ((a) ^ (b))
-#define uint2ll(a)      ((uint64_t)(unsigned long)(a))
-#define ll_rem(a,b)     ((a) % (b))
-
-int32_t float2l(float f);
-int32_t double2l(double f);
-int64_t float2ll(float f);
-int64_t double2ll(double f);
-#define ll2float(a)     ((float) (a))
-#define ll2double(a)    ((double) (a))
-
-/* Useful on machines where jlong and jdouble have different endianness. */
-#define ll2double_bits(a) ((void) 0)
-
-/* comparison operators */
-#define ll_ltz(ll)      ((ll) < 0)
-#define ll_gez(ll)      ((ll) >= 0)
-#define ll_eqz(a)       ((a) == 0)
-#define ll_nez(a)       ((a) != 0)
-#define ll_eq(a, b)     ((a) == (b))
-#define ll_ne(a,b)      ((a) != (b))
-#define ll_ge(a,b)      ((a) >= (b))
-#define ll_le(a,b)      ((a) <= (b))
-#define ll_lt(a,b)      ((a) < (b))
-#define ll_gt(a,b)      ((a) > (b))
-
-#define ll_zero_const   ((int64_t) 0)
-#define ll_one_const    ((int64_t) 1)
-
-int64_t ll_shl(int64_t a, int bits);
-
-#define ll2ptr(a) ((void*)(a))
-#define ptr2ll(a) ((jlong)(a))
-
-/* printf format modifier for printing pointers */
-#define FORMAT64_MODIFIER "I64"
-
-#endif /* !_JAVASOFT_WIN32_TYPEDEF_MD_H_ */
--- a/jdk/src/windows/native/java/net/NetworkInterface.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/native/java/net/NetworkInterface.c	Wed Jul 05 16:41:01 2017 +0200
@@ -554,11 +554,11 @@
     ni_childsID = (*env)->GetFieldID(env, ni_class, "childs", "[Ljava/net/NetworkInterface;");
     ni_ctor = (*env)->GetMethodID(env, ni_class, "<init>", "()V");
 
-    ni_iacls = (*env)->FindClass(env, "Ljava/net/InetAddress;");
+    ni_iacls = (*env)->FindClass(env, "java/net/InetAddress");
     ni_iacls = (*env)->NewGlobalRef(env, ni_iacls);
     ni_iaAddr = (*env)->GetFieldID(env, ni_iacls, "address", "I");
 
-    ni_ia4cls = (*env)->FindClass(env, "Ljava/net/Inet4Address;");
+    ni_ia4cls = (*env)->FindClass(env, "java/net/Inet4Address");
     ni_ia4cls = (*env)->NewGlobalRef(env, ni_ia4cls);
     ni_ia4Ctor = (*env)->GetMethodID(env, ni_ia4cls, "<init>", "()V");
 
@@ -762,17 +762,17 @@
 
 /*
  * Class:     NetworkInterface
- * Method:    getByIndex
+ * Method:    getByIndex0
  * Signature: (I)LNetworkInterface;
  */
-JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex
+JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex0
   (JNIEnv *env, jclass cls, jint index)
 {
     netif *ifList, *curr;
     jobject netifObj = NULL;
 
     if (os_supports_ipv6 && ipv6_available()) {
-        return Java_java_net_NetworkInterface_getByIndex_XP (env, cls, index);
+        return Java_java_net_NetworkInterface_getByIndex0_XP (env, cls, index);
     }
 
     /* get the list of interfaces */
--- a/jdk/src/windows/native/java/net/NetworkInterface_winXP.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/native/java/net/NetworkInterface_winXP.c	Wed Jul 05 16:41:01 2017 +0200
@@ -576,10 +576,10 @@
 
 /*
  * Class:     NetworkInterface
- * Method:    getByIndex
+ * Method:    getByIndex0_XP
  * Signature: (I)LNetworkInterface;
  */
-JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex_XP
+JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex0_XP
   (JNIEnv *env, jclass cls, jint index)
 {
     netif *ifList, *curr;
--- a/jdk/src/windows/native/java/net/TwoStacksPlainDatagramSocketImpl.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/native/java/net/TwoStacksPlainDatagramSocketImpl.c	Wed Jul 05 16:41:01 2017 +0200
@@ -2090,7 +2090,7 @@
          * (for IF).
          */
         if (index > 0) {
-            ni = Java_java_net_NetworkInterface_getByIndex(env, ni_class,
+            ni = Java_java_net_NetworkInterface_getByIndex0(env, ni_class,
                                                                    index);
             if (ni == NULL) {
                 char errmsg[255];
--- a/jdk/src/windows/native/java/net/net_util_md.c	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/native/java/net/net_util_md.c	Wed Jul 05 16:41:01 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright 1997-2007 Sun Microsystems, Inc.  All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,6 @@
 
 #include "net_util.h"
 #include "jni.h"
-#include "typedefs.h"
 
 #ifndef IPTOS_TOS_MASK
 #define IPTOS_TOS_MASK 0x1e
--- a/jdk/src/windows/native/java/net/net_util_md.h	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/src/windows/native/java/net/net_util_md.h	Wed Jul 05 16:41:01 2017 +0200
@@ -329,7 +329,7 @@
 JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByName0_XP
     (JNIEnv *env, jclass cls, jstring name);
 
-JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex_XP
+JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByIndex0_XP
   (JNIEnv *env, jclass cls, jint index);
 
 JNIEXPORT jobject JNICALL Java_java_net_NetworkInterface_getByInetAddress0_XP
--- a/jdk/test/com/sun/jdi/ClassesByName2Test.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/com/sun/jdi/ClassesByName2Test.java	Wed Jul 05 16:41:01 2017 +0200
@@ -134,10 +134,11 @@
                 }
             }
         }
-        /*
-         * resume the target listening for events
-         */
-        listenUntilVMDisconnect();
+
+
+        // Doing vm().exit(0) instead of listenUntilVMDisconnect()
+        // speeds up the test up by more than 50% in -server -Xcomp (solsparc32-fastdebug)
+        vm().exit(0);
 
         /*
          * deal with results of test
--- a/jdk/test/com/sun/jdi/ConnectedVMs.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/com/sun/jdi/ConnectedVMs.java	Wed Jul 05 16:41:01 2017 +0200
@@ -28,7 +28,10 @@
  *
  *  @run build TestScaffold VMConnection TargetListener TargetAdapter
  *  @run compile -g InstTarg.java
- *  @run main ConnectedVMs InstTarg
+ *  @run main ConnectedVMs "Kill"
+ *  @run main ConnectedVMs "Resume to exit"
+ *  @run main ConnectedVMs "dispose()"
+ *  @run main ConnectedVMs "exit()"
  *
  * @summary ConnectedVMs checks the method
  * VirtualMachineManager.connectedVirtualMachines()
@@ -40,14 +43,10 @@
 
 public class ConnectedVMs extends TestScaffold {
     static int failCount = 0;;
-    static int pass;
-    static String[] passNames = {"Kill", "Resume to exit",
-                                 "dispose()", "exit()"};
+    static String passName;
 
     public static void main(String args[]) throws Exception {
-        for (pass=0; pass < passNames.length; pass++) {
-            new ConnectedVMs(args).startTests();
-        }
+        new ConnectedVMs(args[0]).startTests();
         if (failCount > 0) {
             throw new RuntimeException(
              "VirtualMachineManager.connectedVirtualMachines() " +
@@ -58,16 +57,17 @@
         }
     }
 
-    ConnectedVMs(String args[]) throws Exception {
-        super(args);
-        System.out.println("create");
+    ConnectedVMs(String name) throws Exception {
+        super(new String[0]);
+        passName = name;
+        System.out.println("create " + passName);
     }
 
     void vms(int expected) {
         List vms = Bootstrap.virtualMachineManager().
             connectedVirtualMachines();
         if (vms.size() != expected) {
-            System.out.println("FAILURE! " + passNames[pass] +
+            System.out.println("FAILURE! " + passName +
                                " - expected: " + expected +
                                ", got: " + vms.size());
             ++failCount;
@@ -75,27 +75,22 @@
     }
 
     protected void runTests() throws Exception {
-        System.out.println("Testing " + passNames[pass]);
+        System.out.println("Testing " + passName);
         vms(0);
         startToMain("InstTarg");
         ThreadReference thread = waitForVMStart();
         StepEvent stepEvent = stepIntoLine(thread);
         vms(1);
 
-        // pick a way to die
-        switch (pass) {
-            case 0:
-                vm().process().destroy();
-                break;
-            case 1:
-                vm().resume();
-                break;
-            case 2:
-                vm().dispose();
-                break;
-            case 3:
-                vm().exit(1);
-                break;
+        // pick a way to die based on the input arg.
+        if (passName.equals("Kill")) {
+            vm().process().destroy();
+        } else if (passName.equals("Resume to exit")) {
+            vm().resume();
+        } else if (passName.equals("dispose()")) {
+            vm().dispose();
+        } else if (passName.equals("exit()")) {
+            vm().exit(1);
         }
 
         resumeToVMDisconnect();
--- a/jdk/test/com/sun/jdi/sde/MangleStepTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/com/sun/jdi/sde/MangleStepTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -10,7 +10,11 @@
  *  @run build TestScaffold VMConnection TargetListener TargetAdapter InstallSDE
  *  @run compile MangleStepTest.java
  *  @run compile -g  onion/pickle/Mangle.java
- *  @run main MangleStepTest unset Java XYZ Rats bogus
+ *  @run main MangleStepTest unset
+ *  @run main MangleStepTest Java
+ *  @run main MangleStepTest XYZ
+ *  @run main MangleStepTest Rats
+ *  @run main MangleStepTest bogus
  */
 import com.sun.jdi.*;
 import com.sun.jdi.event.*;
@@ -32,9 +36,7 @@
 
     public static void main(String[] args)      throws Exception {
         testSetUp();
-        for (int i = 0; i < args.length; ++i) {
-            new MangleStepTest(args[i]).startTests();
-        }
+        new MangleStepTest(args[0]).startTests();
         if (aTestFailed) {
             throw new Exception("MangleStepTest: failed");
         }
--- a/jdk/test/java/lang/management/ThreadMXBean/Locks.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/java/lang/management/ThreadMXBean/Locks.java	Wed Jul 05 16:41:01 2017 +0200
@@ -197,8 +197,12 @@
             synchronized (ready) {
                 // wait until WaitingThread about to wait for objC
                 thrsync.waitForSignal();
-                // give chance to enter wait.
-                goSleep(100);
+
+                int retryCount = 0;
+                while (waiter.getState() != Thread.State.WAITING
+                       && retryCount++ < 500) {
+                   goSleep(100);
+                }
                 checkBlockedObject(waiter, objC, null, Thread.State.WAITING);
 
                 synchronized (objC) {
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/java/net/NetworkInterface/IndexTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/* @test
+ * @bug 6717876
+ * @summary Make java.net.NetworkInterface.getIndex() public
+ */
+
+import java.net.*;
+import java.util.Enumeration;
+
+public class IndexTest {
+    public static void main(String[] args) throws Exception {
+        Enumeration<NetworkInterface> netifs = NetworkInterface.getNetworkInterfaces();
+        NetworkInterface nif = null;
+        while (netifs.hasMoreElements()) {
+            nif = netifs.nextElement();
+            int index = nif.getIndex();
+            if (index >= 0) {
+                NetworkInterface nif2 = NetworkInterface.getByIndex(index);
+                if (! nif.equals(nif2)) {
+                    throw new RuntimeException("both interfaces should be equal");
+                }
+            }
+        }
+        try {
+            nif = NetworkInterface.getByIndex(-1);
+            throw new RuntimeException("Should have thrown IllegalArgumentException");
+        } catch (IllegalArgumentException e) {
+            // OK
+        }
+        // In all likelyhood, this interface should not exist.
+        nif = NetworkInterface.getByIndex(Integer.MAX_VALUE - 1);
+        if (nif != null) {
+            throw new RuntimeException("getByIndex() should have returned null");
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/java/util/EnumSet/BogusEnumSet.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,93 @@
+/*
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/*
+ * @test
+ * @bug     6739302
+ * @summary Check that deserialization preserves EnumSet integrity
+ * @author  Josh Bloch
+ */
+
+import java.util.*;
+import java.io.*;
+
+public class BogusEnumSet {
+    public static void main(String[] args) throws Throwable {
+        byte[] serializedForm  = {
+            (byte)0xac, (byte)0xed, 0x0, 0x5, 0x73, 0x72, 0x0, 0x18,
+            0x6a,  0x61,  0x76,  0x61, 0x2e,  0x75,  0x74,  0x69,
+            0x6c,  0x2e, 0x52, 0x65, 0x67, 0x75, 0x6c, 0x61, 0x72, 0x45,
+            0x6e, 0x75, 0x6d, 0x53, 0x65, 0x74, 0x2f, 0x58, 0x6f, (byte)0xc7,
+            0x7e, (byte)0xb0, (byte)0xd0, 0x7e, 0x2, 0x0, 0x1, 0x4a, 0x0, 0x8,
+            0x65, 0x6c, 0x65, 0x6d, 0x65, 0x6e, 0x74, 0x73, 0x78, 0x72, 0x0,
+            0x11, 0x6a,  0x61,  0x76,  0x61, 0x2e,  0x75,  0x74,  0x69,
+            0x6c,  0x2e, 0x45, 0x6e, 0x75, 0x6d, 0x53, 0x65, 0x74, 0xe,
+            0x3, 0x21, 0x6a, (byte)0xcd, (byte)0x8c, 0x29, (byte)0xdd, 0x2,
+            0x0, 0x2, 0x4c, 0x0, 0xb, 0x65, 0x6c, 0x65, 0x6d, 0x65, 0x6e, 0x74,
+            0x54, 0x79, 0x70, 0x65, 0x74, 0x0, 0x11, 0x4c, 0x6a, 0x61, 0x76,
+            0x61, 0x2f, 0x6c, 0x61, 0x6e, 0x67, 0x2f, 0x43, 0x6c, 0x61, 0x73,
+            0x73, 0x3b, 0x5b, 0x0, 0x8, 0x75, 0x6e, 0x69, 0x76, 0x65, 0x72,
+            0x73, 0x65, 0x74, 0x0, 0x11, 0x5b, 0x4c, 0x6a, 0x61, 0x76, 0x61,
+            0x2f, 0x6c, 0x61, 0x6e, 0x67, 0x2f, 0x45, 0x6e, 0x75, 0x6d, 0x3b,
+            0x78, 0x70, 0x76, 0x72, 0x0, 0x16, 0x6a, 0x61, 0x76, 0x61, 0x2e,
+            0x6c, 0x61, 0x6e, 0x67, 0x2e, 0x54, 0x68, 0x72, 0x65, 0x61,
+            0x64, 0x24, 0x53, 0x74, 0x61, 0x74, 0x65, 0x0, 0x0, 0x0, 0x0, 0x0,
+            0x0, 0x0, 0x0, 0x12, 0x0, 0x0, 0x78, 0x72, 0x0, 0xe, 0x6a, 0x61,
+            0x76, 0x61, 0x2e, 0x6c, 0x61, 0x6e, 0x67, 0x2e, 0x45, 0x6e, 0x75,
+            0x6d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x12, 0x0, 0x0, 0x78,
+            0x70, 0x75, 0x72, 0x0, 0x19, 0x5b, 0x4c, 0x6a, 0x61, 0x76, 0x61,
+            0x2e, 0x6c, 0x61, 0x6e, 0x67, 0x2e, 0x54, 0x68, 0x72, 0x65, 0x61,
+            0x64, 0x24, 0x53, 0x74, 0x61, 0x74, 0x65, 0x3b, 0x68, (byte)0xa3,
+            (byte)0xb5, (byte)0xd5, 0x11, 0x7d, 0x1b, (byte)0xb3, 0x2, 0x0,
+            0x0, 0x78, 0x70, 0x0, 0x0, 0x0, 0x6, 0x7e, 0x71, 0x0, 0x7e, 0x0,
+            0x5, 0x74, 0x0, 0x3, 0x4e, 0x45, 0x57, 0x7e, 0x71, 0x0, 0x7e, 0x0,
+            0x5, 0x74, 0x0, 0x8, 0x52, 0x55, 0x4e, 0x4e, 0x41, 0x42, 0x4c, 0x45,
+            0x7e, 0x71, 0x0, 0x7e, 0x0, 0x5, 0x74, 0x0, 0x7, 0x42, 0x4c, 0x4f,
+            0x43, 0x4b, 0x45, 0x44, 0x7e, 0x71, 0x0, 0x7e, 0x0, 0x5, 0x74, 0x0,
+            0x7, 0x57, 0x41, 0x49, 0x54, 0x49, 0x4e, 0x47, 0x7e, 0x71, 0x0,
+            0x7e, 0x0, 0x5, 0x74, 0x0, 0xd, 0x54, 0x49, 0x4d, 0x45, 0x44,
+            0x5f, 0x57, 0x41, 0x49, 0x54, 0x49, 0x4e, 0x47, 0x7e, 0x71, 0x0,
+            0x7e, 0x0, 0x5, 0x74, 0x0, 0xa, 0x54, 0x45, 0x52, 0x4d, 0x49,
+            0x4e, 0x41, 0x54, 0x45, 0x44, (byte)0xff, (byte)0xff, (byte)0xff,
+            (byte)0xff, (byte)0xff, (byte)0xff, (byte)0xff, (byte)0xff
+        };
+
+        try {
+          // Should fail, but instead creates corrupt EnumSet
+          @SuppressWarnings("unchecked")
+          EnumSet<Thread.State> es = (EnumSet<Thread.State>)
+              deserialize(serializedForm);
+
+          // Demonstrates corruption
+          System.out.println("Enum size: " + Thread.State.values().length); // 6
+          System.out.println("Set size: " + es.size()); // 64
+          System.out.println("Set: " + es); // Throws IndexOutOfBoundsException
+          throw new AssertionError("Expected exception InvalidObjectException not thrown");
+        } catch (java.io.InvalidObjectException _) { /* OK */ }
+    }
+
+    private static Object deserialize(byte[] sf) throws Throwable {
+      return new ObjectInputStream(
+          new ByteArrayInputStream(sf))
+          .readObject();
+    }
+}
--- a/jdk/test/javax/script/E4XErrorTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/E4XErrorTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6346734
+ * @bug 6346734 6705893
  * @summary We do *not* support E4X (ECMAScript for XML) in our
  * implementation. We want to throw error on XML literals
  * as early as possible rather than at "runtime" - i.e., when
@@ -37,9 +37,10 @@
 
         public static void main(String[] args) throws Exception {
             ScriptEngineManager manager = new ScriptEngineManager();
-            ScriptEngine jsengine = manager.getEngineByName("js");
+            ScriptEngine jsengine = Helper.getJsEngine(manager);
             if (jsengine == null) {
-                throw new RuntimeException("no js engine found");
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
             }
 
             // The test below depends on the error message content
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/javax/script/Helper.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+import javax.script.*;
+
+/**
+ * Helper class to consolidate testing requirements for a js engine.
+ * A js engine is required as part of Sun's product JDK.
+ */
+public class Helper {
+    private Helper() {}; // Don't instantiate
+
+    public static ScriptEngine getJsEngine(ScriptEngineManager m) {
+        ScriptEngine e  = m.getEngineByName("js");
+        if (e == null &&
+            System.getProperty("java.runtime.name").startsWith("Java(TM)")) {
+            // A js engine is requied for Sun's product JDK
+            throw new RuntimeException("no js engine found");
+        }
+        return e;
+    }
+}
--- a/jdk/test/javax/script/JavaScriptScopeTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/JavaScriptScopeTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6346733
+ * @bug 6346733 6705893
  * @summary Verify that independent Bindings instances don't
  * get affected by default scope assignments. Also, verify
  * that script globals can be created and accessed from Java
@@ -36,9 +36,10 @@
 
         public static void main(String[] args) throws Exception {
             ScriptEngineManager manager = new ScriptEngineManager();
-            ScriptEngine jsengine = manager.getEngineByName("js");
+            ScriptEngine jsengine = Helper.getJsEngine(manager);
             if (jsengine == null) {
-                throw new RuntimeException("no js engine found");
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
             }
             jsengine.eval("var v = 'hello';");
             // Create a new scope
--- a/jdk/test/javax/script/NullUndefinedVarTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/NullUndefinedVarTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6346732
+ * @bug 6346732 6705893
  * @summary should be able to assign null and undefined
  * value to JavaScript global variables.
  */
@@ -34,9 +34,10 @@
 
         public static void main(String[] args) throws Exception {
             ScriptEngineManager manager = new ScriptEngineManager();
-            ScriptEngine jsengine = manager.getEngineByName("js");
+            ScriptEngine jsengine = Helper.getJsEngine(manager);
             if (jsengine == null) {
-                throw new RuntimeException("no js engine found");
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
             }
             jsengine.eval("var n = null; " +
                           "if (n !== null) throw 'expecting null';" +
--- a/jdk/test/javax/script/PluggableContextTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/PluggableContextTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6398614
+ * @bug 6398614 6705893
  * @summary Create a user defined ScriptContext and check
  * that script can access variables from non-standard scopes
  */
@@ -35,7 +35,11 @@
         ScriptEngineManager m = new ScriptEngineManager();
         ScriptContext ctx = new MyContext();
         ctx.setAttribute("x", "hello", MyContext.APP_SCOPE);
-        ScriptEngine e = m.getEngineByName("js");
+        ScriptEngine e = Helper.getJsEngine(m);
+        if (e == null) {
+            System.out.println("Warning: No js engine found; test vacuously passes.");
+            return;
+        }
         // the following reference to 'x' throws exception
         // if APP_SCOPE is not searched.
         e.eval("x", ctx);
--- a/jdk/test/javax/script/ProviderTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/ProviderTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -35,9 +35,10 @@
         if (se == null) {
             throw new RuntimeException("can't locate dummy engine");
         }
-        se = manager.getEngineByName("js");
+        se = Helper.getJsEngine(manager);
         if (se == null) {
-            throw new RuntimeException("can't locate JavaScript engine");
+            System.out.println("Warning: No js engine found; test vacuously passes.");
+            return;
         }
     }
 }
--- a/jdk/test/javax/script/RhinoExceptionTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/RhinoExceptionTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,8 +23,8 @@
 
 /*
  * @test
- * @bug 6474943
- * @summary Test that Rhion exception messages are
+ * @bug 6474943 6705893
+ * @summary Test that Rhino exception messages are
  * available from ScriptException.
  */
 
@@ -36,7 +36,11 @@
 
     public static void main(String[] args) throws Exception {
         ScriptEngineManager m = new ScriptEngineManager();
-        ScriptEngine engine = m.getEngineByName("js");
+        ScriptEngine engine = Helper.getJsEngine(m);
+        if (engine == null) {
+            System.out.println("Warning: No js engine found; test vacuously passes.");
+            return;
+        }
         engine.put("msg", ERROR_MSG);
         try {
             engine.eval("throw new Error(msg);");
--- a/jdk/test/javax/script/Test1.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test1.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Create JavaScript engine and execute a simple script.
  * Tests script engine discovery mechanism.
  */
@@ -35,9 +35,10 @@
         public static void main(String[] args) throws Exception {
             System.out.println("\nTest1\n");
             ScriptEngineManager manager = new ScriptEngineManager();
-            ScriptEngine jsengine = manager.getEngineByName("js");
+            ScriptEngine jsengine = Helper.getJsEngine(manager);
             if (jsengine == null) {
-                throw new RuntimeException("no js engine found");
+                     System.out.println("Warning: No js engine found; test vacuously passes.");
+                     return;
             }
             jsengine.eval(new FileReader(
                      new File(System.getProperty("test.src", "."), "Test1.js")));
--- a/jdk/test/javax/script/Test2.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test2.java	Wed Jul 05 16:41:01 2017 +0200
@@ -50,7 +50,11 @@
         public static void main(String[] args) throws Exception {
             System.out.println("\nTest2\n");
             ScriptEngineManager m = new ScriptEngineManager();
-            ScriptEngine eng = m.getEngineByName("js");
+            ScriptEngine eng = Helper.getJsEngine(m);
+            if (eng == null) {
+                     System.out.println("Warning: No js engine found; test vacuously passes.");
+                     return;
+            }
             eng.put("Testobj", new Testobj("Hello World"));
             eng.eval(new FileReader(
                     new File(System.getProperty("test.src", "."), "Test2.js")));
--- a/jdk/test/javax/script/Test3.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test3.java	Wed Jul 05 16:41:01 2017 +0200
@@ -4,6 +4,7 @@
  *
  * This code is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 only, as
+
  * published by the Free Software Foundation.
  *
  * This code is distributed in the hope that it will be useful, but WITHOUT
@@ -23,7 +24,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Test engine and global scopes
  */
 
@@ -37,7 +38,11 @@
             final Reader reader = new FileReader(
                 new File(System.getProperty("test.src", "."), "Test3.js"));
             ScriptEngineManager m = new ScriptEngineManager();
-            final ScriptEngine engine = m.getEngineByName("js");
+            final ScriptEngine engine = Helper.getJsEngine(m);
+            if (engine == null) {
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
+            }
             Bindings en = new SimpleBindings();
             engine.setBindings(en, ScriptContext.ENGINE_SCOPE);
             en.put("key", "engine value");
--- a/jdk/test/javax/script/Test4.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test4.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Test script functions implementing Java interface
  */
 
@@ -34,7 +34,11 @@
         public static void main(String[] args) throws Exception {
             System.out.println("\nTest4\n");
             ScriptEngineManager m = new ScriptEngineManager();
-            ScriptEngine e  = m.getEngineByName("js");
+            ScriptEngine e  = Helper.getJsEngine(m);
+            if (e == null) {
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
+            }
             e.eval(new FileReader(
                 new File(System.getProperty("test.src", "."), "Test4.js")));
             Invocable inv = (Invocable)e;
--- a/jdk/test/javax/script/Test5.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test5.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Tests engine, global scopes and scope hiding.
  */
 
@@ -34,7 +34,11 @@
         public static void main(String[] args) throws Exception {
                 System.out.println("\nTest5\n");
                 ScriptEngineManager m = new ScriptEngineManager();
-                ScriptEngine engine = m.getEngineByName("js");
+                ScriptEngine engine = Helper.getJsEngine(m);
+                if (engine == null) {
+                    System.out.println("Warning: No js engine found; test vacuously passes.");
+                    return;
+                }
                 Bindings g = new SimpleBindings();
                 Bindings e = new SimpleBindings();
                 g.put("key", "value in global");
--- a/jdk/test/javax/script/Test6.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test6.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Test basic script compilation. Value eval'ed from
  * compiled and interpreted scripts should be same.
  */
@@ -35,7 +35,11 @@
         public static void main(String[] args) throws Exception {
             System.out.println("\nTest6\n");
             ScriptEngineManager m = new ScriptEngineManager();
-            ScriptEngine engine = m.getEngineByName("js");
+            ScriptEngine engine = Helper.getJsEngine(m);
+            if (engine == null) {
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
+            }
             Reader reader = new FileReader(
                 new File(System.getProperty("test.src", "."), "Test6.js"));
             engine.eval(reader);
--- a/jdk/test/javax/script/Test7.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test7.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Tests importPackage and java access in script
  */
 
@@ -37,7 +37,11 @@
                 new File(System.getProperty("test.src", "."), "Test7.js");
             Reader r = new FileReader(file);
             ScriptEngineManager m = new ScriptEngineManager();
-            ScriptEngine eng = m.getEngineByName("js");
+            ScriptEngine eng = Helper.getJsEngine(m);
+            if (eng == null) {
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
+            }
             eng.put("filename", file.getAbsolutePath());
             eng.eval(r);
             String str = (String)eng.get("firstLine");
--- a/jdk/test/javax/script/Test8.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/Test8.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6249843
+ * @bug 6249843 6705893
  * @summary Test invoking script function or method from Java
  */
 
@@ -34,7 +34,11 @@
         public static void main(String[] args) throws Exception {
             System.out.println("\nTest8\n");
             ScriptEngineManager m = new ScriptEngineManager();
-            ScriptEngine e  = m.getEngineByName("js");
+            ScriptEngine e  = Helper.getJsEngine(m);
+            if (e == null) {
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
+            }
             e.eval(new FileReader(
                 new File(System.getProperty("test.src", "."), "Test8.js")));
             Invocable inv = (Invocable)e;
--- a/jdk/test/javax/script/VersionTest.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/javax/script/VersionTest.java	Wed Jul 05 16:41:01 2017 +0200
@@ -23,7 +23,7 @@
 
 /*
  * @test
- * @bug 6346729
+ * @bug 6346729 6705893
  * @summary Create JavaScript engine and check language and engine version
  */
 
@@ -37,9 +37,10 @@
 
         public static void main(String[] args) throws Exception {
             ScriptEngineManager manager = new ScriptEngineManager();
-            ScriptEngine jsengine = manager.getEngineByName("js");
+            ScriptEngine jsengine = Helper.getJsEngine(manager);
             if (jsengine == null) {
-                throw new RuntimeException("no js engine found");
+                System.out.println("Warning: No js engine found; test vacuously passes.");
+                return;
             }
             String langVersion = jsengine.getFactory().getLanguageVersion();
             if (! langVersion.equals(JS_LANG_VERSION)) {
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/sun/nio/cs/TestUTF8.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,393 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/*
+ * @test
+ * @bug 4486841
+ * @summary Test UTF-8 charset
+ */
+
+import java.nio.charset.*;
+import java.nio.*;
+import java.util.*;
+
+public class TestUTF8 {
+    static char[] decode(byte[] bb, String csn, boolean testDirect)
+        throws Exception {
+        CharsetDecoder dec = Charset.forName(csn).newDecoder();
+        ByteBuffer bbf;
+        CharBuffer cbf;
+        if (testDirect) {
+            bbf = ByteBuffer.allocateDirect(bb.length);
+            cbf = ByteBuffer.allocateDirect(bb.length*2).asCharBuffer();
+            bbf.put(bb).flip();
+        } else {
+            bbf = ByteBuffer.wrap(bb);
+            cbf = CharBuffer.allocate(bb.length);
+        }
+        CoderResult cr = dec.decode(bbf, cbf, true);
+        if (cr != CoderResult.UNDERFLOW)
+            throw new RuntimeException("Decoding err: " + csn);
+        char[] cc = new char[cbf.position()];
+        cbf.flip(); cbf.get(cc);
+        return cc;
+
+    }
+
+    static CoderResult decodeCR(byte[] bb, String csn, boolean testDirect)
+        throws Exception {
+        CharsetDecoder dec = Charset.forName(csn).newDecoder();
+        ByteBuffer bbf;
+        CharBuffer cbf;
+        if (testDirect) {
+            bbf = ByteBuffer.allocateDirect(bb.length);
+            cbf = ByteBuffer.allocateDirect(bb.length*2).asCharBuffer();
+            bbf.put(bb).flip();
+        } else {
+            bbf = ByteBuffer.wrap(bb);
+            cbf = CharBuffer.allocate(bb.length);
+        }
+        return dec.decode(bbf, cbf, true);
+    }
+
+    static byte[] encode(char[] cc, String csn, boolean testDirect)
+        throws Exception {
+        ByteBuffer bbf;
+        CharBuffer cbf;
+        CharsetEncoder enc = Charset.forName(csn).newEncoder();
+        if (testDirect) {
+            bbf = ByteBuffer.allocateDirect(cc.length * 4);
+            cbf = ByteBuffer.allocateDirect(cc.length * 2).asCharBuffer();
+            cbf.put(cc).flip();
+        } else {
+            bbf = ByteBuffer.allocate(cc.length * 4);
+            cbf = CharBuffer.wrap(cc);
+        }
+
+        CoderResult cr = enc.encode(cbf, bbf, true);
+        if (cr != CoderResult.UNDERFLOW)
+            throw new RuntimeException("Encoding err: " + csn);
+        byte[] bb = new byte[bbf.position()];
+        bbf.flip(); bbf.get(bb);
+        return bb;
+    }
+
+    static CoderResult encodeCR(char[] cc, String csn, boolean testDirect)
+        throws Exception {
+        ByteBuffer bbf;
+        CharBuffer cbf;
+        CharsetEncoder enc = Charset.forName(csn).newEncoder();
+        if (testDirect) {
+            bbf = ByteBuffer.allocateDirect(cc.length * 4);
+            cbf = ByteBuffer.allocateDirect(cc.length * 2).asCharBuffer();
+            cbf.put(cc).flip();
+        } else {
+            bbf = ByteBuffer.allocate(cc.length * 4);
+            cbf = CharBuffer.wrap(cc);
+        }
+        return enc.encode(cbf, bbf, true);
+    }
+
+    static char[] getUTFChars() {
+        char[] cc = new char[0x10000 - 0xe000 + 0xd800 + //bmp
+                             (0x110000 - 0x10000) * 2];    //supp
+        int pos = 0;
+        int i = 0;
+        for (i = 0; i < 0xd800; i++)
+            cc[pos++] = (char)i;
+        for (i = 0xe000; i < 0x10000; i++)
+            cc[pos++] = (char)i;
+        for (i = 0x10000; i < 0x110000; i++) {
+            pos += Character.toChars(i, cc, pos);
+        }
+        return cc;
+    }
+
+    static int to3ByteUTF8(char c, byte[] bb, int pos) {
+        bb[pos++] = (byte)(0xe0 | ((c >> 12)));
+        bb[pos++] = (byte)(0x80 | ((c >> 06) & 0x3f));
+        bb[pos++] = (byte)(0x80 | ((c >> 00) & 0x3f));
+        return 3;
+    }
+
+    static void checkRoundtrip(String csn) throws Exception {
+        System.out.printf("    Check roundtrip <%s>...", csn);
+        char[] cc = getUTFChars();
+        byte[] bb = encode(cc, csn, false);
+        char[] ccO = decode(bb, csn, false);
+
+        if (!Arrays.equals(cc, ccO)) {
+            System.out.printf("    non-direct failed");
+        }
+        bb = encode(cc, csn, true);
+        ccO = decode(bb, csn, true);
+        if (!Arrays.equals(cc, ccO)) {
+            System.out.printf("    (direct) failed");
+        }
+        System.out.println();
+    }
+
+    static void check6ByteSurrs(String csn) throws Exception {
+        System.out.printf("    Check 6-byte Surrogates <%s>...%n", csn);
+        byte[] bb = new byte[(0x110000 - 0x10000) * 6];
+        char[] cc = new char[(0x110000 - 0x10000) * 2];
+        int bpos = 0;
+        int cpos = 0;
+        for (int i = 0x10000; i < 0x110000; i++) {
+            Character.toChars(i, cc, cpos);
+            bpos += to3ByteUTF8(cc[cpos], bb, bpos);
+            bpos += to3ByteUTF8(cc[cpos + 1], bb, bpos);
+            cpos += 2;
+        }
+
+        char[] ccO = decode(bb, csn, false);
+        if (!Arrays.equals(cc, ccO)) {
+            System.out.printf("    decoding failed%n");
+        }
+        ccO = decode(bb, csn, true);
+        if (!Arrays.equals(cc, ccO)) {
+            System.out.printf("    decoding(direct) failed%n");
+        }
+    }
+
+    static void compare(String csn1, String csn2) throws Exception {
+        System.out.printf("    Diff <%s> <%s>...%n", csn1, csn2);
+        char[] cc = getUTFChars();
+
+        byte[] bb1 = encode(cc, csn1, false);
+        byte[] bb2 = encode(cc, csn2, false);
+        if (!Arrays.equals(bb1, bb2))
+            System.out.printf("        encoding failed%n");
+        char[] cc1 = decode(bb1, csn1, false);
+        char[] cc2 = decode(bb1, csn2, false);
+        if (!Arrays.equals(cc1, cc2)) {
+            System.out.printf("        decoding failed%n");
+        }
+
+        bb1 = encode(cc, csn1, true);
+        bb2 = encode(cc, csn2, true);
+        if (!Arrays.equals(bb1, bb2))
+            System.out.printf("        encoding (direct) failed%n");
+        cc1 = decode(bb1, csn1, true);
+        cc2 = decode(bb1, csn2, true);
+        if (!Arrays.equals(cc1, cc2)) {
+            System.out.printf("        decoding (direct) failed%n");
+        }
+    }
+
+    // The first byte is the length of malformed bytes
+    static byte[][] malformed = {
+        // One-byte sequences:
+        {1, (byte)0xFF },
+        {1, (byte)0xC0 },
+        {1, (byte)0x80 },
+
+        {1, (byte)0xFF, (byte)0xFF}, // all ones
+        {1, (byte)0xA0, (byte)0x80}, // 101x first byte first nibble
+
+        // Two-byte sequences:
+        {1, (byte)0xC0, (byte)0x80}, // invalid first byte
+        {1, (byte)0xC1, (byte)0xBF}, // invalid first byte
+        {1, (byte)0xC2, (byte)0x00}, // invalid second byte
+        {1, (byte)0xC2, (byte)0xC0}, // invalid second byte
+        {1, (byte)0xD0, (byte)0x00}, // invalid second byte
+        {1, (byte)0xD0, (byte)0xC0}, // invalid second byte
+        {1, (byte)0xDF, (byte)0x00}, // invalid second byte
+        {1, (byte)0xDF, (byte)0xC0}, // invalid second byte
+
+        // Three-byte sequences
+        {1, (byte)0xE0, (byte)0x80, (byte)0x80},  // 111x first byte first nibble
+        {1, (byte)0xE0, (byte)0x80, (byte)0x80 }, // U+0000 zero-padded
+        {1, (byte)0xE0, (byte)0x81, (byte)0xBF }, // U+007F zero-padded
+        {1, (byte)0xE0, (byte)0x9F, (byte)0xBF }, // U+07FF zero-padded
+
+        {1, (byte)0xE0, (byte)0xC0, (byte)0xBF }, // invalid second byte
+        {2, (byte)0xE0, (byte)0xA0, (byte)0x7F }, // invalid third byte
+        {2, (byte)0xE0, (byte)0xA0, (byte)0xC0 }, // invalid third byte
+        {1, (byte)0xFF, (byte)0xFF, (byte)0xFF }, // all ones
+        {1, (byte)0xE0, (byte)0xC0, (byte)0x80 }, // invalid second byte
+        {1, (byte)0xE0, (byte)0x80, (byte)0xC0 }, // invalid first byte
+
+        // Four-byte sequences
+        {1, (byte)0xF0, (byte)0x80, (byte)0x80, (byte)0x80 }, // U+0000 zero-padded
+        {1, (byte)0xF0, (byte)0x80, (byte)0x81, (byte)0xBF }, // U+007F zero-padded
+        {1, (byte)0xF0, (byte)0x80, (byte)0x9F, (byte)0xBF }, // U+007F zero-padded
+        {1, (byte)0xF0, (byte)0x8F, (byte)0xBF, (byte)0xBF }, // U+07FF zero-padded
+
+        {1, (byte)0xFF, (byte)0xFF, (byte)0xFF, (byte)0xFF }, // all ones
+        {1, (byte)0xF0, (byte)0x80, (byte)0x80, (byte)0x80},  // invalid second byte
+        {1, (byte)0xF0, (byte)0xC0, (byte)0x80, (byte)0x80 }, // invalid second byte
+        {2, (byte)0xF0, (byte)0x90, (byte)0xC0, (byte)0x80 }, // invalid third byte
+        {3, (byte)0xF0, (byte)0x90, (byte)0x80, (byte)0xC0 }, // invalid third byte
+
+        {1, (byte)0xF1, (byte)0xC0, (byte)0x80, (byte)0x80 }, // invalid second byte
+        {2, (byte)0xF1, (byte)0x80, (byte)0xC0, (byte)0x80 }, // invalid third byte
+        {3, (byte)0xF1, (byte)0x80, (byte)0x80, (byte)0xC0 }, // invalid forth byte
+        {1, (byte)0xF4, (byte)0x90, (byte)0x80, (byte)0xC0 }, // out-range 4-byte
+        {1, (byte)0xF4, (byte)0xC0, (byte)0x80, (byte)0xC0 }, // out-range 4-byte
+        {1, (byte)0xF5, (byte)0x80, (byte)0x80, (byte)0xC0 }, // out-range 4-byte
+
+        // Five-byte sequences
+        {5, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x80},  // invalid first byte
+        {5, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x80 }, // U+0000 zero-padded
+        {5, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x81, (byte)0xBF }, // U+007F zero-padded
+        {5, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x9F, (byte)0xBF }, // U+07FF zero-padded
+        {5, (byte)0xF8, (byte)0x80, (byte)0x8F, (byte)0xBF, (byte)0xBF }, // U+FFFF zero-padded
+
+        {1, (byte)0xF8, (byte)0xC0, (byte)0x80, (byte)0x80, (byte)0x80},
+        {2, (byte)0xF8, (byte)0x80, (byte)0xC0, (byte)0x80, (byte)0x80 },
+        {3, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0xC1, (byte)0xBF },
+        {4, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x9F, (byte)0xC0 },
+
+        // Six-byte sequences
+        {6, (byte)0xFC, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x80 }, // U+0000 zero-padded
+        {6, (byte)0xFC, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x81, (byte)0xBF }, // U+007F zero-padded
+        {6, (byte)0xFC, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x9F, (byte)0xBF }, // U+07FF zero-padded
+        {6, (byte)0xFC, (byte)0x80, (byte)0x80, (byte)0x8F, (byte)0xBF, (byte)0xBF }, // U+FFFF zero-padded
+        {1, (byte)0xF8, (byte)0xC0, (byte)0x80, (byte)0x80, (byte)0x80, (byte)0x80 },
+        {2, (byte)0xF8, (byte)0x80, (byte)0xC0, (byte)0x80, (byte)0x80, (byte)0x80 },
+        {3, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0xC1, (byte)0xBF, (byte)0x80 },
+        {4, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x9F, (byte)0xC0, (byte)0x80 },
+        {5, (byte)0xF8, (byte)0x80, (byte)0x80, (byte)0x9F, (byte)0x80, (byte)0xC0 },
+    };
+
+    static void checkMalformed(String csn) throws Exception {
+        boolean failed = false;
+        System.out.printf("    Check malformed <%s>...%n", csn);
+        for (boolean direct: new boolean[] {false, true}) {
+            for (byte[] bins : malformed) {
+                int mlen = bins[0];
+                byte[] bin = Arrays.copyOfRange(bins, 1, bins.length);
+                CoderResult cr = decodeCR(bin, csn, direct);
+                String ashex = "";
+                for (int i = 0; i < bin.length; i++) {
+                    if (i > 0) ashex += " ";
+                        ashex += Integer.toBinaryString((int)bin[i] & 0xff);
+                }
+                if (!cr.isMalformed()) {
+                    System.out.printf("        FAIL(direct=%b): [%s] not malformed.\n", direct, ashex);
+                    failed = true;
+                } else if (cr.length() != mlen) {
+                    System.out.printf("        FAIL(direct=%b): [%s] malformed[len=%d].\n", direct, ashex, cr.length());
+                    failed = true;
+                }
+            }
+        }
+        if (failed)
+            throw new RuntimeException("Check malformed failed " + csn);
+    }
+
+    static boolean check(CharsetDecoder dec, byte[] utf8s, boolean direct, int[] flow) {
+        int inPos = flow[0];
+        int inLen = flow[1];
+        int outPos = flow[2];
+        int outLen = flow[3];
+        int expedInPos = flow[4];
+        int expedOutPos = flow[5];
+        CoderResult expedCR = (flow[6]==0)?CoderResult.UNDERFLOW
+                                          :CoderResult.OVERFLOW;
+        ByteBuffer bbf;
+        CharBuffer cbf;
+        if (direct) {
+            bbf = ByteBuffer.allocateDirect(inPos + utf8s.length);
+            cbf = ByteBuffer.allocateDirect((outPos + outLen)*2).asCharBuffer();
+        } else {
+            bbf = ByteBuffer.allocate(inPos + utf8s.length);
+            cbf = CharBuffer.allocate(outPos + outLen);
+        }
+        bbf.position(inPos);
+        bbf.put(utf8s).flip().position(inPos).limit(inPos + inLen);
+        cbf.position(outPos);
+        dec.reset();
+        CoderResult cr = dec.decode(bbf, cbf, false);
+        if (cr != expedCR ||
+            bbf.position() != expedInPos ||
+            cbf.position() != expedOutPos) {
+            System.out.printf("Expected(direct=%5b): [", direct);
+            for (int i:flow) System.out.print(" " + i);
+            System.out.println("]  CR=" + cr +
+                               ", inPos=" + bbf.position() +
+                               ", outPos=" + cbf.position());
+            return false;
+        }
+        return true;
+    }
+
+    static void checkUnderOverflow(String csn) throws Exception {
+        System.out.printf("    Check under/overflow <%s>...%n", csn);
+        CharsetDecoder dec = Charset.forName(csn).newDecoder();
+        boolean failed = false;
+        byte[] utf8s = new String("\u007f\u07ff\ue000\ud800\udc00").getBytes("UTF-8");
+        int    inlen = utf8s.length;
+
+        for (int inoff = 0; inoff < 20; inoff++) {
+            for (int outoff = 0; outoff < 20; outoff++) {
+        int[][] Flows = {
+            //inpos, inLen, outPos,  outLen, inPosEP,   outposEP,   under(0)/over(1)
+            {inoff,  inlen, outoff,  1,      inoff + 1, outoff + 1, 1},
+            {inoff,  inlen, outoff,  2,      inoff + 3, outoff + 2, 1},
+            {inoff,  inlen, outoff,  3,      inoff + 6, outoff + 3, 1},
+            {inoff,  inlen, outoff,  4,      inoff + 6, outoff + 3, 1},
+            {inoff,  inlen, outoff,  5,      inoff + 10,outoff + 5, 0},
+             // underflow
+            {inoff,  1,     outoff,  5,      inoff + 1, outoff + 1, 0},
+            {inoff,  2,     outoff,  5,      inoff + 1, outoff + 1, 0},
+            {inoff,  3,     outoff,  5,      inoff + 3, outoff + 2, 0},
+            {inoff,  4,     outoff,  5,      inoff + 3, outoff + 2, 0},
+            {inoff,  5,     outoff,  5,      inoff + 3, outoff + 2, 0},
+            {inoff,  6,     outoff,  5,      inoff + 6, outoff + 3, 0},
+            {inoff,  7,     outoff,  5,      inoff + 6, outoff + 3, 0},
+            {inoff,  8,     outoff,  5,      inoff + 6, outoff + 3, 0},
+            {inoff,  9,     outoff,  5,      inoff + 6, outoff + 3, 0},
+            {inoff,  10,    outoff,  5,      inoff + 10,outoff + 5, 0},
+             // 2-byte underflow/overflow
+            {inoff,  2,     outoff,  1,      inoff + 1, outoff + 1, 0},
+            {inoff,  3,     outoff,  1,      inoff + 1, outoff + 1, 1},
+             // 3-byte underflow/overflow
+            {inoff,  4,     outoff,  2,      inoff + 3, outoff + 2, 0},
+            {inoff,  5,     outoff,  2,      inoff + 3, outoff + 2, 0},
+            {inoff,  6,     outoff,  2,      inoff + 3, outoff + 2, 1},
+             // 4-byte underflow/overflow
+            {inoff,  7,     outoff,  4,      inoff + 6, outoff + 3, 0},
+            {inoff,  8,     outoff,  4,      inoff + 6, outoff + 3, 0},
+            {inoff,  9,     outoff,  4,      inoff + 6, outoff + 3, 0},
+            {inoff,  10,    outoff,  4,      inoff + 6, outoff + 3, 1},
+        };
+        for (boolean direct: new boolean[] {false, true}) {
+            for (int[] flow: Flows) {
+                if (!check(dec, utf8s, direct, flow))
+                    failed = true;
+            }
+        }}}
+        if (failed)
+            throw new RuntimeException("Check under/overflow failed " + csn);
+    }
+
+    public static void main(String[] args) throws Exception {
+        checkRoundtrip("UTF-8");
+        check6ByteSurrs("UTF-8");
+        //compare("UTF-8", "UTF-8-OLD");
+        checkMalformed("UTF-8");
+        checkUnderOverflow("UTF-8");
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/sun/security/util/DerValue/Indefinite.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/*
+ * @test
+ * @bug 6731685
+ * @summary CertificateFactory.generateCertificates throws IOException on PKCS7 cert chain
+ */
+
+import java.io.*;
+import sun.security.util.*;
+
+public class Indefinite {
+
+    public static void main(String[] args) throws Exception {
+        byte[] input = {
+            // An OCTET-STRING in 2 parts
+            4, (byte)0x80, 4, 2, 'a', 'b', 4, 2, 'c', 'd', 0, 0,
+            // Garbage follows, may be falsely recognized as EOC
+            0, 0, 0, 0
+        };
+        new DerValue(new ByteArrayInputStream(input));
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/jdk/test/sun/tools/jrunscript/CheckEngine.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+import javax.script.*;
+
+/*
+ * If the JDK being tested is <b>not</b> a Sun product JDK and a js
+ * engine is not present, return an exit code of 2 to indicate that
+ * the jrunscript tests which assume a js engine can be vacuously
+ * passed.
+ */
+public class CheckEngine {
+    public static void main(String... args) {
+        int exitCode = 0;
+        ScriptEngine engine =
+            (new ScriptEngineManager()).getEngineByName("js");
+
+        if (engine == null &&
+            !(System.getProperty("java.runtime.name").startsWith("Java(TM)"))) {
+            exitCode = 2;
+        }
+
+        System.exit(exitCode);
+    }
+}
--- a/jdk/test/sun/tools/jrunscript/common.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/common.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -52,4 +52,5 @@
 
     JRUNSCRIPT="${TESTJAVA}/bin/jrunscript"
     JAVAC="${TESTJAVA}/bin/javac"
+    JAVA="${TESTJAVA}/bin/java"
 }
--- a/jdk/test/sun/tools/jrunscript/jrunscript-DTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscript-DTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscript-DTest.sh
 # @summary Test that output of 'jrunscript -D' 
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 # test whether value specifieD by -D option is passed
 # to script as java.lang.System property.  sysProps is
--- a/jdk/test/sun/tools/jrunscript/jrunscript-argsTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscript-argsTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscript-argsTest.sh
 # @summary Test passing of script arguments from command line
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 # we check whether "excess" args are passed as script arguments
 
--- a/jdk/test/sun/tools/jrunscript/jrunscript-cpTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscript-cpTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscript-cpTest.sh
 # @summary Test -cp option to set classpath
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 rm -f Hello.class
 ${JAVAC} ${TESTSRC}/Hello.java -d .
--- a/jdk/test/sun/tools/jrunscript/jrunscript-eTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscript-eTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscript-eTest.sh
 # @summary Test that output of 'jrunscript -e' matches the dash-e.out file
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 rm -f jrunscript-eTest.out 2>/dev/null
 ${JRUNSCRIPT} -e "println('hello')" > jrunscript-eTest.out 2>&1
--- a/jdk/test/sun/tools/jrunscript/jrunscript-fTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscript-fTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscript-fTest.sh
 # @summary Test that output of 'jrunscript -f' matches the dash-f.out file
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 rm -f jrunscript-fTest.out 2>/dev/null
 ${JRUNSCRIPT} -f ${TESTSRC}/hello.js > jrunscript-fTest.out 2>&1
--- a/jdk/test/sun/tools/jrunscript/jrunscriptTest.sh	Wed Jul 05 16:40:32 2017 +0200
+++ b/jdk/test/sun/tools/jrunscript/jrunscriptTest.sh	Wed Jul 05 16:41:01 2017 +0200
@@ -25,13 +25,19 @@
 
 
 # @test
-# @bug 6265810
+# @bug 6265810 6705893
+# @build CheckEngine
 # @run shell jrunscriptTest.sh
 # @summary Test that output of 'jrunscript' interactive matches the repl.out file
 
 . ${TESTSRC-.}/common.sh
 
 setup
+${JAVA} -cp ${TESTCLASSES} CheckEngine
+if [ $? -eq 2 ]; then
+    echo "No js engine found and engine not required; test vacuously passes."
+    exit 0
+fi
 
 rm -f jrunscriptTest.out 2>/dev/null
 ${JRUNSCRIPT} > jrunscriptTest.out 2>&1 <<EOF
--- a/langtools/.hgtags	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/.hgtags	Wed Jul 05 16:41:01 2017 +0200
@@ -8,3 +8,4 @@
 07c916ecfc71f6bf432e4ff09bfbfb6290b5703c jdk7-b31
 13aee98cc0d8e24a084b62ad1d48d2a49792416c jdk7-b32
 0a5f04fb72825302a80a67c636a7ddc410ead266 jdk7-b33
+4026dece07e86ae75154c05b98ba342d00828ed7 jdk7-b34
--- a/langtools/src/share/classes/com/sun/tools/javac/api/DiagnosticFormatter.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/api/DiagnosticFormatter.java	Wed Jul 05 16:41:01 2017 +0200
@@ -73,9 +73,10 @@
      *
      * @param diag diagnostic to be formatted
      * @param l locale object to be used for i18n
+     * @param fullname whether the source fullname should be printed
      * @return string representation of the diagnostic source
      */
-    public String formatSource(D diag, Locale l);
+    public String formatSource(D diag, boolean fullname, Locale l);
 
     /**
      * Controls the way in which a diagnostic position is displayed.
--- a/langtools/src/share/classes/com/sun/tools/javac/util/AbstractDiagnosticFormatter.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/AbstractDiagnosticFormatter.java	Wed Jul 05 16:41:01 2017 +0200
@@ -94,9 +94,9 @@
         }
     }
 
-    public String formatSource(JCDiagnostic d,Locale l) {
+    public String formatSource(JCDiagnostic d, boolean fullname, Locale l) {
         assert (d.getSource() != null);
-        return d.getSource().getName();
+        return fullname ? d.getSourceName() : d.getSource().getName();
     }
 
     /**
--- a/langtools/src/share/classes/com/sun/tools/javac/util/BasicDiagnosticFormatter.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/BasicDiagnosticFormatter.java	Wed Jul 05 16:41:01 2017 +0200
@@ -108,11 +108,11 @@
     protected String formatMeta(char c, JCDiagnostic d, Locale l) {
         switch (c) {
             case 'b':
-                return formatSource(d, l);
+                return formatSource(d, false, l);
             case 'e':
                 return formatPosition(d, END, l);
             case 'f':
-                return formatSource(d, l);
+                return formatSource(d, true, l);
             case 'l':
                 return formatPosition(d, LINE, l);
             case 'c':
--- a/langtools/src/share/classes/com/sun/tools/javac/util/DiagnosticSource.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/DiagnosticSource.java	Wed Jul 05 16:41:01 2017 +0200
@@ -81,7 +81,7 @@
      * for the current source file.  Zero is returned if no column exists
      * for the given position.
      */
-    public int getColumnNumber(int pos) {
+    public int getColumnNumber(int pos, boolean expandTabs) {
         try {
             if (findLine(pos)) {
                 int column = 0;
@@ -89,7 +89,7 @@
                     if (bp >= bufLen) {
                         return 0;
                     }
-                    if (buf[bp] == '\t') {
+                    if (buf[bp] == '\t' && expandTabs) {
                         column = (column / TabInc * TabInc) + TabInc;
                     } else {
                         column++;
--- a/langtools/src/share/classes/com/sun/tools/javac/util/JCDiagnostic.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/JCDiagnostic.java	Wed Jul 05 16:41:01 2017 +0200
@@ -296,7 +296,7 @@
             line = column = -1;
         else {
             line = source.getLineNumber(n);
-            column = source.getColumnNumber(n);
+            column = source.getColumnNumber(n, true);
         }
     }
 
--- a/langtools/src/share/classes/com/sun/tools/javac/util/Log.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/Log.java	Wed Jul 05 16:41:01 2017 +0200
@@ -244,7 +244,7 @@
         String line = (source == null ? null : source.getLine(pos));
         if (line == null)
             return;
-        int col = source.getColumnNumber(pos);
+        int col = source.getColumnNumber(pos, false);
 
         printLines(writer, line);
         for (int i = 0; i < col - 1; i++) {
--- a/langtools/src/share/classes/com/sun/tools/javac/util/RawDiagnosticFormatter.java	Wed Jul 05 16:40:32 2017 +0200
+++ b/langtools/src/share/classes/com/sun/tools/javac/util/RawDiagnosticFormatter.java	Wed Jul 05 16:41:01 2017 +0200
@@ -50,7 +50,7 @@
         try {
             StringBuffer buf = new StringBuffer();
             if (d.getPosition() != Position.NOPOS) {
-                buf.append(formatSource(d, null));
+                buf.append(formatSource(d, false, null));
                 buf.append(':');
                 buf.append(formatPosition(d, LINE, null));
                 buf.append(':');
@@ -70,12 +70,6 @@
     }
 
     @Override
-    public String formatSource(JCDiagnostic d,Locale l) {
-        assert(d.getSource() != null);
-        return d.getSource().getName();
-    }
-
-    @Override
     protected String formatArgument(JCDiagnostic diag, Object arg, Locale l) {
         String s;
         if (arg instanceof Formattable)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/langtools/test/tools/javac/api/6733837/T6733837.java	Wed Jul 05 16:41:01 2017 +0200
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All Rights Reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ */
+
+/*
+ * @test
+ * @bug     6733837
+ * @summary Compiler API ignores locale settings
+ * @author  Maurizio Cimadamore
+ * @library ../lib
+ */
+
+import java.io.StringWriter;
+import java.io.PrintWriter;
+import java.net.URI;
+import java.util.Arrays;
+import java.util.List;
+import javax.tools.JavaFileObject;
+import javax.tools.SimpleJavaFileObject;
+import static javax.tools.JavaFileObject.Kind;
+import com.sun.source.util.JavacTask;
+
+public class T6733837 extends ToolTester {
+
+    public static void main(String... args) {
+        new T6733837().exec();
+    }
+
+    public void exec() {
+        JavaFileObject sfo = new SimpleJavaFileObject(URI.create(""),Kind.SOURCE) {
+            public CharSequence getCharContent(boolean ignoreEncodingErrors) {
+                return "\tclass ErroneousWithTab";
+            }
+            @Override
+            public String getName() {
+                return "RELATIVEPATH";
+            }
+        };
+        StringWriter sw = new StringWriter();
+        PrintWriter out = new PrintWriter(sw);
+        List<? extends JavaFileObject> files = Arrays.asList(sfo);
+        task = tool.getTask(sw, fm, null, null, null, files);
+        try {
+            ((JavacTask)task).analyze();
+        }
+        catch (Throwable t) {
+            throw new Error("Compiler threw an exception");
+        }
+        System.err.println(sw.toString());
+        if (sw.toString().contains("RELATIVEPATH"))
+            throw new Error("Bad source name in diagnostic");
+    }
+}