# HG changeset patch
# User dchuyko
# Date 1511872935 -10800
# Node ID bafb0db43bfee757d561a8f76f374dd18a3feb42
# Parent  ae61a5eb9da47ef32d5b032a24c9090e59ceb7dd
8191769: AARCH64: Fix hint instructions encoding
Reviewed-by: adinn

diff -r ae61a5eb9da4 -r bafb0db43bfe src/hotspot/cpu/aarch64/assembler_aarch64.hpp
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue Nov 28 12:23:03 2017 +0100
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue Nov 28 15:42:15 2017 +0300
@@ -985,12 +985,33 @@
   }
 
   void hint(int imm) {
-    system(0b00, 0b011, 0b0010, imm, 0b000);
+    system(0b00, 0b011, 0b0010, 0b0000, imm);
   }
 
   void nop() {
     hint(0);
   }
+
+  void yield() {
+    hint(1);
+  }
+
+  void wfe() {
+    hint(2);
+  }
+
+  void wfi() {
+    hint(3);
+  }
+
+  void sev() {
+    hint(4);
+  }
+
+  void sevl() {
+    hint(5);
+  }
+
   // we only provide mrs and msr for the special purpose system
   // registers where op1 (instr[20:19]) == 11 and, (currently) only
   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1