# HG changeset patch
# User aph
# Date 1426873169 0
# Node ID 8c1cc431f38817091c002a8a8ac60e3ca69874fd
# Parent  47544495db2d3d2edf0f85862d8715592fdb919f
8075443: AARCH64: Missed L2I optimizations in C2
Summary: Use iRegIOrL2I for input operands whenever it makes sense.
Reviewed-by: kvn

diff -r 47544495db2d -r 8c1cc431f388 hotspot/src/cpu/aarch64/vm/aarch64.ad
--- a/hotspot/src/cpu/aarch64/vm/aarch64.ad	Wed Jul 05 20:25:16 2017 +0200
+++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad	Fri Mar 20 17:39:29 2015 +0000
@@ -6056,7 +6056,7 @@
 %}
 
 // Store Byte
-instruct storeB_volatile(iRegI src, /* sync_memory*/indirect mem)
+instruct storeB_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
 %{
   match(Set mem (StoreB mem src));
 
@@ -6069,7 +6069,7 @@
 %}
 
 // Store Char/Short
-instruct storeC_volatile(iRegI src, /* sync_memory*/indirect mem)
+instruct storeC_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
 %{
   match(Set mem (StoreC mem src));
 
@@ -6225,7 +6225,7 @@
 // ============================================================================
 // Zero Count Instructions
 
-instruct countLeadingZerosI(iRegINoSp dst, iRegI src) %{
+instruct countLeadingZerosI(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (CountLeadingZerosI src));
 
   ins_cost(INSN_COST);
@@ -6249,7 +6249,7 @@
   ins_pipe(ialu_reg);
 %}
 
-instruct countTrailingZerosI(iRegINoSp dst, iRegI src) %{
+instruct countTrailingZerosI(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (CountTrailingZerosI src));
 
   ins_cost(INSN_COST * 2);
@@ -6935,7 +6935,7 @@
 // which throws a ShouldNotHappen. So, we have to provide two flavours
 // of each rule, one for a cmpOp and a second for a cmpOpU (sigh).
 
-instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
 
   ins_cost(INSN_COST * 2);
@@ -6951,7 +6951,7 @@
   ins_pipe(icond_reg_reg);
 %}
 
-instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
 
   ins_cost(INSN_COST * 2);
@@ -6976,7 +6976,7 @@
 // we ought only to be able to cull one of these variants as the ideal
 // transforms ought always to order the zero consistently (to left/right?)
 
-instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegI src) %{
+instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
 
   ins_cost(INSN_COST * 2);
@@ -6992,7 +6992,7 @@
   ins_pipe(icond_reg);
 %}
 
-instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegI src) %{
+instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
 
   ins_cost(INSN_COST * 2);
@@ -7008,7 +7008,7 @@
   ins_pipe(icond_reg);
 %}
 
-instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src, immI0 zero) %{
+instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
 
   ins_cost(INSN_COST * 2);
@@ -7024,7 +7024,7 @@
   ins_pipe(icond_reg);
 %}
 
-instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src, immI0 zero) %{
+instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
   match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
 
   ins_cost(INSN_COST * 2);
@@ -7476,7 +7476,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct addI_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2) %{
+instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
   match(Set dst (AddI src1 src2));
 
   ins_cost(INSN_COST);
@@ -7869,7 +7869,7 @@
   ins_pipe(idiv_reg_reg);
 %}
 
-instruct signExtract(iRegINoSp dst, iRegI src1, immI_31 div1, immI_31 div2) %{
+instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
   match(Set dst (URShiftI (RShiftI src1 div1) div2));
   ins_cost(INSN_COST);
   format %{ "lsrw $dst, $src1, $div1" %}
@@ -7879,7 +7879,7 @@
   ins_pipe(ialu_reg_shift);
 %}
 
-instruct div2Round(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
+instruct div2Round(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{
   match(Set dst (AddI src (URShiftI (RShiftI src div1) div2)));
   ins_cost(INSN_COST);
   format %{ "addw $dst, $src, LSR $div1" %}
@@ -8189,7 +8189,7 @@
   ins_pipe(ialu_reg);
 %}
 instruct regI_not_reg(iRegINoSp dst,
-                         iRegI src1, immI_M1 m1,
+                         iRegIorL2I src1, immI_M1 m1,
                          rFlagsReg cr) %{
   match(Set dst (XorI src1 m1));
   ins_cost(INSN_COST);
@@ -8206,14 +8206,14 @@
 %}
 
 instruct AndI_reg_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2, immI_M1 m1,
+                         iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
                          rFlagsReg cr) %{
   match(Set dst (AndI src1 (XorI src2 m1)));
   ins_cost(INSN_COST);
-  format %{ "bic  $dst, $src1, $src2" %}
-
-  ins_encode %{
-    __ bic(as_Register($dst$$reg),
+  format %{ "bicw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ bicw(as_Register($dst$$reg),
               as_Register($src1$$reg),
               as_Register($src2$$reg),
               Assembler::LSL, 0);
@@ -8240,14 +8240,14 @@
 %}
 
 instruct OrI_reg_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2, immI_M1 m1,
+                         iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
                          rFlagsReg cr) %{
   match(Set dst (OrI src1 (XorI src2 m1)));
   ins_cost(INSN_COST);
-  format %{ "orn  $dst, $src1, $src2" %}
-
-  ins_encode %{
-    __ orn(as_Register($dst$$reg),
+  format %{ "ornw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ ornw(as_Register($dst$$reg),
               as_Register($src1$$reg),
               as_Register($src2$$reg),
               Assembler::LSL, 0);
@@ -8274,14 +8274,14 @@
 %}
 
 instruct XorI_reg_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2, immI_M1 m1,
+                         iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
                          rFlagsReg cr) %{
   match(Set dst (XorI m1 (XorI src2 src1)));
   ins_cost(INSN_COST);
-  format %{ "eon  $dst, $src1, $src2" %}
-
-  ins_encode %{
-    __ eon(as_Register($dst$$reg),
+  format %{ "eonw  $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ eonw(as_Register($dst$$reg),
               as_Register($src1$$reg),
               as_Register($src2$$reg),
               Assembler::LSL, 0);
@@ -8308,7 +8308,7 @@
 %}
 
 instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8344,7 +8344,7 @@
 %}
 
 instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8380,7 +8380,7 @@
 %}
 
 instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8416,7 +8416,7 @@
 %}
 
 instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
   ins_cost(1.9 * INSN_COST);
@@ -8452,7 +8452,7 @@
 %}
 
 instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
   ins_cost(1.9 * INSN_COST);
@@ -8488,7 +8488,7 @@
 %}
 
 instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
   ins_cost(1.9 * INSN_COST);
@@ -8524,7 +8524,7 @@
 %}
 
 instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8560,7 +8560,7 @@
 %}
 
 instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8596,7 +8596,7 @@
 %}
 
 instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, immI_M1 src4, rFlagsReg cr) %{
   match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
   ins_cost(1.9 * INSN_COST);
@@ -8632,7 +8632,7 @@
 %}
 
 instruct AndI_reg_URShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AndI src1 (URShiftI src2 src3)));
 
@@ -8670,7 +8670,7 @@
 %}
 
 instruct AndI_reg_RShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AndI src1 (RShiftI src2 src3)));
 
@@ -8708,7 +8708,7 @@
 %}
 
 instruct AndI_reg_LShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AndI src1 (LShiftI src2 src3)));
 
@@ -8746,7 +8746,7 @@
 %}
 
 instruct XorI_reg_URShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (XorI src1 (URShiftI src2 src3)));
 
@@ -8784,7 +8784,7 @@
 %}
 
 instruct XorI_reg_RShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (XorI src1 (RShiftI src2 src3)));
 
@@ -8822,7 +8822,7 @@
 %}
 
 instruct XorI_reg_LShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (XorI src1 (LShiftI src2 src3)));
 
@@ -8860,7 +8860,7 @@
 %}
 
 instruct OrI_reg_URShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (OrI src1 (URShiftI src2 src3)));
 
@@ -8898,7 +8898,7 @@
 %}
 
 instruct OrI_reg_RShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (OrI src1 (RShiftI src2 src3)));
 
@@ -8936,7 +8936,7 @@
 %}
 
 instruct OrI_reg_LShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (OrI src1 (LShiftI src2 src3)));
 
@@ -8974,7 +8974,7 @@
 %}
 
 instruct AddI_reg_URShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AddI src1 (URShiftI src2 src3)));
 
@@ -9012,7 +9012,7 @@
 %}
 
 instruct AddI_reg_RShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AddI src1 (RShiftI src2 src3)));
 
@@ -9050,7 +9050,7 @@
 %}
 
 instruct AddI_reg_LShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (AddI src1 (LShiftI src2 src3)));
 
@@ -9088,7 +9088,7 @@
 %}
 
 instruct SubI_reg_URShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (SubI src1 (URShiftI src2 src3)));
 
@@ -9126,7 +9126,7 @@
 %}
 
 instruct SubI_reg_RShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (SubI src1 (RShiftI src2 src3)));
 
@@ -9164,7 +9164,7 @@
 %}
 
 instruct SubI_reg_LShift_reg(iRegINoSp dst,
-                         iRegI src1, iRegI src2,
+                         iRegIorL2I src1, iRegIorL2I src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst (SubI src1 (LShiftI src2 src3)));
 
@@ -9228,7 +9228,7 @@
 
 // Shift Left followed by Shift Right.
 // This idiom is used by the compiler for the i2b bytecode etc.
-instruct sbfmwI(iRegINoSp dst, iRegI src, immI lshift_count, immI rshift_count)
+instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
 %{
   match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
   // Make sure we are not going to exceed what sbfmw can do.
@@ -9274,7 +9274,7 @@
 
 // Shift Left followed by Shift Right.
 // This idiom is used by the compiler for the i2b bytecode etc.
-instruct ubfmwI(iRegINoSp dst, iRegI src, immI lshift_count, immI rshift_count)
+instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
 %{
   match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
   // Make sure we are not going to exceed what ubfmw can do.
@@ -9296,7 +9296,7 @@
 %}
 // Bitfield extract with shift & mask
 
-instruct ubfxwI(iRegINoSp dst, iRegI src, immI rshift, immI_bitmask mask)
+instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
 %{
   match(Set dst (AndI (URShiftI src rshift) mask));
 
@@ -9362,7 +9362,7 @@
   ins_pipe(ialu_reg_reg_extr);
 %}
 
-instruct extrOrI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
+instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
 %{
   match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
@@ -9392,7 +9392,7 @@
   ins_pipe(ialu_reg_reg_extr);
 %}
 
-instruct extrAddI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
+instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
 %{
   match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
@@ -9571,7 +9571,7 @@
 %};
 
 
-instruct AddExtI_sxth(iRegINoSp dst, iRegI src1, iRegI src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
+instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
@@ -9584,7 +9584,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct AddExtI_sxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
+instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
@@ -9597,7 +9597,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct AddExtI_uxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
+instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
@@ -9663,7 +9663,7 @@
 %}
 
 
-instruct AddExtI_uxtb_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_255 mask, rFlagsReg cr)
+instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (AndI src2 mask)));
   ins_cost(INSN_COST);
@@ -9676,7 +9676,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct AddExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
+instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
 %{
   match(Set dst (AddI src1 (AndI src2 mask)));
   ins_cost(INSN_COST);
@@ -9728,7 +9728,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct SubExtI_uxtb_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_255 mask, rFlagsReg cr)
+instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
 %{
   match(Set dst (SubI src1 (AndI src2 mask)));
   ins_cost(INSN_COST);
@@ -9741,7 +9741,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct SubExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
+instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
 %{
   match(Set dst (SubI src1 (AndI src2 mask)));
   ins_cost(INSN_COST);
@@ -10343,7 +10343,7 @@
 %}
 
 // this pattern occurs in bigmath arithmetic
-instruct convUI2L_reg_reg(iRegLNoSp dst, iRegI src, immL_32bits mask)
+instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 %{
   match(Set dst (AndL (ConvI2L src) mask));
 
@@ -10369,7 +10369,7 @@
   ins_pipe(ialu_reg);
 %}
 
-instruct convI2B(iRegINoSp dst, iRegI src, rFlagsReg cr)
+instruct convI2B(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
 %{
   match(Set dst (Conv2B src));
   effect(KILL cr);
@@ -10457,7 +10457,7 @@
   ins_pipe(pipe_class_default);
 %}
 
-instruct convI2F_reg_reg(vRegF dst, iRegI src) %{
+instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
   match(Set dst (ConvI2F src));
 
   ins_cost(INSN_COST * 5);
@@ -10509,7 +10509,7 @@
   ins_pipe(pipe_class_default);
 %}
 
-instruct convI2D_reg_reg(vRegD dst, iRegI src) %{
+instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
   match(Set dst (ConvI2D src));
 
   ins_cost(INSN_COST * 5);
@@ -10772,7 +10772,7 @@
 // ============================================================================
 // Overflow Math Instructions
 
-instruct overflowAddI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
 %{
   match(Set cr (OverflowAddI op1 op2));
 
@@ -10785,7 +10785,7 @@
   ins_pipe(icmp_reg_reg);
 %}
 
-instruct overflowAddI_reg_imm(rFlagsReg cr, iRegI op1, immIAddSub op2)
+instruct overflowAddI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
 %{
   match(Set cr (OverflowAddI op1 op2));
 
@@ -10824,7 +10824,7 @@
   ins_pipe(icmp_reg_imm);
 %}
 
-instruct overflowSubI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+instruct overflowSubI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
 %{
   match(Set cr (OverflowSubI op1 op2));
 
@@ -10837,7 +10837,7 @@
   ins_pipe(icmp_reg_reg);
 %}
 
-instruct overflowSubI_reg_imm(rFlagsReg cr, iRegI op1, immIAddSub op2)
+instruct overflowSubI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
 %{
   match(Set cr (OverflowSubI op1 op2));
 
@@ -10876,7 +10876,7 @@
   ins_pipe(icmp_reg_imm);
 %}
 
-instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegI op1)
+instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegIorL2I op1)
 %{
   match(Set cr (OverflowSubI zero op1));
 
@@ -10902,7 +10902,7 @@
   ins_pipe(icmp_reg_imm);
 %}
 
-instruct overflowMulI_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+instruct overflowMulI_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
 %{
   match(Set cr (OverflowMulI op1 op2));
 
@@ -10923,7 +10923,7 @@
   ins_pipe(pipe_slow);
 %}
 
-instruct overflowMulI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, rFlagsReg cr)
+instruct overflowMulI_reg_branch(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, label labl, rFlagsReg cr)
 %{
   match(If cmp (OverflowMulI op1 op2));
   predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
@@ -11393,7 +11393,7 @@
 
 %}
 
-instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q, rFlagsReg cr)
+instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
 %{
   match(Set dst (CmpLTMask p q));
   effect(KILL cr);
@@ -11414,7 +11414,7 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegI src, immI0 zero, rFlagsReg cr)
+instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
 %{
   match(Set dst (CmpLTMask src zero));
   effect(KILL cr);
@@ -11548,7 +11548,7 @@
 // shorter than (cmp; branch), have the additional benefit of not
 // killing the flags.
 
-instruct cmpI_imm0_branch(cmpOp cmp, iRegI op1, immI0 op2, label labl, rFlagsReg cr) %{
+instruct cmpI_imm0_branch(cmpOp cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
   match(If cmp (CmpI op1 op2));
   predicate(n->in(1)->as_Bool()->_test._test == BoolTest::ne
             || n->in(1)->as_Bool()->_test._test == BoolTest::eq);
diff -r 47544495db2d -r 8c1cc431f388 hotspot/src/cpu/aarch64/vm/aarch64_ad.m4
--- a/hotspot/src/cpu/aarch64/vm/aarch64_ad.m4	Wed Jul 05 20:25:16 2017 +0200
+++ b/hotspot/src/cpu/aarch64/vm/aarch64_ad.m4	Fri Mar 20 17:39:29 2015 +0000
@@ -24,11 +24,13 @@
 dnl and shift patterns patterns used in aarch64.ad.
 dnl
 // BEGIN This section of the file is automatically generated. Do not edit --------------
-
+dnl
+define(`ORL2I', `ifelse($1,I,orL2I)')
+dnl
 define(`BASE_SHIFT_INSN',
 `
 instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
-                         iReg$1 src1, iReg$1 src2,
+                         iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
                          immI src3, rFlagsReg cr) %{
   match(Set dst ($2$1 src1 ($4$1 src2 src3)));
 
@@ -48,7 +50,7 @@
 define(`BASE_INVERTED_INSN',
 `
 instruct $2$1_reg_not_reg(iReg$1NoSp dst,
-                         iReg$1 src1, iReg$1 src2, imm$1_M1 m1,
+                         iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_M1 m1,
                          rFlagsReg cr) %{
 dnl This ifelse is because hotspot reassociates (xor (xor ..)..)
 dnl into this canonical form.
@@ -70,7 +72,7 @@
 define(`INVERTED_SHIFT_INSN',
 `
 instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
-                         iReg$1 src1, iReg$1 src2,
+                         iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
                          immI src3, imm$1_M1 src4, rFlagsReg cr) %{
 dnl This ifelse is because hotspot reassociates (xor (xor ..)..)
 dnl into this canonical form.
@@ -92,7 +94,7 @@
 %}')dnl
 define(`NOT_INSN',
 `instruct reg$1_not_reg(iReg$1NoSp dst,
-                         iReg$1 src1, imm$1_M1 m1,
+                         iReg$1`'ORL2I($1) src1, imm$1_M1 m1,
                          rFlagsReg cr) %{
   match(Set dst (Xor$1 src1 m1));
   ins_cost(INSN_COST);
@@ -113,7 +115,7 @@
 BASE_SHIFT_INSN(L, $1, $2, $3, $4)')dnl
 dnl
 define(`BOTH_INVERTED_INSNS',
-`BASE_INVERTED_INSN(I, $1, $2, $3, $4)
+`BASE_INVERTED_INSN(I, $1, $2w, $3, $4)
 BASE_INVERTED_INSN(L, $1, $2, $3, $4)')dnl
 dnl
 define(`BOTH_INVERTED_SHIFT_INSNS',
@@ -149,7 +151,7 @@
 define(`BFM_INSN',`
 // Shift Left followed by Shift Right.
 // This idiom is used by the compiler for the i2b bytecode etc.
-instruct $4$1(iReg$1NoSp dst, iReg$1 src, immI lshift_count, immI rshift_count)
+instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rshift_count)
 %{
   match(Set dst EXTEND($1, $3, src, lshift_count, rshift_count));
   // Make sure we are not going to exceed what $4 can do.
@@ -176,7 +178,7 @@
 dnl
 // Bitfield extract with shift & mask
 define(`BFX_INSN',
-`instruct $3$1(iReg$1NoSp dst, iReg$1 src, immI rshift, imm$1_bitmask mask)
+`instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
 %{
   match(Set dst (And$1 ($2$1 src rshift) mask));
 
@@ -215,7 +217,7 @@
 // Rotations
 
 define(`EXTRACT_INSN',
-`instruct extr$3$1(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, immI lshift, immI rshift, rFlagsReg cr)
+`instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
 %{
   match(Set dst ($3$1 (LShift$1 src1 lshift) (URShift$1 src2 rshift)));
   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & $2));
@@ -299,7 +301,7 @@
 // Add/subtract (extended)
 dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
 define(`ADD_SUB_CONV', `
-instruct $3Ext$1(iReg$2NoSp dst, iReg$2 src1, iReg$1orL2I src2, rFlagsReg cr)
+instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2, rFlagsReg cr)
 %{
   match(Set dst ($3$2 src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
@@ -315,7 +317,7 @@
 ADD_SUB_CONV(I,L,Sub,sub,sxtw);
 dnl
 define(`ADD_SUB_EXTENDED', `
-instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr)
+instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr)
 %{
   match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
   ins_cost(INSN_COST);
@@ -337,7 +339,7 @@
 dnl
 dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, shift type)
 define(`ADD_SUB_ZERO_EXTEND', `
-instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, imm$1_$2 mask, rFlagsReg cr)
+instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, rFlagsReg cr)
 %{
   match(Set dst ($3$1 src1 (And$1 src2 mask)));
   ins_cost(INSN_COST);