diff -r 6845bb645be5 -r 2f5e556a6037 hotspot/src/cpu/arm/vm/macroAssembler_arm.hpp
--- a/hotspot/src/cpu/arm/vm/macroAssembler_arm.hpp	Wed Feb 15 17:26:37 2017 -0800
+++ b/hotspot/src/cpu/arm/vm/macroAssembler_arm.hpp	Wed Feb 15 22:19:13 2017 -0500
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -402,6 +402,29 @@
   void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
                                      Register tmp, Label& slow_case, int* counter_addr);
 
+  void resolve_jobject(Register value, Register tmp1, Register tmp2);
+
+#if INCLUDE_ALL_GCS
+  // G1 pre-barrier.
+  // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
+  // If store_addr != noreg, then previous value is loaded from [store_addr];
+  // in such case store_addr and new_val registers are preserved;
+  // otherwise pre_val register is preserved.
+  void g1_write_barrier_pre(Register store_addr,
+                            Register new_val,
+                            Register pre_val,
+                            Register tmp1,
+                            Register tmp2);
+
+  // G1 post-barrier.
+  // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
+  void g1_write_barrier_post(Register store_addr,
+                             Register new_val,
+                             Register tmp1,
+                             Register tmp2,
+                             Register tmp3);
+#endif // INCLUDE_ALL_GCS
+
 #ifndef AARCH64
   void nop() {
     mov(R0, R0);