src/hotspot/os_cpu/solaris_x86/orderAccess_solaris_x86.hpp
author erikj
Fri, 05 Oct 2018 09:59:30 -0700
branchihse-runtestprebuilt-branch
changeset 56931 aff106ae3507
parent 50429 83aec1d357d4
child 53244 9807daeb47c4
permissions -rw-r--r--
Fix CDS support. Change ParseKeywordVariable parameter name to enable JTREG_KEYWORDS parameter. Fix test list arg.

/*
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 * accompanied this code).
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#ifndef OS_CPU_SOLARIS_X86_VM_ORDERACCESS_SOLARIS_X86_HPP
#define OS_CPU_SOLARIS_X86_VM_ORDERACCESS_SOLARIS_X86_HPP

// Included in orderAccess.hpp header file.

// Compiler version last used for testing: solaris studio 12u3
// Please update this information when this file changes

// Implementation of class OrderAccess.

// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
inline void compiler_barrier() {
  __asm__ volatile ("" : : : "memory");
}

inline void OrderAccess::loadload()   { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore()  { compiler_barrier(); }
inline void OrderAccess::storeload()  { fence();            }

inline void OrderAccess::acquire()    { compiler_barrier(); }
inline void OrderAccess::release()    { compiler_barrier(); }

inline void OrderAccess::fence() {
#ifdef AMD64
  __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
#else
  __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
#endif
  compiler_barrier();
}

#endif // OS_CPU_SOLARIS_X86_VM_ORDERACCESS_SOLARIS_X86_HPP