8143925: Enhancing CounterMode.crypt() for AES
Summary: Add intrinsic for CounterMode.crypt() to leverage the parallel nature of AES in Counter(CTR) Mode.
Reviewed-by: kvn, ascarpino
Contributed-by: kishor.kharbas@intel.com
/*
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#ifndef CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
#define CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
#include "runtime/globals_extension.hpp"
#include "runtime/vm_version.hpp"
class VM_Version : public Abstract_VM_Version {
friend class JVMCIVMStructs;
protected:
static int _cpu;
static int _model;
static int _model2;
static int _variant;
static int _revision;
static int _stepping;
static void get_processor_features();
public:
// Initialization
static void initialize();
// Asserts
static void assert_is_initialized() {
}
enum Family {
CPU_ARM = 'A',
CPU_BROADCOM = 'B',
CPU_CAVIUM = 'C',
CPU_DEC = 'D',
CPU_INFINEON = 'I',
CPU_MOTOROLA = 'M',
CPU_NVIDIA = 'N',
CPU_AMCC = 'P',
CPU_QUALCOM = 'Q',
CPU_MARVELL = 'V',
CPU_INTEL = 'i',
};
enum Feature_Flag {
CPU_FP = (1<<0),
CPU_ASIMD = (1<<1),
CPU_EVTSTRM = (1<<2),
CPU_AES = (1<<3),
CPU_PMULL = (1<<4),
CPU_SHA1 = (1<<5),
CPU_SHA2 = (1<<6),
CPU_CRC32 = (1<<7),
CPU_A53MAC = (1 << 30),
CPU_DMB_ATOMICS = (1 << 31),
};
static int cpu_family() { return _cpu; }
static int cpu_model() { return _model; }
static int cpu_model2() { return _model2; }
static int cpu_variant() { return _variant; }
static int cpu_revision() { return _revision; }
};
#endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP