src/hotspot/cpu/arm/c1_LinearScan_arm.hpp
author coleenp
Wed, 06 Jun 2018 10:45:40 -0400
changeset 50429 83aec1d357d4
parent 47216 71c04702a3d5
child 52351 0ecb4e520110
permissions -rw-r--r--
8204301: Make OrderAccess functions available to hpp rather than inline.hpp files Summary: move orderAccess.inline.hpp into orderAccess.hpp and remove os.hpp inclusion and conditional os::is_MP() for fence on x86 platforms Reviewed-by: dholmes, hseigel

/*
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
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 * 2 along with this work; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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#ifndef CPU_ARM_VM_C1_LINEARSCAN_ARM_HPP
#define CPU_ARM_VM_C1_LINEARSCAN_ARM_HPP

inline bool LinearScan::is_processed_reg_num(int reg_num) {
  return reg_num < pd_nof_cpu_regs_processed_in_linearscan ||
         reg_num >= pd_nof_cpu_regs_frame_map;
}

inline int LinearScan::num_physical_regs(BasicType type) {
#ifndef AARCH64
  if (type == T_LONG || type == T_DOUBLE) return 2;
#endif // !AARCH64
  return 1;
}


inline bool LinearScan::requires_adjacent_regs(BasicType type) {
#ifdef AARCH64
  return false;
#else
  return type == T_DOUBLE || type == T_LONG;
#endif // AARCH64
}

inline bool LinearScan::is_caller_save(int assigned_reg) {
  assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
  // TODO-AARCH64 try to add callee-saved registers
  return true;
}


inline void LinearScan::pd_add_temps(LIR_Op* op) {
  // No extra temporals on ARM
}


// Implementation of LinearScanWalker

inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
#ifndef __SOFTFP__
  if (cur->type() == T_FLOAT || cur->type() == T_DOUBLE) {
    _first_reg = pd_first_fpu_reg;
    _last_reg = pd_first_fpu_reg + pd_nof_fpu_regs_reg_alloc - 1;
    return true;
  }
#endif // !__SOFTFP__

  // Use allocatable CPU registers otherwise
  _first_reg = pd_first_cpu_reg;
  _last_reg = pd_first_cpu_reg + FrameMap::adjust_reg_range(pd_nof_cpu_regs_reg_alloc) - 1;
  return true;
}

#endif // CPU_ARM_VM_C1_LINEARSCAN_ARM_HPP