--- a/hotspot/src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp Tue Dec 10 14:29:43 2013 +0100
+++ b/hotspot/src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp Wed Dec 11 00:06:11 2013 +0100
@@ -58,35 +58,35 @@
- sync two-way memory barrier, aka fence
- lwsync orders Store|Store,
- Load|Store,
- Load|Load,
- but not Store|Load
+ Load|Store,
+ Load|Load,
+ but not Store|Load
- eieio orders memory accesses for device memory (only)
- isync invalidates speculatively executed instructions
- From the POWER ISA 2.06 documentation:
- "[...] an isync instruction prevents the execution of
- instructions following the isync until instructions
- preceding the isync have completed, [...]"
- From IBM's AIX assembler reference:
- "The isync [...] instructions causes the processor to
- refetch any instructions that might have been fetched
- prior to the isync instruction. The instruction isync
- causes the processor to wait for all previous instructions
- to complete. Then any instructions already fetched are
- discarded and instruction processing continues in the
- environment established by the previous instructions."
+ From the POWER ISA 2.06 documentation:
+ "[...] an isync instruction prevents the execution of
+ instructions following the isync until instructions
+ preceding the isync have completed, [...]"
+ From IBM's AIX assembler reference:
+ "The isync [...] instructions causes the processor to
+ refetch any instructions that might have been fetched
+ prior to the isync instruction. The instruction isync
+ causes the processor to wait for all previous instructions
+ to complete. Then any instructions already fetched are
+ discarded and instruction processing continues in the
+ environment established by the previous instructions."
semantic barrier instructions:
(as defined in orderAccess.hpp)
- release orders Store|Store, (maps to lwsync)
- Load|Store
+ Load|Store
- acquire orders Load|Store, (maps to lwsync)
- Load|Load
+ Load|Load
- fence orders Store|Store, (maps to sync)
- Load|Store,
- Load|Load,
- Store|Load
+ Load|Store,
+ Load|Load,
+ Store|Load
*/
#define strasm_sync "\n sync \n"