--- a/hotspot/src/cpu/x86/vm/x86_32.ad	Thu Jul 03 11:01:32 2008 -0700
+++ b/hotspot/src/cpu/x86/vm/x86_32.ad	Fri Jul 11 01:14:44 2008 -0700
@@ -4754,6 +4754,33 @@
   interface(CONST_INTER);
 %}
 
+operand immI_1() %{
+  predicate( n->get_int() == 1 );
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+operand immI_2() %{
+  predicate( n->get_int() == 2 );
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
+operand immI_3() %{
+  predicate( n->get_int() == 3 );
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 // Pointer Immediate
 operand immP() %{
   match(ConP);
@@ -8943,6 +8970,63 @@
   ins_pipe( ialu_reg_long_mem );
 %}
 
+// Shift Left Long by 1
+instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
+  predicate(UseNewLongLShift);
+  match(Set dst (LShiftL dst cnt));
+  effect(KILL cr);
+  ins_cost(100);
+  format %{ "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi" %}
+  ins_encode %{
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+  %}
+  ins_pipe( ialu_reg_long );
+%}
+
+// Shift Left Long by 2
+instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
+  predicate(UseNewLongLShift);
+  match(Set dst (LShiftL dst cnt));
+  effect(KILL cr);
+  ins_cost(100);
+  format %{ "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi\n\t" 
+            "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi" %}
+  ins_encode %{
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+  %}
+  ins_pipe( ialu_reg_long );
+%}
+
+// Shift Left Long by 3
+instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
+  predicate(UseNewLongLShift);
+  match(Set dst (LShiftL dst cnt));
+  effect(KILL cr);
+  ins_cost(100);
+  format %{ "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi\n\t" 
+            "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi\n\t" 
+            "ADD    $dst.lo,$dst.lo\n\t"
+            "ADC    $dst.hi,$dst.hi" %}
+  ins_encode %{
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+    __ addl($dst$$Register,$dst$$Register);
+    __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
+  %}
+  ins_pipe( ialu_reg_long );
+%}
+
 // Shift Left Long by 1-31
 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
   match(Set dst (LShiftL dst cnt));