--- a/src/hotspot/cpu/x86/vm_version_x86.cpp Thu Apr 11 12:06:58 2019 -0700
+++ b/src/hotspot/cpu/x86/vm_version_x86.cpp Thu Apr 11 19:36:00 2019 -0400
@@ -680,7 +680,7 @@
_features &= ~CPU_HT;
}
- if( is_intel() ) { // Intel cpus specific settings
+ if (is_intel()) { // Intel cpus specific settings
if (is_knights_family()) {
_features &= ~CPU_VZEROUPPER;
}
@@ -781,7 +781,7 @@
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
}
} else {
- if(supports_sse4_1()) {
+ if (supports_sse4_1()) {
if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
}
@@ -1001,7 +1001,7 @@
} else if (UseAVX == 1 || UseAVX == 2) {
// 32 bytes vectors (in YMM) are only supported with AVX+
max_vector_size = 32;
- } else if (UseAVX > 2 ) {
+ } else if (UseAVX > 2) {
// 64 bytes vectors (in ZMM) are only supported with AVX 3
max_vector_size = 64;
}
@@ -1165,38 +1165,38 @@
}
}
- if( is_amd() ) { // AMD cpus specific settings
- if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
+ if (is_amd_family()) { // AMD cpus specific settings
+ if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
// Use it on new AMD cpus starting from Opteron.
UseAddressNop = true;
}
- if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
+ if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
// Use it on new AMD cpus starting from Opteron.
UseNewLongLShift = true;
}
- if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
+ if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
if (supports_sse4a()) {
UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
} else {
UseXmmLoadAndClearUpper = false;
}
}
- if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
- if( supports_sse4a() ) {
+ if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
+ if (supports_sse4a()) {
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
} else {
UseXmmRegToRegMoveAll = false;
}
}
- if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
- if( supports_sse4a() ) {
+ if (FLAG_IS_DEFAULT(UseXmmI2F)) {
+ if (supports_sse4a()) {
UseXmmI2F = true;
} else {
UseXmmI2F = false;
}
}
- if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
- if( supports_sse4a() ) {
+ if (FLAG_IS_DEFAULT(UseXmmI2D)) {
+ if (supports_sse4a()) {
UseXmmI2D = true;
} else {
UseXmmI2D = false;
@@ -1214,7 +1214,7 @@
}
// some defaults for AMD family 15h
- if ( cpu_family() == 0x15 ) {
+ if (cpu_family() == 0x15) {
// On family 15h processors default is no sw prefetch
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
@@ -1239,8 +1239,8 @@
}
#endif // COMPILER2
- // Some defaults for AMD family 17h
- if ( cpu_family() == 0x17 ) {
+ // Some defaults for AMD family 17h || Hygon family 18h
+ if (cpu_family() == 0x17 || cpu_family() == 0x18) {
// On family 17h processors use XMM and UnalignedLoadStores for Array Copy
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
@@ -1256,29 +1256,29 @@
}
}
- if( is_intel() ) { // Intel cpus specific settings
- if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
+ if (is_intel()) { // Intel cpus specific settings
+ if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
UseStoreImmI16 = false; // don't use it on Intel cpus
}
- if( cpu_family() == 6 || cpu_family() == 15 ) {
- if( FLAG_IS_DEFAULT(UseAddressNop) ) {
+ if (cpu_family() == 6 || cpu_family() == 15) {
+ if (FLAG_IS_DEFAULT(UseAddressNop)) {
// Use it on all Intel cpus starting from PentiumPro
UseAddressNop = true;
}
}
- if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
+ if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
}
- if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
- if( supports_sse3() ) {
+ if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
+ if (supports_sse3()) {
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
} else {
UseXmmRegToRegMoveAll = false;
}
}
- if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
+ if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
#ifdef COMPILER2
- if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
+ if (FLAG_IS_DEFAULT(MaxLoopPad)) {
// For new Intel cpus do the next optimization:
// don't align the beginning of a loop if there are enough instructions
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
@@ -1324,7 +1324,7 @@
FLAG_SET_DEFAULT(UseIncDec, false);
}
}
- if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
+ if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
}
}