--- a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java Thu Oct 17 20:27:44 2019 +0100
+++ b/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java Thu Oct 17 20:53:35 2019 +0100
@@ -25,6 +25,11 @@
package org.graalvm.compiler.asm.aarch64;
+import static jdk.vm.ci.aarch64.AArch64.CPU;
+import static jdk.vm.ci.aarch64.AArch64.rscratch1;
+import static jdk.vm.ci.aarch64.AArch64.rscratch2;
+import static jdk.vm.ci.aarch64.AArch64.sp;
+import static jdk.vm.ci.aarch64.AArch64.zr;
import static org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode.BASE_REGISTER_ONLY;
import static org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode.EXTENDED_REGISTER_OFFSET;
import static org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode.IMMEDIATE_SCALED;
@@ -35,13 +40,6 @@
import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.NO_WORK;
import org.graalvm.compiler.asm.BranchTargetOutOfBoundsException;
-
-import static jdk.vm.ci.aarch64.AArch64.CPU;
-import static jdk.vm.ci.aarch64.AArch64.r8;
-import static jdk.vm.ci.aarch64.AArch64.r9;
-import static jdk.vm.ci.aarch64.AArch64.sp;
-import static jdk.vm.ci.aarch64.AArch64.zr;
-
import org.graalvm.compiler.asm.Label;
import org.graalvm.compiler.core.common.NumUtil;
import org.graalvm.compiler.debug.GraalError;
@@ -52,7 +50,7 @@
public class AArch64MacroAssembler extends AArch64Assembler {
- private final ScratchRegister[] scratchRegister = new ScratchRegister[]{new ScratchRegister(r8), new ScratchRegister(r9)};
+ private final ScratchRegister[] scratchRegister = new ScratchRegister[]{new ScratchRegister(rscratch1), new ScratchRegister(rscratch2)};
// Points to the next free scratch register
private int nextFreeScratchRegister = 0;
@@ -339,10 +337,13 @@
* Generates a 64-bit immediate move code sequence.
*
* @param dst general purpose register. May not be null, stackpointer or zero-register.
- * @param imm
+ * @param imm the value to move into the register
+ * @param annotateImm Flag denoting if annotation should be added.
*/
- private void mov64(Register dst, long imm) {
+ private void mov64(Register dst, long imm, boolean annotateImm) {
// We have to move all non zero parts of the immediate in 16-bit chunks
+ int numMovs = 0;
+ int pos = position();
boolean firstMove = true;
for (int offset = 0; offset < 64; offset += 16) {
int chunk = (int) (imm >> offset) & NumUtil.getNbitNumberInt(16);
@@ -355,8 +356,12 @@
} else {
movk(64, dst, chunk, offset);
}
+ ++numMovs;
}
assert !firstMove;
+ if (annotateImm) {
+ annotateImmediateMovSequence(pos, numMovs);
+ }
}
/**
@@ -378,7 +383,6 @@
*/
public void mov(Register dst, long imm, boolean annotateImm) {
assert dst.getRegisterCategory().equals(CPU);
- int pos = position();
if (imm == 0L) {
movx(dst, zr);
} else if (LogicalImmediateTable.isRepresentable(true, imm) != LogicalImmediateTable.Representable.NO) {
@@ -391,10 +395,7 @@
mov(dst, (int) imm);
sxt(64, 32, dst, dst);
} else {
- mov64(dst, imm);
- if (annotateImm) {
- annotatePatchingImmediateNativeAddress(pos, 64, 4);
- }
+ mov64(dst, imm, annotateImm);
}
}
@@ -448,7 +449,7 @@
}
}
if (annotateImm) {
- annotatePatchingImmediateNativeAddress(pos, 48, 3);
+ annotateImmediateMovSequence(pos, 3);
}
assert !firstMove;
}
@@ -1307,6 +1308,20 @@
super.fmsub(size, dst, dst, d, n);
}
+ /**
+ * dst = src1 * src2 + src3.
+ *
+ * @param size register size.
+ * @param dst floating point register. May not be null.
+ * @param src1 floating point register. May not be null.
+ * @param src2 floating point register. May not be null.
+ * @param src3 floating point register. May not be null.
+ */
+ @Override
+ public void fmadd(int size, Register dst, Register src1, Register src2, Register src3) {
+ super.fmadd(size, dst, src1, src2, src3);
+ }
+
/* Branches */
/**
@@ -1364,32 +1379,32 @@
case 64: {
// Be careful with registers: it's possible that x, y, and dst are the same
// register.
- Register rscratch1 = sc1.getRegister();
- Register rscratch2 = sc2.getRegister();
- mul(64, rscratch1, x, y); // Result bits 0..63
- smulh(64, rscratch2, x, y); // Result bits 64..127
+ Register temp1 = sc1.getRegister();
+ Register temp2 = sc2.getRegister();
+ mul(64, temp1, x, y); // Result bits 0..63
+ smulh(64, temp2, x, y); // Result bits 64..127
// Top is pure sign ext
- subs(64, zr, rscratch2, rscratch1, ShiftType.ASR, 63);
+ subs(64, zr, temp2, temp1, ShiftType.ASR, 63);
// Copy all 64 bits of the result into dst
- mov(64, dst, rscratch1);
- mov(rscratch1, 0x80000000);
+ mov(64, dst, temp1);
+ mov(temp1, 0x80000000);
// Develop 0 (EQ), or 0x80000000 (NE)
- cmov(32, rscratch1, rscratch1, zr, ConditionFlag.NE);
- cmp(32, rscratch1, 1);
+ cmov(32, temp1, temp1, zr, ConditionFlag.NE);
+ cmp(32, temp1, 1);
// 0x80000000 - 1 => VS
break;
}
case 32: {
- Register rscratch1 = sc1.getRegister();
- smaddl(rscratch1, x, y, zr);
+ Register temp1 = sc1.getRegister();
+ smaddl(temp1, x, y, zr);
// Copy the low 32 bits of the result into dst
- mov(32, dst, rscratch1);
- subs(64, zr, rscratch1, rscratch1, ExtendType.SXTW, 0);
+ mov(32, dst, temp1);
+ subs(64, zr, temp1, temp1, ExtendType.SXTW, 0);
// NE => overflow
- mov(rscratch1, 0x80000000);
+ mov(temp1, 0x80000000);
// Develop 0 (EQ), or 0x80000000 (NE)
- cmov(32, rscratch1, rscratch1, zr, ConditionFlag.NE);
- cmp(32, rscratch1, 1);
+ cmov(32, temp1, temp1, zr, ConditionFlag.NE);
+ cmp(32, temp1, 1);
// 0x80000000 - 1 => VS
break;
}
@@ -1703,6 +1718,9 @@
Register reg = AArch64.cpuRegisters.get(regEncoding);
// 1 => 64; 0 => 32
int size = sizeEncoding * 32 + 32;
+ if (!NumUtil.isSignedNbit(21, branchOffset)) {
+ throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
+ }
switch (type) {
case BRANCH_NONZERO:
super.cbnz(size, reg, branchOffset, branch);
@@ -1805,24 +1823,24 @@
}
/**
- * Emits elf patchable adrp add sequence.
+ * Emits elf patchable adrp ldr sequence.
*/
- public void adrAddRel(int srcSize, Register result, AArch64Address a) {
+ public void adrpLdr(int srcSize, Register result, AArch64Address a) {
if (codePatchingAnnotationConsumer != null) {
- codePatchingAnnotationConsumer.accept(new ADRADDPRELMacroInstruction(position()));
+ codePatchingAnnotationConsumer.accept(new AdrpLdrMacroInstruction(position()));
}
super.adrp(a.getBase());
this.ldr(srcSize, result, a);
}
- public static class ADRADDPRELMacroInstruction extends CodeAnnotation implements MacroInstruction {
- public ADRADDPRELMacroInstruction(int position) {
+ public static class AdrpLdrMacroInstruction extends CodeAnnotation implements MacroInstruction {
+ public AdrpLdrMacroInstruction(int position) {
super(position);
}
@Override
public String toString() {
- return "ADR_PREL_PG";
+ return "ADRP_LDR";
}
@Override