--- a/src/hotspot/cpu/x86/vm_version_x86.cpp Thu Oct 17 20:27:44 2019 +0100
+++ b/src/hotspot/cpu/x86/vm_version_x86.cpp Thu Oct 17 20:53:35 2019 +0100
@@ -35,6 +35,7 @@
#include "utilities/virtualizationSupport.hpp"
#include "vm_version_x86.hpp"
+#include OS_HEADER_INLINE(os)
int VM_Version::_cpu;
int VM_Version::_model;
@@ -380,6 +381,10 @@
__ cmpl(rax, 0xE0);
__ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
+ __ movl(rax, Address(rsi, 0));
+ __ cmpl(rax, 0x50654); // If it is Skylake
+ __ jcc(Assembler::equal, legacy_setup);
// If UseAVX is unitialized or is set by the user to include EVEX
if (use_evex) {
// EVEX setup: run in lowest evex mode
@@ -464,6 +469,11 @@
__ cmpl(rax, 0xE0);
__ jcc(Assembler::notEqual, legacy_save_restore);
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
+ __ movl(rax, Address(rsi, 0));
+ __ cmpl(rax, 0x50654); // If it is Skylake
+ __ jcc(Assembler::equal, legacy_save_restore);
+
// If UseAVX is unitialized or is set by the user to include EVEX
if (use_evex) {
// EVEX check: run in lowest evex mode
@@ -608,6 +618,16 @@
guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
#endif
+#ifdef _LP64
+ // assigning this field effectively enables Unsafe.writebackMemory()
+ // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
+ // that is only implemented on x86_64 and only if the OS plays ball
+ if (os::supports_map_sync()) {
+ // publish data cache line flush size to generic field, otherwise
+ // let if default to zero thereby disabling writeback
+ _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
+ }
+#endif
// If the OS doesn't support SSE, we can't use this feature even if the HW does
if (!os::supports_sse())
_features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
@@ -649,6 +669,9 @@
}
if (FLAG_IS_DEFAULT(UseAVX)) {
FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
+ if (is_intel_family_core() && _model == CPU_MODEL_SKYLAKE && _stepping < 5) {
+ FLAG_SET_DEFAULT(UseAVX, 2); //Set UseAVX=2 for Skylake
+ }
} else if (UseAVX > use_avx_limit) {
warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
@@ -1048,6 +1071,13 @@
}
#endif // COMPILER2 && ASSERT
+ if (!FLAG_IS_DEFAULT(AVX3Threshold)) {
+ if (!is_power_of_2(AVX3Threshold)) {
+ warning("AVX3Threshold must be a power of 2");
+ FLAG_SET_DEFAULT(AVX3Threshold, 4096);
+ }
+ }
+
#ifdef _LP64
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
UseMultiplyToLenIntrinsic = true;