--- a/src/hotspot/cpu/aarch64/aarch64.ad Thu Oct 17 20:27:44 2019 +0100
+++ b/src/hotspot/cpu/aarch64/aarch64.ad Thu Oct 17 20:53:35 2019 +0100
@@ -957,6 +957,146 @@
V3, V3_H
);
+// Class for 128 bit register v4
+reg_class v4_reg(
+ V4, V4_H
+);
+
+// Class for 128 bit register v5
+reg_class v5_reg(
+ V5, V5_H
+);
+
+// Class for 128 bit register v6
+reg_class v6_reg(
+ V6, V6_H
+);
+
+// Class for 128 bit register v7
+reg_class v7_reg(
+ V7, V7_H
+);
+
+// Class for 128 bit register v8
+reg_class v8_reg(
+ V8, V8_H
+);
+
+// Class for 128 bit register v9
+reg_class v9_reg(
+ V9, V9_H
+);
+
+// Class for 128 bit register v10
+reg_class v10_reg(
+ V10, V10_H
+);
+
+// Class for 128 bit register v11
+reg_class v11_reg(
+ V11, V11_H
+);
+
+// Class for 128 bit register v12
+reg_class v12_reg(
+ V12, V12_H
+);
+
+// Class for 128 bit register v13
+reg_class v13_reg(
+ V13, V13_H
+);
+
+// Class for 128 bit register v14
+reg_class v14_reg(
+ V14, V14_H
+);
+
+// Class for 128 bit register v15
+reg_class v15_reg(
+ V15, V15_H
+);
+
+// Class for 128 bit register v16
+reg_class v16_reg(
+ V16, V16_H
+);
+
+// Class for 128 bit register v17
+reg_class v17_reg(
+ V17, V17_H
+);
+
+// Class for 128 bit register v18
+reg_class v18_reg(
+ V18, V18_H
+);
+
+// Class for 128 bit register v19
+reg_class v19_reg(
+ V19, V19_H
+);
+
+// Class for 128 bit register v20
+reg_class v20_reg(
+ V20, V20_H
+);
+
+// Class for 128 bit register v21
+reg_class v21_reg(
+ V21, V21_H
+);
+
+// Class for 128 bit register v22
+reg_class v22_reg(
+ V22, V22_H
+);
+
+// Class for 128 bit register v23
+reg_class v23_reg(
+ V23, V23_H
+);
+
+// Class for 128 bit register v24
+reg_class v24_reg(
+ V24, V24_H
+);
+
+// Class for 128 bit register v25
+reg_class v25_reg(
+ V25, V25_H
+);
+
+// Class for 128 bit register v26
+reg_class v26_reg(
+ V26, V26_H
+);
+
+// Class for 128 bit register v27
+reg_class v27_reg(
+ V27, V27_H
+);
+
+// Class for 128 bit register v28
+reg_class v28_reg(
+ V28, V28_H
+);
+
+// Class for 128 bit register v29
+reg_class v29_reg(
+ V29, V29_H
+);
+
+// Class for 128 bit register v30
+reg_class v30_reg(
+ V30, V30_H
+);
+
+// Class for 128 bit register v31
+reg_class v31_reg(
+ V31, V31_H
+);
+
// Singleton class for condition codes
reg_class int_flags(RFLAGS);
@@ -1502,7 +1642,7 @@
// adr(rscratch2, retaddr)
// lea(rscratch1, RuntimeAddress(addr)
// stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)))
- // blrt rscratch1
+ // blr(rscratch1)
CodeBlob *cb = CodeCache::find_blob(_entry_point);
if (cb) {
return MacroAssembler::far_branch_size();
@@ -1621,16 +1761,23 @@
// branch if we need to invalidate the method later
__ nop();
+ if (C->clinit_barrier_on_entry()) {
+ assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
+
+ Label L_skip_barrier;
+
+ __ mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
+ __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
+ __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
+ __ bind(L_skip_barrier);
+ }
+
int bangsize = C->bang_size_in_bytes();
if (C->need_stack_bang(bangsize) && UseStackBanging)
__ generate_stack_overflow_check(bangsize);
__ build_frame(framesize);
- if (NotifySimulator) {
- __ notify(Assembler::method_entry);
- }
-
if (VerifyStackAtCalls) {
Unimplemented();
}
@@ -1691,10 +1838,6 @@
__ remove_frame(framesize);
- if (NotifySimulator) {
- __ notify(Assembler::method_reentry);
- }
-
if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
__ reserved_stack_check();
}
@@ -2042,17 +2185,21 @@
//=============================================================================
const bool Matcher::match_rule_supported(int opcode) {
-
+ if (!has_match_rule(opcode))
+ return false;
+
+ bool ret_value = true;
switch (opcode) {
- default:
- break;
+ case Op_CacheWB:
+ case Op_CacheWBPreSync:
+ case Op_CacheWBPostSync:
+ if (!VM_Version::supports_data_cache_line_flush()) {
+ ret_value = false;
+ }
+ break;
}
- if (!has_match_rule(opcode)) {
- return false;
- }
-
- return true; // Per default match rules are supported.
+ return ret_value; // Per default match rules are supported.
}
const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
@@ -2356,47 +2503,6 @@
void Compile::reshape_address(AddPNode* addp) {
}
-// helper for encoding java_to_runtime calls on sim
-//
-// this is needed to compute the extra arguments required when
-// planting a call to the simulator blrt instruction. the TypeFunc
-// can be queried to identify the counts for integral, and floating
-// arguments and the return type
-
-static void getCallInfo(const TypeFunc *tf, int &gpcnt, int &fpcnt, int &rtype)
-{
- int gps = 0;
- int fps = 0;
- const TypeTuple *domain = tf->domain();
- int max = domain->cnt();
- for (int i = TypeFunc::Parms; i < max; i++) {
- const Type *t = domain->field_at(i);
- switch(t->basic_type()) {
- case T_FLOAT:
- case T_DOUBLE:
- fps++;
- default:
- gps++;
- }
- }
- gpcnt = gps;
- fpcnt = fps;
- BasicType rt = tf->return_type();
- switch (rt) {
- case T_VOID:
- rtype = MacroAssembler::ret_type_void;
- break;
- default:
- rtype = MacroAssembler::ret_type_integral;
- break;
- case T_FLOAT:
- rtype = MacroAssembler::ret_type_float;
- break;
- case T_DOUBLE:
- rtype = MacroAssembler::ret_type_double;
- break;
- }
-}
#define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
MacroAssembler _masm(&cbuf); \
@@ -2407,17 +2513,8 @@
__ INSN(REG, as_Register(BASE)); \
}
-typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
-typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
-typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt,
- MacroAssembler::SIMD_RegVariant T, const Address &adr);
-
- // Used for all non-volatile memory accesses. The use of
- // $mem->opcode() to discover whether this pattern uses sign-extended
- // offsets is something of a kludge.
- static void loadStore(MacroAssembler masm, mem_insn insn,
- Register reg, int opcode,
- Register base, int index, int size, int disp)
+
+static Address mem2address(int opcode, Register base, int index, int size, int disp)
{
Address::extend scale;
@@ -2436,16 +2533,34 @@
}
if (index == -1) {
- (masm.*insn)(reg, Address(base, disp));
+ return Address(base, disp);
} else {
assert(disp == 0, "unsupported address mode: disp = %d", disp);
- (masm.*insn)(reg, Address(base, as_Register(index), scale));
+ return Address(base, as_Register(index), scale);
}
}
+
+typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
+typedef void (MacroAssembler::* mem_insn2)(Register Rt, Register adr);
+typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
+typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt,
+ MacroAssembler::SIMD_RegVariant T, const Address &adr);
+
+ // Used for all non-volatile memory accesses. The use of
+ // $mem->opcode() to discover whether this pattern uses sign-extended
+ // offsets is something of a kludge.
+ static void loadStore(MacroAssembler masm, mem_insn insn,
+ Register reg, int opcode,
+ Register base, int index, int size, int disp)
+ {
+ Address addr = mem2address(opcode, base, index, size, disp);
+ (masm.*insn)(reg, addr);
+ }
+
static void loadStore(MacroAssembler masm, mem_float_insn insn,
- FloatRegister reg, int opcode,
- Register base, int index, int size, int disp)
+ FloatRegister reg, int opcode,
+ Register base, int index, int size, int disp)
{
Address::extend scale;
@@ -2467,8 +2582,8 @@
}
static void loadStore(MacroAssembler masm, mem_vector_insn insn,
- FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
- int opcode, Register base, int index, int size, int disp)
+ FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
+ int opcode, Register base, int index, int size, int disp)
{
if (index == -1) {
(masm.*insn)(reg, T, Address(base, disp));
@@ -3346,7 +3461,7 @@
// some calls to generated routines (arraycopy code) are scheduled
// by C2 as runtime calls. if so we can call them using a br (they
- // will be in a reachable segment) otherwise we have to use a blrt
+ // will be in a reachable segment) otherwise we have to use a blr
// which loads the absolute address into a register.
address entry = (address)$meth$$method;
CodeBlob *cb = CodeCache::find_blob(entry);
@@ -3357,16 +3472,12 @@
return;
}
} else {
- int gpcnt;
- int fpcnt;
- int rtype;
- getCallInfo(tf(), gpcnt, fpcnt, rtype);
Label retaddr;
__ adr(rscratch2, retaddr);
__ lea(rscratch1, RuntimeAddress(entry));
// Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
__ stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)));
- __ blrt(rscratch1, gpcnt, fpcnt, rtype);
+ __ blr(rscratch1);
__ bind(retaddr);
__ add(sp, sp, 2 * wordSize);
}
@@ -3410,7 +3521,7 @@
assert_different_registers(oop, box, tmp, disp_hdr);
- // Load markOop from object into displaced_header.
+ // Load markWord from object into displaced_header.
__ ldr(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
if (UseBiasedLocking && !UseOptoBiasInlining) {
@@ -3418,17 +3529,17 @@
}
// Check for existing monitor
- __ tbnz(disp_hdr, exact_log2(markOopDesc::monitor_value), object_has_monitor);
-
- // Set tmp to be (markOop of object | UNLOCK_VALUE).
- __ orr(tmp, disp_hdr, markOopDesc::unlocked_value);
+ __ tbnz(disp_hdr, exact_log2(markWord::monitor_value), object_has_monitor);
+
+ // Set tmp to be (markWord of object | UNLOCK_VALUE).
+ __ orr(tmp, disp_hdr, markWord::unlocked_value);
// Initialize the box. (Must happen before we update the object mark!)
__ str(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
- // Compare object markOop with an unlocked value (tmp) and if
- // equal exchange the stack address of our box with object markOop.
- // On failure disp_hdr contains the possibly locked markOop.
+ // Compare object markWord with an unlocked value (tmp) and if
+ // equal exchange the stack address of our box with object markWord.
+ // On failure disp_hdr contains the possibly locked markWord.
__ cmpxchg(oop, tmp, box, Assembler::xword, /*acquire*/ true,
/*release*/ true, /*weak*/ false, disp_hdr);
__ br(Assembler::EQ, cont);
@@ -3442,10 +3553,10 @@
// We did not see an unlocked object so try the fast recursive case.
// Check if the owner is self by comparing the value in the
- // markOop of object (disp_hdr) with the stack pointer.
+ // markWord of object (disp_hdr) with the stack pointer.
__ mov(rscratch1, sp);
__ sub(disp_hdr, disp_hdr, rscratch1);
- __ mov(tmp, (address) (~(os::vm_page_size()-1) | (uintptr_t)markOopDesc::lock_mask_in_place));
+ __ mov(tmp, (address) (~(os::vm_page_size()-1) | markWord::lock_mask_in_place));
// If condition is true we are cont and hence we can store 0 as the
// displaced header in the box, which indicates that it is a recursive lock.
__ ands(tmp/*==0?*/, disp_hdr, tmp); // Sets flags for result
@@ -3460,15 +3571,15 @@
// otherwise m->owner may contain a thread or a stack address.
//
// Try to CAS m->owner from NULL to current thread.
- __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value));
+ __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes()-markWord::monitor_value));
__ cmpxchg(tmp, zr, rthread, Assembler::xword, /*acquire*/ true,
/*release*/ true, /*weak*/ false, noreg); // Sets flags for result
// Store a non-null value into the box to avoid looking like a re-entrant
// lock. The fast-path monitor unlock code checks for
- // markOopDesc::monitor_value so use markOopDesc::unused_mark which has the
- // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
- __ mov(tmp, (address)markOopDesc::unused_mark());
+ // markWord::monitor_value so use markWord::unused_mark which has the
+ // relevant bit set, and also matches ObjectSynchronizer::enter.
+ __ mov(tmp, (address)markWord::unused_mark().value());
__ str(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
__ bind(cont);
@@ -3500,10 +3611,10 @@
// Handle existing monitor.
__ ldr(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
- __ tbnz(disp_hdr, exact_log2(markOopDesc::monitor_value), object_has_monitor);
+ __ tbnz(disp_hdr, exact_log2(markWord::monitor_value), object_has_monitor);
// Check if it is still a light weight lock, this is is true if we
- // see the stack address of the basicLock in the markOop of the
+ // see the stack address of the basicLock in the markWord of the
// object.
__ cmpxchg(oop, box, disp_hdr, Assembler::xword, /*acquire*/ false,
@@ -3514,7 +3625,8 @@
// Handle existing monitor.
__ bind(object_has_monitor);
- __ add(tmp, tmp, -markOopDesc::monitor_value); // monitor
+ STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
+ __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
__ ldr(rscratch1, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
__ ldr(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
__ eor(rscratch1, rscratch1, rthread); // Will be 0 if we are the owner.
@@ -3688,7 +3800,7 @@
static const int hi[Op_RegL + 1] = { // enum name
0, // Op_Node
0, // Op_Set
- OptoReg::Bad, // Op_RegN
+ OptoReg::Bad, // Op_RegN
OptoReg::Bad, // Op_RegI
R0_H_num, // Op_RegP
OptoReg::Bad, // Op_RegF
@@ -4774,6 +4886,258 @@
interface(REG_INTER);
%}
+operand vRegD_V4()
+%{
+ constraint(ALLOC_IN_RC(v4_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V5()
+%{
+ constraint(ALLOC_IN_RC(v5_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V6()
+%{
+ constraint(ALLOC_IN_RC(v6_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V7()
+%{
+ constraint(ALLOC_IN_RC(v7_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V8()
+%{
+ constraint(ALLOC_IN_RC(v8_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V9()
+%{
+ constraint(ALLOC_IN_RC(v9_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V10()
+%{
+ constraint(ALLOC_IN_RC(v10_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V11()
+%{
+ constraint(ALLOC_IN_RC(v11_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V12()
+%{
+ constraint(ALLOC_IN_RC(v12_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V13()
+%{
+ constraint(ALLOC_IN_RC(v13_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V14()
+%{
+ constraint(ALLOC_IN_RC(v14_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V15()
+%{
+ constraint(ALLOC_IN_RC(v15_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V16()
+%{
+ constraint(ALLOC_IN_RC(v16_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V17()
+%{
+ constraint(ALLOC_IN_RC(v17_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V18()
+%{
+ constraint(ALLOC_IN_RC(v18_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V19()
+%{
+ constraint(ALLOC_IN_RC(v19_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V20()
+%{
+ constraint(ALLOC_IN_RC(v20_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V21()
+%{
+ constraint(ALLOC_IN_RC(v21_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V22()
+%{
+ constraint(ALLOC_IN_RC(v22_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V23()
+%{
+ constraint(ALLOC_IN_RC(v23_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V24()
+%{
+ constraint(ALLOC_IN_RC(v24_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V25()
+%{
+ constraint(ALLOC_IN_RC(v25_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V26()
+%{
+ constraint(ALLOC_IN_RC(v26_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V27()
+%{
+ constraint(ALLOC_IN_RC(v27_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V28()
+%{
+ constraint(ALLOC_IN_RC(v28_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V29()
+%{
+ constraint(ALLOC_IN_RC(v29_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V30()
+%{
+ constraint(ALLOC_IN_RC(v30_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
+operand vRegD_V31()
+%{
+ constraint(ALLOC_IN_RC(v31_reg));
+ match(RegD);
+ op_cost(0);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
// Flags register, used as output of signed compare instructions
// note that on AArch64 we also use this register as the output for
@@ -6568,7 +6932,7 @@
instruct loadP(iRegPNoSp dst, memory mem)
%{
match(Set dst (LoadP mem));
- predicate(!needs_acquiring_load(n));
+ predicate(!needs_acquiring_load(n) && (n->as_Load()->barrier_data() == 0));
ins_cost(4 * INSN_COST);
format %{ "ldr $dst, $mem\t# ptr" %}
@@ -7261,6 +7625,7 @@
instruct loadP_volatile(iRegPNoSp dst, /* sync_memory*/indirect mem)
%{
match(Set dst (LoadP mem));
+ predicate(n->as_Load()->barrier_data() == 0);
ins_cost(VOLATILE_REF_COST);
format %{ "ldar $dst, $mem\t# ptr" %}
@@ -7419,6 +7784,47 @@
// ---------------- end of volatile loads and stores ----------------
+instruct cacheWB(indirect addr)
+%{
+ predicate(VM_Version::supports_data_cache_line_flush());
+ match(CacheWB addr);
+
+ ins_cost(100);
+ format %{"cache wb $addr" %}
+ ins_encode %{
+ assert($addr->index_position() < 0, "should be");
+ assert($addr$$disp == 0, "should be");
+ __ cache_wb(Address($addr$$base$$Register, 0));
+ %}
+ ins_pipe(pipe_slow); // XXX
+%}
+
+instruct cacheWBPreSync()
+%{
+ predicate(VM_Version::supports_data_cache_line_flush());
+ match(CacheWBPreSync);
+
+ ins_cost(100);
+ format %{"cache wb presync" %}
+ ins_encode %{
+ __ cache_wbsync(true);
+ %}
+ ins_pipe(pipe_slow); // XXX
+%}
+
+instruct cacheWBPostSync()
+%{
+ predicate(VM_Version::supports_data_cache_line_flush());
+ match(CacheWBPostSync);
+
+ ins_cost(100);
+ format %{"cache wb postsync" %}
+ ins_encode %{
+ __ cache_wbsync(false);
+ %}
+ ins_pipe(pipe_slow); // XXX
+%}
+
// ============================================================================
// BSWAP Instructions
@@ -7958,6 +8364,17 @@
ins_pipe(pipe_class_empty);
%}
+instruct castLL(iRegL dst)
+%{
+ match(Set dst (CastLL dst));
+
+ size(0);
+ format %{ "# castLL of $dst" %}
+ ins_encode(/* empty encoding */);
+ ins_cost(0);
+ ins_pipe(pipe_class_empty);
+%}
+
// ============================================================================
// Atomic operation instructions
//
@@ -8145,6 +8562,7 @@
instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
+ predicate(n->as_LoadStore()->barrier_data() == 0);
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
@@ -8258,7 +8676,7 @@
instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
- predicate(needs_acquiring_load_exclusive(n));
+ predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
@@ -8389,6 +8807,7 @@
%}
instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
+ predicate(n->as_LoadStore()->barrier_data() == 0);
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
@@ -8488,7 +8907,7 @@
%}
instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
- predicate(needs_acquiring_load_exclusive(n));
+ predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
@@ -8589,6 +9008,7 @@
%}
instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
+ predicate(n->as_LoadStore()->barrier_data() == 0);
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
@@ -8696,8 +9116,8 @@
%}
instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
- predicate(needs_acquiring_load_exclusive(n));
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
+ predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
ins_cost(VOLATILE_REF_COST);
effect(KILL cr);
format %{
@@ -8747,6 +9167,7 @@
%}
instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
+ predicate(n->as_LoadStore()->barrier_data() == 0);
match(Set prev (GetAndSetP mem newv));
ins_cost(2 * VOLATILE_REF_COST);
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
@@ -8790,7 +9211,7 @@
%}
instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{
- predicate(needs_acquiring_load_exclusive(n));
+ predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
match(Set prev (GetAndSetP mem newv));
ins_cost(VOLATILE_REF_COST);
format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
@@ -13863,7 +14284,7 @@
format %{ "fcmps $src1, 0.0" %}
ins_encode %{
- __ fcmps(as_FloatRegister($src1$$reg), 0.0D);
+ __ fcmps(as_FloatRegister($src1$$reg), 0.0);
%}
ins_pipe(pipe_class_compare);
@@ -13892,7 +14313,7 @@
format %{ "fcmpd $src1, 0.0" %}
ins_encode %{
- __ fcmpd(as_FloatRegister($src1$$reg), 0.0D);
+ __ fcmpd(as_FloatRegister($src1$$reg), 0.0);
%}
ins_pipe(pipe_class_compare);
@@ -13968,7 +14389,7 @@
Label done;
FloatRegister s1 = as_FloatRegister($src1$$reg);
Register d = as_Register($dst$$reg);
- __ fcmps(s1, 0.0D);
+ __ fcmps(s1, 0.0);
// installs 0 if EQ else -1
__ csinvw(d, zr, zr, Assembler::EQ);
// keeps -1 if less or unordered else installs 1
@@ -13995,7 +14416,7 @@
Label done;
FloatRegister s1 = as_FloatRegister($src1$$reg);
Register d = as_Register($dst$$reg);
- __ fcmpd(s1, 0.0D);
+ __ fcmpd(s1, 0.0);
// installs 0 if EQ else -1
__ csinvw(d, zr, zr, Assembler::EQ);
// keeps -1 if less or unordered else installs 1
@@ -14551,9 +14972,10 @@
// TODO
// provide a near and far version of this code
-instruct safePoint(iRegP poll)
+instruct safePoint(rFlagsReg cr, iRegP poll)
%{
match(SafePoint poll);
+ effect(KILL cr);
format %{
"ldrw zr, [$poll]\t# Safepoint: poll for GC"