--- a/hotspot/src/cpu/sparc/vm/sparc.ad Tue Aug 16 11:53:57 2011 -0700
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad Tue Aug 16 16:59:46 2011 -0700
@@ -471,9 +471,6 @@
source %{
#define __ _masm.
-// Block initializing store
-#define ASI_BLK_INIT_QUAD_LDD_P 0xE2
-
// tertiary op of a LoadP or StoreP encoding
#define REGP_OP true
@@ -2819,10 +2816,10 @@
Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
Register base_pointer_arg = reg_to_register_object($base$$reg);
-
+
Label loop;
__ mov(nof_bytes_arg, nof_bytes_tmp);
-
+
// Loop and clear, walking backwards through the array.
// nof_bytes_tmp (if >0) is always the number of bytes to zero
__ bind(loop);
@@ -6269,6 +6266,7 @@
instruct prefetchr( memory mem ) %{
match( PrefetchRead mem );
ins_cost(MEMORY_REF_COST);
+ size(4);
format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
opcode(Assembler::prefetch_op3);
@@ -6277,9 +6275,9 @@
%}
instruct prefetchw( memory mem ) %{
- predicate(AllocatePrefetchStyle != 3 );
match( PrefetchWrite mem );
ins_cost(MEMORY_REF_COST);
+ size(4);
format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
opcode(Assembler::prefetch_op3);
@@ -6287,24 +6285,62 @@
ins_pipe(iload_mem);
%}
-// Use BIS instruction to prefetch.
-instruct prefetchw_bis( memory mem ) %{
- predicate(AllocatePrefetchStyle == 3);
- match( PrefetchWrite mem );
- ins_cost(MEMORY_REF_COST);
-
- format %{ "STXA G0,$mem\t! // Block initializing store" %}
- ins_encode %{
- Register base = as_Register($mem$$base);
- int disp = $mem$$disp;
- if (disp != 0) {
- __ add(base, AllocatePrefetchStepSize, base);
- }
- __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
+// Prefetch instructions for allocation.
+
+instruct prefetchAlloc( memory mem ) %{
+ predicate(AllocatePrefetchInstr == 0);
+ match( PrefetchAllocation mem );
+ ins_cost(MEMORY_REF_COST);
+ size(4);
+
+ format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
+ opcode(Assembler::prefetch_op3);
+ ins_encode( form3_mem_prefetch_write( mem ) );
+ ins_pipe(iload_mem);
+%}
+
+// Use BIS instruction to prefetch for allocation.
+// Could fault, need space at the end of TLAB.
+instruct prefetchAlloc_bis( iRegP dst ) %{
+ predicate(AllocatePrefetchInstr == 1);
+ match( PrefetchAllocation dst );
+ ins_cost(MEMORY_REF_COST);
+ size(4);
+
+ format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
+ ins_encode %{
+ __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
%}
ins_pipe(istore_mem_reg);
%}
+// Next code is used for finding next cache line address to prefetch.
+#ifndef _LP64
+instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
+ match(Set dst (CastX2P (AndI (CastP2X src) mask)));
+ ins_cost(DEFAULT_COST);
+ size(4);
+
+ format %{ "AND $src,$mask,$dst\t! next cache line address" %}
+ ins_encode %{
+ __ and3($src$$Register, $mask$$constant, $dst$$Register);
+ %}
+ ins_pipe(ialu_reg_imm);
+%}
+#else
+instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
+ match(Set dst (CastX2P (AndL (CastP2X src) mask)));
+ ins_cost(DEFAULT_COST);
+ size(4);
+
+ format %{ "AND $src,$mask,$dst\t! next cache line address" %}
+ ins_encode %{
+ __ and3($src$$Register, $mask$$constant, $dst$$Register);
+ %}
+ ins_pipe(ialu_reg_imm);
+%}
+#endif
+
//----------Store Instructions-------------------------------------------------
// Store Byte
instruct storeB(memory mem, iRegI src) %{