src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java
--- a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java Tue Mar 12 12:12:01 2019 -0700
+++ b/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java Tue Mar 12 19:17:42 2019 +0100
@@ -33,6 +33,9 @@
import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.ADD_TO_BASE;
import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.ADD_TO_INDEX;
import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.NO_WORK;
+
+import org.graalvm.compiler.asm.BranchTargetOutOfBoundsException;
+
import static jdk.vm.ci.aarch64.AArch64.CPU;
import static jdk.vm.ci.aarch64.AArch64.r8;
import static jdk.vm.ci.aarch64.AArch64.r9;
@@ -1452,7 +1455,7 @@
*
* @param cmp general purpose register. May not be null, zero-register or stackpointer.
* @param uimm6 Unsigned 6-bit bit index.
- * @param label Can only handle 21-bit word-aligned offsets for now. May be unbound. Non null.
+ * @param label Can only handle 16-bit word-aligned offsets for now. May be unbound. Non null.
*/
public void tbnz(Register cmp, int uimm6, Label label) {
assert NumUtil.isUnsignedNbit(6, uimm6);
@@ -1472,7 +1475,7 @@
*
* @param cmp general purpose register. May not be null, zero-register or stackpointer.
* @param uimm6 Unsigned 6-bit bit index.
- * @param label Can only handle 21-bit word-aligned offsets for now. May be unbound. Non null.
+ * @param label Can only handle 16-bit word-aligned offsets for now. May be unbound. Non null.
*/
public void tbz(Register cmp, int uimm6, Label label) {
assert NumUtil.isUnsignedNbit(6, uimm6);
@@ -1681,6 +1684,9 @@
int sizeEncoding = information & NumUtil.getNbitNumberInt(6);
int regEncoding = information >>> 6;
Register reg = AArch64.cpuRegisters.get(regEncoding);
+ if (!NumUtil.isSignedNbit(16, branchOffset)) {
+ throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
+ }
switch (type) {
case BRANCH_BIT_NONZERO:
super.tbnz(reg, sizeEncoding, branchOffset, branch);