hotspot/src/cpu/x86/vm/x86_64.ad
changeset 28954 7dda6c26cc98
parent 24018 77b156916bab
child 30194 bec4681af8cb
--- a/hotspot/src/cpu/x86/vm/x86_64.ad	Tue Feb 10 16:53:00 2015 +0000
+++ b/hotspot/src/cpu/x86/vm/x86_64.ad	Tue Feb 10 21:32:05 2015 +0100
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -5319,70 +5319,9 @@
   ins_pipe(pipe_slow); // XXX
 %}
 
-// Prefetch instructions.
+// Prefetch instructions for allocation.
 // Must be safe to execute with invalid address (cannot fault).
 
-instruct prefetchr( memory mem ) %{
-  predicate(ReadPrefetchInstr==3);
-  match(PrefetchRead mem);
-  ins_cost(125);
-
-  format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
-  ins_encode %{
-    __ prefetchr($mem$$Address);
-  %}
-  ins_pipe(ialu_mem);
-%}
-
-instruct prefetchrNTA( memory mem ) %{
-  predicate(ReadPrefetchInstr==0);
-  match(PrefetchRead mem);
-  ins_cost(125);
-
-  format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
-  ins_encode %{
-    __ prefetchnta($mem$$Address);
-  %}
-  ins_pipe(ialu_mem);
-%}
-
-instruct prefetchrT0( memory mem ) %{
-  predicate(ReadPrefetchInstr==1);
-  match(PrefetchRead mem);
-  ins_cost(125);
-
-  format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
-  ins_encode %{
-    __ prefetcht0($mem$$Address);
-  %}
-  ins_pipe(ialu_mem);
-%}
-
-instruct prefetchrT2( memory mem ) %{
-  predicate(ReadPrefetchInstr==2);
-  match(PrefetchRead mem);
-  ins_cost(125);
-
-  format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
-  ins_encode %{
-    __ prefetcht2($mem$$Address);
-  %}
-  ins_pipe(ialu_mem);
-%}
-
-instruct prefetchwNTA( memory mem ) %{
-  match(PrefetchWrite mem);
-  ins_cost(125);
-
-  format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
-  ins_encode %{
-    __ prefetchnta($mem$$Address);
-  %}
-  ins_pipe(ialu_mem);
-%}
-
-// Prefetch instructions for allocation.
-
 instruct prefetchAlloc( memory mem ) %{
   predicate(AllocatePrefetchInstr==3);
   match(PrefetchAllocation mem);