--- a/hotspot/src/cpu/x86/vm/assembler_x86.cpp Fri Oct 09 20:45:45 2015 +0000
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.cpp Thu Oct 15 13:28:22 2015 +0200
@@ -770,6 +770,7 @@
case 0x55: // andnps
case 0x56: // orps
case 0x57: // xorps
+ case 0x59: //mulpd
case 0x6E: // movd
case 0x7E: // movd
case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
@@ -3030,6 +3031,15 @@
emit_int8(imm8);
}
+void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
+ assert(VM_Version::supports_sse2(), "");
+ int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
+ VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
+ emit_int8(0x15);
+ emit_int8((unsigned char)(0xC0 | encode));
+ emit_int8(imm8);
+}
+
void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
assert(VM_Version::supports_sse4_1(), "");
int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
@@ -3048,6 +3058,15 @@
emit_int8(imm8);
}
+void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
+ assert(VM_Version::supports_sse2(), "");
+ int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
+ VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
+ emit_int8((unsigned char)0xC4);
+ emit_int8((unsigned char)(0xC0 | encode));
+ emit_int8(imm8);
+}
+
void Assembler::pmovzxbw(XMMRegister dst, Address src) {
assert(VM_Version::supports_sse4_1(), "");
if (VM_Version::supports_evex()) {
@@ -4063,6 +4082,16 @@
}
}
+void Assembler::mulpd(XMMRegister dst, Address src) {
+ _instruction_uses_vl = true;
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ if (VM_Version::supports_evex()) {
+ emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
+ } else {
+ emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
+ }
+}
+
void Assembler::mulps(XMMRegister dst, XMMRegister src) {
_instruction_uses_vl = true;
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
@@ -4251,6 +4280,26 @@
emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
}
+void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
+ _instruction_uses_vl = true;
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ if (VM_Version::supports_evex()) {
+ emit_simd_arith_q(0x15, dst, src, VEX_SIMD_66);
+ } else {
+ emit_simd_arith(0x15, dst, src, VEX_SIMD_66);
+ }
+}
+
+void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
+ _instruction_uses_vl = true;
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ if (VM_Version::supports_evex()) {
+ emit_simd_arith_q(0x14, dst, src, VEX_SIMD_66);
+ } else {
+ emit_simd_arith(0x14, dst, src, VEX_SIMD_66);
+ }
+}
+
void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
if (VM_Version::supports_avx512dq()) {
@@ -4871,8 +4920,9 @@
}
-// AND packed integers
+// logical operations packed integers
void Assembler::pand(XMMRegister dst, XMMRegister src) {
+ _instruction_uses_vl = true;
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
}
@@ -4893,6 +4943,17 @@
emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
}
+void Assembler::pandn(XMMRegister dst, XMMRegister src) {
+ _instruction_uses_vl = true;
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ if (VM_Version::supports_evex()) {
+ emit_simd_arith_q(0xDF, dst, src, VEX_SIMD_66);
+ }
+ else {
+ emit_simd_arith(0xDF, dst, src, VEX_SIMD_66);
+ }
+}
+
void Assembler::por(XMMRegister dst, XMMRegister src) {
_instruction_uses_vl = true;
NOT_LP64(assert(VM_Version::supports_sse2(), ""));