--- a/hotspot/src/cpu/x86/vm/icache_x86.hpp	Tue Nov 23 15:01:43 2010 -0500
+++ b/hotspot/src/cpu/x86/vm/icache_x86.hpp	Tue Nov 23 13:22:55 2010 -0800
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -22,6 +22,9 @@
  *
  */
 
+#ifndef CPU_X86_VM_ICACHE_X86_HPP
+#define CPU_X86_VM_ICACHE_X86_HPP
+
 // Interface for updating the instruction cache.  Whenever the VM modifies
 // code, part of the processor instruction cache potentially has to be flushed.
 
@@ -53,3 +56,5 @@
   };
 #endif // AMD64
 };
+
+#endif // CPU_X86_VM_ICACHE_X86_HPP