--- a/hotspot/src/share/vm/c1/c1_LinearScan.cpp	Wed Jul 28 17:57:43 2010 -0400
+++ b/hotspot/src/share/vm/c1/c1_LinearScan.cpp	Tue Aug 03 08:13:38 2010 -0400
@@ -169,7 +169,11 @@
 }
 
 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
+#if defined(__SOFTFP__) || defined(E500V2)
+  return i->reg_num() >= LIR_OprDesc::vreg_base;
+#else
   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
+#endif // __SOFTFP__ or E500V2
 }
 
 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
@@ -177,7 +181,11 @@
 }
 
 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
+#if defined(__SOFTFP__) || defined(E500V2)
+  return false;
+#else
   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
+#endif // __SOFTFP__ or E500V2
 }
 
 bool LinearScan::is_in_fpu_register(const Interval* i) {
@@ -2010,12 +2018,18 @@
         return LIR_OprFact::single_cpu_oop(assigned_reg);
       }
 
+#ifdef __SOFTFP__
+      case T_FLOAT:  // fall through
+#endif // __SOFTFP__
       case T_INT: {
         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
         return LIR_OprFact::single_cpu(assigned_reg);
       }
 
+#ifdef __SOFTFP__
+      case T_DOUBLE:  // fall through
+#endif // __SOFTFP__
       case T_LONG: {
         int assigned_regHi = interval->assigned_regHi();
         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
@@ -2033,7 +2047,7 @@
 #ifdef _LP64
         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
 #else
-#ifdef SPARC
+#if defined(SPARC) || defined(PPC)
         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
 #else
         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
@@ -2041,6 +2055,7 @@
 #endif // LP64
       }
 
+#ifndef __SOFTFP__
       case T_FLOAT: {
 #ifdef X86
         if (UseSSE >= 1) {
@@ -2069,6 +2084,11 @@
         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
+#elif defined(ARM)
+        assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
+        assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
+        assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
+        LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
 #else
         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
@@ -2076,6 +2096,7 @@
 #endif
         return result;
       }
+#endif // __SOFTFP__
 
       default: {
         ShouldNotReachHere();
@@ -2638,6 +2659,12 @@
 #ifdef SPARC
       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
 #endif
+#ifdef ARM
+      assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
+#endif
+#ifdef PPC
+      assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
+#endif
 
       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
 #ifdef _LP64
@@ -6135,6 +6162,17 @@
             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
 
+            LIR_Op2* prev_cmp = NULL;
+
+            for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
+              prev_op = instructions->at(j);
+              if(prev_op->code() == lir_cmp) {
+                assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
+                prev_cmp = (LIR_Op2*)prev_op;
+                assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
+              }
+            }
+            assert(prev_cmp != NULL, "should have found comp instruction for branch");
             if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
 
               TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
@@ -6142,6 +6180,7 @@
               // eliminate a conditional branch to the immediate successor
               prev_branch->change_block(last_branch->block());
               prev_branch->negate_cond();
+              prev_cmp->set_condition(prev_branch->cond());
               instructions->truncate(instructions->length() - 1);
             }
           }