17723 n->as_Vector()->length() == 8); |
17723 n->as_Vector()->length() == 8); |
17724 match(Set dst (LShiftVB src shift)); |
17724 match(Set dst (LShiftVB src shift)); |
17725 ins_cost(INSN_COST); |
17725 ins_cost(INSN_COST); |
17726 format %{ "shl $dst, $src, $shift\t# vector (8B)" %} |
17726 format %{ "shl $dst, $src, $shift\t# vector (8B)" %} |
17727 ins_encode %{ |
17727 ins_encode %{ |
17728 int sh = (int)$shift$$constant & 31; |
17728 int sh = (int)$shift$$constant; |
17729 if (sh >= 8) { |
17729 if (sh >= 8) { |
17730 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17730 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17731 as_FloatRegister($src$$reg), |
17731 as_FloatRegister($src$$reg), |
17732 as_FloatRegister($src$$reg)); |
17732 as_FloatRegister($src$$reg)); |
17733 } else { |
17733 } else { |
17742 predicate(n->as_Vector()->length() == 16); |
17742 predicate(n->as_Vector()->length() == 16); |
17743 match(Set dst (LShiftVB src shift)); |
17743 match(Set dst (LShiftVB src shift)); |
17744 ins_cost(INSN_COST); |
17744 ins_cost(INSN_COST); |
17745 format %{ "shl $dst, $src, $shift\t# vector (16B)" %} |
17745 format %{ "shl $dst, $src, $shift\t# vector (16B)" %} |
17746 ins_encode %{ |
17746 ins_encode %{ |
17747 int sh = (int)$shift$$constant & 31; |
17747 int sh = (int)$shift$$constant; |
17748 if (sh >= 8) { |
17748 if (sh >= 8) { |
17749 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17749 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17750 as_FloatRegister($src$$reg), |
17750 as_FloatRegister($src$$reg), |
17751 as_FloatRegister($src$$reg)); |
17751 as_FloatRegister($src$$reg)); |
17752 } else { |
17752 } else { |
17762 n->as_Vector()->length() == 8); |
17762 n->as_Vector()->length() == 8); |
17763 match(Set dst (RShiftVB src shift)); |
17763 match(Set dst (RShiftVB src shift)); |
17764 ins_cost(INSN_COST); |
17764 ins_cost(INSN_COST); |
17765 format %{ "sshr $dst, $src, $shift\t# vector (8B)" %} |
17765 format %{ "sshr $dst, $src, $shift\t# vector (8B)" %} |
17766 ins_encode %{ |
17766 ins_encode %{ |
17767 int sh = (int)$shift$$constant & 31; |
17767 int sh = (int)$shift$$constant; |
17768 if (sh >= 8) sh = 7; |
17768 if (sh >= 8) sh = 7; |
17769 sh = -sh & 7; |
|
17770 __ sshr(as_FloatRegister($dst$$reg), __ T8B, |
17769 __ sshr(as_FloatRegister($dst$$reg), __ T8B, |
17771 as_FloatRegister($src$$reg), sh); |
17770 as_FloatRegister($src$$reg), sh); |
17772 %} |
17771 %} |
17773 ins_pipe(vshift64_imm); |
17772 ins_pipe(vshift64_imm); |
17774 %} |
17773 %} |
17777 predicate(n->as_Vector()->length() == 16); |
17776 predicate(n->as_Vector()->length() == 16); |
17778 match(Set dst (RShiftVB src shift)); |
17777 match(Set dst (RShiftVB src shift)); |
17779 ins_cost(INSN_COST); |
17778 ins_cost(INSN_COST); |
17780 format %{ "sshr $dst, $src, $shift\t# vector (16B)" %} |
17779 format %{ "sshr $dst, $src, $shift\t# vector (16B)" %} |
17781 ins_encode %{ |
17780 ins_encode %{ |
17782 int sh = (int)$shift$$constant & 31; |
17781 int sh = (int)$shift$$constant; |
17783 if (sh >= 8) sh = 7; |
17782 if (sh >= 8) sh = 7; |
17784 sh = -sh & 7; |
|
17785 __ sshr(as_FloatRegister($dst$$reg), __ T16B, |
17783 __ sshr(as_FloatRegister($dst$$reg), __ T16B, |
17786 as_FloatRegister($src$$reg), sh); |
17784 as_FloatRegister($src$$reg), sh); |
17787 %} |
17785 %} |
17788 ins_pipe(vshift128_imm); |
17786 ins_pipe(vshift128_imm); |
17789 %} |
17787 %} |
17793 n->as_Vector()->length() == 8); |
17791 n->as_Vector()->length() == 8); |
17794 match(Set dst (URShiftVB src shift)); |
17792 match(Set dst (URShiftVB src shift)); |
17795 ins_cost(INSN_COST); |
17793 ins_cost(INSN_COST); |
17796 format %{ "ushr $dst, $src, $shift\t# vector (8B)" %} |
17794 format %{ "ushr $dst, $src, $shift\t# vector (8B)" %} |
17797 ins_encode %{ |
17795 ins_encode %{ |
17798 int sh = (int)$shift$$constant & 31; |
17796 int sh = (int)$shift$$constant; |
17799 if (sh >= 8) { |
17797 if (sh >= 8) { |
17800 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17798 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17801 as_FloatRegister($src$$reg), |
17799 as_FloatRegister($src$$reg), |
17802 as_FloatRegister($src$$reg)); |
17800 as_FloatRegister($src$$reg)); |
17803 } else { |
17801 } else { |
17804 __ ushr(as_FloatRegister($dst$$reg), __ T8B, |
17802 __ ushr(as_FloatRegister($dst$$reg), __ T8B, |
17805 as_FloatRegister($src$$reg), -sh & 7); |
17803 as_FloatRegister($src$$reg), sh); |
17806 } |
17804 } |
17807 %} |
17805 %} |
17808 ins_pipe(vshift64_imm); |
17806 ins_pipe(vshift64_imm); |
17809 %} |
17807 %} |
17810 |
17808 |
17812 predicate(n->as_Vector()->length() == 16); |
17810 predicate(n->as_Vector()->length() == 16); |
17813 match(Set dst (URShiftVB src shift)); |
17811 match(Set dst (URShiftVB src shift)); |
17814 ins_cost(INSN_COST); |
17812 ins_cost(INSN_COST); |
17815 format %{ "ushr $dst, $src, $shift\t# vector (16B)" %} |
17813 format %{ "ushr $dst, $src, $shift\t# vector (16B)" %} |
17816 ins_encode %{ |
17814 ins_encode %{ |
17817 int sh = (int)$shift$$constant & 31; |
17815 int sh = (int)$shift$$constant; |
17818 if (sh >= 8) { |
17816 if (sh >= 8) { |
17819 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17817 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17820 as_FloatRegister($src$$reg), |
17818 as_FloatRegister($src$$reg), |
17821 as_FloatRegister($src$$reg)); |
17819 as_FloatRegister($src$$reg)); |
17822 } else { |
17820 } else { |
17823 __ ushr(as_FloatRegister($dst$$reg), __ T16B, |
17821 __ ushr(as_FloatRegister($dst$$reg), __ T16B, |
17824 as_FloatRegister($src$$reg), -sh & 7); |
17822 as_FloatRegister($src$$reg), sh); |
17825 } |
17823 } |
17826 %} |
17824 %} |
17827 ins_pipe(vshift128_imm); |
17825 ins_pipe(vshift128_imm); |
17828 %} |
17826 %} |
17829 |
17827 |
17888 n->as_Vector()->length() == 4); |
17886 n->as_Vector()->length() == 4); |
17889 match(Set dst (LShiftVS src shift)); |
17887 match(Set dst (LShiftVS src shift)); |
17890 ins_cost(INSN_COST); |
17888 ins_cost(INSN_COST); |
17891 format %{ "shl $dst, $src, $shift\t# vector (4H)" %} |
17889 format %{ "shl $dst, $src, $shift\t# vector (4H)" %} |
17892 ins_encode %{ |
17890 ins_encode %{ |
17893 int sh = (int)$shift$$constant & 31; |
17891 int sh = (int)$shift$$constant; |
17894 if (sh >= 16) { |
17892 if (sh >= 16) { |
17895 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17893 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17896 as_FloatRegister($src$$reg), |
17894 as_FloatRegister($src$$reg), |
17897 as_FloatRegister($src$$reg)); |
17895 as_FloatRegister($src$$reg)); |
17898 } else { |
17896 } else { |
17907 predicate(n->as_Vector()->length() == 8); |
17905 predicate(n->as_Vector()->length() == 8); |
17908 match(Set dst (LShiftVS src shift)); |
17906 match(Set dst (LShiftVS src shift)); |
17909 ins_cost(INSN_COST); |
17907 ins_cost(INSN_COST); |
17910 format %{ "shl $dst, $src, $shift\t# vector (8H)" %} |
17908 format %{ "shl $dst, $src, $shift\t# vector (8H)" %} |
17911 ins_encode %{ |
17909 ins_encode %{ |
17912 int sh = (int)$shift$$constant & 31; |
17910 int sh = (int)$shift$$constant; |
17913 if (sh >= 16) { |
17911 if (sh >= 16) { |
17914 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17912 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17915 as_FloatRegister($src$$reg), |
17913 as_FloatRegister($src$$reg), |
17916 as_FloatRegister($src$$reg)); |
17914 as_FloatRegister($src$$reg)); |
17917 } else { |
17915 } else { |
17927 n->as_Vector()->length() == 4); |
17925 n->as_Vector()->length() == 4); |
17928 match(Set dst (RShiftVS src shift)); |
17926 match(Set dst (RShiftVS src shift)); |
17929 ins_cost(INSN_COST); |
17927 ins_cost(INSN_COST); |
17930 format %{ "sshr $dst, $src, $shift\t# vector (4H)" %} |
17928 format %{ "sshr $dst, $src, $shift\t# vector (4H)" %} |
17931 ins_encode %{ |
17929 ins_encode %{ |
17932 int sh = (int)$shift$$constant & 31; |
17930 int sh = (int)$shift$$constant; |
17933 if (sh >= 16) sh = 15; |
17931 if (sh >= 16) sh = 15; |
17934 sh = -sh & 15; |
|
17935 __ sshr(as_FloatRegister($dst$$reg), __ T4H, |
17932 __ sshr(as_FloatRegister($dst$$reg), __ T4H, |
17936 as_FloatRegister($src$$reg), sh); |
17933 as_FloatRegister($src$$reg), sh); |
17937 %} |
17934 %} |
17938 ins_pipe(vshift64_imm); |
17935 ins_pipe(vshift64_imm); |
17939 %} |
17936 %} |
17942 predicate(n->as_Vector()->length() == 8); |
17939 predicate(n->as_Vector()->length() == 8); |
17943 match(Set dst (RShiftVS src shift)); |
17940 match(Set dst (RShiftVS src shift)); |
17944 ins_cost(INSN_COST); |
17941 ins_cost(INSN_COST); |
17945 format %{ "sshr $dst, $src, $shift\t# vector (8H)" %} |
17942 format %{ "sshr $dst, $src, $shift\t# vector (8H)" %} |
17946 ins_encode %{ |
17943 ins_encode %{ |
17947 int sh = (int)$shift$$constant & 31; |
17944 int sh = (int)$shift$$constant; |
17948 if (sh >= 16) sh = 15; |
17945 if (sh >= 16) sh = 15; |
17949 sh = -sh & 15; |
|
17950 __ sshr(as_FloatRegister($dst$$reg), __ T8H, |
17946 __ sshr(as_FloatRegister($dst$$reg), __ T8H, |
17951 as_FloatRegister($src$$reg), sh); |
17947 as_FloatRegister($src$$reg), sh); |
17952 %} |
17948 %} |
17953 ins_pipe(vshift128_imm); |
17949 ins_pipe(vshift128_imm); |
17954 %} |
17950 %} |
17958 n->as_Vector()->length() == 4); |
17954 n->as_Vector()->length() == 4); |
17959 match(Set dst (URShiftVS src shift)); |
17955 match(Set dst (URShiftVS src shift)); |
17960 ins_cost(INSN_COST); |
17956 ins_cost(INSN_COST); |
17961 format %{ "ushr $dst, $src, $shift\t# vector (4H)" %} |
17957 format %{ "ushr $dst, $src, $shift\t# vector (4H)" %} |
17962 ins_encode %{ |
17958 ins_encode %{ |
17963 int sh = (int)$shift$$constant & 31; |
17959 int sh = (int)$shift$$constant; |
17964 if (sh >= 16) { |
17960 if (sh >= 16) { |
17965 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17961 __ eor(as_FloatRegister($dst$$reg), __ T8B, |
17966 as_FloatRegister($src$$reg), |
17962 as_FloatRegister($src$$reg), |
17967 as_FloatRegister($src$$reg)); |
17963 as_FloatRegister($src$$reg)); |
17968 } else { |
17964 } else { |
17969 __ ushr(as_FloatRegister($dst$$reg), __ T4H, |
17965 __ ushr(as_FloatRegister($dst$$reg), __ T4H, |
17970 as_FloatRegister($src$$reg), -sh & 15); |
17966 as_FloatRegister($src$$reg), sh); |
17971 } |
17967 } |
17972 %} |
17968 %} |
17973 ins_pipe(vshift64_imm); |
17969 ins_pipe(vshift64_imm); |
17974 %} |
17970 %} |
17975 |
17971 |
17977 predicate(n->as_Vector()->length() == 8); |
17973 predicate(n->as_Vector()->length() == 8); |
17978 match(Set dst (URShiftVS src shift)); |
17974 match(Set dst (URShiftVS src shift)); |
17979 ins_cost(INSN_COST); |
17975 ins_cost(INSN_COST); |
17980 format %{ "ushr $dst, $src, $shift\t# vector (8H)" %} |
17976 format %{ "ushr $dst, $src, $shift\t# vector (8H)" %} |
17981 ins_encode %{ |
17977 ins_encode %{ |
17982 int sh = (int)$shift$$constant & 31; |
17978 int sh = (int)$shift$$constant; |
17983 if (sh >= 16) { |
17979 if (sh >= 16) { |
17984 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17980 __ eor(as_FloatRegister($dst$$reg), __ T16B, |
17985 as_FloatRegister($src$$reg), |
17981 as_FloatRegister($src$$reg), |
17986 as_FloatRegister($src$$reg)); |
17982 as_FloatRegister($src$$reg)); |
17987 } else { |
17983 } else { |
17988 __ ushr(as_FloatRegister($dst$$reg), __ T8H, |
17984 __ ushr(as_FloatRegister($dst$$reg), __ T8H, |
17989 as_FloatRegister($src$$reg), -sh & 15); |
17985 as_FloatRegister($src$$reg), sh); |
17990 } |
17986 } |
17991 %} |
17987 %} |
17992 ins_pipe(vshift128_imm); |
17988 ins_pipe(vshift128_imm); |
17993 %} |
17989 %} |
17994 |
17990 |
18052 ins_cost(INSN_COST); |
18048 ins_cost(INSN_COST); |
18053 format %{ "shl $dst, $src, $shift\t# vector (2S)" %} |
18049 format %{ "shl $dst, $src, $shift\t# vector (2S)" %} |
18054 ins_encode %{ |
18050 ins_encode %{ |
18055 __ shl(as_FloatRegister($dst$$reg), __ T2S, |
18051 __ shl(as_FloatRegister($dst$$reg), __ T2S, |
18056 as_FloatRegister($src$$reg), |
18052 as_FloatRegister($src$$reg), |
18057 (int)$shift$$constant & 31); |
18053 (int)$shift$$constant); |
18058 %} |
18054 %} |
18059 ins_pipe(vshift64_imm); |
18055 ins_pipe(vshift64_imm); |
18060 %} |
18056 %} |
18061 |
18057 |
18062 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{ |
18058 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{ |
18065 ins_cost(INSN_COST); |
18061 ins_cost(INSN_COST); |
18066 format %{ "shl $dst, $src, $shift\t# vector (4S)" %} |
18062 format %{ "shl $dst, $src, $shift\t# vector (4S)" %} |
18067 ins_encode %{ |
18063 ins_encode %{ |
18068 __ shl(as_FloatRegister($dst$$reg), __ T4S, |
18064 __ shl(as_FloatRegister($dst$$reg), __ T4S, |
18069 as_FloatRegister($src$$reg), |
18065 as_FloatRegister($src$$reg), |
18070 (int)$shift$$constant & 31); |
18066 (int)$shift$$constant); |
18071 %} |
18067 %} |
18072 ins_pipe(vshift128_imm); |
18068 ins_pipe(vshift128_imm); |
18073 %} |
18069 %} |
18074 |
18070 |
18075 instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{ |
18071 instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{ |
18078 ins_cost(INSN_COST); |
18074 ins_cost(INSN_COST); |
18079 format %{ "sshr $dst, $src, $shift\t# vector (2S)" %} |
18075 format %{ "sshr $dst, $src, $shift\t# vector (2S)" %} |
18080 ins_encode %{ |
18076 ins_encode %{ |
18081 __ sshr(as_FloatRegister($dst$$reg), __ T2S, |
18077 __ sshr(as_FloatRegister($dst$$reg), __ T2S, |
18082 as_FloatRegister($src$$reg), |
18078 as_FloatRegister($src$$reg), |
18083 -(int)$shift$$constant & 31); |
18079 (int)$shift$$constant); |
18084 %} |
18080 %} |
18085 ins_pipe(vshift64_imm); |
18081 ins_pipe(vshift64_imm); |
18086 %} |
18082 %} |
18087 |
18083 |
18088 instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{ |
18084 instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{ |
18091 ins_cost(INSN_COST); |
18087 ins_cost(INSN_COST); |
18092 format %{ "sshr $dst, $src, $shift\t# vector (4S)" %} |
18088 format %{ "sshr $dst, $src, $shift\t# vector (4S)" %} |
18093 ins_encode %{ |
18089 ins_encode %{ |
18094 __ sshr(as_FloatRegister($dst$$reg), __ T4S, |
18090 __ sshr(as_FloatRegister($dst$$reg), __ T4S, |
18095 as_FloatRegister($src$$reg), |
18091 as_FloatRegister($src$$reg), |
18096 -(int)$shift$$constant & 31); |
18092 (int)$shift$$constant); |
18097 %} |
18093 %} |
18098 ins_pipe(vshift128_imm); |
18094 ins_pipe(vshift128_imm); |
18099 %} |
18095 %} |
18100 |
18096 |
18101 instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{ |
18097 instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{ |
18104 ins_cost(INSN_COST); |
18100 ins_cost(INSN_COST); |
18105 format %{ "ushr $dst, $src, $shift\t# vector (2S)" %} |
18101 format %{ "ushr $dst, $src, $shift\t# vector (2S)" %} |
18106 ins_encode %{ |
18102 ins_encode %{ |
18107 __ ushr(as_FloatRegister($dst$$reg), __ T2S, |
18103 __ ushr(as_FloatRegister($dst$$reg), __ T2S, |
18108 as_FloatRegister($src$$reg), |
18104 as_FloatRegister($src$$reg), |
18109 -(int)$shift$$constant & 31); |
18105 (int)$shift$$constant); |
18110 %} |
18106 %} |
18111 ins_pipe(vshift64_imm); |
18107 ins_pipe(vshift64_imm); |
18112 %} |
18108 %} |
18113 |
18109 |
18114 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{ |
18110 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{ |
18117 ins_cost(INSN_COST); |
18113 ins_cost(INSN_COST); |
18118 format %{ "ushr $dst, $src, $shift\t# vector (4S)" %} |
18114 format %{ "ushr $dst, $src, $shift\t# vector (4S)" %} |
18119 ins_encode %{ |
18115 ins_encode %{ |
18120 __ ushr(as_FloatRegister($dst$$reg), __ T4S, |
18116 __ ushr(as_FloatRegister($dst$$reg), __ T4S, |
18121 as_FloatRegister($src$$reg), |
18117 as_FloatRegister($src$$reg), |
18122 -(int)$shift$$constant & 31); |
18118 (int)$shift$$constant); |
18123 %} |
18119 %} |
18124 ins_pipe(vshift128_imm); |
18120 ins_pipe(vshift128_imm); |
18125 %} |
18121 %} |
18126 |
18122 |
18127 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
18123 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
18157 ins_cost(INSN_COST); |
18153 ins_cost(INSN_COST); |
18158 format %{ "shl $dst, $src, $shift\t# vector (2D)" %} |
18154 format %{ "shl $dst, $src, $shift\t# vector (2D)" %} |
18159 ins_encode %{ |
18155 ins_encode %{ |
18160 __ shl(as_FloatRegister($dst$$reg), __ T2D, |
18156 __ shl(as_FloatRegister($dst$$reg), __ T2D, |
18161 as_FloatRegister($src$$reg), |
18157 as_FloatRegister($src$$reg), |
18162 (int)$shift$$constant & 63); |
18158 (int)$shift$$constant); |
18163 %} |
18159 %} |
18164 ins_pipe(vshift128_imm); |
18160 ins_pipe(vshift128_imm); |
18165 %} |
18161 %} |
18166 |
18162 |
18167 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{ |
18163 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{ |
18170 ins_cost(INSN_COST); |
18166 ins_cost(INSN_COST); |
18171 format %{ "sshr $dst, $src, $shift\t# vector (2D)" %} |
18167 format %{ "sshr $dst, $src, $shift\t# vector (2D)" %} |
18172 ins_encode %{ |
18168 ins_encode %{ |
18173 __ sshr(as_FloatRegister($dst$$reg), __ T2D, |
18169 __ sshr(as_FloatRegister($dst$$reg), __ T2D, |
18174 as_FloatRegister($src$$reg), |
18170 as_FloatRegister($src$$reg), |
18175 -(int)$shift$$constant & 63); |
18171 (int)$shift$$constant); |
18176 %} |
18172 %} |
18177 ins_pipe(vshift128_imm); |
18173 ins_pipe(vshift128_imm); |
18178 %} |
18174 %} |
18179 |
18175 |
18180 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ |
18176 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ |
18183 ins_cost(INSN_COST); |
18179 ins_cost(INSN_COST); |
18184 format %{ "ushr $dst, $src, $shift\t# vector (2D)" %} |
18180 format %{ "ushr $dst, $src, $shift\t# vector (2D)" %} |
18185 ins_encode %{ |
18181 ins_encode %{ |
18186 __ ushr(as_FloatRegister($dst$$reg), __ T2D, |
18182 __ ushr(as_FloatRegister($dst$$reg), __ T2D, |
18187 as_FloatRegister($src$$reg), |
18183 as_FloatRegister($src$$reg), |
18188 -(int)$shift$$constant & 63); |
18184 (int)$shift$$constant); |
18189 %} |
18185 %} |
18190 ins_pipe(vshift128_imm); |
18186 ins_pipe(vshift128_imm); |
18191 %} |
18187 %} |
18192 |
18188 |
18193 //----------PEEPHOLE RULES----------------------------------------------------- |
18189 //----------PEEPHOLE RULES----------------------------------------------------- |